Clock generation circuit and clock generation method
A clock generation circuit combining a current comparator and an integrator replaces the traditional frequency and phase detector and charge pump structure, solving the problems of clock signal frequency stability and nonlinear error. This achieves low-power, high-precision clock signal generation, with flexible design and reduced R&D costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-26
- Publication Date
- 2026-04-21
AI Technical Summary
In existing technologies, the clock signal frequency stability of ring oscillators and traditional PLL/FLL architectures is poor and nonlinear errors exist, which leads to increased chip area and power consumption, and reduced system flexibility.
A combination of current comparator and integrator is used to replace the frequency and phase detector and charge pump structure. Differential current is generated by feedback current generation unit and reference current generation unit, control voltage is generated by integrator, clock signal is generated by voltage-controlled oscillator, and reference current is generated by zero-temperature resistor to reduce noise sources.
It reduces chip area and power consumption, improves clock signal accuracy and frequency stability, enables dynamic adjustment of loop bandwidth and response speed, enhances system flexibility, and reduces R&D risks.
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Figure CN121907235A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a clock generation circuit and clock generation method. Background Technology
[0002] In microcontrollers, IoT chips, and other embedded systems that are extremely sensitive to cost and power consumption, on-chip clock sources typically employ ring oscillators or charge pump-based phase-locked loop (PLL) / frequency-locked loop (FLL) architectures to provide clock signals.
[0003] In existing technologies, ring oscillators are easily affected by variations in process technology, voltage, and temperature, resulting in poor frequency stability of the clock signal. Traditional PLL / FLL systems convert phase errors into current pulses via a phase-frequency detector (PFD) and a charge pump, which are then filtered by a loop filter to control a voltage-controlled oscillator (VCO) to provide the clock signal. However, the PFD and charge pump-based architecture inherently suffers from nonlinear errors such as dead time and current mismatch, limiting the accuracy of the clock signal. To reduce these nonlinear errors, a larger loop filter is required, increasing chip area and power consumption. Furthermore, traditional architectures are difficult to adjust bandwidth after manufacturing, reducing system flexibility. Summary of the Invention
[0004] In view of the above problems, the purpose of this application is to provide a clock generation circuit and clock generation method, which can effectively reduce power consumption and chip area while improving the accuracy of clock signals.
[0005] According to one aspect of the present invention, a clock generation circuit is provided, comprising: a current comparator for providing a differential current between a reference current and a feedback current, the current comparator including a feedback current generation unit for generating the feedback current; an integrator for integrating the differential current to generate a control voltage; and a voltage-controlled oscillator for generating a clock signal based on the control voltage, wherein the feedback current generation unit includes a first capacitor and a second capacitor, the first capacitor and the second capacitor being respectively connected between the integrator and a first voltage, and the feedback current generation unit alternately charging the first capacitor and the second capacitor according to a feedback signal of the clock signal to provide the feedback current.
[0006] Optionally, the feedback current generation unit further includes: a first switching element and a second switching element connected in series between the integrator and the first voltage, the common node of the first switching element and the second switching element being connected to the first voltage via the first capacitor; and a third switching element and a fourth switching element connected in series between the integrator and the first voltage, the common node of the third switching element and the fourth switching element being connected to the first voltage via the second capacitor, wherein the second switching element and the third switching element are turned on according to the valid level of the feedback signal and turned off according to the invalid level of the feedback signal; the first switching element and the fourth switching element are turned off according to the valid level of the feedback signal and turned on according to the invalid level of the feedback signal, and the capacitance values of the first capacitor and the second capacitor are equal.
[0007] Optionally, the current comparator further includes a reference current generation unit, which is connected to the common node of the feedback current generation unit and the integrator, and is used to provide the reference current.
[0008] Optionally, the reference current generation unit includes a resistor connected between the second voltage and the integrator.
[0009] Optionally, the resistor is a zero-temperature resistor.
[0010] Optionally, the reference current generation unit includes: a fifth and a sixth switching element connected in series between the second voltage and the integrator; a third capacitor, the common node of the fifth and sixth switching elements being connected to the second voltage via the third capacitor; a seventh and an eighth switching element connected in series between the second voltage and the integrator; and a fourth capacitor, the common node of the seventh and eighth switching elements being connected to the second voltage via the fourth capacitor, wherein the fifth and eighth switching elements are turned on according to the effective level of the reference clock and turned off according to the invalid level of the reference clock; the sixth and seventh switching elements are turned off according to the effective level of the reference clock and turned on according to the invalid level of the reference clock, and the capacitance values of the third and fourth capacitors are equal.
[0011] Optionally, the integrator includes: an operational amplifier with a first input terminal connected to the current comparator, a second input terminal connected to a reference voltage, and an output terminal providing the control voltage; and an integrating capacitor connected between the first input terminal and the output terminal of the operational amplifier, for providing multiple capacitance values, the capacitance values being used to adjust the bandwidth of the clock generation circuit.
[0012] Optionally, the reference voltage is half of the second voltage.
[0013] According to another aspect of the present invention, a clock generation method is provided, comprising: alternately charging a first capacitor and a second capacitor according to a feedback signal of a clock signal to provide a feedback current; obtaining a difference current between a reference current and the feedback current; integrating the difference current through an integrator to generate a control voltage; and generating a clock signal according to the control voltage, wherein the first capacitor and the second capacitor are respectively connected between the integrator and the first voltage.
[0014] Optionally, the capacitance values of the first capacitor and the second capacitor are equal.
[0015] Optionally, the step of obtaining the reference current includes: applying a second voltage to a resistor to provide the reference current; or alternately charging a third capacitor and a fourth capacitor according to a reference clock to provide the reference current, wherein the third capacitor and the fourth capacitor are respectively connected between the second voltage and the integrator, and the capacitance values of the third capacitor and the fourth capacitor are equal.
[0016] Optionally, the resistor is a zero-temperature resistor.
[0017] Optionally, it further includes: adjusting the capacitance value of the integrating capacitor in the integrator to adjust the setup time of the clock signal.
[0018] According to the clock generation circuit and method disclosed in this application, a combination of a current comparator and an integrator replaces the traditional frequency and phase detector and charge pump structure, simplifying the circuit structure and helping to reduce chip area and power consumption. At the same time, it avoids introducing the inherent nonlinear errors of traditional architectures, thus improving the accuracy of the clock signal.
[0019] Furthermore, generating the reference current based on zero-temperature resistance can reduce noise sources and decrease the impact of temperature changes on the reference current, which is more conducive to improving frequency stability and accuracy.
[0020] Furthermore, by adjusting the capacitance of the integrating capacitor, the loop bandwidth and response speed can be dynamically adjusted, thereby optimizing the clock signal setup time and stability. The clock generation circuit design offers greater flexibility, allowing it to be matched to different operating conditions and reducing R&D risks and costs. Attached Figure Description
[0021] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:
[0022] Figure 1 A schematic structural diagram of the clock generation circuit of this application is shown;
[0023] Figure 2ASchematic structural diagrams of current comparators in some embodiments are shown;
[0024] Figure 2B Show Figure 2A The equivalent circuit diagram of the current comparator shown is as follows;
[0025] Figure 3A Schematic structural diagrams of current comparators in some other embodiments are shown;
[0026] Figure 3B Show Figure 3A The equivalent circuit diagram of the current comparator shown is as follows;
[0027] Figures 4A-4D The following are waveform diagrams illustrating the operation of the clock generation circuit of this application in some embodiments;
[0028] Figures 5A-5D The following are waveform diagrams illustrating the operation of the clock generation circuit of this application in some other embodiments;
[0029] Figure 6 A schematic flowchart of the clock generation method of this application is shown. Detailed Implementation
[0030] Various embodiments of the present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.
[0031] Furthermore, certain terms are used in this specification and claims to refer to specific components. Those skilled in the art will understand that manufacturers may use different names to refer to the same component. This specification and claims do not distinguish components based on differences in name, but rather on differences in function.
[0032] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.
[0033] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0034] It should also be noted that in the various methods and processes of this application, the order of the steps does not imply the order of execution, nor does it constitute any limitation on the implementation process of the embodiments of this application.
[0035] Figure 1 A schematic structural diagram of the clock generation circuit of this application is shown. (As shown...) Figure 1 As shown, the clock generation circuit 100 provided in this application includes at least: a current comparator 110, an integrator 120, and a voltage-controlled oscillator 140.
[0036] Current comparator 110 is used to provide the difference current ΔI between the reference current Iref and the feedback current Ifb. For example... Figure 1 As shown, in some embodiments, the current comparator 110 includes a feedback current generation unit 111 and a reference current generation unit 112. The feedback current generation unit 111 is used to generate a feedback current Ifb, and the reference current generation unit 112 is used to generate a reference current Iref. The common node (node A) of the feedback current generation unit 111 and the reference current generation unit 112 provides a differential current ΔI.
[0037] Integrator 120 is connected to node A and is used to integrate the differential current ΔI to generate the control voltage Vctrl. For example... Figure 1 As shown, integrator 120 includes operational amplifier 121 and integrating capacitor Cint. The first input terminal of the operational amplifier is connected to node A, the second input terminal receives the reference voltage Vref, and the output terminal outputs the control voltage Vctrl. Figure 1 In this example, the inverting input of operational amplifier 121 is used as the first input and the non-inverting input as the second input. The integrating capacitor Cint is connected between the output of operational amplifier 121 and the first input to integrate the difference current ΔI.
[0038] The voltage-controlled oscillator 140 generates a clock signal clk_out based on the control voltage Vctrl.
[0039] In some embodiments, the clock generation circuit 100 further includes a frequency divider 150 connected between the voltage-controlled oscillator 140 and the current comparator 110, specifically the feedback current generation unit 111, for dividing the clock signal clk_out to generate a feedback signal clk_fb for the clock signal clk_out. The feedback current generation unit 111 generates a feedback current Ifb based on the feedback signal clk_fb.
[0040] In some embodiments, the clock generation circuit 100 further includes a loop filter 130 connected between the integrator 120 and the voltage-controlled oscillator 140, for filtering the control voltage Vctrl to suppress high-frequency noise, thereby further improving the stability of the clock signal clk_out. The loop filter 130 is, for example, an RC filter.
[0041] Figure 2A Schematic structural diagrams of current comparator 110a in some embodiments are shown. For example... Figure 2A As shown, the current comparator 110a includes a feedback current generation unit 111 and a reference current generation unit 112a.
[0042] The feedback current generation unit 111 includes a first capacitor C1 and a second capacitor C2 connected between node A and a first voltage, respectively. Hereinafter, the first voltage is taken as ground voltage GND. Preferably, the capacitance values of both the first capacitor C1 and the second capacitor C2 are Ca. The feedback current generation unit 111 alternately charges the first capacitor C1 and the second capacitor C2 according to the feedback signal clk_fb to provide a continuous feedback current Ifb. Specifically, the feedback current generation unit 111 also includes first switching elements K1 to fourth switching elements K4. The first switching element K1 and the second switching element K2 are connected in series between node A and the ground voltage GND, and the first capacitor C1 is connected between the common node of the first switching element K1 and the second switching element K2 and the ground voltage GND. The third switching element K3 and the fourth switching element K4 are connected in series between node A and the ground voltage GND, and the second capacitor C2 is connected between the common node of the third switching element K3 and the fourth switching element K4 and the ground voltage GND. In this embodiment, the second switching element K2 and the third switching element K3 are turned on according to the valid level of the feedback signal clk_fb, and turned off according to the invalid level of the feedback signal clk_fb; the first switching element K1 and the fourth switching element K4 are turned off according to the valid level of the feedback signal clk_fb, and turned on according to the invalid level of the feedback signal clk_fb, thereby realizing the alternating charging of the first capacitor C1 and the second capacitor C2. In some embodiments, the first switching element K1 to the fourth switching element K4 are switching transistors. Taking MOSFETs as an example, the first switching element K1 and the fourth switching element K4 can be one of NMOS and PMOS, and the second switching element K2 and the third switching element K3 can be the other of NMOS and PMOS. Therefore, the feedback signal clk_fb can directly control the first switching element K1 to the fourth switching element K4. In some other embodiments, the first switching element K1 to the fourth switching element K4 have the same type. In this case, the clock generation circuit may also include an inverting circuit to provide the inverted signal of the feedback signal clk_fb. Accordingly, the second switching element K2 and the third switching element K3 can be controlled by the feedback signal clk_fb, and the first switching element K1 and the fourth switching element K4 can be controlled by the inverted signal of the feedback signal clk_fb.
[0043] The reference current generation unit 112a includes a third capacitor C3 and a fourth capacitor C4 connected between the second voltage and node A, respectively. Hereinafter, the second voltage is taken as the power supply voltage VDD. Preferably, the capacitance values of both the third capacitor C3 and the fourth capacitor C4 are Cb. The reference current generation unit 112a alternately charges the third capacitor C3 and the fourth capacitor C4 according to a reference clock to provide a continuous reference current Iref. Specifically, the reference current generation unit 112a also includes a fifth switching element K5 to an eighth switching element K8. The fifth switching element K5 and the sixth switching element K6 are connected in series between the power supply voltage VDD and node A. The third capacitor C3 is connected between the common node of the fifth switching element K5 and the sixth switching element K6 and the power supply voltage VDD. The seventh switching element K7 and the eighth switching element K8 are connected in series between the power supply voltage VDD and node A. The fourth capacitor C4 is connected between the common node of the seventh switching element K7 and the eighth switching element K8 and the power supply voltage VDD. Specifically, the fifth switching element K5 and the eighth switching element K8 are turned on according to the valid level of the reference clock and turned off according to the invalid level of the reference clock; the sixth switching element K6 and the seventh switching element K7 are turned off according to the valid level of the reference clock and turned on according to the invalid level of the reference clock. The fifth to eighth switching elements K5 can also be switching transistors, and their on / off control principle is similar to that of the first to fourth switching elements K4, which will not be described in detail here.
[0044] It should be understood that the first voltage and the second voltage can reuse other existing voltages in the circuit, as long as the first voltage is less than the second voltage.
[0045] Figure 2B The equivalent circuit diagram of current comparator 110a is shown. Figure 2B As shown, when the capacitance values of the first capacitor C1 and the second capacitor C2 are equal and are Ca, and the capacitance values of the third capacitor C3 and the fourth capacitor C4 are equal and are Cb, the reference current generation unit 112a can be equivalent to a capacitor with a capacitance value of 2Cb, and the feedback current generation unit 111 can be equivalent to a capacitor with a capacitance value of 2Ca.
[0046] The formulas for calculating the reference current Iref and the feedback current Ifb within one clock cycle are as follows: (1) and (2): (1), (2), Where Iref is the reference current, Ifb is the feedback current, VDD is the power supply voltage, Vref is the reference voltage, Fref is the frequency of the reference clock, 2Cb is the equivalent capacitance of the reference current generation unit, 2Ca is the equivalent capacitance of the feedback current generation unit, and Ffb is the frequency of the feedback signal.
[0047] Combination Figure 1 The difference current ΔI between the reference current Iref and the feedback current Ifb is converted into the control voltage Vctrl by the integrator 120. After feedback adjustment in the loop, the reference current Iref is finally equal to the feedback current Ifb, and Fref and Ffb are equal. At this time, the frequency relationship between the clock signal clk_out, the feedback signal clk_fb and the reference clock is as follows (3):
[0048] Fout=N×Fref=N×Ffb(3)
[0049] Where N is the division ratio of the frequency divider 150, Fout is the frequency of the clock signal clk_out, Fref is the frequency of the reference clock, and Ffb is the frequency of the feedback signal.
[0050] The loop gain is calculated by disconnecting the loop from the output of the voltage-controlled oscillator 140, as shown in equation (4): (4), Wherein, loop gain is the loop gain, Fout is the frequency of the clock signal clk_out, Fi is the input frequency of the frequency divider 150, 2Cb is the equivalent capacitance value of the reference current generation unit 112a, 2Ca is the equivalent capacitance value of the feedback current generation unit 111, Vref is the reference voltage, Fref is the frequency of the reference clock, Av is the gain of the integrator 120, Kvco is the gain of the voltage-controlled oscillator 140, N is the division ratio of the frequency divider 150, s is the complex frequency variable, fLPF is the cutoff frequency of the loop filter 130, and Cint is the capacitance value of the integrating capacitor in the integrator 120. In this loop, the dominant pole is at the input of the integrator 120, and the secondary pole is at the loop filter 130.
[0051] Therefore, when the reference voltage Vref is half of the supply voltage VDD and Ca=Cb, the formula for calculating the loop bandwidth is as follows (5): (5), Where fu is the loop bandwidth, loop gain is the loop gain, wp1 is the main pole angular frequency at the input of integrator 120, Vref is the reference voltage, Kvco is the gain of the voltage-controlled oscillator, Cb is the capacitance of a single capacitor in the reference current generation unit, N is the division ratio of frequency divider 150, and Cint is the capacitance of the integrating capacitor in integrator 120.
[0052] According to the above formula (5), the loop bandwidth fu can be adjusted by adjusting the capacitance value of the integrating capacitor Cint, that is, adjusting the setup time of the clock signal clk_out and the response time of the loop.
[0053] Figure 3A Schematic structural diagrams of the current comparator 110b in some other embodiments are shown. For example... Figure 3A As shown, in a preferred embodiment, the current comparator 110b includes a feedback current generation unit 111 and a reference current generation unit 112b.
[0054] The feedback current generation unit 111 also includes a first capacitor C1, a second capacitor C2, and first switching elements K1 to fourth switching elements K4. The feedback current generation unit 111 can be referred to the description of Figure 2 above, and will not be repeated here.
[0055] Figure 3A The reference current generation unit 112b in the current comparator 110b shown is... Figure 2A The reference current generation unit 112a in the above examples has a different structure. Specifically, the reference current generation unit 112b includes a resistor R connected between the supply voltage VDD and node A. The resistor R is preferably a zero-temperature resistor, meaning that the resistance value of the resistor R will not drift with temperature changes, thereby ensuring the stability of the reference current Iref.
[0056] Figure 3B The equivalent circuit diagram of current comparator 110b is shown. Figure 3B As shown, when the capacitance values of the first capacitor C1 and the second capacitor C2 are equal and are Ca, the feedback current generation unit 111 can be equivalent to a capacitor with a capacitance value of 2Ca.
[0057] When the reference voltage Vref is half of the supply voltage VDD, the formulas for calculating the reference current Iref and the feedback current Ifb in one clock cycle are as follows: (6) and (7): (6), (7), Where Iref is the reference current, Ifb is the feedback current, VDD is the supply voltage, R is the resistance value, 2Ca is the equivalent capacitance value of the feedback current generation unit, and Ffb is the frequency of the feedback signal clk_fb.
[0058] Combination Figure 1 The difference current ΔI between the reference current Iref and the feedback current Ifb is converted into a control voltage Vctrl by the integrator 120. After feedback adjustment in the loop, the reference current Iref eventually equals the feedback current Ifb. At this time, the frequency relationship between the clock signal clk_out and the feedback signal clk_fb is as follows (8): (8), Where Fout is the frequency of the clock signal clk_out, Ffb is the frequency of the feedback signal clk_fb, N is the division ratio of the frequency divider 150, R is the resistance value of the resistor in the reference current generation unit, and Ca is the capacitance value of a single capacitor in the feedback signal generation unit.
[0059] According to the above formula (8), when the differential current ΔI is provided by the current comparator 110b, the frequency of the clock signal clk_out is determined by the resistance value of the resistor in the reference current generation unit and the capacitance value of the single capacitor in the feedback signal generation unit.
[0060] The loop gain is calculated by disconnecting the loop from the output of the voltage-controlled oscillator 140, as shown in equation (9): (9), Wherein, loop gain is the loop gain, Fout is the frequency of the clock signal clk_out, Fi is the input frequency of frequency divider 150, VDD is the supply voltage, Ca is the capacitance of a single capacitor in the feedback current generation unit, R is the resistance of the resistor in the reference current generation unit, Av is the gain of integrator 120, Kvco is the gain of voltage-controlled oscillator 140, N is the division ratio of frequency divider 150, s is the complex frequency variable, fLPF is the cutoff frequency of loop filter 130, and Cint is the capacitance of the integrating capacitor in integrator 120. In this loop, the dominant pole is at the input of integrator 120, and the secondary pole is at loop filter 130.
[0061] The formula for calculating the loop bandwidth is as follows (10): (10) Where fu is the loop bandwidth, loop gain is the loop gain, wp1 is the main pole angular frequency at the input of integrator 120, VDD is the supply voltage, Kvco is the gain of the voltage-controlled oscillator, Ca is the capacitance of a single capacitor in the feedback current generation unit, N is the division ratio of frequency divider 150, and Cint is the capacitance of the integrating capacitor in integrator 120.
[0062] According to the above formula (10), the loop bandwidth fu can be adjusted by adjusting the capacitance value of the integrating capacitor Cint, that is, adjusting the setup time of the clock signal clk_out and the response time of the loop.
[0063] Figures 4A-4D The diagram shows waveforms of the clock generation circuit of this application in some embodiments. Specifically, the clock generation circuit 100 includes, for example, the following waveforms. Figure 3AThe current comparator 110b shown is an example. Relevant parameters are as follows: the integrating capacitor of the integrator 120 is 3pF; the first capacitor C1 and the second capacitor C2 in the feedback current generation unit 111 have equal capacitance values of 500fF; the supply voltage VDD is 1.6V; the reference voltage Vref is half of the supply voltage VDD, i.e., 0.8V; the clock signal generation circuit starts at t1 = 35μs. Figure 4A The waveforms of the reference voltage Vref and the voltage Va at node A are shown after the clock signal generation circuit is started. Figure 4B Show Figure 4A A magnified view of a portion of region I in the middle. Figure 4C The frequency waveform of the clock signal clk_out is shown. Figure 4D The waveform of the control voltage Vctrl is shown. (Combined with the above...) Figures 4A-4D When the integrating capacitor is 3pF, the setup time of the clock signal clk_out is approximately 20μs.
[0064] Figures 5A-5D The diagram shows waveforms of the clock generation circuit of this application in some embodiments. Specifically, the clock generation circuit 100 includes, for example, the following waveforms. Figure 3A The current comparator 110b shown is an example. Relevant parameters are as follows: the integrating capacitor of the integrator 120 is 7pF; the first capacitor C1 and the second capacitor C2 in the feedback current generation unit 111 have equal capacitance values of 500fF; the supply voltage VDD is 1.6V; the reference voltage Vref is half of the supply voltage VDD, i.e., 0.8V; the clock signal generation circuit starts at t2 = 35μs. Figure 5A The waveforms of the reference voltage Vref and the voltage Va at node A are shown after the clock signal generation circuit is started. Figure 5B Show Figure 4A A magnified view of a portion of region I in the middle. Figure 5C The frequency waveform of the clock signal clk_out is shown. Figure 5D The waveform of the control voltage Vctrl is shown. Combined with the above... Figures 4A-4D When the integrating capacitor is 7pF, the setup time of the clock signal clk_out is approximately 70μs.
[0065] According to the above Figures 4A to 5DDifferent examples demonstrate that, according to the clock generation circuit provided in this application, the loop bandwidth can be adjusted by changing the capacitance value of the integrating capacitor Cint in the integrator 120, while keeping other parameters unchanged. Therefore, the clock generation circuit provided in this application has a more flexible design. Specifically, the integrating capacitor Cint can provide multiple capacitance values, so that even after the clock generation circuit is fabricated, the loop bandwidth can still be adjusted by selecting the capacitance value of the integrating capacitor Cint, significantly reducing R&D risk and cost. More specifically, the integrating capacitor can include a capacitor array, and its capacitance value can be adjusted by adjusting the number of capacitors connected to the operational amplifier 121. The adjustment method can include adjusting the number of connected capacitors through metal options or FIB (Focused Ion Beam); it can also be adjusted by configuring a switch network through a register; and it can also be implemented through other related technologies, which this application does not limit in detail.
[0066] The clock generation circuit disclosed in this application replaces the traditional frequency and phase detector and charge pump structure with a combination of current comparator and integrator, simplifying the circuit structure and reducing chip area and power consumption. It also avoids introducing the inherent nonlinear errors of traditional architectures, thus improving the accuracy of the clock signal.
[0067] Furthermore, generating the reference current based on zero-temperature resistance can reduce noise sources and decrease the impact of temperature changes on the reference current, which is more conducive to improving frequency stability and accuracy.
[0068] Furthermore, by adjusting the capacitance of the integrating capacitor, the loop bandwidth and response speed can be dynamically adjusted, thereby optimizing the clock signal setup time and stability. The clock generation circuit design offers greater flexibility, allowing it to be matched to different operating conditions and reducing R&D risks and costs.
[0069] This application also discloses a clock generation method. Figure 6 A schematic flowchart of the clock generation method of this application is shown. This clock generation method can be implemented, for example, by the clock generation circuit 100 disclosed in this application. Figure 6 As shown, the clock generation method provided in this application includes the following steps:
[0070] In step S11, the first capacitor and the second capacitor are alternately charged according to the feedback signal of the clock signal to provide feedback current;
[0071] In step S12, the difference current between the reference current and the feedback current is obtained;
[0072] In step S13, the differential current is integrated using an integrator to generate a control voltage; and
[0073] In step S14, a clock signal is generated based on the control voltage.
[0074] The first capacitor and the second capacitor are connected between the integrator and the first voltage, respectively. Preferably, the capacitance values of the first capacitor and the second capacitor are equal.
[0075] According to the clock generation method disclosed in this application, a technical solution that uses the difference current between the reference current and the feedback current to provide the control voltage replaces the traditional frequency and phase detector and charge pump structure, simplifying the circuit structure and helping to reduce chip area and power consumption. At the same time, it avoids introducing the inherent nonlinear errors of traditional architectures, thus improving the accuracy of the clock signal.
[0076] Furthermore, in some embodiments, the third and fourth capacitors can be alternately charged according to a reference clock to provide a reference current, wherein the third and fourth capacitors are respectively connected between the second voltage and the integrator. Preferably, the third and fourth capacitors have the same capacitance value. In a preferred embodiment, the reference current can be provided by applying a second voltage to a resistor. Preferably, this resistor is a zero-temperature resistor. Generating the reference current based on a zero-temperature resistor can reduce noise sources and reduce the impact of temperature changes on the reference current, which is more conducive to improving frequency stability and accuracy.
[0077] Furthermore, in some embodiments, the clock generation method provided in this application further includes adjusting the capacitance value of the integrating capacitor in the integrator to adjust the setup time of the clock signal. By adjusting the capacitance value of the integrating capacitor, the loop bandwidth and response speed can be dynamically adjusted, thereby optimizing the setup time and stability of the clock signal and achieving a balance between accuracy and power consumption under different operating conditions. Specifically, the integrating capacitor Cint can provide multiple capacitance values, so that after the clock generation circuit is fabricated, the loop bandwidth can still be adjusted by selecting the capacitance value of the integrating capacitor Cint, which greatly reduces the R&D risk and cost. More specifically, the integrating capacitor can include a capacitor array, and the capacitance value of the integrating capacitor can be adjusted by adjusting the number of capacitors connected to the operational amplifier 121. The adjustment method can include adjusting the number of connected capacitors through metal options or FIB (Focused Ion Beam); it can also be adjusted by configuring the switch network through registers; it can also be implemented through other related technologies, which this application does not limit in detail.
[0078] The embodiments described above, as per the examples of this application, do not exhaustively describe all details, nor do they limit this application to the specific embodiments described above. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. The scope of protection of this application should be determined by the scope defined in the claims of this application.
Claims
1. A clock generation circuit, wherein, include: A current comparator is used to provide a differential current between a reference current and a feedback current, the current comparator including a feedback current generation unit for generating the feedback current; An integrator is used to integrate the differential current to generate a control voltage; as well as A voltage-controlled oscillator is used to generate a clock signal based on the control voltage. The feedback current generation unit includes a first capacitor and a second capacitor, which are respectively connected between the integrator and the first voltage. The feedback current generation unit alternately charges the first capacitor and the second capacitor according to the feedback signal of the clock signal to provide the feedback current.
2. The clock generation circuit according to claim 1, wherein, The feedback current generation unit further includes: A first switching element and a second switching element are connected in series between the integrator and the first voltage, and the common node of the first switching element and the second switching element is connected to the first voltage via the first capacitor; and A third and a fourth switching element are connected in series between the integrator and the first voltage, and the common node of the third and fourth switching elements is connected to the first voltage via the second capacitor. The second and third switching elements are turned on according to the valid level of the feedback signal and turned off according to the invalid level of the feedback signal; the first and fourth switching elements are turned off according to the valid level of the feedback signal and turned on according to the invalid level of the feedback signal; the capacitance values of the first and second capacitors are equal.
3. The clock generation circuit according to claim 1, wherein, The current comparator further includes a reference current generation unit, which is connected to the common node of the feedback current generation unit and the integrator, and is used to provide the reference current.
4. The clock generation circuit according to claim 3, wherein, The reference current generation unit includes: A resistor is connected between the second voltage and the integrator.
5. The clock generation circuit according to claim 4, wherein, The resistor is a zero-temperature resistor.
6. The clock generation circuit according to claim 3, wherein, The reference current generation unit includes: A fifth and a sixth switching element are connected in series between the second voltage and the integrator; The third capacitor is used to connect the common node of the fifth and sixth switching elements to the second voltage. A seventh and eighth switching element connected in series between the second voltage and the integrator; and The fourth capacitor connects the common node of the seventh and eighth switching elements to the second voltage. The fifth and eighth switching elements are turned on according to the effective level of the reference clock and turned off according to the invalid level of the reference clock; the sixth and seventh switching elements are turned off according to the effective level of the reference clock and turned on according to the invalid level of the reference clock; the third and fourth capacitors have the same capacitance value.
7. The clock generation circuit according to any one of claims 4-6, wherein, The integrator includes: An operational amplifier, with its first input connected to the current comparator, its second input connected to a reference voltage, and its output providing the control voltage; and An integrating capacitor, connected between the first input and output terminals of the operational amplifier, provides multiple capacitance values for adjusting the bandwidth of the clock generation circuit.
8. The clock generation circuit according to claim 7, wherein, The reference voltage is half of the second voltage.
9. A clock generation method, wherein, include: The first and second capacitors are charged alternately according to the feedback signal of the clock signal to provide feedback current; Obtain the difference current between the reference current and the feedback current; The differential current is integrated using an integrator to generate a control voltage; as well as A clock signal is generated based on the control voltage. The first capacitor and the second capacitor are respectively connected between the integrator and the first voltage.
10. The clock generation method according to claim 9, wherein, The first capacitor and the second capacitor have the same capacitance value.
11. The clock generation method according to claim 9, wherein, The steps for obtaining the reference current include: A second voltage is applied to the resistor to provide the reference current; or The third and fourth capacitors are alternately charged according to a reference clock to provide the reference current. The third and fourth capacitors are respectively connected between the second voltage and the integrator, and the capacitance values of the third and fourth capacitors are equal.
12. The clock generation method according to claim 11, wherein, The resistor is a zero-temperature resistor.
13. The clock generation method according to any one of claims 9-12, wherein, Also includes: Adjust the capacitance of the integrating capacitor in the integrator to adjust the setup time of the clock signal.