Self-trimming ring oscillator for phase-locked loop
By using a multi-stage differential pair of a self-tuning ring oscillator and a control voltage sampling unit, the problem of limited frequency adjustment range of the phase-locked loop (PLL) was solved, enabling frequency expansion and flexible adjustment under different conditions, thus improving the applicability of the PLL.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 58TH RES INST OF CETC
- Filing Date
- 2025-12-26
- Publication Date
- 2026-04-21
AI Technical Summary
Existing phase-locked loops have limited frequency adjustment range, making it difficult to meet the high frequency coverage requirements of modern communication and digital systems, especially due to the influence of component parasitic parameters, manufacturing process, power supply voltage, and temperature of voltage-controlled oscillators.
A self-tuning ring oscillator is adopted, and through multi-level differential pairs and control voltage sampling units, combined with a level counter, the automatic switching and precise adjustment of frequency levels are realized. The frequency modulation capacitor bank composed of a switched capacitor array and varactor diodes is used to enhance the flexibility and adaptability of frequency adjustment.
This technology extends the frequency range of the phase-locked loop (PLL) under different process conditions, temperatures, and power supply voltages, improving frequency adaptability and practicality, and enhancing the versatility of PLL applications in systems.
Smart Images
Figure CN121907236A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of CMOS phase-locked loop technology, and in particular to a self-adjusting ring oscillator for a phase-locked loop. Background Technology
[0002] With the continuous development of communication technology, various electronic systems have experienced rapid advancements. Phase-locked loops (PLLs) play a crucial role in modern data transmission and communication systems. In communication systems, PLLs generate stable single-frequency signals, serving as the frequency source for frequency synthesizers. In digital systems, PLLs provide a stable clock and can flexibly adjust the clock frequency to meet changing needs. Frequency adjustment range is a critical indicator for PLLs; the frequency range that the PLL output can cover directly impacts its applicability to various systems. Currently, systems are becoming increasingly diversified and integrated, placing higher demands on the frequency coverage of PLLs. The frequency adjustment range of a PLL is directly influenced by the voltage-controlled oscillator (VCO) within it. Therefore, a wide-range ring oscillator suitable for PLLs is essential for improving the frequency performance of both the PLL and the digital system clock.
[0003] Figure 1 This is a commonly used ring oscillator circuit, containing five differential pairs (A1, A2, A3, A4, A5). Each differential pair amplifies the input signal and introduces a phase shift φ, with the total phase shift Φ from all differential pairs. Depending on the circuit's phase-frequency characteristics, the phase shift Φ caused by the differential pairs varies for different input frequencies. Considering only the fundamental harmonic, for a given frequency f0, when the total phase shift Φ is exactly 180°, the cascaded differential pairs form positive feedback, and the ring oscillator will output a signal at frequency f0. The control voltage alters the phase shift characteristics of the differential pairs, changing the frequency f0 at which the phase shift is exactly 180°, thus changing the oscillator's output frequency.
[0004] In commonly used ring oscillators, the mechanism for changing the frequency by controlling the voltage is relatively simple, and the frequency conversion method is affected by the parasitic parameters of the components themselves, resulting in a limited adjustable frequency range. Furthermore, the phase-frequency characteristics of the differential pair are greatly affected by device fabrication, power supply voltage, and temperature, which limits the usable output frequency range of voltage-controlled oscillators in practical engineering. The output range of the oscillator directly affects the frequency range of the phase-locked loop (PLL), which further impacts the PLL's frequency adaptability, practicality, and applicability within the system. Summary of the Invention
[0005] The purpose of this invention is to provide a self-adjusting ring oscillator for phase-locked loops to solve the problems in the prior art.
[0006] To solve the above-mentioned technical problems, the present invention provides a self-adjusting ring oscillator for a phase-locked loop, comprising:
[0007] The control voltage sampling unit requires the oscillator control voltage generated by the phase-locked loop as input to realize the automatic frequency range switching function;
[0008] A gear counter, connected to the control voltage sampling unit, is used to record the current frequency gear and generate a gear control signal;
[0009] A multi-position differential pair is connected to a position counter. The multi-position differential pair requires the oscillator control voltage of the phase-locked loop as input and receives the position control signal sent by the position counter to generate clock signals of various frequencies.
[0010] In one embodiment, the multi-stage differential pair includes: three N-type MOSFETs, two resistors, and a frequency-modulated capacitor bank; the three N-type MOSFETs and two resistors are connected in a simple differential pair form, with two N-type MOSFETs as input differential pair transistors, and the output stage is connected to the frequency-modulated capacitor bank, which consists of a switched capacitor array and varactor diodes. The switched capacitor array includes several sets of fixed capacitors connected in series with the N-type MOSFETs to form a switched capacitor bank.
[0011] In one embodiment, the control voltage sampling unit includes: a first comparator to a fourth comparator, an AND gate, an OR gate, a delay chain, a first NMOS transistor, a first PMOS transistor, and a fixed capacitor;
[0012] The negative input of the first comparator, the positive input of the second comparator, and the positive input of the fourth comparator are all connected to the control voltage. The positive input of the first comparator is connected to the high voltage threshold, the negative input of the second comparator is connected to the low voltage threshold, and the negative input of the fourth comparator is connected to VDD / 2. The outputs of the first and second comparators are respectively connected to the two inputs of an AND gate. The output of the AND gate is simultaneously connected to the gate of the first PMOS transistor and the first input of an OR gate. The second input of the OR gate is connected to the output of the third comparator. The output of the AND gate is connected to the gate of the first NMOS transistor through a delay. The source of the first PMOS transistor is connected to VDD, and the source of the first NMOS transistor is grounded. The drains of the first PMOS transistor and the drain of the first NMOS transistor are both connected to the positive input of the third comparator, and the negative input of the third comparator is connected to the high voltage threshold. The first end of the fixed capacitor is connected to the positive input of the third comparator, and the second end is grounded.
[0013] The first comparator, the second comparator, and the AND gate constitute a trigger judgment structure; the first PMOS transistor, the first NMOS transistor, and the fixed capacitor constitute a charging and discharging structure; the third comparator, the OR gate, and the delay chain constitute a pulse generation structure; and the fourth comparator serves as a carry / borrow judgment structure, outputting a carry / borrow judgment signal.
[0014] In one embodiment, when the control voltage is higher than the high voltage threshold or lower than the low voltage threshold, the first PMOS transistor is turned on, the fixed capacitor begins to charge, and after a charging time tc, the voltage of the fixed capacitor reaches the threshold, the output is pulled high, and after a very short holding time, the first NMOS transistor is turned on, the fixed capacitor discharges rapidly, and the output returns to the low level, forming a short pulse.
[0015] After a short pulse is generated, if the control voltage remains above the high voltage threshold or below the low voltage threshold, the first PMOS transistor continues to slowly charge the fixed capacitor. After the same charging time, the control voltage sampling unit generates the next short pulse and enters the next cycle. If the control voltage rises to the high voltage threshold or falls to the low voltage threshold, the first NMOS transistor quickly discharges the fixed capacitor. The control voltage then rises above the high voltage threshold or falls below the low voltage threshold again, maintaining the judgment time t of the control voltage sampling unit. sw Before the specified time, the control voltage sampling unit no longer generates short pulses.
[0016] In one embodiment, the gear counter includes an n-bit up / down counter and an overflow prevention logic unit embedded therein; the two input signals of the n-bit up / down counter are a short pulse trigger signal and a carry / remove signal, and the output is a gear control signal V. SW <n:1>The number of bits in the n-bit up / down counter is the same as the number of bits in the frequency range of the multi-range differential pair.
[0017] In one embodiment, when the gear counter receives a short pulse trigger signal generated by the control voltage sampling unit, and the carry / reload signal is 1, V SW <n:1>The binary value is incremented by 1; when a short pulse trigger signal is received from the control voltage sampling unit, and the carry / borrow signal is 0, V SW <n:1>Subtract 1 from the binary value;
[0018] The function of the anti-overflow logic unit is to ensure that even when the gear counter is already at its highest position, it will still receive a short pulse trigger signal from the control voltage sampling unit, and the carry / reload signal is 1. SW <n:1>The binary value will not change; similarly, when the gear counter is already at its lowest bit, even if it receives another short pulse trigger signal from the control voltage sampling unit, and the carry / reload signal is 0, V SW <n:1>The binary value will not change.
[0019] This invention provides a self-tuning ring oscillator for phase-locked loops. Traditional differential pair units are replaced with multi-stage differential pairs. By incorporating a switchable capacitor array, the multi-stage differential pairs can achieve wide frequency coverage through the switched capacitor array and precise output frequency adjustment by changing the varactor tube capacitance through control voltage. Furthermore, a self-tuning structure consisting of a control voltage sampling unit and a stage counter is added. This structure can automatically adjust the frequency stage for different process angles, temperatures, power supply voltage conditions, and frequency requirements, avoiding the use of additional external control signals and further improving the practicality of the ring oscillator. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of a traditional ring oscillator.
[0021] Figure 2 This is a schematic diagram of the self-adjusting ring oscillator provided by the present invention.
[0022] Figure 3 This is a schematic diagram of the structure of a multi-level differential pair unit.
[0023] Figure 4 This is a schematic diagram of the control voltage sampling unit.
[0024] Figure 5 This is a schematic diagram of the gear counter.
[0025] Figure 6 This is a schematic diagram of the frequency range of each setting on a self-adjusting ring oscillator.
[0026] Figure 7 This is a schematic diagram of the waveforms of the oscillator during the adjustment process. Detailed Implementation
[0027] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of a self-tuning ring oscillator for a phase-locked loop (PLL) according to the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0028] This invention provides a self-tuning ring oscillator for a phase-locked loop (PLL), comprising a multi-stage differential pair (DP1, DP2, DP3, DP4, DP5), a control voltage sampling unit, and a stage counter. The control voltage sampling unit requires the oscillator control voltage V generated by the PLL. ctrl As input, it is used to realize the automatic frequency range switching function; the range counter is connected to the control voltage sampling unit and the multi-range differential pair to record the current frequency range and send the range control signal to the multi-range differential pair; the multi-range differential pair is connected to the range counter and requires the oscillator control voltage V of the phase-locked loop. ctrl As input, it is used to generate clock signals at various frequencies.
[0029] like Figure 2 As shown, the control voltage V ctrl Generated by the phase-locked loop feedback loop, it is input to differential pairs DP1, DP2, DP3, DP4, and DP5, and simultaneously input to the control voltage sampling unit. After passing through the control voltage sampling unit and the gear counter, it forms a binary gear control signal V. SW <n:1>Control voltage V ctrl and gear control signal V SW <n:1>Both functions change the phase frequency characteristics of the differential pair, thereby altering the output frequency of the oscillator. Their difference lies in the control voltage V. ctrl This is a traditional frequency control method that can achieve precise frequency adjustment, but it is limited by the performance limitations of the varactor tube, and changes in temperature, power supply voltage, and process angle can lead to a smaller usable frequency range. The gear control signal V... SW <n:1>By using a switched capacitor array, the limitation of the range of varactor tube capacitance can be overcome, enabling automatic frequency adjustment over a wider range, allowing the oscillator to output a wider frequency range under various operating conditions.
[0030] The circuit structure of a multi-level differential pair is as follows: Figure 3 As shown, the output frequency of the oscillator can be changed by synchronously altering the equivalent capacitance value of the frequency-modulated capacitor bank C in each differential pair. The frequency-modulated capacitor bank includes a switched capacitor array and a varactor transistor C. V The switched capacitor array consists of fixed capacitors C1, C2, ..., C n It consists of MOSFETs used for switching. Compared to varactor transistors, switched capacitor arrays have a wider range of capacitance values, and the value of n can be increased or decreased according to actual needs to change the number of capacitors in the capacitor bank, resulting in greater design flexibility. Since the gear switching signal is a binary digital signal, in actual design, the capacitance value of C2 can be twice that of C1, the capacitance value of C3 can be four times that of C1, the capacitance value of C4 can be eight times that of C1, and so on. This allows the equivalent capacitance value contributed by the switched capacitor array to change with the gear control signal V. SW <n:1>It changes with the magnitude of the value.
[0031] The circuit structure of the control voltage sampling unit is as follows: Figure 4 As shown, the circuit consists of comparators (COMP1, COMP2, COMP3, COMP4), MOSFETs (MP1, MN1) for charging and discharging, and a fixed capacitor C for timing. T Composition. By adjusting the dimensions of MN1 and MP1 respectively, C can be controlled separately. T The charging and discharging speeds, where the discharging speed must be much greater than the charging speed. In a typical type II phase-locked loop, when the multi-stage differential pair is centered, the varactor C... V When the adjustment range is insufficient to make the output frequency reach the target frequency, ideally, due to the feedback characteristics of the phase-locked loop, the control voltage V... ctrl It will remain at 0 or VDD. Comparators COMP1 and COMP2 can be used to determine whether the phase-locked loop is in this operating state. When the control voltage V ctrl Above the high voltage threshold (V high or below the low voltage threshold (V) low When ), charging tube MP1 is turned on, and fixed capacitor C T Charging begins, and after a certain charging time tc, the fixed capacitor C... T When the voltage reaches the threshold, the output is pulled high. After a very short holding time, the discharge tube MN1 is turned on, and the fixed capacitor C... T A rapid discharge returns the output to a low level, thus creating a short pulse. After the short pulse is formed, if the control voltage V... ctrl Still higher than V high or below V low Then the charging tube MP1 will continue to be the fixed capacitor C. T Slow charging; after the same charging time, the control voltage sampling unit generates the next short pulse and enters the next cycle. If the control voltage V... ctrl Rise or fall to V high and V low Between these points, the discharge tube MN1 quickly discharges the fixed capacitor C. T Discharge, under control voltage V ctrl Upgraded to V again high Above or down to V low The following maintains the judgment time t of the control voltage sampling unit. sw Before the specified time, the control voltage sampling unit no longer generates short pulses. The control voltage is maintained at V. high The above or V low In the following case, assuming the duration of the short pulse is negligible, each pulse held for t... sw A short pulse is generated for each time interval. If the pulse falls out of the interval and then re-enters, the timing t must be reset. sw That's when short pulses are generated.
[0032] like Figure 5 As shown, the gear counter is actually a rising-edge triggered, up-and-down counter. The output array of the counter is the gear control signal V. SW <n:1>When a short pulse trigger signal is received from the control voltage sampling unit, and the carry / borrow signal is 1, V SW <n:1>The binary value is incremented by 1; when a short pulse trigger signal is received from the control voltage sampling unit, and the carry / borrow signal is 0, V SW <n:1>The binary value is decremented by 1. Based on a traditional up / down counter, an anti-overflow logic unit has been added to meet practical needs. This ensures that even when the counter is already at its highest bit, it will not overflow if it receives a short pulse trigger signal from the control voltage sampling unit again, and the carry / borrow signal is 1. SW <n:1>The binary value will not change. Similarly, when the counter is already at its least significant bit, even if it receives another short pulse trigger signal from the control voltage sampling unit, and the carry / borrow signal is 0, V SW <n:1>The binary value will not change. Furthermore, the counter has a reset signal input interface.
[0033] In summary, when the frequency range is set appropriately, the self-adjusting ring oscillator of this invention, operating within the phase-locked loop, will attempt to adjust the frequency range to a suitable level if it is not at the required range, provided that the frequency range setting is appropriate, provided that the frequency range is not set correctly. During this process, without considering signal rise time and device delay, V... SW <n:1>The binary value will be incremented or decremented by 1 until the appropriate level is reached. Then, V... ctrl The value automatically decreases or increases to V due to the feedback loop of the phase-locked loop. low and V high Between these points, the gear shift stops and the phase-locked loop gradually locks in place.
[0034] To aid in illustrating the design and operation of the self-tuning ring oscillator, simplified diagrams are used. Figure 6 When n is 3, the typical frequency range for each gear is: Figure 7 For n to be 3 and the target gear signal V SW When <1:0> is 101, the waveforms of each signal during the phase-locked loop (PLL) locking process from the start to the final lock are shown. It should be noted that... Figure 5 and Figure 6 Both figures are presented in a very simplified form and use non-precise scales. These two figures are not precise simulation curves, but only approximate curves, and are only used to conveniently and clearly illustrate the purpose of the embodiments of the present invention.
[0035] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A self-adjusting ring oscillator for a phase-locked loop, characterized in that, include: The control voltage sampling unit requires the oscillator control voltage generated by the phase-locked loop as input to realize the automatic frequency range switching function; A gear counter, connected to the control voltage sampling unit, is used to record the current frequency gear and generate a gear control signal; A multi-position differential pair is connected to a position counter. The multi-position differential pair requires the oscillator control voltage of the phase-locked loop as input and receives the position control signal sent by the position counter to generate clock signals of various frequencies.
2. The self-adjusting ring oscillator for a phase-locked loop as described in claim 1, characterized in that, The multi-stage differential pair includes: three N-type MOSFETs, two resistors, and a frequency-modulated capacitor bank; the three N-type MOSFETs and two resistors are connected in a simple differential pair form, with two N-type MOSFETs as the input differential pair transistors, and the output stage is connected to the frequency-modulated capacitor bank, which consists of a switched capacitor array and varactor diodes. The switched capacitor array includes several sets of fixed capacitors connected in series with the N-type MOSFETs to form a switched capacitor bank.
3. The self-adjusting ring oscillator for a phase-locked loop as described in claim 1, characterized in that, The control voltage sampling unit includes: a first comparator to a fourth comparator, an AND gate, an OR gate, a delay chain, a first NMOS transistor, a first PMOS transistor, and a fixed capacitor; The negative input of the first comparator, the positive input of the second comparator, and the positive input of the fourth comparator are all connected to the control voltage. The positive input of the first comparator is connected to the high voltage threshold, the negative input of the second comparator is connected to the low voltage threshold, and the negative input of the fourth comparator is connected to VDD / 2. The outputs of the first and second comparators are respectively connected to the two inputs of an AND gate. The output of the AND gate is simultaneously connected to the gate of the first PMOS transistor and the first input of an OR gate. The second input of the OR gate is connected to the output of the third comparator. The output of the AND gate is connected to the gate of the first NMOS transistor through a delay. The source of the first PMOS transistor is connected to VDD, and the source of the first NMOS transistor is grounded. The drains of the first PMOS transistor and the drain of the first NMOS transistor are both connected to the positive input of the third comparator, and the negative input of the third comparator is connected to the high voltage threshold. The first end of the fixed capacitor is connected to the positive input of the third comparator, and the second end is grounded. The first comparator, the second comparator, and the AND gate constitute a trigger judgment structure; the first PMOS transistor, the first NMOS transistor, and the fixed capacitor constitute a charging and discharging structure; the third comparator, the OR gate, and the delay chain constitute a pulse generation structure; and the fourth comparator serves as a carry / borrow judgment structure, outputting a carry / borrow judgment signal.
4. The self-adjusting ring oscillator for a phase-locked loop as described in claim 3, characterized in that, When the control voltage is higher than the high voltage threshold or lower than the low voltage threshold, the first PMOS transistor is turned on, and the fixed capacitor begins to charge. After the charging time tc, the voltage of the fixed capacitor reaches the threshold, and the output is pulled high. After a very short holding time, the first NMOS transistor is turned on, the fixed capacitor discharges rapidly, and the output returns to the low level, forming a short pulse. After a short pulse is generated, if the control voltage remains above the high voltage threshold or below the low voltage threshold, the first PMOS transistor continues to slowly charge the fixed capacitor. After the same charging time, the control voltage sampling unit generates the next short pulse and enters the next cycle. If the control voltage rises to the high voltage threshold or falls to the low voltage threshold, the first NMOS transistor quickly discharges the fixed capacitor. The control voltage then rises above the high voltage threshold or falls below the low voltage threshold again, maintaining the judgment time t of the control voltage sampling unit. sw Before the specified time, the control voltage sampling unit no longer generates short pulses.
5. The self-adjusting ring oscillator for a phase-locked loop as described in claim 1, characterized in that, The gear counter includes an n-bit up / down counter and an embedded overflow prevention logic unit; the two input signals of the n-bit up / down counter are a short pulse trigger signal and a carry / remove signal, and the output is a gear control signal V. SW <n:1> The number of bits in the n-bit up / down counter is the same as the number of bits in the frequency range of the multi-range differential pair.< / n:1> 6. The self-adjusting ring oscillator for a phase-locked loop as described in claim 5, characterized in that, When the gear counter receives a short pulse trigger signal generated by the control voltage sampling unit, and the carry / reload signal is 1, V SW <n:1>The binary value is incremented by 1; when a short pulse trigger signal is received from the control voltage sampling unit, and the carry / borrow signal is 0, V SW <n:1> Subtract 1 from the binary value;< / n:1> The function of the anti-overflow logic unit is to ensure that even when the gear counter is already at its highest position, it will still receive a short pulse trigger signal from the control voltage sampling unit, and the carry / reload signal is 1. SW <n:1> The binary value will not change;< / n:1> Similarly, when the gear counter is already at its lowest position, even if it receives another short pulse trigger signal from the control voltage sampling unit, and the carry / reload signal is 0, V SW <n:1> The binary value will not change.< / n:1>