Low-delay FFT multiplexing pulse compression method

Abstract

The invention discloses a low-delay FFT (Fast Fourier Transform) multiplexing pulse compression method, which comprises the following steps of: sending an input sequence into an FFT core in parallel, and inputting the input sequence into P paths of FFT cores in parallel to obtain an out-of-order frequency domain sequence; acting the out-of-order frequency domain sequence with a matched filtering coefficient H (k) to obtain a complex multiplication result; processing the complex multiplication result through the same operation core and outputting a sequential time domain compression result; and one of DIT and DIF is selected for front-end extraction and rear-end extraction, and the DIT and the DIF are complementary in pairs, so that the bit sorting influence in the whole operation chain is self-counteracted, and data rearrangement cache during operation is omitted. According to the low-delay FFT multiplexing pulse compression method provided by the invention, data rearrangement cache is eliminated, FFT kernel drop resources are multiplexed, and high-sampling stream data real-time pulse compression is realized.

Description

Technical Field

[0001] This invention belongs to the field of radar signal processing technology, specifically relating to a low-latency FFT multiplexing pulse compression method. Background Technology

[0002] Pulse compression technology, a core component of modern radar systems, effectively resolves the contradiction between radar range and range resolution by transmitting wideband signals and compressing them at the receiver. This contradiction stems from a fundamental principle of radar theory: range resolution depends on signal bandwidth, while detection range depends on signal duration. The duration-bandwidth product of a simple pulse signal is approximately 1, leading to a decrease in resolution as the detection range increases, and vice versa. Pulse compression technology transmits signals with a large duration-bandwidth product (such as linear frequency modulated signals) and uses a matched filter at the receiver to process the echo signal, compressing the wide pulse into a narrow pulse, thus simultaneously achieving the advantages of long detection range and high resolution.

[0003] Pulse compression technology achieves high range resolution by processing wide-pulse signals. Its core computational load primarily comes from frequency domain processing (such as Fast Fourier Transform (FFT) / Inverse IFFT) and filtering operations. With modern radar systems evolving towards multi-functionality and high performance, the amount of data processed by signals has increased dramatically, leading to ever-increasing demands on processing speed and real-time performance. For large-time-bandwidth product signals, these operations involve enormous computational loads, especially in scenarios like autonomous driving where extremely high real-time performance is required. The time a processor spends processing data should be shorter than the time it spends collecting data to ensure the system can perceive the environment and respond in real time.

[0004] As radar systems evolve towards higher resolution and real-time performance, traditional serial or single-platform processing architectures are no longer sufficient to meet the demands for low latency and high throughput. Therefore, designing a low-latency, real-time pulse compression parallel computing architecture has significant theoretical and technical value. Summary of the Invention

[0005] This invention provides a low-latency FFT multiplexing pulse compression method to solve the technical problem of insufficient accuracy of traditional early warning methods mentioned above. The specific technical solution is as follows:

[0006] A low-latency FFT multiplexing pulse compression method includes the following steps:

[0007] The input sequence is fed into the FFT kernel in P-way parallel mode to obtain an out-of-order frequency domain sequence.

[0008] The disordered frequency domain sequence is applied to the matched filter coefficients H(k) to obtain a complex multiplication result;

[0009] The results of the complex multiplication are processed by the same kernel and the sequential time-domain compressed results are output.

[0010] By using either DIT or DIF for front-end extraction and back-end extraction respectively, and pairing them to complement each other, the bit sorting effect in the overall operation chain cancels out, thus saving the time of runtime data rearrangement caching.

[0011] Furthermore, the bit sorting module in the data path is moved to the IFFT input, so that the FFT output and IFFT input share the same buffer for the two sorting operations. During runtime, only one data side re-sorting is required to complete pulse compression under the DIT-DIF pairwise process.

[0012] Furthermore, the matched filter coefficients H(k) are pre-sorted offline and then stored in a fixed manner according to the same rule as the out-of-order address of the front-end FFT output. The rearranged coefficients are used directly in the multiplication stage, thereby eliminating the remaining data side rearrangement and completely eliminating the sorting unit in the data path.

[0013] Furthermore, the same operational core is an FFT core, which completes the inverse transformation without adding an IFFT hard core by first swapping the real and imaginary parts of the complex number, then performing the FFT, and then swapping the real and imaginary parts again.

[0014] Furthermore, after the second swap of the real and imaginary parts, the result is multiplied by a scaling factor of 1 / N. This multiplication is performed by directly truncating the low-order parts. This can be achieved without an additional multiplier.

[0015] Furthermore, the DIT and DIF operations share the same rotation factor ROM to save on complex coefficient storage.

[0016] Furthermore, when the parallelism P = 2 p And the total number of points in the input sequence N = 2 l When (l>p), first group the P-path data naturally in the form of DIT, and continue the radix-2 butterfly recursion within each group.

[0017] Furthermore, when P>2, the parallel basis P is decomposed into P / 2 basis 2 subgroups, and the process is still executed using the DIT-DIF complementary process, with no change in hardware resources.

[0018] Furthermore, the FFT core adopts a synthesizable radix-2 fixed-point FFT IP core within an FPGA or ASIC, and is adapted through parallelism P when the data sampling rate is higher than the clock frequency.

[0019] Furthermore, the input sequence is high-speed ADC stream data, with a processing delay of less than N / P clock cycles, enabling real-time pulse compression.

[0020] The low-latency FFT multiplexing pulse compression method provided by this invention eliminates data rearrangement buffering, reuses FFT core resources, and realizes real-time pulse compression of high-sampling stream data.

[0021] When using FFT / IFFT algorithms to reduce the computational complexity of DFT / IDFT, bit sorting is introduced during stream processing. The low-latency FFT multiplexing pulse compression method provided in this invention utilizes a design method combining DIT and DIF, which eliminates the time delay and increased storage introduced by bit sorting, reduces the computational delay of the pulse compression algorithm, and reduces the necessary storage area.

[0022] The low-latency FFT multiplexing pulse compression method provided by this invention further parallelizes the computing architecture. When implemented in parallel, the FFT IP core is used instead of the IFFT computing core, which requires the development of only one operator, reducing the difficulty of operator development. At the same time, it can share the twitch factor with the FFT operation, which can save the cache size required for the twitch factor and further adapt to high-burst parallel data scenarios. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of a frequency domain pulse compression method based on DFT;

[0025] Figure 2 This is a schematic diagram of a frequency domain pulse compression method based on FFT;

[0026] Figure 3 This is a schematic diagram of a DIT-FFT butterfly operation;

[0027] Figure 4 This is a schematic diagram of the DIT-FFT operation unit;

[0028] Figure 5 This is a schematic diagram of a DIF-FFT butterfly operation;

[0029] Figure 6 This is a schematic diagram of the DIF-FFT operation unit;

[0030] Figure 7 It is a block diagram that decomposes an N-point DFT into two N / 2 DFT combination diagrams;

[0031] Figure 8This is a schematic diagram of IFFT computation based on an FFT processing kernel;

[0032] Figure 9 This is a schematic diagram of the low-latency FFT multiplexing pulse compression method of this application;

[0033] Figure 10 This is a schematic diagram of another embodiment of the low-latency FFT multiplexing pulse compression method of this application;

[0034] Figure 11 This is a schematic diagram of another embodiment of the low-latency FFT multiplexing pulse compression method of this application;

[0035] Figure 12 This is a schematic diagram of the parallel mode of the low-latency FFT multiplexing pulse compression method of this application. Detailed Implementation

[0036] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0037] like Figure 1 As shown, pulse compression is actually an application of matched filtering. Based on knowledge of digital signal processing, we know that filtering is the input signal... and filter To reduce computational resources, convolution calculations can be performed in the frequency domain. Input signal The discrete Fourier transform (DFT) of the sum is: The calculation formula is as follows:

[0038]

[0039] Where N is the number of signal sampling points.

[0040] The Discrete Fourier Transform (DFT) of filter h(n) is H(k), which is the transfer function of the filter, and its calculation formula is:

[0041]

[0042] And the output signal s o (n) is S i The product of H(k) and H(k) is then used to calculate the result of the inverse discrete Fourier transform (IDFT), and the calculation formula is as follows:

[0043]

[0044] In practical calculations, to reduce computational complexity and increase project feasibility, the Fast Fourier Transform (FFT) with a symmetric structure is generally chosen instead of the Discrete Fourier Transform (DFT). Its computational flowchart and implementation process are shown in Figure 2. This further reduces algorithm complexity, thereby reducing the consumption of hardware resources such as DSPs and subtractors. However, while reducing algorithm complexity, it also introduces an additional cost: after the data undergoes the Fast Discrete Fourier Transform calculation, the data sequence is rearranged in a regular manner.

[0045] FFT algorithms can be divided into two types: Decimation in Time (DIT) and Decimation in Frequency (DIF). Furthermore, FFT algorithms can form different basis sets based on different data groups. This invention provides a derivation of a 2-based FFT algorithm and, based on the characteristics of the algorithm structure, designs a more resource-efficient hardware architecture.

[0046] For the DIT-FFT algorithm, if we select based on time parity, we pre-determine the number of points in the sequence x(n). , where l is a positive integer. Divide the sequence x(n) into the following two groups according to the parity of the index n:

[0047]

[0048] Then its N-point radix-2 time-decimation discrete Fourier transform is:

[0049]

[0050] in The rotation factor of the original signal sequence. It is the rotation factor of the new sequence after parity splitting of the original signal sequence.

[0051] For ease of expression and subsequent formula simplification, let X1(k) and X2(k) be defined as the N / 2-point discrete Fourier transforms of x1(r) and x2(r), respectively. Therefore, X(k) can be further expressed as:

[0052]

[0053] Based on the three properties of the rotation factor, we can further derive the formulas for the discrete Fourier transforms of X(k) at the first N / 2 points and the last N / 2 points:

[0054]

[0055] As can be seen from the above formula, due to this symmetric property, it is only necessary to calculate the interval. The discrete Fourier transform values ​​of all X1(k) and X2(k) can be obtained by simple multiplication-addition / subtraction to obtain the discrete Fourier transform of all X(k).

[0056] Figure 3 is a basic schematic diagram of the DIT-FFT butterfly operation. Subsequent more complex butterfly operation relationships are all completed by iterating or topologically constructing based on the basic butterfly operation shown in this figure. Figure 4 To complete a basic butterfly computation, the diagram shows the hardware resources required for a basic DIT-FFT disc operation unit, which requires one multiplier and two adders / subtractors.

[0057] For the DIF-FFT algorithm, if we use the frequency-based sampling method, we still pre-determine the number of points in the sequence x(n). , where l is a positive integer. We first divide the sequence x(n) into two parts according to the order of n, and the derivation structure is as follows:

[0058]

[0059] According to the above formula, sampling by frequency means dividing the sequence X(k) into two groups based on the parity of the index k: one group is k=2r, and the other group is k=2r+1. For ease of expression, let:

[0060]

[0061] Then the discrete Fourier transform of its N-point radix-2 frequency decimation method is:

[0062]

[0063] According to the above formula, it can be seen that the radix-2 frequency decimation method can also transform an N-point Discrete Fourier Transform into two N / 2-point Discrete Fourier Transforms. However, unlike the time decimation method, it is necessary to divide the sequence x(n) into two parts, the first N / 2 points and the last N / 2 points, and then perform the operation according to the butterfly rule shown in Figure 5. Similar to the time decimation method, the hardware resources required for the frequency decimation method to complete a basic butterfly operation are shown in Figure 6. Therefore, a basic DIF-FFT butterfly operation unit also only requires one multiplier and two adders / subtractors.

[0064] Although the two butterfly algorithms mentioned above can reduce the computational complexity of complex multiplication and addition in Discrete Fourier Transform from... Reduce to However, this also brings about the problem shown in Figure 7, namely the data sequence problem. Figure 7(a) is a schematic diagram of the sequence of the decimation-time method (DIT), and Figure 7(b) is a schematic diagram of the sequence of the decimation-frequency method (DIF). Both figures use N=8 as an example. In particular, if the DFT of N / 2 points in the figure is infinitely divided and conquered... Figure 3 or Figure 5 The basic unit shown is the FFT algorithm. In stream processing architectures, additional data sequence sorting requires additional cache space.

[0065] In pulse compression calculations, two operators, FFT and IFFT, are used. These two operators have similar structures and their processing procedures are largely the same. The formulas for FFT and IFFT are as follows:

[0066]

[0067]

[0068] For ease of explanation, unless otherwise specified, the ranges of n and k in subsequent occurrences are all within [the specified range]. And all are integers.

[0069] In the hardware implementation, the calculation is simplified by exchanging the real and imaginary parts. For ease of expression and derivation in the following text, we give the following definition. Expressing the exchange of real and imaginary parts.

[0070] Performing two Swap_IQ operations on both sides of x(n), keeping the left side unchanged, and expanding the right side once with Swap_IQ, the simplified result is as follows:

[0071]

[0072] Observing the simplified result of the above equation and comparing it with the aforementioned FFT formula, we find that it contains the Swap_IQ[X(k)] Discrete Fourier Transform, thus we have:

[0073]

[0074] The above formula shows that after swapping the real and imaginary parts of the sequence X(k), performing an N-point FFT, and then swapping the real and imaginary parts of the result and multiplying it by the scaling factor 1 / N, the result of performing an IFFT on the sequence X(k) can also be obtained. The calculation flowchart is shown in Figure 8.

[0075] Therefore, it is evident that using FFT operators to perform IFFT operations can save hardware resources consumed in calculating conjugates. This is because, for the hardware system, swapping the real and imaginary parts of the sequence incurs no computational or storage overhead, and the subsequent division by N can also be performed by truncation.

[0076] Based on the preceding analysis and discussion, we can draw a basic conclusion: if FFT is used instead of DFT to reduce computational complexity, a new problem will be introduced, namely the sequence sorting problem.

[0077] In stream processing architectures, if the processed data sequence is reordered due to computation, additional buffering is needed to correct the sequence. Only after correction can the data enter subsequent computation modules to obtain the correct results, as shown in Figure 2. However, based on the previous derivation and Figure 7, the bit sorting operation can be placed after FFT / IFFT or before FFT / IFFT during the entire computation process. However, this requires modifying the corresponding extraction strategy for FFT / IFFT; whether using DIT or DIF, the computational resources used remain unchanged.

[0078] Based on the above analysis, this application proposes a low-latency FFT multiplexing pulse compression method, comprising the following steps:

[0079] S1: The input sequence is fed into the FFT kernel in P-way parallel mode to obtain an out-of-order frequency domain sequence;

[0080] S2: The disordered frequency domain sequence is applied to the matched filter coefficients H(k) to obtain a complex multiplication result;

[0081] S3: The complex multiplication result is processed by the same operation kernel and the sequential time-domain compressed result is output;

[0082] In this method, DIT and DIF are selected for front-end extraction and back-end extraction respectively, and they are paired and complementary, so that the bit sorting effect in the overall operation chain cancels out, thereby saving the runtime data rearrangement cache.

[0083] As a preferred implementation, the bit sorting module in the data path is moved to the IFFT input, so that the FFT output and IFFT input share the same buffer for both sorting. During runtime, only one data-side resort is required to complete pulse compression in the DIT-DIF pairwise process. For example... Figure 9 As shown, by reasonably selecting the extraction strategy and adjusting the bit sorting operation in the shaded diagram to before IFFT, the two bit sorting modules can cancel each other out. This not only saves the memory consumed by two position sorting operations but also reduces the latency of the stream processing architecture without adding extra computing resources.

[0084] As a preferred implementation, the matched filter coefficients H(k) are pre-sorted offline according to the same rules as the out-of-order addresses of the front-end FFT output and then stored in a fixed manner. The rearranged coefficients are directly used in the complex multiplication stage, thereby eliminating the remaining data-side rearrangement and completely eliminating sorting units within the data path. For example... Figure 10 As shown, complex multiplication is performed on the sorted filter coefficients and the data sequence. Since the filter coefficients are calculated offline and stored in the on-chip storage space, the sorting of positions does not result in additional memory consumption.

[0085] As a preferred implementation, using the same computational core as the FFT core, the inverse transform is completed without increasing the IFFT hard core by first swapping the real and imaginary parts of the complex number (Swap_IQ), then performing the FFT, and then swapping the real and imaginary parts again. Further, after the second swap of the real and imaginary parts, the result is multiplied by a scaling factor 1 / N. The multiplication is achieved by directly truncating the low-order parts. Bitwise implementation eliminates the need for an additional multiplier. Furthermore, the DIT and DIF operations share the same twitch factor ROM to save on complex coefficient storage.

[0086] Specifically, such as Figure 11 As shown, the commutation method proposed in this invention can perform IFFT operations using FFT operators without increasing hardware resources. This method unifies paired FFT and IFFT operators into operations using only the FFT operator, further reducing the difficulty of hardware operator development. Furthermore, the 1 / N operation in the shaded box on the right side of Figure 11 does not require increasing the number of multipliers, because the number of points compressed in each pulse is a power of 2. Multiplying the result by 1 / N is equivalent to truncating the lower log2 N bits of the result.

[0087] In addition, in the computational flowchart shown in Figure 11, both the left and right shaded areas contain FFT computational flowcharts, but the difference lies in the decimation strategy used for the FFT in the two flowcharts. If DIT-FFT is selected on the left, then only DIF-FFT can be selected on the right, and vice versa. The specific selection can be based on the input signal s. i The rules for (n) are determined.

[0088] To optimize the overall architecture, the FFT operation architectures on both sides can share the rotation factor, which will further save memory, especially in the case of parallel computing where resource savings are more significant.

[0089] As a preferred implementation, when the parallelism And the total number of points in the input sequence N = 2 lWhen (l>p), the P-way data is first naturally grouped in DIT form, and radix-2 butterfly recursion continues within each group. When P>2, the parallel radix P is decomposed into P / 2 radix-2 subgroups, and the DIT-DIF complementary process is still executed, with no change in hardware resources.

[0090] In FPGA or ASIC platforms, when the sampling rate of an ADC is particularly high or the data volume is very large, and the main clock frequency cannot handle the data in real time, hardware resources are typically used to trade off speed. This application proposes the concept of parallelism P, which refers to the number of data points that can be processed in each clock cycle. p is the parallel dimension, and the relationship between the parallel dimension p and the parallelism P is as follows: In radix-2 FFT operations, the number of points to be processed must be a power of 2. To facilitate the design of parallel architectures, the number of computation points can also be expressed as... ,Right now Where l>p. Typically, in high-speed ADCs, the number of parallel paths is generally a power of 2 due to device architecture design, making this derivation very suitable for systems where the data source is a high-speed ADC. In such acquisition systems, P data points can be acquired per sampling cycle of the ADC clock. In this application, the input sequence is high-speed ADC stream data, with a processing delay of less than N / P clock cycles, achieving real-time pulse compression.

[0091] Therefore, it can be seen that the data source naturally groups the FFT points according to the DIT form based on the parallelism P. Figure 12 The parallel low-latency frequency domain pulse compression method is a specific approach to parallel pulse compression. The block diagram uses P=2 as an example. It can be seen that the input data x... i (2n) and x i (2n+1) represents the number of samples drawn into the system according to time. The shaded area on the left side of the diagram represents the number of samples drawn according to time. Figure 3 and Figure 4 The recurrence relation shown completes the DIT-FFT operation; the shaded area on the right side of the figure represents the operation according to... Figure 5 and Figure 6 The recurrence relation shown completes the DIF-FFT operation. Furthermore, disregarding the time decimation of parallel paths, the FFT input data x at N / 2 points in each single path... i (2n) or x i (2n+1) is continuous in time. A single-path decimation method is used, and after the operation, the data sequence is rearranged due to the butterfly operation. The subsequent N / 2-point DIT-FFT will restore the sequence to its original form. The small box in the shaded area on the right uses the FFT kernel to perform the IFFT operation. This has two advantages: first, only one operator needs to be developed, reducing the difficulty of operator development; second, it can share the twitch factor W with the FFT operation on the left.N (The superscripts n and k are sequences from 0 to N / 2-1), which can save the cache size required for N / 2 rotation factors.

[0092] In summary, the above architecture implementation method, in scenarios where the data source is AD, employs time decimation for the parallel FFT (N points) in the left shaded area and frequency decimation for the serial FFT (N / 2 points) on a single path; conversely, it employs frequency decimation for the parallel IFFT (N points) in the right shaded area and time decimation for the serial IFFT (N / 2 points) on a single path. In other streaming data scenarios, the specific method used depends on the data sequence characteristics of the data source. However, the FFT and IFFT used in pairs in the parallel or serial parts must satisfy the condition that one is DIT and the other is DIF. The matched filter H(k) only needs to be sorted and stored offline according to the corresponding operation rules and sorting method (DIT / DIF), without requiring additional storage or computational resources. The computational resources and cache size are the same regardless of the combination used.

[0093] When P is in the form of other integer powers of 2, it can be followed as Figure 12 A serial-to-parallel conversion is performed, meaning the parallel part is derived using the radix P, while the internal serial part is derived using the radix 2. Since P is also an integer power of 2, the parallel radix P can also be decomposed into P / 2 radix 2 forms. The former uses fewer hardware resources, while the latter is more versatile.

[0094] The FFT core uses a synthesizable radix-2 fixed-point FFT IP core within an FPGA or ASIC, with parallelism P adapted to handle data sampling rates higher than the clock frequency. However, the FFT / IFFT IP cores provided by Xilinx do not support computations with data rates exceeding the clock sampling frequency. The parallel pulse compression calculation method proposed in this application can also utilize the IP cores provided by Xilinx. Figure 12 The PE is calculated using FFT(N / 2), which allows for further development based on the official IP core, saving development time in engineering and expanding the functional scope of the computing core.

[0095] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the above embodiments do not limit the present invention in any way, and all technical solutions obtained by equivalent substitution or equivalent transformation fall within the protection scope of the present invention.

Claims

1. A low-latency FFT multiplexing pulse compression method, characterized in that, Includes the following steps: The input sequence is fed into the FFT kernel in P-way parallel mode to obtain an out-of-order frequency domain sequence. The disordered frequency domain sequence is applied to the matched filter coefficients H(k) to obtain a complex multiplication result; The results of the complex multiplication are processed by the same kernel and the sequential time-domain compressed results are output. By using either DIT or DIF for front-end extraction and back-end extraction respectively, and pairing them to complement each other, the bit sorting effect in the overall operation chain cancels out, thus saving the time of runtime data rearrangement caching.

2. The low-latency FFT multiplexing pulse compression method according to claim 1, characterized in that, By shifting the bit sorting module in the data path to the IFFT input, the FFT output and IFFT input share the same buffer for both sorting. During runtime, only one data side re-sorting is required to complete pulse compression in the DIT-DIF pairwise process.

3. The low-latency FFT multiplexing pulse compression method according to claim 1, characterized in that, The matched filter coefficients H(k) are pre-sorted offline and then stored in a fixed manner according to the same rule as the out-of-order address of the front-end FFT output. The rearranged coefficients are used directly in the multiplication stage, thereby eliminating the remaining data side rearrangement and completely eliminating the sorting unit in the data path.

4. The low-latency FFT multiplexing pulse compression method according to claim 1, characterized in that, The same operational core is the FFT core. The inverse transformation is completed without adding an IFFT hard core by first swapping the real and imaginary parts of the complex number, then performing the FFT, and then swapping the real and imaginary parts again.

5. The low-latency FFT multiplexing pulse compression method according to claim 4, characterized in that, After the second exchange of the real and imaginary parts, the result is multiplied by a scaling factor of 1 / N. This multiplication is performed by directly truncating the low-order parts. Bitwise implementation, no additional multiplier required.

6. The low-latency FFT multiplexing pulse compression method according to claim 1, characterized in that, The DIT and DIF operations share the same rotation factor to save storage of complex coefficients.

7. The low-latency FFT multiplexing pulse compression method according to claim 1, characterized in that, Parallelism The total number of points in the input sequence is N = 2. l If l>p, where p is the parallel dimension, first group the P-way data naturally in DIT form, and then continue the radix-2 butterfly recursion within each group.

8. The low-latency FFT multiplexing pulse compression method according to claim 7, characterized in that, When P>2, the parallel basis P is decomposed into P / 2 basis 2 subgroups, and the DIT-DIF complementary process is still executed, with no change in hardware resources.

9. The low-latency FFT multiplexing pulse compression method according to claim 1, characterized in that, The FFT core uses a synthesizable radix-2 fixed-point FFT IP core within an FPGA or ASIC, and is adapted through parallelism P when the data sampling rate is higher than the clock frequency.

10. The low-latency FFT multiplexing pulse compression method according to claim 1, characterized in that, The input sequence is high-speed ADC stream data, with a processing delay of less than N / P clock cycles, enabling real-time pulse compression.

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