Semiconductor device and electronic system including the same

Abstract

Embodiments of the present disclosure provide a semiconductor device and an electronic system including the same. The semiconductor device includes: a substrate; a stacked structure including dielectric patterns and conductive patterns vertically and alternately stacked on the substrate; the source electrode conductive pattern is located on the stacking structure; the upper wire is located between the stacking structure and the source electrode conductive pattern; and a vertical structure penetrating the stack structure and the upper conductive line and electrically connected to the source conductive pattern. A vertical thickness of the upper conductive line is greater than a vertical thickness of each of the conductive patterns. The vertical structure includes: a lower portion penetrating the stack structure; and an upper portion connected to the lower portion and penetrating the upper wire. The minimum horizontal width of the upper portion is larger than the minimum horizontal width of the lower portion.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices and electronic systems including such semiconductor devices. Background Technology

[0002] In electronic systems that require data storage, semiconductor devices capable of storing large amounts of data are needed. Therefore, research has been conducted to increase the data storage capacity of semiconductor devices. For example, as a method to increase the data storage capacity of semiconductor devices, it has been proposed that semiconductor devices include storage cells arranged in three dimensions instead of two dimensions. Summary of the Invention

[0003] Some embodiments of the present invention provide a semiconductor device with improved reliability.

[0004] Some embodiments of the present invention provide an electronic system that includes semiconductor devices with improved reliability.

[0005] The purposes of this invention are not limited to those mentioned above, and those skilled in the art will clearly understand from the following description other purposes not mentioned above.

[0006] According to some embodiments of the present invention, a semiconductor device may include: a substrate; a stacked structure including a plurality of dielectric patterns and a plurality of conductive patterns vertically and alternately stacked on the substrate; a source conductive pattern located on the stacked structure; an upper conductor located between the stacked structure and the source conductive pattern; and a plurality of vertical structures penetrating (i.e., extending into or through) the stacked structure and the upper conductor and electrically connected to the source conductive pattern. The thickness of the upper conductor may be greater than the thickness of each of the conductive patterns. The vertical structure may include: a lower portion penetrating the stacked structure; and an upper portion connected to the lower portion and penetrating the upper conductor. The minimum width of the upper portion may be greater than the minimum width of the lower portion.

[0007] According to some embodiments of the present invention, a semiconductor device may include: a peripheral circuit structure including a substrate, a plurality of peripheral circuits integrated on the substrate, and a plurality of first bonding pads connected to the peripheral circuits; and a cell array structure including a plurality of second bonding pads bonded to the first bonding pads. The cell array structure may include: a stacked structure including a plurality of dielectric patterns and a plurality of conductive patterns stacked vertically and alternately; a source conductive pattern located on the stacked structure; an upper conductor located between the stacked structure and the source conductive pattern; a plurality of vertical structures penetrating the stacked structure and the upper conductor and electrically connected to the source conductive pattern; a plurality of bit lines extending laterally across the stacked structure and connected to the vertical structures; a first interlayer dielectric layer located between the upper conductor and the source conductive pattern; and a second interlayer dielectric layer located between the upper conductor and the stacked structure. The thickness of the upper conductor may be greater than the thickness of each conductive pattern. The vertical structure may include: a lower portion that penetrates the stacked structure; and an upper portion that connects to the lower portion and penetrates the upper conductor. The minimum width of the upper portion may be greater than the minimum width of the lower portion. The upper conductor is configured as the gate electrode of an erase control transistor that causes gate-induced drain leakage (GIDL).

[0008] According to some embodiments of the present invention, an electronic system may include: a semiconductor device including a substrate and a cell array structure located on the substrate; and a controller electrically connected to the semiconductor device via input / output pads and controlling the semiconductor device. The cell array structure may include: a stacked structure including a plurality of dielectric patterns and a plurality of conductive patterns vertically and alternately stacked on the substrate; a plurality of vertical structures penetrating the stacked structure; source conductive patterns located on the stacked structure and connected to the vertical structures; and an upper conductor located between the stacked structure and the source conductive patterns. The thickness of the upper conductor may be greater than the thickness of each of the conductive patterns. The vertical structure may include: a lower portion penetrating the stacked structure; and an upper portion connected to the lower portion and penetrating the upper conductor. The minimum width of the upper portion may be greater than the minimum width of the lower portion. Attached Figure Description

[0009] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, wherein like reference numerals (when used) denote corresponding elements in several views, wherein: Figure 1 This is a simplified schematic diagram illustrating an electronic system including semiconductor devices according to some embodiments of the concept of the present invention; Figure 2 This is a simplified perspective view illustrating an electronic system including semiconductor devices according to some embodiments of the present invention; Figure 3 and Figure 4 This is a simplified schematic cross-sectional view illustrating some embodiments of a semiconductor package according to the present invention; Figure 5 This is a schematic top view illustrating some embodiments of a semiconductor device according to the present invention; Figure 6A and Figure 6B They are respectively along Figure 5 The schematic cross-sectional views taken by lines A-A' and B-B' illustrate semiconductor devices according to some embodiments of the present invention. Figure 7 It shows Figure 6A An enlarged view of section P; and Figures 8 to 18 This is a schematic cross-sectional view illustrating an intermediate process in an example method for manufacturing a semiconductor device according to some embodiments of the present invention. Detailed Implementation

[0010] Some illustrative embodiments of the present invention will now be described with reference to the accompanying drawings.

[0011] Figure 1 This is a simplified schematic diagram illustrating an electronic system including semiconductor devices according to some embodiments of the present invention.

[0012] refer to Figure 1 An electronic system 1000, according to some embodiments of the present invention, may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a storage device including one or more semiconductor devices 1100, or may be an electronic device including a storage device. For example, the electronic system 1000 may be a solid-state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device, each electronic system including one or more semiconductor devices 1100.

[0013] Semiconductor device 1100 may be a non-volatile memory device, such as a NAND flash memory device. Semiconductor device 1100 may include a first structure 1100F and a second structure 1100S located on the first structure 1100F. In some embodiments, the first structure 1100F may be disposed on one side of the second structure 1100S.

[0014] The first structure 1100F can be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S can be a memory cell structure, which includes a bit line BL, a common source line CSL, a word line WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0015] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and upper transistors UT1 and UT2 may vary depending on the embodiment. The number of memory cell transistors MCT may vary depending on the embodiment.

[0016] In some embodiments, upper transistors UT1 and UT2 may include string select transistors, and lower transistors LT1 and LT2 may include ground select transistors. Gate lower lines LL1 and LL2 may be the gate electrodes of lower transistors LT1 and LT2, respectively. Word line WL may be the gate electrode of memory cell transistor MCT, and gate upper lines UL1 and UL2 may be the gate electrodes of upper transistors UT1 and UT2, respectively.

[0017] In some embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series. As may be used herein, the term “connected” (or “connecting”) or similar terms such as “contact” or “contacting” are intended to refer to a physical and / or electrical connection between two or more elements and may include other intermediate elements. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed phases. One or both of the lower erase control transistor LT1 and the upper erase control transistor UT1 may be used to perform an erase operation in which gate-induced drain leakage (GIDL) is used to erase data stored in the memory cell transistor MCT.

[0018] The common source line CSL, the first lower gate line LL1 and the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first connection line 1115 extending from the first structure 1100F toward the second structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second connection line 1125 extending from the first structure 1100F to the second structure 1100S.

[0019] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one of the multiple memory cell transistors (MCTs) to select a memory cell transistor. The logic circuit 1130 can control the decoder circuit 1110 and the page buffer 1120. The semiconductor device 1100 can communicate with the controller 1200 via one or more input / output pads 1101 electrically connected to the logic circuit 1130. The input / output pads 1101 can be electrically connected to the logic circuit 1130 via corresponding input / output connection lines 1135 extending from the first structure 1100F to the second structure 1100S.

[0020] Although not shown, the first structure 1100F may include a voltage generator. The voltage generator can generate the programming voltage, read voltage, pass voltage, and verification voltage required to operate the memory cell string CSTR. The programming voltage may be relatively higher than the read voltage, pass voltage, and verification voltage (e.g., about 20V to about 40V).

[0021] In some embodiments, the first structure 1100F may include high-voltage transistors and low-voltage transistors. The decoder circuit 1110 may include a pass transistor connected to the word line WL of the memory cell string CSTR. The pass transistor may include a high-voltage transistor capable of withstanding high voltages (such as the programming voltage applied to the word line WL during programming operations). The page buffer 1120 may also include a high-voltage transistor capable of withstanding high voltages.

[0022] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface (I / F) 1230. According to some embodiments, the electronic system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.

[0023] Processor 1210 can control the overall operation of electronic system 1000, including controller 1200. Processor 1210 can operate based on predetermined firmware and can control NAND controller 1220 to access semiconductor device 1100. NAND controller 1220 may include NAND interface 1221 for processing communication with semiconductor device 1100. NAND interface 1221 can be used to transmit control commands for controlling semiconductor device 1100, data intended to be written to the memory cell transistors (MCTs) of semiconductor device 1100, and / or data intended to be read from the memory cell transistors (MCTs) of semiconductor device 1100. Host interface 1230 can provide electronic system 1000 with communication with an external host (not explicitly shown). When a control command is received from an external host via host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0024] Figure 2 This is a simplified perspective view illustrating an electronic system including semiconductor devices according to some embodiments of the present invention.

[0025] refer to Figure 2 An electronic system 2000 according to some embodiments of the present invention may include a motherboard 2001, and may also include a controller 2002 mounted on the motherboard 2001, at least one semiconductor package 2003, and dynamic random access memory (DRAM) 2004. The semiconductor package 2003 and DRAM 2004 may be connected to the controller 2002 via wiring patterns 2005 formed on the motherboard 2001.

[0026] The motherboard 2001 may include a connector 2006, which includes multiple pins for connection to an external host. The number and arrangement of the multiple pins in the connector 2006 may vary based on the communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 may communicate with the external host via one or more interfaces, such as Universal Serial Bus (USB), Peripheral Component Interconnect (PIC-Express), Serial Advanced Technology Attachment (SATA), and M-PHY for Universal Flash Memory (UFS). In some embodiments, the electronic system 2000 may operate via power supplied from the external host through the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) through which power supplied from the external host is distributed to the controller 2002 and the semiconductor package 2003.

[0027] The controller 2002 can write data to the semiconductor package 2003, read data from the semiconductor package 2003, or increase the operating speed of the electronic system 2000.

[0028] DRAM 2004 can be a buffer memory that reduces the speed difference between an external host and the semiconductor package 2003, which serves as data storage space. The DRAM 2004 included in the electronic system 2000 can operate as a high-speed cache memory and can provide space for temporary data storage during the control operation of the semiconductor package 2003. When DRAM 2004 is included in the electronic system 2000, the controller 2002 can include not only a NAND controller for controlling the semiconductor package 2003 but also a DRAM controller for controlling the DRAM 2004.

[0029] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other on the motherboard 2001. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 located on the package substrate 2100, an adhesive layer 2300 disposed on the bottom surface of the semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 to the package substrate 2100, and a molding layer 2500 located on the package substrate 2100 covering the semiconductor chip 2200 and the connection structure 2400. The term “covers” (or “covering” or similar terms, as may be used herein) is intended to broadly refer to an element, structure, or layer located on or above another element, structure, or layer, whether directly on it or with one or more other intermediate elements, structures, or layers in between.

[0030] The packaging substrate 2100 may be a printed circuit board including an upper pad 2130 disposed thereon. Each semiconductor chip 2200 may include one or more input / output pads 2210. The input / output pads 2210 may correspond to... Figure 1 The input / output pads 1101. Each semiconductor chip 2200 may include a stacked structure 3210 and a vertical structure 3220. Each semiconductor chip 2200 may include a semiconductor device that will be discussed below in some embodiments according to the concept of the present invention.

[0031] In some embodiments, the connection structure 2400 may be a bonding line that electrically connects the input / output pads 2210 to the corresponding upper pads 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other in a bonding line manner and may be electrically connected to the upper pads 2130 of the package substrate 2100. In some embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a connection structure such as a through-silicon via (TSV) rather than a connection structure 2400 configured as a bonding line.

[0032] In some embodiments, the controller 2002 and the semiconductor chip 2200 may be included in a single package. For example, the controller 2002 and the semiconductor chip 2200 may be mounted on a medium substrate other than the motherboard 2001 and may be interconnected by wiring formed on the medium substrate.

[0033] Figure 3 and Figure 4 This is a simplified schematic cross-sectional view illustrating some embodiments of a semiconductor package according to the present invention. Figure 3 and Figure 4 All depicted Figure 2 The example of the semiconductor package shown conceptually illustrates the following along... Figure 2 The cross-section of the semiconductor package shown is taken from line I-I'.

[0034] refer to Figure 3 The printed circuit board can be used as the packaging substrate 2100 of the semiconductor package 2003. The packaging substrate 2100 may include a packaging substrate body 2120 and upper pads disposed on the top surface of the packaging substrate body 2120 (see...). Figure 2 The upper pad 2130 and the lower pad 2125 are disposed on or exposed on the bottom surface of the package substrate body 2120, and an internal line 2135 are provided. The upper pad 2130 and the lower pad 2125 are electrically connected to each other in the package substrate body 2120 via the internal line 2135. The upper pad 2130 can be electrically connected to the connection structure 2400. The lower pad 2125 can be connected to the wiring pattern 2005 of the motherboard 2001 in the electronic system 2000 via a conductive connector 2800 (e.g., a solder bump), such as... Figure 2 As shown.

[0035] Each semiconductor chip 2200 may include a semiconductor substrate 3010, and may also include a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010 in a vertical direction perpendicular to the surface of the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region, the peripheral circuit region including peripheral wiring 3110. The second structure 3200 may include a source structure 3205, a stacked structure 3210 located on the source structure 3205, a vertical structure 3220 and a separator structure 3230 penetrating (i.e., extending vertically into or through) the stacked structure 3210, a bit line 3240 electrically connected to the vertical structure 3220, and a corresponding word line electrically connected to the stacked structure 3210 (see [link to documentation]). Figure 1 The unit contact plug of the WL). Each of the first structure 3100, the second structure 3200 and the semiconductor chip 2200 may also include the separation structure discussed above.

[0036] Each semiconductor chip 2200 may include one or more through-wires 3245 extending vertically into the second structure 3200 and electrically connected to the peripheral wiring 3110 of the first structure 3100. The through-wires 3245 may be disposed outside the stacked structure 3210 in a horizontal direction parallel to the surface of the semiconductor substrate 3010, and may also be configured to penetrate the stacked structure 3210. Each semiconductor chip 2200 may also include one or more input / output pads 2210 electrically connected to the peripheral wiring 3110 of the first structure 3100 (see also...). Figure 2 (of 2210).

[0037] refer to Figure 4 In the semiconductor package 2003A, each semiconductor chip 2200 may include a semiconductor substrate 4010, a first structure 4100 located on the semiconductor substrate 4010, and a second structure 4200 disposed on the first structure 4100 and to which the wafer is bonded.

[0038] The first structure 4100 may include a peripheral circuit region, which includes peripheral wiring 4110 and a first bonding structure 4150. The second structure 4200 may include a source structure 4205, a stacked structure 4210 between the source structure 4205 and the first structure 4100, a vertical structure 4220 penetrating (i.e., extending vertically into or through) the stacked structure 4210, and a separator structure 4230, as well as corresponding word lines electrically connected to the stacked structure 4210 (see [link to documentation]). Figure 1 The second bonding structure 4250 of the word line WL. For example, the second bonding structure 4250 can be electrically connected to the corresponding vertical structure 4220 and the corresponding word line (see See) via a bit line 4240 electrically connected to the vertical structure 4220 and a cell contact plug electrically connected to the word line WL. Figure 1 (WL). The first joining structure 4150 of the first structure 4100 and the second joining structure 4250 of the second structure 4200 can join and contact each other. The joining portion of the first joining structure 4150 and the second joining structure 4250 can be formed of, for example, copper (Cu).

[0039] According to some embodiments discussed above, each of the first structure 4100, the second structure 4200, and the semiconductor chip 2200 may further include a source structure. Each semiconductor chip 2200 may also include input / output pads electrically connected to the peripheral wiring 4110 of the first structure 4100 (see...). Figure 2 (of 2210).

[0040] Figure 3 or Figure 4Semiconductor chips 2200 can be electrically connected to each other via a connection structure 2400 configured as bonding wires. In some embodiments, in the presence of... Figure 3 or Figure 4 In a semiconductor package of semiconductor chip 2200, semiconductor chip 2200 can be electrically connected to each other via a connection structure 3265 or 4265 including a through electrode such as a through silicon via (TSV).

[0041] Figure 3 The first structure 3100 and Figure 4 The first structure 4100 may correspond to the peripheral circuit structure that will be discussed in the following embodiments, and Figure 3 The second structure 3200 and Figure 4 The second structure 4200 may correspond to the cell array structure that will be discussed in the following embodiments.

[0042] Figure 5 This is a schematic top view illustrating some embodiments of a semiconductor device according to the present invention. Figure 6A and Figure 6B They are respectively along Figure 5 The schematic cross-sectional views taken along lines A-A' and B-B' illustrate semiconductor devices according to some embodiments of the concept of the present invention. Figure 7 It shows Figure 6A Enlarged view of section P.

[0043] refer to Figure 5 , Figure 6A and Figure 6B According to some embodiments, the semiconductor device may include a peripheral circuit structure PS located on a substrate 200, and may also include a cell array structure CS located on the peripheral circuit structure PS in a third direction D3 (i.e., vertical direction) perpendicular to the surface of the substrate 200.

[0044] According to some embodiments, when the cell array structure CS is bonded to the peripheral circuit structure PS, the cell capacity per unit area of ​​the semiconductor device conceived according to the present invention can be increased. Furthermore, since the peripheral circuit structure PS and the cell array structure CS can be manufactured separately and then bonded to each other, damage to the peripheral circuit PTR, described subsequently, due to various thermal processing techniques can be prevented, and thus the reliability and electrical performance of the semiconductor device can be improved.

[0045] The peripheral circuit structure PS may include a substrate 200, a peripheral circuit PTR for controlling the memory cell array, and peripheral interlayer dielectric layers 210 and 220 covering the peripheral circuit PTR. The peripheral circuit PTR may be integrated on the top surface of the substrate 200. A surface dielectric layer 201 may be provided on the back surface of the substrate 200.

[0046] The substrate 200 can be formed by depositing a semiconductor material. The substrate 200 may include at least one selected from silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and mixtures thereof. The substrate 200 may include one or more of doped semiconductors and undoped intrinsic semiconductors. The substrate 200 may have at least one structure selected from single-crystal structures, amorphous structures, and polycrystalline structures.

[0047] The substrate 200 may have a top surface that is parallel to a first direction D1 and a second direction D2 that intersects the first direction D1 and is perpendicular to a third direction D3. The first direction D1, the second direction D2, and the third direction D3 may be orthogonal to each other.

[0048] The peripheral circuitry PTR can be row and column decoders, page buffers, and control circuitry. For example, the peripheral circuitry PTR can include NMOS and PMOS transistors. The peripheral circuitry line (PLP) can be electrically connected to the peripheral circuitry PTR via the peripheral contact plug (PCR).

[0049] The peripheral contact plug PCR may each have a width in a first direction D1 or a second direction D2, and for example, the width may be increased in a third direction D3. The peripheral contact plug PCR and the peripheral circuit line PLP may include a conductive material such as a metal.

[0050] Peripheral interlayer dielectric layers 210 and 220 may be disposed on the top surface of substrate 200. On substrate 200, peripheral interlayer dielectric layers 210 and 220 may cover peripheral circuit PTR, peripheral contact plug PCR, and peripheral circuit line PLP. Peripheral contact plug PCR and peripheral circuit line PLP may be electrically connected to peripheral circuit PTR. Peripheral interlayer dielectric layers 210 and 220 may include one or more of silicon oxide layer, silicon nitride layer, silicon oxynitride layer, and low dielectric constant (low k) dielectric layer.

[0051] A first bonding pad BP1 may be provided in the uppermost outermost interlayer dielectric layer 220. The uppermost outermost interlayer dielectric layer 220 may not cover the top surface of the first bonding pad BP1. The top surface of the uppermost outermost interlayer dielectric layer 220 may be substantially coplanar with the top surface of the first bonding pad BP1. The first bonding pad BP1 may be electrically connected to the peripheral circuit PTR via the peripheral circuit line PLP and the peripheral contact plug PCR.

[0052] The cell array structure CS can be set on the peripheral circuit structure PS. The cell array structure CS of a semiconductor device can include the cell array region CR and the peripheral region ER.

[0053] The cell array structure CS may include a memory cell array comprising memory cells arranged in three dimensions. The cell array structure CS may include a source conductive pattern SCP, a stacked structure ST, a vertical structure VS, an upper conductor 140, a bit line BL, and a cell contact plug CPLG.

[0054] The stacked structure ST may include conductive patterns GE1 and GE2 and dielectric patterns ILD1 and ILD2 that are alternately stacked along a third direction D3 (or a vertical direction) perpendicular to a first direction D1 and a second direction D2 that intersect each other.

[0055] In some embodiments, conductive patterns GE1 and GE2 may include a first erase gate pattern and a second erase gate pattern adjacent to the source conductive pattern SCP, a ground select gate pattern located on the second erase gate pattern, a plurality of cell gate patterns stacked on the ground select gate pattern on the third direction D3, and a string select gate pattern located on the uppermost cell gate pattern.

[0056] The conductive patterns GE1 and GE2 of the stacked structure ST can be stacked in a reverse stepped structure on the peripheral region ER. For example, the conductive patterns GE1 and GE2 can have a length that increases in the first direction D1 as the distance from the peripheral circuit structure PS in the third direction D3 increases.

[0057] On the peripheral region ER, the ends of conductive patterns GE1 and GE2 can be positioned at different locations horizontally and vertically. The ends of conductive patterns GE1 and GE2 can be correspondingly connected to the unit contact plug CPLG.

[0058] In some embodiments, the stacked structure ST may include a first stacked structure ST1 and a second stacked structure ST2 located on the first stacked structure ST1. The first stacked structure ST1 may include a first dielectric pattern ILD1 and a first conductive pattern GE1 alternately stacked on a third direction D3, and the second stacked structure ST2 may include a second dielectric pattern ILD2 and a second conductive pattern GE2 alternately stacked on a third direction D3.

[0059] The second stacked structure ST2 can be disposed between the first stacked structure ST1 and the peripheral circuit structure PS. For example, the second stacked structure ST2 can be disposed on the bottom surface of the lowest first dielectric pattern of the first dielectric pattern ILD1 included in the first stacked structure ST1. Although the uppermost second dielectric pattern of the second dielectric pattern ILD2 included in the second stacked structure ST2 is in contact with the lowest first dielectric pattern of the first dielectric pattern ILD1 included in the first stacked structure ST1, the inventive concept is not limited thereto, and a single dielectric layer can be provided between the uppermost second conductive pattern of the second conductive pattern GE2 included in the second stacked structure ST2 and the lowest first conductive pattern of the first conductive pattern GE1 included in the first stacked structure ST1.

[0060] The lowest second conductive pattern in the second conductive pattern GE2 included in the second stacked structure ST2 can have a minimum length in the first direction D1, and the uppermost first conductive pattern in the first conductive pattern GE1 included in the first stacked structure ST1 can have a maximum length in the first direction D1.

[0061] The first conductive pattern GE1 and the second conductive pattern GE2 may comprise metallic materials. For example, the first conductive pattern GE1 and the second conductive pattern GE2 may comprise at least one selected from metals (e.g., tungsten, molybdenum, nickel, copper, or aluminum), conductive metal nitrides (e.g., titanium nitride or tantalum nitride), and transition metals (e.g., titanium or tantalum).

[0062] The first dielectric pattern ILD1 and the second dielectric pattern ILD2 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, and low-k dielectrics. For example, the first dielectric pattern ILD1 and the second dielectric pattern ILD2 may include high-density plasma (HDP) oxide or tetraethyl orthosilicate (TEOS).

[0063] According to some embodiments, the semiconductor device may be a vertical NAND flash memory device, and in this case, the first conductive pattern GE1 and the second conductive pattern GE2 of the stacked structure ST can be used as a reference. Figure 1 The gate lower lines LL1 and LL2, word line WL, and gate upper lines UL1 and UL2 are discussed.

[0064] The planarized dielectric layer 105 may cover the ends of the stepped structure of the stacked structure ST. The planarized dielectric layer 105 may have a substantially flat top surface. The planarized dielectric layer 105 may include a single dielectric layer or multiple stacked dielectric layers. The planarized dielectric layer 105 may have a substantially flat top surface and a substantially flat bottom surface. The top surface of the planarized dielectric layer 105 may be substantially coplanar with the top surface of the stacked structure ST (or the top surface of the uppermost first dielectric pattern ILD1), and the bottom surface of the planarized dielectric layer 105 may be substantially coplanar with the bottom surface of the stacked structure ST (or the bottom surface of the lowermost dielectric pattern ILD2).

[0065] The upper conductor 140 may be disposed on the stacked structure ST. The upper conductor 140 may be disposed on the uppermost first dielectric pattern ILD1 of the stacked structure ST. For example, the upper conductor 140 may comprise polysilicon and may also comprise silicon oxide. The upper conductor 140 may also comprise impurities having a first conductivity type, but the inventive concept is not limited thereto. Alternatively, the upper conductor 140 may comprise metal.

[0066] In some embodiments, the upper conductor 140 can be used as an erase control transistor, which transmits signals through the cell string (see [link]). Figure 1 The upper part of the CSTR generates gate-induced drain leakage (GIDL) to control the erase operation. For example, the upper conductor 140 can be used to erase data stored in the cell string (see [link to CSTR]). Figure 1 In the data erasure operation of CSTR).

[0067] On the cell array region CR, multiple vertical structures VS can penetrate the stacked structure ST and the upper conductor 140. When viewed in a cross-sectional view, the vertical structures VS can be arranged in a straight line or a zigzag pattern along one direction.

[0068] In some embodiments, each vertical structure VS may be disposed in a vertical channel hole penetrating the stacked structure ST. In some embodiments, the vertical channel hole may include a first vertical channel hole penetrating the first stacked structure ST1, and may also include a second vertical channel hole penetrating the second stacked structure ST2 and connected to the first vertical channel hole.

[0069] Each vertical structure VS may include a first vertical extension in a first vertical channel hole and a second vertical extension in a second vertical channel hole. The first and second vertical extensions may be a single structure extending continuously without an interface. The first vertical extension may have sidewalls with a constant slope from its bottom to its top. Similarly, the second vertical extension may have sidewalls with a constant slope from its bottom to its top. For example, each of the first and second vertical extensions may have a width in a first direction D1 or a second direction D2, and this width may decrease as the distance from the substrate 200 increases in a third direction D3. The first and second vertical extensions may have different diameters at their connection portion. A step difference may be provided at the connection portion where the first and second vertical extensions connect to each other.

[0070] However, the inventive concept is not limited thereto, and unlike what is shown, each vertical structure VS may have three or more vertical extensions with stepped differences at two or more boundaries. Alternatively, each vertical structure VS may have flat sidewalls without stepped differences.

[0071] refer to Figure 6A and Figure 7 Each vertical structure VS can extend in a third direction D3 perpendicular to the top surface of the substrate 200 to penetrate the stacked structure ST and the upper conductor 140 and connect to the source conductive pattern SCP.

[0072] Each vertical structure VS may include a vertical channel pattern VP, a data storage pattern DSP, and a vertical dielectric pattern VI. For example, the vertical dielectric pattern VI may include at least one material selected from silicon oxide and silicon nitride, but the embodiments are not limited thereto.

[0073] For example, a vertical channel pattern VP can be macaroni-shaped or tubular with closed top and bottom. A vertical channel pattern VP can have inner sidewalls defining an internal space and outer sidewalls adjacent to the stacked structure ST. A vertical channel pattern VP can surround the outer sidewalls and top surface of a vertical dielectric pattern VI. The term "surround" (or "surrounds" or similar terms) as used herein is intended to broadly refer to an element, structure, or layer that surrounds, encloses, or surrounds another element, structure, or layer on all sides, but breaks or gaps may also be present. Thus, for example, a material layer with voids or gaps can still "surround" another layer it surrounds.

[0074] The vertical channel pattern VP can include semiconductor materials such as silicon (Si), germanium (Ge), or mixtures thereof. For example, the vertical channel pattern VP can include polycrystalline silicon. The vertical channel pattern VP including semiconductor materials can be used as the channel for upper transistors UT1 and UT2, memory cell transistors MCT, and lower transistors LT1 and LT2, all of which are referenced. Figure 1 The vertical channel pattern VP can be horizontally adjacent to the upper conductor 140 (e.g., in the first direction D1 or the second direction D2) and can be used as the channel for the erase control transistor used by the upper conductor 140.

[0075] The data storage pattern DSP can extend on the third direction D3 and surround the outer wall of the vertical channel pattern VP. The data storage pattern DSP can be a through-face or tubular shape with an open top. The data storage pattern DSP can be formed from a single thin layer or multiple thin layers. In some embodiments of the present invention, the data storage pattern DSP can include a tunnel dielectric pattern TIP, a charge storage pattern CIP, and a barrier dielectric pattern BKP sequentially stacked on the sidewall of the vertical channel pattern VP and used as a data storage layer of a NAND flash memory device. For example, the charge storage pattern CIP can be a trapping dielectric layer, a floating gate electrode, or a dielectric layer comprising conductive nanodots. The tunnel dielectric pattern TIP can include one of several suitable materials with a band gap larger than that of the charge storage pattern CIP, and the barrier dielectric pattern BKP can be a high dielectric constant (high k) dielectric layer, such as an alumina layer or a hafnium oxide layer.

[0076] The vertical structure VS may include a portion penetrating the lower part of the stacked structure ST, and may also include an upper part connected to the lower part and penetrating the first interlayer dielectric layer 130, the second interlayer dielectric layer 150, and the upper conductor 140. For example, the lower part of the vertical structure VS may include a first vertical extension and a second vertical extension penetrating the aforementioned first stacked structure ST1 and second stacked structure ST2. The upper part of the vertical structure VS may refer to the portion that extends continuously from the lower part of the vertical structure VS onto the stacked structure ST without an interface.

[0077] The lower part of the vertical structure VS can have a minimum width W3 at the same height as the top surface of the stacked structure ST. For example, the lower part of the vertical structure VS can have a minimum width W3 at the same height as the top surface of the uppermost first dielectric pattern ILD1 in the second direction D2.

[0078] The upper part of the vertical structure VS can have a minimum width W4 that is greater than the minimum width W3 of the lower part of the vertical structure VS. For example, the upper part of the vertical structure VS can have a width greater than the minimum width W3 of the lower part of the vertical structure VS, and a step difference can be formed at the height where the lower part of the vertical structure VS connects to the upper part of the vertical structure VS (e.g., the same height as the top surface of the uppermost first dielectric pattern ILD1). The upper part of the vertical structure VS can have a minimum width W4 at the same height as the top surface of the first interlayer dielectric layer 130. For example, the widths of the upper and lower parts of the vertical structure VS can each be widths in the horizontal direction (e.g., the second direction D2).

[0079] On the top surface of each vertical structure VS, a recess GR recessed toward the substrate 200 can be formed. For example, the recess GR can be an internal space surrounded by the inner surface of the vertical channel pattern VP. Furthermore, relative to the upper surface of the substrate 200, which serves as a reference layer, the uppermost end point VP_U of the vertical channel pattern VP and the uppermost end point DSP_U of the data storage pattern DSP can be substantially coplanar with each other and can be located at a height higher than the height of the top surface VI_U of the vertical dielectric pattern VI in the third direction D3. Relative to the upper surface of the substrate 200, the uppermost end point VP_U of the vertical channel pattern VP and the uppermost end point DSP_U of the data storage pattern DSP can be located at a height higher than the height of the top surface 140_U of the upper conductor 140 in the third direction D3.

[0080] The horizontal width of the groove GR can gradually increase as the distance from the vertical dielectric pattern VI decreases; that is, the horizontal width of the groove GR can increase as the groove GR gets closer to the top surface VI_U of the vertical dielectric pattern VI. The width of the groove GR can gradually increase as the distance from the stacked structure ST or the substrate 200 decreases. For example, the groove GR can have a first width W1 at its top end and a second width W2 at its bottom end, and the second width W2 can be greater than the first width W1. The first width W1 and the second width W2 of the groove GR can refer to the width along the second direction D2 at the top and bottom ends, respectively.

[0081] The thickness T1 of the upper conductor 140 in the third direction D3 can be greater than the thickness T2 of the conductive patterns GE1 and GE2 in the third direction D3 of the stacked structure ST. For example, the thickness T2 of the conductive patterns GE1 and GE2 can be substantially similar to each other and can have a value similar to the thickness T2 of the uppermost conductive pattern GE1T among the conductive patterns GE1 and GE2. The thickness T1 of the upper conductor 140 can be greater than the thickness T2 of the uppermost conductive pattern GE1T, and for example, it can be about twice the thickness T2 of the uppermost conductive pattern GE1T. For example, the thickness T1 of the upper conductor 140 can range from about 20 nm to about 1 μm.

[0082] A horizontal dielectric pattern HP can be disposed between the data storage pattern DSP and the conductive patterns GE1 and GE2 of the stacked structure ST. The horizontal dielectric pattern HP can extend from the sidewalls of the conductive patterns GE1 and GE2 to the top and bottom surfaces of the conductive patterns GE1 and GE2. The horizontal dielectric pattern HP may include a high-k dielectric layer. For example, the horizontal dielectric pattern HP may include a metal oxide containing a first metal, and the first metal may be one of aluminum (Al) and hafnium (Hf).

[0083] A high-k dielectric layer may not be separately provided between the upper conductor 140 and the data storage pattern DSP. For example, the upper conductor 140 may be in contact with the data storage pattern DSP. In addition, the upper conductor 140 may not include the metal oxides discussed above. In other words, the upper conductor 140 may not include the first metal (e.g., aluminum or hafnium).

[0084] According to some embodiments of the present invention, the upper conductor 140 can be configured as the gate electrode of an erase transistor that induces gate-induced drain leakage (GIDL) on the stacked structure ST. The thickness T1 of the upper conductor 140 can be greater than the thickness T2 of the conductive patterns GE1 and GE2 in the stacked structure ST, and the thickness T1 of the upper conductor 140 can be formed to be relatively large, which can lead to an increase in the efficiency of gate-induced drain leakage. Furthermore, a high-k dielectric layer may not be separately disposed between the upper conductor 140 and the data storage pattern DSP, and thus the efficiency of gate-induced drain leakage can be further increased. Therefore, semiconductor devices according to some embodiments of the present invention can achieve improved reliability.

[0085] A source conductive pattern SCP can be disposed on the vertical structure VS and the partition structure SS, which will be discussed below, and can be electrically connected to the vertical structure VS. The source conductive pattern SCP may include a first portion SCP_a extending along a first direction D1 and a second direction D2 on the upper conductor 140, and may also include a second portion SCP_b having a connection to the first portion SCP_a and penetrating at least a portion of the upper conductor 140. The second portion SCP_b may protrude toward the groove GR. In some embodiments, the second portion SCP_b may be connected to the corresponding vertical structure VS.

[0086] The first portion SCP_a may contact the uppermost end DSP_U of the data storage pattern DSP and the uppermost end VP_U of the vertical channel pattern VP. When viewed in a top view, the second portion SCP_b may overlap with the groove GR. As used herein, "element A overlaps with element B in direction X" (or similar language) means that there is at least one line extending in direction X and intersecting both elements A and B. The second portion SCP_b may protrude toward the groove GR of the vertical structure VS, and the vertical structure VS may surround the second portion SCP_b. The second portion SCP_b may contact the inner surface of the vertical channel pattern VP, which forms the groove GR. The second portion SCP_b may be perpendicularly spaced from the vertical dielectric pattern VI, and the bottom surface of the second portion SCP_b may be located at a height in the third direction D3 relative to the upper surface of the substrate 200 that is higher than the height of the top surface VI_U of the vertical dielectric pattern VI. Additionally, the second part of SCP_b may be horizontally adjacent to the upper conductor 140, and the bottom surface of the second part of SCP_b may be located at a height higher than the top surface of the uppermost conductive pattern GE1T in the conductive patterns GE1 and GE2 of the stacked structure ST.

[0087] For example, the source conductive pattern SCP may include polycrystalline silicon and may also include impurities having a first conductivity type (e.g., n-type). For example, the source conductive pattern SCP may also include at least one selected from phosphorus (P), arsenic (As), and antimony (Sb). The concentration of the impurity having the first conductivity type in the source conductive pattern SCP may differ from the concentration of the impurity having the first conductivity type in the vertical channel pattern VP. For example, the source conductive pattern SCP may include a first concentration of impurities having the first conductivity type, and the vertical channel pattern VP may include a second concentration of impurities having the first conductivity type, different from the first concentration. For example, the first concentration may be greater than the second concentration.

[0088] A first interlayer dielectric layer 130 may be disposed on the upper conductor 140. The first interlayer dielectric layer 130 may cover the top surface 140_U of the upper conductor 140. The first interlayer dielectric layer 130 may be disposed between the upper conductor 140 and the source conductive pattern SCP. A second interlayer dielectric layer 150 may be disposed between the upper conductor 140 and the stacked structure ST. For example, the first interlayer dielectric layer 130 and the second interlayer dielectric layer 150 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0089] Return to reference Figure 5 , Figure 6A and Figure 6BA first lower dielectric layer 160, a second lower dielectric layer 170, a third lower dielectric layer 180, and a fourth lower dielectric layer 190 may be sequentially disposed on the bottom surface of the planarized dielectric layer 105 and the bottom surface of the stacked structure ST. The first lower dielectric layer 160 may cover the bottom surface of the vertical structure VS. For example, the first lower dielectric layer 160, the second lower dielectric layer 170, the third lower dielectric layer 180, and the fourth lower dielectric layer 190 may include one or more of silicon oxide and silicon oxynitride.

[0090] A separator structure SS may be provided between the vertical structures VS, extending along a first direction D1 from the cell array region CR toward the peripheral region ER. The separator structure SS may penetrate the stacked structure ST and the upper conductor 140 vertically (e.g., in a third direction D3). The top surface of the separator structure SS may be located at a height lower than the height of the top surface of the first interlayer dielectric layer 130. For example, the separator structure SS may comprise one or more of silicon oxide and silicon oxynitride.

[0091] A bit line conductive pad BLPAD can be formed on the bottom end of the vertical structure VS, and a bit line contact plug BCT can penetrate the first lower dielectric layer 160 to connect and bond with the bit line conductive pad BLPAD. The bit line conductive pad BLPAD can include undoped semiconductor material, doped semiconductor material, or conductive material.

[0092] On the peripheral region ER, the cell contact plug CPLG can penetrate the first lower dielectric layer 160 and the planarized dielectric layer 105 to connect and bond with the pad portions of the first conductive pattern GE1 and the second conductive pattern GE2. The vertical length of the cell contact plug CPLG can decrease as the distance from the cell array region CR decreases. The bottom surfaces of the cell contact plug CPLG can be substantially coplanar with each other.

[0093] Each cell contact plug CPLG may include a barrier metal layer and a metal layer, the barrier metal layer comprising a conductive metal nitride (e.g., titanium nitride or tantalum nitride) and the metal layer comprising a metal (e.g., tungsten, titanium, or tantalum).

[0094] On the cell array region CR, a bit line BL can be provided in the second lower dielectric layer 170. The bit line BL can extend in the second direction D2, while also extending across the stack structure ST. The bit line BL can be electrically connected to the vertical structure VS via a bit line contact plug BCT.

[0095] On the peripheral region ER, a first lower conductor 175 may be provided in the second lower dielectric layer 170. On the peripheral region ER, the first lower conductor 175 may be connected to the cell contact plug CPLG.

[0096] A second lower conductor 185 may be provided in the third lower dielectric layer 180. On the cell array region CR, the second lower conductor 185 may be electrically connected to the bit line BL. On the peripheral region ER, the second lower conductor 185 may be electrically connected to the first lower conductor 175.

[0097] A second bonding pad BP2 may be provided in the fourth lower dielectric layer 190. Multiple second bonding pads BP2 may be electrically connected to a second lower conductor 185. The bit line BL, the first lower conductor 175, the second lower conductor 185, and the second bonding pad BP2 may be formed of aluminum, copper, or tungsten.

[0098] The second bonding pad BP2 can be electrically and physically connected to the first bonding pad BP1 using a bonding method. For example, the second bonding pad BP2 can be in direct contact with the first bonding pad BP1.

[0099] The second bonding pad BP2 may include the same metal material as the first bonding pad BP1. The second bonding pad BP2 may have a shape, width, and area that are substantially the same as those of the first bonding pad BP1.

[0100] The upper dielectric layer 310 can cover the source conductive pattern SCP. The upper pathway VA can be configured to penetrate the upper dielectric layer 310 to electrically connect with the source conductive pattern SCP.

[0101] A wiring pad (PAD) may be provided on the upper dielectric layer 310. A cover dielectric layer 320 may be provided on the upper dielectric layer 310, and the cover dielectric layer 320 may cover the wiring pad (PAD).

[0102] A cap dielectric layer 320 may be disposed on the front surface of the upper dielectric layer 310. For example, the cap dielectric layer 320 may be a silicon nitride layer or a silicon oxynitride layer. Although not shown, for example, a passivation layer may be additionally disposed on the cap dielectric layer 320. For example, the passivation layer (not shown) may comprise a polyimide-based material, such as photosensitive polyimide (PSPI).

[0103] Figures 8 to 18 This is a schematic cross-sectional view illustrating an intermediate process in an illustrative method for manufacturing a semiconductor device according to some embodiments of the present invention. Figures 8 to 18 It can correspond to Figure 6A .

[0104] refer to Figure 8 It can provide a peripheral circuit structure PS, which includes a peripheral circuit PTR formed on the substrate 200.

[0105] For example, the formation of the peripheral circuit structure PS may include: forming a device isolation layer defining an active region in the substrate 200; forming a peripheral circuit PTR on the active region on the substrate 200; forming a peripheral contact plug PCR, a peripheral circuit line PLP and a first bonding pad BP1 electrically connected to the peripheral circuit PTR; and forming peripheral interlayer dielectric layers 210 and 220 on the substrate 200 covering the peripheral contact plug PCR, the peripheral circuit line PLP and the first bonding pad BP1.

[0106] The substrate 200 can be formed by depositing a semiconductor material. The substrate 200 may include at least one material selected from, for example, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and mixtures thereof. The substrate 200 may include one or more of doped semiconductors and undoped intrinsic semiconductors. The substrate 200 may include at least one material selected from single-crystal structures, amorphous structures, and polycrystalline structures. A surface dielectric layer 201 may be provided on the back surface of the substrate 200.

[0107] Row and column decoders, page buffers, and control circuitry, serving as peripheral circuitry PTRs, can be formed on substrate 200. The peripheral circuitry PTR may include metal-oxide-semiconductor (MOS) transistors, each using substrate 200 as a channel.

[0108] Peripheral interlayer dielectric layers 210 and 220 may include a single dielectric layer covering the peripheral circuit PTR or multiple stacked dielectric layers covering the peripheral circuit PTR. For example, peripheral interlayer dielectric layers 210 and 220 may include multiple lower dielectric layers and etch stop layers between the lower dielectric layers. Peripheral interlayer dielectric layers 210 and 220 may include one or more of silicon oxide layers, silicon nitride layers, silicon oxynitride layers, and low-k dielectric layers.

[0109] The peripheral contact plug PCR can be formed as a portion penetrating the peripheral interlayer dielectric layers 210 and 220 to connect with the peripheral circuit PTR. The peripheral circuit line PLP can be formed by depositing and patterning the conductive layer.

[0110] The first bonding pad BP1 can be formed in the uppermost outermost interlayer dielectric layer 220 of the outermost interlayer dielectric layers 210 and 220. The first bonding pad BP1 can be electrically connected to the outermost circuit PTR through the outermost contact plug PCR and the outermost circuit line PLP.

[0111] The first bonding pad BP1 can be formed using a damascene process. The top surface of the first bonding pad BP1 may be substantially coplanar with the top surface of the uppermost peripheral interlayer dielectric layer 220. In the following description, the phrase "substantially coplanar" may mean that a planarization process has been performed. Planarization processes may include, for example, chemical mechanical polishing (CMP) processes or etch-back processes, but the embodiments are not limited thereto.

[0112] refer to Figure 9 A sub-substrate 100 may be provided. The sub-substrate 100 may include at least one selected from silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and mixtures thereof.

[0113] A preliminary interlayer dielectric layer 110, a preliminary semiconductor layer 120, a first interlayer dielectric layer 130, an upper conductive line 140, and a second interlayer dielectric layer 150 may be sequentially formed on the sub-substrate 100. The preliminary interlayer dielectric layer 110, the first interlayer dielectric layer 130, and the second interlayer dielectric layer 150 may comprise at least one material selected from silicon oxide, silicon nitride, and silicon oxynitride. For example, the preliminary semiconductor layer 120 and the upper conductive line 140 may comprise polysilicon.

[0114] refer to Figure 10 The first trench TR1 can be formed to penetrate the first interlayer dielectric layer 130 and the second interlayer dielectric layer 150, the upper conductor 140, and the preliminary semiconductor layer 120. Furthermore, the second trench TR2 can be formed to penetrate the second interlayer dielectric layer 150 and the upper conductor 140. The first trench TR1 and the second trench TR2 can be formed by repeatedly performing a patterning process. For example, relative to the surface of the sub-substrate 100, the bottom end of the first trench TR1 can be located at a height lower than the bottom end of the second trench TR2 in the third direction D3. For example, when viewed in a cross-sectional view, the first trench TR1 and the second trench TR2 can each be circular or elliptical, having a major axis in the first direction D1 or the second direction D2.

[0115] A first barrier pattern BRP1 and a first gap-filling pattern GF1 can be sequentially formed to fill a first trench TR1. The term "fill" (or "fills" or similar terms) is intended to mean completely filling a defined space (e.g., the first trench TR1 and the second trench TR2) or partially filling a defined space; that is, the defined space does not need to be completely filled, but may, for example, be partially filled or have gaps or other spaces distributed throughout. Each first barrier pattern BRP1 may conformally cover the inner wall of the first trench TR1, and the first gap-filling pattern GF1 may be correspondingly formed on the first barrier pattern BRP1. The term "conformally" (or "conformal" or similar terms), as may be used herein in the context of a material layer or coating, is intended broadly to mean a material layer or coating having a substantially uniform cross-sectional thickness relative to the profile of the surface on which the material layer is applied. A second barrier pattern BRP2 and a second gap-filling pattern GF2 can be sequentially formed to fill a second trench TR2. The second barrier pattern BRP2 may conformally cover the inner wall of the second trench TR2, and the second gap-filling pattern GF2 may be formed on the second barrier pattern BRP2. For example, the first barrier pattern BRP1 and the second barrier pattern BRP2 may include conductive metal nitrides (e.g., titanium nitride or tantalum nitride), and the first gap-filling pattern GF1 and the second gap-filling pattern GF2 may include metals (e.g., tungsten, titanium, or tantalum).

[0116] refer to Figure 11 A first molded structure ML1 and a second molded structure ML2 can be formed on the second interlayer dielectric layer 150.

[0117] The formation of the first molding structure ML1 may include vertically and alternately stacking a first dielectric pattern ILD1 and a first sacrificial layer SL1. In the first molding structure ML1, the first sacrificial layer SL1 may be formed of a material capable of being selectively etched relative to the first dielectric pattern ILD1. For example, the first sacrificial layer SL1 may be formed of a dielectric material different from the dielectric material of the first dielectric pattern ILD1. For example, the first sacrificial layer SL1 may include silicon nitride, and the first dielectric pattern ILD1 may include one or more of silicon oxide, silicon oxynitride, and low-k dielectrics.

[0118] The first dielectric pattern ILD1 and the first sacrificial layer SL1 can be deposited using, for example, thermochemical vapor deposition (CVD), plasma-enhanced CVD, physical CVD, or atomic layer deposition (ALD).

[0119] In the first molding structure ML1, a patterning process can be performed to form first channel holes CH1. For example, when viewed in a cross-sectional view, each of the first channel holes CH1 may have a circular or elliptical shape, the circular or elliptical shape having a major axis in a first direction D1 or a second direction D2. In the first molding structure ML1, a patterning process can be performed to form separation trenches STR. For example, when viewed in a cross-sectional view, the separation trenches STR may be strip-shaped or groove-shaped. When performing the patterning process, a first gap fill pattern GF1 and a second gap fill pattern GF2 can be used as etch stop layers.

[0120] The second molding structure ML2 can be formed on the first molding structure ML1. The formation of the second molding structure ML2 can be substantially the same as the formation of the first molding structure ML1. For example, the formation of the second molding structure ML2 may include vertically and alternately stacking a second dielectric pattern ILD2 and a second sacrificial layer SL2 on the first molding structure ML1.

[0121] The second sacrificial layer SL2 can be formed of the same material as the first sacrificial layer SL1, and can have a thickness substantially the same as the first sacrificial layer SL1. The second sacrificial layer SL2 can be formed of a dielectric material different from the dielectric material of the second dielectric pattern ILD2. For example, the second sacrificial layer SL2 can be formed of a silicon nitride layer, and the second dielectric pattern ILD2 can be formed of a silicon oxide layer.

[0122] The second dielectric pattern ILD2 and the second sacrificial layer SL2 can be deposited using, for example, thermochemical vapor deposition (CVD), plasma-enhanced CVD, physical CVD, or atomic layer deposition (ALD).

[0123] In the second molding structure ML2, a patterning process can be performed to form a second channel hole CH2. For example, when viewed in a cross-sectional view, each of the second channel holes CH2 may have a circular or elliptical shape, the circular or elliptical shape having a major axis in a first direction D1 or a second direction D2. The second channel hole CH2 may be connected to the first channel hole CH1, and the channel hole CH may be formed to penetrate the first molding structure ML1 and the second molding structure ML2. In the second molding structure ML2, a patterning process may additionally be performed to form separating grooves STR to penetrate the first molding structure ML1 and the second molding structure ML2.

[0124] When the patterning process is performed, the first gap-filling pattern GF1 and the second gap-filling pattern GF2, as well as the first barrier pattern BRP1 and the second barrier pattern BRP2, can penetrate at least a portion of the preliminary interlayer dielectric layer 110. Furthermore, the bottom ends of the first trench TR1 and the second trench TR2 can be located at a lower height.

[0125] refer to Figure 11 and Figure 12 The first gap fill pattern GF1 and the second gap fill pattern GF2, as well as the first barrier pattern BRP1 and the second barrier pattern BRP2, filling the first trench TR1 and the second trench TR2 can be selectively removed. For example, a wet etching process can be performed to remove the first gap fill pattern GF1 and the second gap fill pattern GF2, as well as the first barrier pattern BRP1 and the second barrier pattern BRP2.

[0126] A preliminary vertical structure pVS can be formed to fill the via CH and the first trench TR1. The formation of the preliminary vertical structure pVS may include: sequentially depositing a data storage layer DSL and a vertical channel layer VL in the via CH and the first trench TR1; filling the via CH and the first trench TR1 with a preliminary vertical dielectric pattern pVI; and etching and planarizing the data storage layer DSL and the vertical channel layer VL on the uppermost second dielectric pattern ILD2. Subsequently, bit line conductive pads BLPADs can be formed correspondingly on the top of the vertical channel layer VL and the preliminary vertical dielectric pattern pVI. The bit line conductive pads BLPADs may be impurity-doped regions or formed of a conductive material. The top surface of the bit line conductive pads BLPADs may be coplanar with the top surface of the uppermost second dielectric pattern ILD2. The data storage layer DSL may include a tunnel dielectric layer TIL, a charge storage layer CIL, and a barrier dielectric layer BKL stacked sequentially.

[0127] For example, chemical vapor deposition (CVD) or atomic layer deposition (ALD) can be used to deposit a data storage layer DSL and a vertical channel layer VL with constant thickness. For example, the charge storage layer CIL can be a trapping dielectric layer, a floating gate electrode, or a dielectric layer comprising conductive nanodots. The tunnel dielectric layer TIL can include one of several suitable materials with a band gap larger than that of the charge storage layer CIL, and the blocking dielectric layer BKL can be a high-k dielectric layer, such as an alumina layer or a hafnium oxide layer. For example, the initial vertical dielectric pattern pVI can include at least one selected from silicon oxide and silicon nitride. For example, the vertical channel layer VL can include a semiconductor material such as silicon (Si), germanium (Ge), or mixtures thereof.

[0128] A separator structure SS can be formed to fill the separator trench STR and the second trench TR2. The separator structure SS can be a multilayer structure or a single-layer structure. For example, the separator structure SS can include one or more of silicon oxide and silicon oxynitride.

[0129] A process can be performed to replace the first sacrificial layer SL1 and the second sacrificial layer SL2 of the first molded structure ML1 and the second molded structure ML2 with the first conductive pattern GE1 and the second conductive pattern GE2. Therefore, a stacked structure ST can be formed on the second interlayer dielectric layer 150.

[0130] The replacement process of replacing the first sacrificial layer SL1 and the second sacrificial layer SL2 with the first conductive pattern GE1 and the second conductive pattern GE2 may include: isotropically etching the first sacrificial layer SL1 and the second sacrificial layer SL2 using an etching formulation that has etch selectivity relative to the first dielectric pattern ILD1 and the second dielectric pattern ILD2, the vertical structure VS and the second interlayer dielectric layer 150; depositing a conductive layer therein to fill the blank spaces where the first sacrificial layer SL1 and the second sacrificial layer SL2 have been removed; and performing an isotropic etching process to divide the conductive layer into a plurality of conductive patterns.

[0131] According to some embodiments of the present invention, an upper conductive line 140 can be formed, and a first trench TR1 and a second trench TR2 can be formed to penetrate the upper conductive line 140. A first gap fill pattern GF1 and a second gap fill pattern GF2 can be readily formed in the first trench TR1 and the second trench TR2, and the first gap fill pattern GF1 and the second gap fill pattern GF2 can be used as etch stop layers during the patterning of the first molding structure ML1 and the second molding structure ML2. For example, the first gap fill pattern GF1 and the second gap fill pattern GF2 can prevent the etching of the underlying structure during the process of etching the first molding structure ML1 and the second molding structure ML2, each having a large aspect ratio, and can achieve improved reliability in semiconductor device manufacturing. The first gap fill pattern GF1 and the second gap fill pattern GF2 can then be removed, and the first trench TR1 and the second trench TR2 can be used as spaces to form the initial vertical structure pVS, resulting in efficient semiconductor device manufacturing.

[0132] refer to Figure 13 A first lower dielectric layer 160 can be formed on the stacked structure ST. Bit line contact plugs (BCTs) can be formed to penetrate the first lower dielectric layer 160 for connection and engagement with the vertical structure VS. Bit line contact plugs (BCTs) can contact the bit line conductive pads (BLPADs) of the vertical structure VS.

[0133] A second lower dielectric layer 170 may be formed on the first lower dielectric layer 160. A bit line BL may be formed to penetrate the second lower dielectric layer 170. The bit line BL may be electrically connected to the bit line contact plug BCT.

[0134] A third lower dielectric layer 180 may be formed on the second lower dielectric layer 170. A second lower conductor 185 may be formed to penetrate the third lower dielectric layer 180. The second lower conductor 185 may be connected to the bit line BL.

[0135] A fourth lower dielectric layer 190 may be formed on the third lower dielectric layer 180. A second bonding pad BP2 may be formed to penetrate the fourth lower dielectric layer 190.

[0136] refer to Figure 14 , Figure 13 The initial unit array structure can be joined to form on Figure 8 The peripheral circuit structure PS is on the substrate 200. Therefore, the first bonding pad BP1 of the peripheral circuit structure PS can be bonded to the second bonding pad BP2 of the preliminary cell array structure.

[0137] When the first bonding pad BP1 is bonded to the second bonding pad BP2, the preliminary cell array structure can be inverted. For example, the sub-substrate 100 of the preliminary cell array structure can be located at the top.

[0138] refer to Figure 14 and Figure 15 The sub-substrate 100 can be removed, exposing the top surface of the preliminary vertical structure pVS. For example, the removal of the sub-substrate 100 can be achieved by at least one process selected from polishing, planarization, dry etching, and wet etching. The term "exposed" (or "exposed" or similar terms) may be used herein to describe relationships between components and / or to refer to intermediate processes in the manufacture of semiconductor devices, but may not require the exposure of specific components in the finished device. Similarly, the term "not exposed" may be used to describe relationships between components and / or to refer to intermediate processes in the manufacture of semiconductor devices, but may not require specific components to be unexposed in the finished device.

[0139] An isotropic etching process can be performed on the upper portion of the preliminary interlayer dielectric layer 110 and the data storage layer DSL. The upper portion of the data storage layer DSL can be etched to form a data storage pattern DSP. Furthermore, the upper portion of the vertical channel layer VL can be exposed. The data storage pattern DSP may include a tunnel dielectric pattern TIP, a charge storage pattern CIP, and a barrier dielectric pattern BKP.

[0140] The isotropic etching process for the data storage layer DSL can use an etching formulation that is selective for etching relative to the data storage layer DSL. The etching process for the data storage layer DSL may include isotropically etching the barrier dielectric layer (BKL), the charge storage layer (CIL), and the tunnel dielectric layer (TIL).

[0141] refer to Figure 16 A semiconductor material can be coated onto the preliminary semiconductor layer 120 and the preliminary vertical structure pVS. This coating of semiconductor material allows the preliminary semiconductor layer 120 to be connected to the preliminary vertical structure pVS. For example, the semiconductor material may include polycrystalline silicon.

[0142] An etch-back process can be performed on the initial semiconductor layer 120. This etch-back process can be performed to expose the top surface pVI_U of the initial vertical dielectric pattern pVI.

[0143] refer to Figure 16 and Figure 17 The upper part of the initial vertical dielectric pattern pVI can be partially and selectively removed. Removing the upper part of the initial vertical dielectric pattern pVI can form the vertical dielectric pattern VI.

[0144] The initial semiconductor layer 120 can be removed, and a portion of the vertical channel layer VL can also be removed. Removing the initial semiconductor layer 120 exposes the top surface of the first interlayer dielectric layer 130. Removing a portion of the vertical channel layer VL partially exposes the upper sidewall of the data storage pattern DSP. Removing a portion of the vertical channel layer VL forms the initial vertical channel pattern pVP. For example, a stripping process can be used to remove the initial semiconductor layer 120 and a portion of the vertical channel layer VL.

[0145] refer to Figure 17 and Figure 18 A vertical channel pattern (VP) and a source conductive pattern (SCP) can be formed. The vertical channel pattern (VP) can be formed by coating a semiconductor material onto the initial vertical channel pattern (VP). The vertical channel pattern (VP) can extend to horizontally adjoin the first interlayer dielectric layer 130 and the upper conductor 140. A reference can be formed on the inner wall of the vertical channel pattern (VP). Figure 7 The groove GR is discussed. When the vertical channel pattern VP is formed, a vertical structure VS can be formed.

[0146] The source-conductive pattern SCP can be formed to be electrically connected to the vertical structure VS. The source-conductive pattern SCP may include a first portion SCP_a located on the first interlayer dielectric layer 130 and a second portion SCP_b protruding from the first portion SCP_a toward the vertical structure VS. The second portion SCP_b may fill the space in the vertical structure VS.

[0147] Return to reference Figure 6A An upper dielectric layer 310 can be formed on the source conductive pattern SCP. An upper pathway VA can be formed to penetrate the upper dielectric layer 310.

[0148] Routing pads (PADs) can be formed on the upper dielectric layer 310. The routing pads (PADs) can be electrically connected to the upper path (VA). A cover dielectric layer 320 can be formed to cover the routing pads (PADs).

[0149] Semiconductor devices according to some embodiments of the present invention may include an upper conductor located on a stacked structure. The upper conductor may be configured as the gate electrode of an eraser transistor that causes gate-induced drain leakage (GIDL) on the stacked structure, and the thickness of the upper conductor may be greater than the thickness of each conductive pattern in the stacked structure. For example, because the upper conductor is formed to be thicker than the conductive patterns, the efficiency of gate-induced drain leakage can be improved and the reliability of the semiconductor device can be enhanced.

[0150] Furthermore, a gap-fill pattern adjacent to the upper conductor can be formed during the formation of the upper conductor. To form a stacked structure, the gap-fill pattern can be used as an etch stop layer for etching molded structures with a large aspect ratio, and thus can improve reliability in semiconductor device manufacturing.

[0151] Although the invention has been described in conjunction with some embodiments of the inventive concept shown in the accompanying drawings, those skilled in the art will understand that various changes and modifications can be made without departing from the technical spirit and essential characteristics of the inventive concept. It will be apparent to those skilled in the art that various substitutions, modifications, and alterations can be made without departing from the scope and spirit of the inventive concept.

Claims

1. A semiconductor device, the semiconductor device comprising: substrate; A stacked structure comprising alternatingly stacked dielectric patterns and conductive patterns on a substrate in a vertical direction perpendicular to the surface of the substrate; A source conductive pattern is located on the stacked structure; An upper conductor, wherein the upper conductor is located between the stacked structure and the source conductive pattern; as well as Multiple vertical structures extend through the stacked structure and the upper conductor in the vertical direction and are electrically connected to the source conductive pattern. Wherein, the thickness of the upper conductor in the vertical direction is greater than the thickness of each of the plurality of conductive patterns in the vertical direction. Each of the plurality of vertical structures includes: a lower portion extending through the stacked structure; and an upper portion connected to the lower portion and extending through the upper conductor. Wherein, the minimum width of the upper part in the horizontal direction parallel to the surface of the substrate is greater than the minimum width of the lower part in the horizontal direction.

2. The semiconductor device according to claim 1, wherein, The thickness of the upper conductor in the vertical direction has a value of about 20 nm to about 1 μm.

3. The semiconductor device according to claim 1, wherein, Each of the plurality of conductive patterns comprises a metallic material, and The upper conductor comprises polycrystalline silicon.

4. The semiconductor device according to claim 1, wherein, The source conductive pattern includes: The first part, the first part being located on the upper conductor; and The second part is connected to the first part and extends through at least a portion of the upper conductor. The second part is connected to the plurality of vertical structures.

5. The semiconductor device according to claim 4, wherein, The second part is horizontally adjacent to the upper conductor.

6. The semiconductor device according to claim 4, wherein, When viewed from above, the second portion at least partially overlaps with the plurality of vertical structures, and The plurality of vertical structures extend around the second part.

7. The semiconductor device according to claim 4, wherein, Relative to the surface of the substrate, the top surface of the uppermost conductive pattern among the plurality of conductive patterns is at a lower height than the bottom surface of the second portion.

8. The semiconductor device according to claim 1, wherein, Each of the plurality of vertical structures includes: Vertical dielectric pattern; A vertical channel pattern extending around the sidewalls and top surface of the vertical dielectric pattern; and A data storage pattern that extends around the sidewall of the vertical channel pattern.

9. The semiconductor device according to claim 8, wherein, Relative to the surface of the substrate, the uppermost end of the vertical channel pattern and the uppermost end of the data storage pattern are higher than the top surface of the upper conductor in the vertical direction.

10. The semiconductor device according to claim 8, wherein, The source conductive pattern includes impurities of a first concentration having a first conductivity type. The vertical channel pattern includes impurities of a second concentration having the first conductivity type, and The first concentration is greater than the second concentration.

11. The semiconductor device of claim 8, further comprising a plurality of horizontal dielectric patterns located between the plurality of conductive patterns and the data storage pattern. in, The upper conductor is in contact with the data storage pattern.

12. The semiconductor device according to claim 11, wherein, Each of the plurality of horizontal dielectric patterns includes a metal oxide containing a first metal, and The upper conductor does not contain the first metal.

13. The semiconductor device of claim 1, further comprising a separator extending vertically through the stacked structure. in, The dividing structure extends through the upper conductor.

14. A semiconductor device, said semiconductor device comprising: The peripheral circuit structure includes a substrate, a plurality of peripheral circuits integrated on the substrate, and a plurality of first bonding pads electrically connected to the plurality of peripheral circuits. as well as A cell array structure, the cell array structure including a plurality of second bonding pads bonded to the plurality of first bonding pads, The cell array structure includes: a stacked structure comprising a plurality of dielectric patterns and a plurality of conductive patterns alternately stacked in a vertical direction perpendicular to the surface of the substrate; a source conductive pattern located on the stacked structure; an upper conductor located between the stacked structure and the source conductive pattern; a plurality of vertical structures extending through the stacked structure and the upper conductor and electrically connected to the source conductive pattern; a plurality of bit lines extending across the stacked structure and electrically connected to the vertical structures; a first interlayer dielectric layer located between the upper conductor and the source conductive pattern; and a second interlayer dielectric layer located between the upper conductor and the stacked structure. Wherein, the thickness of the upper conductor in the vertical direction is greater than the thickness of each of the plurality of conductive patterns in the vertical direction. Each of the plurality of vertical structures includes: a lower portion extending through the stacked structure; and an upper portion connected to the lower portion and extending through the upper conductor. Wherein, the minimum width of the upper part in the horizontal direction parallel to the surface of the substrate is greater than the minimum width of the lower part in the horizontal direction, and The upper conductor is configured as the gate electrode of the erase control transistor, which is configured to cause gate-induced drain leakage.

15. The semiconductor device according to claim 14, wherein, Each of the plurality of conductive patterns comprises a metallic material, and The upper conductor comprises polycrystalline silicon.

16. The semiconductor device of claim 14, wherein, The source conductive pattern includes: The first part, the first part being located on the upper conductor; and The second part is connected to the first part and extends through at least a portion of the upper conductor. The second part is connected to the plurality of vertical structures.

17. The semiconductor device according to claim 14, wherein, Each of the plurality of vertical structures includes: Vertical dielectric pattern; A vertical channel pattern extending around the sidewalls and top surface of the vertical dielectric pattern; and A data storage pattern that extends around the sidewall of the vertical channel pattern.

18. The semiconductor device of claim 17, further comprising a plurality of horizontal dielectric patterns located between the plurality of conductive patterns and the data storage pattern. in, The upper conductor is in contact with the data storage pattern.

19. An electronic system comprising: A semiconductor device, the semiconductor device comprising a substrate and a cell array structure located on the substrate; as well as A controller, electrically connected to the semiconductor device via input / output pads, controls the semiconductor device. The unit array structure includes: a stacked structure comprising a plurality of dielectric patterns and a plurality of conductive patterns alternately stacked on the substrate in a vertical direction perpendicular to the surface of the substrate; a plurality of vertical structures extending through the stacked structure; a source conductive pattern located on the stacked structure and electrically connected to the plurality of vertical structures; and an upper conductor located between the stacked structure and the source conductive pattern. Wherein, the thickness of the upper conductor in the vertical direction is greater than the thickness of each of the plurality of conductive patterns in the vertical direction. Each of the plurality of vertical structures includes: a lower portion extending through the stacked structure; and an upper portion connected to the lower portion and extending through the upper conductor. Wherein, the minimum width of the upper part in the horizontal direction parallel to the surface of the substrate is greater than the minimum width of the lower part in the horizontal direction.

20. The electronic system according to claim 19, wherein, The cell array structure also includes: Multiple bit lines extend across the stacked structure and are electrically connected to the multiple vertical structures; A first interlayer dielectric layer is located between the upper conductor and the source conductive pattern; and A second interlayer dielectric layer is located between the upper conductor and the stacked structure. The upper conductor is the gate electrode of the erase control transistor, which is configured to cause gate-induced drain leakage.

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