Negative feedback variable resistance device and negative feedback charging circuit

Abstract

The invention provides a negative feedback variable resistance device and a negative feedback charging circuit, and relates to the technical field of semiconductor devices, and the negative feedback variable resistance device comprises an MOS structure main body, a grid electrode of the MOS structure main body is distributed in a #-shaped frame, and an active region is intensively formed in a central region of the #-shaped frame and serves as a positive electrode of the negative feedback variable resistance device; the peripheral doped region is distributed in the gap region of the #-shaped frame and surrounds the positive electrode, the peripheral doped region comprises a near-center doped region adjacent to the positive electrode and a far-center doped region adjacent to the near-center doped region and close to the edge of the #-shaped frame, and a PN junction structure surrounding the positive electrode is formed at the junction of the near-center doped region and the far-center doped region; and all the grids and the peripheral far-center doped region are interconnected to form a negative electrode of the negative feedback variable resistance device. The beneficial effects are that negative feedback resistance characteristics of low bias voltage, low resistance and high bias voltage and high resistance can be realized, dynamic requirements of charging and discharging control and other scenes on the resistor can be precisely met, and resistance-capacitance coordinated regulation and control can be realized without an extra circuit.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a negative feedback variable resistor device and a negative feedback charging circuit. Background Technology

[0002] In electronic circuits, resistors are one of the core components, widely used in signal conditioning, charge and discharge control, and other scenarios. Especially in circuits that require dynamic switching of operating states (such as capacitor charge and discharge control circuits), dynamic requirements are placed on the resistance value: during the charging phase, the resistor needs to maintain a high resistance value to ensure that all external charge can be fully charged into the capacitor, preventing charge leakage through the resistor and reducing charging efficiency; while during the discharging phase, the resistor needs to maintain a low resistance value to quickly release the charge stored in the capacitor, reduce RC time delay, and improve the state switching speed of subsequent circuits.

[0003] In existing technologies, conventional resistors have fixed resistance values, which cannot meet the aforementioned dynamic requirements. To meet this requirement, existing solutions typically require the design of complex auxiliary circuits to detect the charging and discharging state, and then use switching circuits to switch resistors of different resistance values ​​to achieve dynamic resistance adjustment. However, such solutions not only lead to redundant circuit structures and an increased number of components, but also increase the risk of failure due to the increased connection nodes of multiple components, which is detrimental to the miniaturization and high reliability design of the circuit.

[0004] Some existing solutions attempt to achieve this through, for example Figure 1 The multi-device combination shown forms a negative feedback mechanism, which indirectly adjusts the gate voltage by using voltage changes, thereby controlling the current change. However, it is essentially an indirect control, which has a response delay in signal transmission and is difficult to adapt to high-speed charging and discharging scenarios. On the other hand, its function depends on the coordinated work of multiple devices. Once any device deviates, the entire negative feedback mechanism will fail, and its reliability is limited by the coordination accuracy between devices.

[0005] Furthermore, in special scenarios such as high-reliability 2-port devices, due to the strict requirements for structural simplification and reliability, complex auxiliary circuits or multi-device combination schemes are not allowed in the design. However, the existing technology lacks a solution that can achieve dynamic resistance switching with a single device, which limits the improvement of circuit performance.

[0006] Therefore, there is an urgent need for a negative feedback resistor device that is simple in structure, highly reliable, and capable of dynamic resistance adjustment, in order to meet the dynamic requirements of scenarios such as charge and discharge control, and to adapt to the design requirements of highly reliable 2-port devices. Summary of the Invention

[0007] To address the problems existing in the prior art, the present invention provides a negative feedback variable resistor device, comprising: The MOS structure body has a gate distributed in a grid-like frame, and the active region of the MOS structure body is concentrated in the central region of the grid-like frame and serves as the positive electrode of the negative feedback variable resistor device. The peripheral doped region is distributed in the gap area of ​​the grid frame and surrounds the positive electrode. The peripheral doped region includes a near-center doped region adjacent to the positive electrode and a far-center doped region adjacent to the near-center doped region and close to the edge of the grid frame. The boundary between the near-center doped region and the far-center doped region forms a PN junction structure surrounding the positive electrode. All of the gates and the surrounding far-center doped regions are interconnected to form the negative electrode of the negative feedback variable resistor device.

[0008] Preferably, the positive electrode and the near-center doped region are semiconductor implantation regions of a first conductivity type, and the far-center doped region is a semiconductor implantation region of a second conductivity type. The first conductivity type and the second conductivity type are opposite semiconductor doping types.

[0009] Preferably, the main body of the MOS structure is a depletion-type NMOS, the corresponding positive electrode and the near-center doped region are N+ type semiconductor injection regions, and the far-center doped region is a P+ type semiconductor injection region.

[0010] Preferably, the MOS structure further includes a substrate, on which the gate region, the positive electrode, and the peripheral doped region are formed, and the substrate is an N-type implantation region.

[0011] Preferably, the main body of the MOS structure is a depletion-type PMOS, the corresponding positive electrode and the near-center doped region are P+ type semiconductor injection regions, and the far-center doped region is an N+ type semiconductor injection region.

[0012] Preferably, the MOS structure further includes a substrate, on which the gate region, the positive electrode, and the peripheral doped region are formed, and the substrate is a P-type implantation region.

[0013] The present invention also provides a negative feedback charging circuit, including an energy storage capacitor and a subsequent circuit connected in parallel across the energy storage capacitor, wherein the aforementioned negative feedback variable resistor is also connected in parallel across the energy storage capacitor.

[0014] Preferably, one end of the negative feedback variable resistor is connected to a charging switch.

[0015] The above technical solution has the following advantages or beneficial effects: 1) By combining the MOS structure with the surrounding PN junction structure, a dual control mechanism of gate surface modulation and PN junction side modulation is realized, which can achieve negative feedback resistance characteristics of low bias voltage and low resistance and high bias voltage and high resistance. It can accurately meet the dynamic requirements of resistance in scenarios such as charge and discharge control, and achieve resistance and capacitance coordinated control without additional circuitry. 2) The MOS structure and the all-around PN junction structure are integrated into a single device, which can work through only the positive and negative 2-port structure, eliminating the failure risk of existing multi-device collaboration, and adapting to the miniaturization and integration design requirements of high-reliability 2-port devices. 3) The resistance value regulation of the negative feedback variable resistor device of the present invention is based on the physical extension of the gate depletion layer and the PN junction depletion layer, which is a direct regulation mechanism. This reduces the response delay to the nanosecond level, making it suitable for high-speed charging and discharging, high-frequency signal conditioning and other scenarios. At the same time, by adjusting parameters such as the grid gate size and doping concentration, the negative feedback slope of the resistance value as the bias voltage changes can be precisely customized to meet the different requirements of different circuits for regulation accuracy. Attached Figure Description

[0016] Figure 1 A schematic diagram illustrating the negative feedback mechanism formed by combining existing multiple devices; Figure 2 A schematic diagram of a negative feedback variable resistor device is shown in a preferred embodiment of the present invention. Figure 3 for Figure 2 A cross-sectional view along the AA direction; Figure 4 for Figure 2 A cross-sectional view along the BB direction; Figure 5 This is a schematic diagram of a negative feedback charging circuit in a preferred embodiment of the present invention. Detailed Implementation

[0017] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. The present invention is not limited to this embodiment; other embodiments that conform to the spirit of the present invention may also fall within the scope of the present invention.

[0018] In a preferred embodiment of the present invention, based on the aforementioned problems existing in the prior art, a negative feedback variable resistor device is provided, aiming to solve the problems that fixed resistors in the prior art cannot meet the dynamic requirements of circuits, and that traditional composite circuit structures are complex and have low reliability. Figures 2 to 4 As shown, the negative feedback variable resistor device of the present invention includes: The MOS structure body has a gate 1 distributed in a grid-like frame. The active region of the MOS structure body is concentrated in the central region of the grid-like frame and serves as the positive electrode 2 of the negative feedback variable resistor device. The peripheral doped region is distributed in the gap area of ​​the grid-shaped frame and surrounds the positive electrode. The peripheral doped region includes the near-center doped region 3 which is adjacent to the positive electrode and the far-center doped region 4 which is adjacent to the near-center doped region 3 and close to the edge of the grid-shaped frame. The PN junction structure surrounding the positive electrode is formed at the junction of the near-center doped region 3 and the far-center doped region 4. All gates 1 and the surrounding far-center doped regions 4 are interconnected to form the negative electrode 5 of the negative feedback variable resistor device.

[0019] In a preferred embodiment of the present invention, the positive electrode 2 and the near-center doped region 3 are semiconductor implantation regions of the first conductivity type, and the far-center doped region 4 is a semiconductor implantation region of the second conductivity type. The first conductivity type and the second conductivity type are opposite semiconductor doping types.

[0020] Specifically, the negative feedback variable resistor device of the present invention integrates a surrounding PN junction structure on the basis of a MOS structure body, and is implemented using a nine-grid surrounding layout. The MOS structure body includes a gate 1, an active region, and a substrate 6. The gate 1 adopts a grid-shaped frame design, which forms the skeleton of the nine-grid layout, dividing the device plane into a typical nine-grid region consisting of a central region and eight gap regions surrounding the central region.

[0021] Furthermore, the active region is the core of carrier transport in the main body of the MOS structure, and is concentrated in the central area of ​​the nine-square grid to form the positive electrode 2 of the negative feedback variable resistor device of the present invention; the substrate 6 serves as the base of the main body of the MOS structure, supporting the grid-shaped gate 1, the central positive electrode 2 and the subsequent peripheral doped regions, providing a basic channel for carrier transport.

[0022] To overcome the limitations of traditional MOS structures that rely on a single gate for control, this invention integrates a surrounding PN junction structure within the gaps of a nine-grid layout, specifically achieved through peripheral doped regions. These peripheral doped regions surround the central positive electrode 2 and are divided into a near-center doped region 3 adjacent to the central positive electrode 2 (located in the inner ring of the nine-grid layout) and a far-center doped region 4 near the edge of the grid-shaped gate 1 (located in the outer ring of the nine-grid layout). The near-center doped region 3 shares the same conductivity type as the central positive electrode 2, representing an extension of the active region of the MOS structure, and together with the substrate 6, forms the carrier channels of the MOS structure. The far-center doped region 4 has the opposite conductivity type to the near-center doped region 3, and together they form a closed surrounding PN junction at the boundary between the inner and outer rings of the nine-grid layout.

[0023] Furthermore, all the grid-shaped gates 1 are electrically connected to the peripheral far-center doped region 4 to form the negative electrode 5 of the negative feedback variable resistor device of the present invention. Through the nine-grid surrounding layout, the central positive electrode 2 is surrounded in all directions by the near-center doped region 3, the surrounding PN junction and the grid-shaped gates 1.

[0024] Based on the above structural design, dual synergistic control of surface modulation and PN junction modulation is achieved to realize the negative feedback resistance characteristics of low bias voltage and high bias voltage. Surface modulation is implemented based on the grid-shaped gate 1 of the MOS structure, which is an inherent control characteristic of the MOS structure. When a bias voltage is applied between the positive and negative electrodes of the negative feedback variable resistor device of this invention, an electric field is formed between the grid-shaped gate 1 and the substrate 6. This electric field controls the thickness of the depletion layer below the gate, thus achieving surface modulation. Consequently, under low bias voltage, the electric field strength is weak, and the depletion layer below the gate is thin, preventing significant compression of the carrier channels, allowing carriers to pass smoothly through the active region channels of the MOS structure. Under high bias voltage, the electric field strength is significantly enhanced, and the depletion layer below the gate is greatly thickened, compressing the carrier channels extending from the central positive electrode 2 from the device surface dimension, reducing the carrier transport space.

[0025] The above-mentioned PN junction modulation is based on a wraparound PN junction, which is an additional control dimension on the basis of the main MOS structure. Since the conductivity types of the far-center doped region 4 and the near-center doped region 3 are opposite, the formed wraparound PN junction will adjust the degree of reverse bias with the change of the bias voltage between the positive and negative electrodes. Thus, under low bias voltage, the degree of reverse bias of the PN junction is weak, and its depletion layer range is small, limited only to the vicinity of the junction region, and will not affect the conduction of the carrier channel. Under high bias voltage, the degree of reverse bias of the PN junction is intensified, and the depletion layer extends towards the near-center doped region 3 (carrier channel side), squeezing the carrier channel from the side dimension of the device, and further reducing the carrier transport space.

[0026] Furthermore, leveraging the all-around encirclement characteristic of the nine-grid layout, both modulation effects are weak at low bias voltages, resulting in fully open carrier channels and low-resistance device characteristics. At high bias voltages, both modulation effects are simultaneously enhanced, squeezing the carrier channels from the surface and sides, ultimately closing the channels and resulting in high-resistance device characteristics. This achieves the negative feedback resistance variation characteristics of low resistance at low bias voltage and high resistance at high bias voltage. It is evident that the resistance control of this invention is based on the physical extension of the gate depletion layer and the PN junction depletion layer, constituting a direct control mechanism. This shortens the response delay to the nanosecond level, making it suitable for scenarios such as high-speed charging and discharging and high-frequency signal conditioning. Simultaneously, by adjusting parameters such as the grid gate size and doping concentration, the negative feedback slope of the resistance change with bias voltage can be precisely customized, meeting the differentiated control precision requirements of various circuits.

[0027] Furthermore, this invention supports both depletion-type NMOS and PMOS structures, which can be adapted to circuit scenarios with positive / negative power supply respectively. The basic two-finger structure can be expanded into a single-finger or multi-finger structure, adapting to scenarios such as low-power signal circuits and high-power circuits respectively. In addition to charge and discharge control, it can also be directly applied to negative feedback circuits such as VGA gain adjustment, current suppression, and oscillator frequency stabilization, effectively solving the problems of poor linearity of traditional fixed resistors and the single function of traditional MOS devices, and significantly expanding the application boundaries of negative feedback resistors.

[0028] Example 1 In this embodiment, the main body of the MOS structure is a depletion-type NMOS, the corresponding positive electrode 2 and near-center doped region 3 are N+ type semiconductor injection regions, and the far-center doped region 4 is a P+ type semiconductor injection region.

[0029] The MOS structure also includes a substrate 6, on which the gate 1, the positive electrode 2 and the peripheral doped region are formed. The substrate 6 is an N-type implantation region.

[0030] Example 2 In this embodiment, the main body of the MOS structure is a depletion-type PMOS, the corresponding positive electrode 2 and the near-center doped region 3 are P+ type semiconductor injection regions, and the far-center doped region 4 is an N+ type semiconductor injection region.

[0031] The MOS structure also includes a substrate 6, on which the gate 1, the positive electrode 2 and the peripheral doped region are formed. The substrate 6 is a P-type implantation region.

[0032] The present invention also provides a negative feedback charging circuit, including an energy storage capacitor C and a subsequent circuit connected in parallel across the energy storage capacitor C. The energy storage capacitor C is further connected in parallel with the aforementioned negative feedback variable resistor device R.

[0033] In a preferred embodiment of the present invention, one end of the negative feedback variable resistor device R is connected to the charging switch K.

[0034] Specifically, in this embodiment, when the charging switch K is just closed, the charging voltage is input, the bias voltage across the energy storage capacitor C is low, and the negative feedback variable resistor device R is in a low-resistance state. At this time, the energy storage capacitor C is rapidly pre-charged through the negative feedback variable resistor device R. As charging progresses, the voltage of the energy storage capacitor C increases, and the resistance of the negative feedback variable resistor device R increases sharply to near infinity. At this time, the negative feedback variable resistor device R is approximately open-circuited, and all the charging current flows to the energy storage capacitor C without shunt leakage, ensuring that the capacitor is fully charged. After the energy storage capacitor C is fully charged, the negative feedback variable resistor device R maintains a high-resistance state to prevent the energy storage capacitor C from leaking through the resistor. At the same time, the charging signal can directly supply power to the subsequent circuit.

[0035] When the charging switch is turned off, the resistance of the negative feedback variable resistor device drops to near zero, returning to a low-resistance state. This allows for rapid release of capacitor charge, significantly shortens the RC time delay, and greatly improves the state switching speed of subsequent circuits. RC-resistance coordinated control can be achieved without additional circuitry.

[0036] The above description is merely a preferred embodiment of the present invention and does not limit the implementation and protection scope of the present invention. Those skilled in the art should realize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present invention.

Claims

1. A negative feedback variable resistor device, characterized in that, include: The MOS structure body has a gate distributed in a grid-like frame, and the active region of the MOS structure body is concentrated in the central region of the grid-like frame and serves as the positive electrode of the negative feedback variable resistor device. The peripheral doped region is distributed in the gap area of ​​the grid frame and surrounds the positive electrode. The peripheral doped region includes a near-center doped region adjacent to the positive electrode and a far-center doped region adjacent to the near-center doped region and close to the edge of the grid frame. The boundary between the near-center doped region and the far-center doped region forms a PN junction structure surrounding the positive electrode. All of the gates and the surrounding far-center doped regions are interconnected to form the negative electrode of the negative feedback variable resistor device.

2. The negative feedback variable resistor device according to claim 1, characterized in that, The positive electrode and the near-center doped region are semiconductor implantation regions of the first conductivity type, and the far-center doped region is a semiconductor implantation region of the second conductivity type. The first conductivity type and the second conductivity type are opposite semiconductor doping types.

3. The negative feedback variable resistor device according to claim 2, characterized in that, The main body of the MOS structure is a depletion-type NMOS, and the corresponding positive electrode and the near-center doped region are N+ type semiconductor injection regions, while the far-center doped region is a P+ type semiconductor injection region.

4. The negative feedback variable resistor device according to claim 3, characterized in that, The MOS structure also includes a substrate, on which the gate, the positive electrode and the peripheral doped region are formed, and the substrate is an N-type implantation region.

5. The negative feedback variable resistor device according to claim 2, characterized in that, The main body of the MOS structure is a depletion-type PMOS, and the corresponding positive electrode and the near-center doped region are P+ type semiconductor injection regions, while the far-center doped region is an N+ type semiconductor injection region.

6. The negative feedback variable resistor device according to claim 5, characterized in that, The MOS structure also includes a substrate, on which the gate, the positive electrode and the peripheral doped region are formed, and the substrate is a P-type implantation region.

7. A negative feedback charging circuit, comprising an energy storage capacitor and a subsequent circuit connected in parallel across the energy storage capacitor, characterized in that, The energy storage capacitor is further connected in parallel with a negative feedback variable resistor device as described in any one of claims 1-6.

8. The negative feedback charging circuit according to claim 7, characterized in that, One end of the negative feedback variable resistor is connected to a charging switch.

Images