Thin film transistor structure with ITO in contact with IGZO and preparation method of thin film transistor structure

Abstract

The invention relates to the technical field of thin film transistors, in particular to a thin film transistor structure with ITO making contact with IGZO and a preparation method of the thin film transistor structure. The second metal layer is prepared behind the first insulating layer, and then the first electrode layer is used for protecting the contact area of the active layer and the second metal layer, so that the damage of the second metal layer to a back channel of the active layer in a traditional thin film transistor structure can be effectively avoided, and the short circuit problem caused by corrosion of a metal source and a metal drain is solved. In addition, the use of the first electrode layer improves the stability of the characteristics of the thin film transistor, especially in the aspect of avoiding copper diffusion and metal corrosion. According to the structural design, the number of additional photomasks is not increased, the production efficiency can be improved, the production cost is reduced, and the product stability and yield are effectively improved.

Description

Technical Field

[0001] This invention relates to the field of thin-film transistor technology, specifically to a thin-film transistor structure with ITO contact IGZO and its fabrication method. Background Technology

[0002] Thin-film transistors (TFTs) are the core units of semiconductor devices such as display panels, and their structural stability and electrical characteristics directly affect the overall performance of the devices. Back-channel etched (BCE) TFTs are widely used in the industry due to their advantages such as simple manufacturing process and controllable cost. However, traditional BCE TFT structures have the following key technical problems: IGZO back channel damage, short circuit problems caused by Cu diffusion and corrosion, and the negative impact of SD materials on TFT characteristics.

[0003] To address the aforementioned issues, there is an urgent need for a BCE TFT structure design that can simultaneously resolve back channel damage, Cu diffusion short circuits, and optimize contact characteristics without increasing process complexity. Summary of the Invention

[0004] To address the above technical problems, this invention provides a thin-film transistor structure with ITO contact IGZO and its fabrication method.

[0005] A thin-film transistor structure with ITO contact IGZO includes a glass substrate on which a first metal layer (1) and a first insulating layer (2) covering the first metal layer (1) are sequentially disposed. A first electrode layer (4) and an active layer (5) are disposed on the first metal layer (1), with the first electrode layer (4) in direct contact with the active layer (5). A second metal layer (3) is disposed and connected to the active layer (5) through an electrical connection with the first electrode layer (4), so that the active layer (5) is not in direct contact with the second metal layer (4). A second insulating layer (6) is disposed on the active layer (5) and the second metal layer (4), and a second electrode layer (7) is disposed on the second insulating layer (6), with the second electrode layer (7) being electrically connected to the first metal layer (1) through a contact hole penetrating the second insulating layer (6) and the first insulating layer (2).

[0006] Furthermore, a third insulating layer (8) is provided on the upper part of the second insulating layer (6).

[0007] Furthermore, the second electrode layer (7) is electrically connected to the first metal layer (1) through a contact hole penetrating the third insulating layer (8), the second insulating layer (6) and the first insulating layer (2).

[0008] Furthermore, the second electrode layer (7) is electrically connected to the second metal layer (3) and the first electrode layer (4) respectively through contact holes penetrating the insulating layer.

[0009] Furthermore, the first metal layer (1) is a gate metal layer, the first insulating layer (2) is a gate insulating layer, the second metal layer (3) is a source / drain metal layer, and the second insulating layer (6) is a gate insulating layer.

[0010] Furthermore, the first electrode layer (4) is a pixel electrode layer, and the second electrode layer (7) is a common electrode layer.

[0011] Furthermore, the first electrode layer (4) is a common electrode layer, and the second electrode layer (7) is a pixel electrode layer.

[0012] Furthermore, the second insulating layer (6) serves as the dielectric of the pixel capacitor.

[0013] Furthermore, the first metal layer (1) is composed of Ti / Cu, the first insulating layer (2) is composed of SiNx / SiO2, the first electrode layer (4) is composed of ITO, the active layer (5) is composed of IGZO, and the second electrode layer (7) is composed of ITO.

[0014] Furthermore, the second metal layer (3) is composed of MoNb / Cu, and the second insulating layer (6) is composed of SiO2 / SiNx. Furthermore, the second metal layer (3) is composed of Ti / Cu, and the second insulating layer (6) is composed of SiO2.

[0015] The present invention further protects the method for fabricating transistor structures, including the following methods: Based on the transistor structure, a first metal layer (1), a second metal layer (3), a first electrode layer (4), an active layer (5), and a second electrode layer (7) are deposited using physical vapor deposition, and patterned by coating, exposure, development, wet etching, and photoresist stripping. A first insulating layer (2), a second insulating layer (6), and a third insulating layer (8) are deposited using chemical vapor deposition. Contact holes are drilled on the first metal layer (1), the second metal layer (3), and the first electrode layer (4) through the steps of coating, exposure, development, dry etching, and photoresist stripping.

[0016] Beneficial effects This invention achieves an ITO-contact IGZO TFT structure by adjusting the deposition order of the electrode layers without increasing the number of photomasks. By changing the order of the active layer, electrode layer, and source / drain metal layers, the etching of the active layer during electrode layer patterning can be effectively avoided. It also avoids damage to the back channel of the active layer during source / drain metal layer patterning, as is common in traditional BCE (Back Channel Etching) structures. This reduces the risk of TFT characteristic conductor shift or negative shift during the manufacturing process. The ITO-IGZO contact avoids metal contact between the IGZO and the source / drain electrodes. When IGZO contacts a metal (such as copper), oxygen in the IGZO combines with metal atoms, increasing oxygen vacancies. This increase in oxygen vacancies leads to an increase in donor levels in the IGZO band structure and also increases the risk of hydrogen diffusion into the IGZO. The combination of these factors increases the risk of negative shift in TFT characteristics. The ITO-contact IGZO TFT structure in this patent effectively avoids this problem. Copper ions readily diffuse within the insulating layer and cannot form a dense oxide layer to prevent further diffusion. Therefore, copper diffusion often leads to short circuits between metal layers in copper-interconnected IGZO TFTs. Specifically, the short circuit originates at the tip of the metal layer between the gate metal layer and the source / drain metal layer. In this patented design, the source / drain metal is connected to the ITO electrode layer, which can transfer the tip to the ITO, thus avoiding the problem of copper ion diffusion and reducing the risk of short circuits between metal layers. Attached Figure Description

[0017] Figure 1 : TFT device structure diagram of Example 1; Figure 2 : TFT device structure diagram of Example 2; Figure 3 : TFT device structure diagram of Example 3; Figure 4 : TFT device structure diagram of Example 4.

[0018] Reference numerals: 1-First metal layer; 2-First insulating layer; 3-Second metal layer; 4-First electrode layer; 5-Active layer; 6-Second insulating layer; 7-Second electrode layer; 8-Third insulating layer. Detailed Implementation

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Example 1 The patterning process in Example 1 is as follows: Figure 1 As shown, the specific steps are as follows: Step 1: Gate metal layer fabrication: The first metal layer 1 is deposited on the glass substrate by physical vapor deposition; excess metal is removed by coating photoresist, exposure, development, and wet etching. After stripping the photoresist, the patterned first metal layer 1 is obtained. The first metal layer is composed of Ti / Cu.

[0021] Step 2: Gate insulating layer preparation: The first insulating layer 2 is deposited on the surface of the first metal layer 1 by chemical vapor deposition. The first insulating layer 2 is composed of SiNx / SiO2.

[0022] Step 3: Source and drain metal layer preparation: A second metal layer 3 is deposited on the surface of the first insulating layer 2 using physical vapor deposition; after coating with photoresist, exposure, development, and wet etching patterning, the photoresist is stripped off to obtain the second metal layer 3, which is composed of MoNb / Cu.

[0023] Step 4: Deposit the first electrode layer 4 on the surface of the first insulating layer 2 and the second metal layer 3 using physical vapor deposition; after coating with photoresist, exposure, development, wet etching patterning, and stripping the photoresist, anneal at 200-250℃ for 30-60 min to obtain the first electrode layer 4, which is composed of ITO.

[0024] Step 5: Deposit active layer 5 on the surface of first electrode layer 4 and first insulating layer 2 using physical vapor deposition; after coating with photoresist, exposure, development, and dry etching patterning, strip the photoresist to obtain active layer 5, which is composed of IGZO.

[0025] Step 6: Deposit the second insulating layer 6 using chemical vapor deposition. The second insulating layer 6 is composed of SiO2 / SiNx.

[0026] Step 7: Through coating, exposure, development, dry etching, and photoresist stripping steps, as shown above the first metal layer 1... Figure 1 Holes are drilled as shown so that the second electrode layer 7 can overlap with the first metal layer 1 during subsequent deposition.

[0027] Step 8: Deposit the second electrode layer 7 using physical vapor deposition. The second electrode layer 7 is made of ITO. After coating with photoresist, exposure, development, and wet etching patterning, the second electrode layer 7 and the first metal layer 1 are connected through contact holes to obtain the TFT device.

[0028] Example 2 The patterning process in Example 2 is as follows: Figure 2 As shown, the specific steps are as follows: Steps one through six are the same as in Example 1. The difference is that the patterning process in Example 2 is as follows: Figure 2 As shown.

[0029] Step 7: Through coating, exposure, development, dry etching, and photoresist stripping steps, as shown above the first metal layer 1... Figure 2 Holes are drilled as shown so that the second electrode layer 7 can overlap with the first metal layer 1, the second metal layer-3 and the first electrode layer-4 during subsequent deposition.

[0030] Step 8: Deposit the second electrode layer 7 using physical vapor deposition. The second electrode layer 7 is made of ITO. After coating with photoresist, exposure, development, and wet etching patterning, the second electrode layer 7 is connected to the first metal layer 1, the second metal layer-3, and the first electrode layer-4 through contact holes to obtain the TFT device.

[0031] Example 3 The patterning process in Example 3 is as follows: Figure 3 As shown, the specific steps are as follows: The steps of the first and second steps are the same as in Example 1. The difference is that the patterning process in Example 3 is as follows: Figure 3 As shown.

[0032] Step 3: Deposit the first electrode layer 4 on the surface of the first insulating layer 2 using physical vapor deposition; after coating with photoresist, exposure, development, wet etching patterning, and stripping the photoresist, anneal at 200-250℃ for 30-60 min to obtain the first electrode layer 4, which is composed of ITO.

[0033] Step 4: Deposit active layer 5 on the surface of the first electrode layer 4 using physical vapor deposition; after coating with photoresist, exposure, development, and dry etching patterning, strip the photoresist to obtain active layer 5, which is composed of IGZO.

[0034] Step 5: Deposit a second insulating layer 6 on the surface of the active layer 5 using chemical vapor deposition; the second insulating layer 6 is composed of SiO2.

[0035] Step 6: After coating with photoresist, exposure, development, dry etching and photoresist stripping, the second insulating layer 6 is patterned to form an overlap hole above the first electrode layer 4 so that the second metal layer 3 can be electrically connected to the first electrode layer 4 during subsequent deposition, and to reduce the risk of damage to the active layer 5 during the etching process.

[0036] Step 7: Deposit the second metal layer 3 using physical vapor deposition; after coating with photoresist, exposure, development, and wet etching patterning, peel off the photoresist to obtain the second metal layer 3, which is composed of Ti / Cu.

[0037] Step 8: Deposit a third insulating layer 8 on the surface of the second metal layer 3 and the second insulating layer 6 using chemical vapor deposition; the third insulating layer 8 is composed of SiO2 / SiNx.

[0038] Step 9: Through coating, exposure, development, dry etching, and photoresist stripping steps, openings are made above the first metal layer 1, the second metal layer 3, and the first electrode layer 4 so that the second electrode layer 7 can overlap with the first metal layer 1, the second metal layer 3, and the first electrode layer 4 respectively during subsequent deposition.

[0039] Step 10: Deposit the second electrode layer 7 using physical vapor deposition. The second electrode layer is made of ITO. After coating with photoresist, exposure, development, and wet etching patterning, the second electrode layer 7 is connected to the first metal layer 1, the second metal layer 3, and the first electrode layer 4 through contact holes to obtain the TFT device.

[0040] Example 4 The patterning process in Example 4 is as follows: Figure 4 As shown, the specific steps are as follows: Steps one through eight are the same as in Example 3. The difference is that the patterning process in Example 4 is as follows: Figure 4 As shown.

[0041] Step 9: Through coating, exposure, development, dry etching, and photoresist stripping steps, an opening is made above the first metal layer 1 so that the second electrode layer 7 can overlap with the first metal layer 1 during subsequent deposition.

[0042] Step 10: Deposit the second electrode layer 7 using physical vapor deposition. The second electrode layer is made of ITO. After coating with photoresist, exposure, development, and wet etching for patterning, the second electrode layer 7 and the first metal layer 1 are connected through contact holes to obtain the TFT device.

[0043] The specific embodiments described above further illustrate the technical problems solved, the technical solutions, and the beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention. These specific embodiments are merely explanations of the present invention and are not limitations thereof. Those skilled in the art, after reading this specification, can make modifications to these embodiments without contributing any inventive step, but such modifications are protected by patent law as long as they fall within the scope of the claims of the present invention.

Claims

1. A thin-film transistor structure with ITO contact IGZO, characterized in that, The device includes a glass substrate on which a first metal layer (1) and a first insulating layer (2) covering the first metal layer (1) are sequentially disposed. A first electrode layer (4) and an active layer (5) are disposed on the first insulating layer (2). The first electrode layer (4) is in direct contact with the active layer (5). A second metal layer (3) is disposed and connected to the active layer (5) through an electrical connection with the first electrode layer (4), so that the active layer (5) is not in direct contact with the second metal layer (3). A second insulating layer (6) is disposed on the active layer (5) and the second metal layer (4), and a second electrode layer (7) is disposed on the second insulating layer (6). The second electrode layer (7) is electrically connected to the first metal layer (1) through a contact hole penetrating the second insulating layer (6) and the first insulating layer (2).

2. The transistor structure according to claim 1, characterized in that, A third insulating layer (8) is provided on the upper part of the second insulating layer (6).

3. The transistor structure according to claim 2, characterized in that, The second electrode layer (7) is electrically connected to the first metal layer (1) through a contact hole that penetrates the third insulating layer (8), the second insulating layer (6) and the first insulating layer (2).

4. The transistor structure according to claim 1 or claim 2, characterized in that, The second electrode layer (7) is electrically connected to the second metal layer (3) and the first electrode layer (4) respectively through contact holes penetrating the insulating layer.

5. The transistor structure according to claim 1, characterized in that, The first metal layer (1) is the gate metal layer, the first insulating layer (2) is the gate insulating layer, and the second metal layer (3) is the source and drain metal layer.

6. The transistor structure according to claim 3, characterized in that, The first electrode layer (4) is a pixel electrode layer, and the second electrode layer (7) is a common electrode layer.

7. The transistor structure according to claim 4, characterized in that, The first electrode layer (4) is a common electrode layer, and the second electrode layer (7) is a pixel electrode layer.

8. The transistor structure according to any one of claims 5 or 6, characterized in that, The second insulating layer (6) serves as the dielectric of the pixel capacitor.

9. The transistor structure according to claim 1, characterized in that, The first metal layer (1) is composed of Ti / Cu, the first insulating layer (2) is composed of SiNx / SiO2, the first electrode layer (4) is composed of ITO, the active layer (5) is composed of IGZO, and the second electrode layer (7) is composed of ITO.

10. The transistor structure according to claim 1, characterized in that, The second metal layer (3) is composed of MoNb / Cu, and the second insulating layer (6) is composed of SiO2 / SiN x constitute.

11. The transistor structure according to claim 2, characterized in that, The second metal layer (3) is composed of Ti / Cu, and the second insulating layer (6) is composed of SiO2.

12. The method for fabricating a transistor structure according to claim 1, characterized in that, Including the following methods: Based on the transistor structure, a first metal layer (1), a second metal layer (3), a first electrode layer (4), an active layer (5), and a second electrode layer (7) are deposited using physical vapor deposition, and patterned by coating, exposure, development, wet etching, and photoresist stripping. A first insulating layer (2), a second insulating layer (6), and a third insulating layer (8) are deposited using chemical vapor deposition. Contact holes are drilled on the first metal layer (1), the second metal layer (3), and the first electrode layer (4) through the steps of coating, exposure, development, dry etching, and photoresist stripping.

Images