LED chip with vertical structure and preparation method thereof

Abstract

The invention provides an LED chip with a vertical structure and a preparation method thereof. The chip comprises a conductive substrate, a bonding metal layer, a reflecting layer, an ITO thin film layer, an epitaxial layer and an N electrode from bottom to top in sequence, and the ITO thin film layer is clamped between the reflecting layer and the epitaxial layer. The ITO thin film layer is inserted between the reflecting layer and the epitaxial layer, so that the problem of electric leakage of the chip caused by migration of reflecting layer metal to the defect position of the epitaxial layer is effectively solved, the proportion of the chip with unstable electrical property is reduced, and the reliability of the LED chip with the vertical structure is improved.

Description

Technical Field

[0001] This invention relates to the field of light-emitting diodes, and more particularly to a vertical structure LED chip and its fabrication method. Background Technology

[0002] Compared to upright and flip-chip structures, vertical LED chips have advantages such as better heat dissipation, ability to carry large currents, high luminous intensity, low power consumption, and long lifespan.

[0003] In the design of vertical LED chips, improving external quantum efficiency (EQE) is one of the core objectives for enhancing device performance. Improving EQE heavily depends on two key factors: the ability to uniformly distribute current and the light extraction efficiency.

[0004] To simultaneously meet the requirements of high reflectivity and good conductivity, existing technologies typically deposit a reflective layer composed of metals such as Ag, Au, Al, Mg, Ni, and Ti directly on a p-type epitaxial layer. This reflective layer serves two purposes: firstly, it reflects light propagating towards the substrate back to the light-emitting surface through high optical reflectivity, improving light extraction efficiency; secondly, it acts as a current spreading layer, reducing ohmic contact resistance and promoting uniform lateral current distribution.

[0005] However, the aforementioned metallic materials are prone to metal migration during device operation. If dislocations or other crystal defects exist in the epitaxial layer, metal atoms in the reflective layer can easily diffuse into the semiconductor along the defect channels. This metal migration not only reduces luminous efficiency but may also cause increased leakage current or even short circuits, leading to electrical instability and decreased reliability in the LED chip.

[0006] Figure 1 The image shown is a scanning electron microscope (SEM) image of a vertical structure LED chip fabricated using existing technology, clearly showing that the reflective layer metal has migrated into its interior along the epitaxial layer defects. Summary of the Invention

[0007] In view of the above problems, the present invention provides a vertical structure LED chip and its preparation method to solve the problems of electrical instability and decreased reliability of existing LED chips caused by the diffusion of metal in the reflective layer along the epitaxial layer defects.

[0008] To achieve the above and other related objectives, the present invention provides a vertical structure LED chip, which, from bottom to top, includes a conductive substrate, a bonding metal layer, a reflective layer, an epitaxial layer, and an N-electrode; it also includes an ITO thin film layer sandwiched between the reflective layer and the epitaxial layer.

[0009] The vertical structure LED chip provided by this invention inserts an ITO thin film layer between the epitaxial layer and the reflective layer. ITO is a metal oxide ceramic material that can be formed into a very dense and continuous thin film through processes such as sputtering. This structure physically isolates the reflective layer from the epitaxial layer. Because the melting point and recrystallization temperature of ITO are much higher than those of commonly used reflective layer metals such as Ag and Al, its chemical bonds are very strong and it is very stable at LED operating temperatures, effectively preventing Ag and Al atoms from diffusing into the epitaxial layer through lattice gaps or grain boundaries. Even if a small amount of Ag... + Al + Once metal ions are generated, the dense ITO thin film layer also changes their migration path and dynamics, greatly increasing the difficulty of metal migration and improving the problem of electrical instability and abnormal reliability of LED chips caused by the migration of metal from the reflective layer to the epitaxial layer.

[0010] As an optional embodiment of the vertical structure LED chip of the present invention, the ITO thin film layer is an indium tin oxide thin film, with the weight ratio of indium oxide to tin oxide being 85%:15% to 95%:5%, and the thickness of the ITO thin film layer being 300Å to 6000Å.

[0011] As an alternative to the vertical structure LED chip of the present invention, the material of the reflective layer is Ag or NiAg alloy, and the thickness of the reflective layer is 200Å to 10000Å.

[0012] As an optional embodiment of the vertical structure LED chip of the present invention, the vertical projection of the epitaxial layer on the conductive substrate plane completely covers the vertical projection of the reflective layer on the conductive substrate plane; the vertical projection of the reflective layer on the conductive substrate plane completely covers the vertical projection of the ITO thin film layer on the conductive substrate plane.

[0013] As an alternative embodiment of the vertical structure LED chip of the present invention, the epitaxial layer consists of a P-type layer, a quantum well layer, and an N-type layer from bottom to top; the epitaxial layer is composed of at least one selected from GaAs-based compound semiconductors, GaN-based compound semiconductors, and ZnO-based compound semiconductors.

[0014] As an optional embodiment of the vertical structure LED chip of the present invention, the LED chip further includes a current blocking layer, which is in contact with the epitaxial layer above and with the bonding metal layer, the reflective layer and the ITO thin film layer below; the vertical projection of the current blocking layer on the conductive substrate plane is a closed ring, and the closed ring pattern corresponds to the outer edge of the epitaxial layer.

[0015] This invention also provides a method for fabricating a vertical LED chip, comprising the following steps: S1. Provide a growth substrate and form an epitaxial layer on the growth substrate; the epitaxial layer includes an N-type layer, a quantum well layer and a P-type layer stacked sequentially on the growth substrate; S2. Form a current blocking layer on the P-type layer; pattern the current blocking layer to expose part of the P-type layer; S3. Form an ITO thin film layer on the P-type layer and the current blocking layer; pattern the ITO thin film layer to expose part of the current blocking layer; S4. Form a reflective layer on the ITO thin film layer and the current blocking layer; pattern the reflective layer to expose part of the current blocking layer; S5. Form a bonding metal layer on the reflective layer; S6. Bond a conductive substrate onto the bonding metal layer; S7. Remove the growth substrate to expose the N-type layer; S8. Etching removes the periphery of the epitaxial layer to form the epitaxial layer mesa structure; S9. Form an N-electrode on the surface of the N-type layer.

[0016] As an optional embodiment of the preparation method of the present invention, the method for forming the ITO thin film layer in step S3 is to sputter or vapor-deposit the ITO thin film on the surface of the P-type layer and the current blocking layer; the method for patterning the ITO thin film layer is to etch away the edge of the ITO thin film; a portion of the formed ITO thin film layer is in contact with the P-type layer and a portion is in contact with the current blocking layer.

[0017] As an optional embodiment of the preparation method of the present invention, the method for forming the reflective layer in step S4 is to sputter or vapor-deposit the reflective layer on the surface of the ITO thin film layer and the current blocking layer; the method for patterning the reflective layer is to etch or peel off the reflective layer at the edge; the formed reflective layer completely covers the ITO thin film layer and covers part of the current blocking layer.

[0018] As an optional embodiment of the preparation method of the present invention, in step S2, the vertical projection of the current blocking layer on the plane of the conductive substrate is a closed annular pattern and covers the edge region of the epitaxial layer; in step S5, the bonding metal layer completely covers the reflective layer and covers the area of ​​the current blocking layer not covered by the reflective layer; in step S8, the edges of the epitaxial layer are etched away to obtain the epitaxial layer mesa structure, exposing part of the current blocking layer; the projection of the epitaxial layer mesa structure on the plane of the conductive substrate completely covers the vertical projection of the reflective layer on the plane of the conductive substrate.

[0019] Additional aspects and advantages of the invention will be set forth in part in the description which follows, some of which will become clear as the description proceeds, and others will be learned by practicing the invention. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a SEM image of the metal migration of the reflective layer to the epitaxial layer in a vertically structured LED chip in the prior art.

[0022] Figure 2 This is a cross-sectional schematic diagram of the epitaxial layer after growth in an embodiment of the present invention.

[0023] Figure 3 This is a cross-sectional view of the current blocking layer after it has been formed in an embodiment of the present invention.

[0024] Figure 4 This is a cross-sectional view of the patterned current blocking layer in an embodiment of the present invention.

[0025] Figure 5 This is a schematic cross-sectional view of the patterned ITO thin film layer in an embodiment of the present invention.

[0026] Figure 6 This is a schematic cross-sectional view of the patterned reflective layer in an embodiment of the present invention.

[0027] Figure 7 This is a cross-sectional view of the bonding metal layer after it has been formed in an embodiment of the present invention.

[0028] Figure 8 This is a cross-sectional view of the conductive substrate after bonding in an embodiment of the present invention.

[0029] Figure 9 This is a cross-sectional view after removing the growth substrate in an embodiment of the present invention.

[0030] Figure 10 This is a cross-sectional schematic diagram of the epitaxial layer after etching to form a mesa structure in an embodiment of the present invention.

[0031] Figure 11 This is a cross-sectional view of the N-electrode formed in an embodiment of the present invention.

[0032] Figure 12 This is a top view of the current blocking layer and epitaxial layer mesa structure in an embodiment of the present invention.

[0033] Component labeling explanation: 10-Conductive substrate, 11-Bonding metal layer, 12-Reflective layer, 13-ITO thin film layer, 14-Current blocking layer, 15-Epipolar layer, 151-P-type layer, 152-Quantum well layer, 153-N-type layer, 16-Growth substrate, 17-N-electrode. Detailed Implementation

[0034] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0035] The invention will be described more specifically in the following paragraphs by way of example with reference to the accompanying drawings. It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the invention. Although the illustrations only show components related to the invention and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0036] The current fabrication process for vertical LED chips mainly involves growing an epitaxial layer on a growth substrate, then fabricating a reflective layer and a bonding metal layer on the epitaxial layer, bonding the epitaxial layer to a conductive substrate, removing the growth substrate by laser lift-off or wet etching, transferring the epitaxial layer to the conductive substrate, and finally fabricating the N-electrode. The current spread and reflective layer design of vertical LED chips are crucial for improving the chip's external quantum efficiency. Typically, the reflective layer requires a metal with high conductivity and high reflectivity, such as Ag, Au, Al, Mg, Ni, or Ti. However, these metals are prone to metal migration issues in LEDs, leading to chip leakage.

[0037] The applicant discovered in their research that the reflective layer is in direct contact with the P-type layer, leading to metal migration from the reflective layer to defects in the epitaxial layer. This results in electrical instability and reliability issues in the chip. The main component of the ITO thin film is indium tin oxide, with a bandgap of 3.5 eV to 4.5 eV, a transmittance greater than 85% in the visible light range, and a resistivity less than 10⁻⁶. -3Its high transmittance, good conductivity, and high stability make it ideal as a transparent conductive layer for LED chips. This application innovatively inserts an ITO thin film layer between the epitaxial layer and the reflective layer. ITO is prepared through processes such as sputtering, forming a very dense and continuous thin film. This structure physically isolates the reflective layer from the epitaxial layer. Because the melting point and recrystallization temperature of ITO are much higher than those of commonly used reflective layer metals such as Ag and Al, its chemical bonds are very strong and it is very stable at LED operating temperatures, effectively preventing Ag and Al atoms from diffusing into the epitaxial layer through lattice gaps or grain boundaries. Even with a small amount of Ag... + Al + Once metal ions are generated, the dense ITO thin film layer also changes their migration path and dynamics, greatly increasing the difficulty of metal migration and improving the problem of electrical instability and abnormal reliability of LED chips caused by the migration of metal from the reflective layer to the epitaxial layer.

[0038] Based on this, embodiments of this application provide a vertical structure LED chip, such as... Figure 11 As shown, from bottom to top, it includes a conductive substrate 10, a bonding metal layer 11, a reflective layer 12, an epitaxial layer 15, and an N-electrode 17; it also includes an ITO thin film layer 13, which is sandwiched between the reflective layer 12 and the epitaxial layer 15.

[0039] It should be noted that inserting an ITO thin film layer between the epitaxial layer and the reflective layer not only prevents the metal from the reflective layer from migrating to the epitaxial layer, but also improves current spreading. In existing technologies, the current flow path is from the reflective layer to the P-type layer. In this application, an ITO thin film layer is inserted between the epitaxial layer and the reflective layer, changing the current flow path to flow from the reflective layer through the ITO thin film layer, and then from the ITO thin film layer to the P-type layer. ITO has excellent lateral conductivity. When current enters the ITO thin film layer from the reflective layer, although the resistivity of ITO is higher than that of metals, it is much lower than that of semiconductors. The current spreads rapidly laterally within the ITO thin film layer and then is uniformly injected into the P-type layer. This "current spreading" effect means that in most areas of the interface between the reflective layer and the ITO thin film layer, the vertical current density is actually very low. The driving force (current density) for electromigration is greatly dispersed and weakened by the ITO thin film layer. If there were no ITO thin film layer between the reflective layer and the epitaxial layer, all the current would have to be concentrated at the contact point between the reflective layer and the P-type layer, resulting in extremely high current density at that point and more significant electromigration.

[0040] In some embodiments, the ITO thin film layer 13 is an indium tin oxide (ITO) thin film, with an ITO to tin oxide weight ratio of 85%:15% to 95%:5%, and the thickness of the ITO thin film 13 is 300 Å to 6000 Å. It should be noted that ITO itself has high intrinsic transmittance in the visible light range, and appropriate Sn doping improves conductivity without significantly introducing light absorption. Excessive Sn content will lead to a decrease in short-wavelength transmittance due to increased free carrier absorption and defects. On the other hand, the sheet resistance of the ITO thin film layer determines its lateral conductivity; the thicker the ITO, the lower the sheet resistance and the more uniform the current spread. Furthermore, the refractive index of ITO (approximately 1.9-2.0) is between that of GaN (approximately 2.4) and air / encapsulant (approximately 1.5), and it inherently has an anti-reflection effect, resulting in an optically optimal thickness. Excessive ITO thickness increases absorption loss and leads to high internal stress, making the film prone to microcracks and reducing reliability and conductivity uniformity. Therefore, the selection of the material ratio (i.e., the ratio of indium oxide to tin oxide) and thickness of ITO films requires a comprehensive optimization process that balances conductivity, light transmittance, contact resistance, process cost, and reliability.

[0041] In some embodiments, the reflective layer 12 is made of Ag or a NiAg alloy, and its thickness is 200 Å to 10000 Å. It should be noted that vertical LED structures require reflecting light emitted towards the conductive substrate back to the light-emitting surface; therefore, high reflectivity of the reflective layer is a primary requirement. In the blue-green light band (450 nm to 550 nm), Ag has a reflectivity of 95% to 98%, the highest among all metals; simultaneously, its low resistivity contributes to vertical conductivity. Ni primarily enhances interfacial adhesion, reacting with the P-type layer or ITO to form an interface with low contact resistance. Furthermore, the thickness of the reflective layer needs to be controlled within the aforementioned range. If the reflective layer is too thin, the reflectivity will significantly decrease due to film discontinuities or interference effects; if the reflective layer is too thick, the internal stress of the metal film is high, easily leading to warping or peeling from the substrate, and resulting in wasted costs.

[0042] In some embodiments, the vertical projection of the epitaxial layer 15 onto the plane of the conductive substrate 10 completely covers the vertical projection of the reflective layer 12 onto the plane of the conductive substrate 10; the vertical projection of the reflective layer 12 onto the plane of the conductive substrate 10 completely covers the vertical projection of the ITO thin film layer 13 onto the plane of the conductive substrate 10. It should be noted that the reflective layer material is typically metal, and metal materials are prone to metal migration problems in LEDs. The fact that the projection of the reflective layer onto the plane of the conductive substrate is completely covered by the projection of the epitaxial MESA mesa helps to prevent metal migration to the PN junction of the epitaxial layer, thus avoiding LED chip failure. Furthermore, the complete coverage of the ITO thin film layer by the reflective layer prevents the ITO thin film layer from being corroded by chemical reagents during patterned wet etching of the reflective layer, thus avoiding adhesion abnormalities such as edge curling and peeling of the reflective layer.

[0043] In some embodiments, the epitaxial layer 15 consists of a P-type layer 151, a quantum well layer 152, and an N-type layer 153 from bottom to top; the epitaxial layer 15 is composed of at least one selected from GaAs-based compound semiconductors, GaN-based compound semiconductors, and ZnO-based compound semiconductors. It should be noted that GaAs-based compound semiconductors are III-V group direct bandgap semiconductor materials represented by gallium arsenide (GaAs); GaN-based compound semiconductors are wide bandgap III-V group semiconductor materials with gallium nitride (GaN) as the core; and ZnO-based compound semiconductors are II-VI group wide bandgap semiconductor materials mainly composed of zinc oxide (ZnO). The LED chip structure of this application is applicable to all of these epitaxial material systems.

[0044] In some embodiments, the LED chip further includes a current blocking layer 14, which contacts the epitaxial layer 15 above and the bonding metal layer 11, reflective layer 12, and ITO thin film layer 13 below. The vertical projection of the current blocking layer 14 onto the plane of the conductive substrate 10 is a closed ring, and the closed ring pattern corresponds to the outer edge of the epitaxial layer 15. It should be noted that the closed ring pattern of the current blocking layer ensures that the edge of the epitaxial layer mesa is surrounded by the current blocking layer, effectively improving the leakage problem caused by metal contamination on the sidewall of the epitaxial layer mesa.

[0045] This application also provides a method for fabricating a vertical structure LED chip, including the following steps: S1. Provide a growth substrate 16 and form an epitaxial layer 15 on the growth substrate 16; the epitaxial layer 15 includes an N-type layer 153, a quantum well layer 152 and a P-type layer 151 stacked sequentially on the growth substrate 16. S2. A current blocking layer 14 is formed on the P-type layer 151; the current blocking layer 14 is patterned to expose a portion of the P-type layer 151; S3. An ITO thin film layer 13 is formed on the P-type layer 151 and the current blocking layer 14; the ITO thin film layer 13 is patterned to expose part of the current blocking layer 14. S4. A reflective layer 12 is formed on the ITO thin film layer 13 and the current blocking layer 14; the reflective layer 12 is patterned to expose part of the current blocking layer 14. S5. A bonding metal layer 11 is formed on the reflective layer 12; S6. Bond the conductive substrate 10 onto the bonding metal layer 11; S7. Remove the growth substrate 16 to expose the N-type layer 153; S8. Etch away the periphery of the epitaxial layer 15 to form an epitaxial layer mesa structure; S9. An N-electrode 17 is formed on the surface of the N-type layer 153.

[0046] In some embodiments, the method for forming the ITO thin film layer 13 in step S3 is to sputter or vapor-deposit an ITO thin film on the surfaces of the P-type layer 151 and the current blocking layer 14; the method for patterning the ITO thin film layer 13 is to etch away the edges of the ITO thin film; a portion of the formed ITO thin film layer 13 contacts the P-type layer 151, and a portion contacts the current blocking layer 14. It should be noted that since the wet etching technique used in the subsequent patterning of the reflective layer and the epitaxial layer may cause the ITO thin film layer to be etched, the prepared ITO thin film layer needs to be patterned to completely cover the interior of the reflective layer and the epitaxial layer.

[0047] In some embodiments, the method for forming the reflective layer 12 in step S4 is to sputter or vapor-deposit the reflective layer on the surface of the ITO thin film layer 13 and the current blocking layer 14; the method for patterning the reflective layer 12 is to etch or strip away the reflective layer 12 at its edges; the formed reflective layer 12 completely covers the ITO thin film layer 13 and covers a portion of the current blocking layer 14.

[0048] In some embodiments, in step S2, the vertical projection of the current blocking layer 14 onto the plane of the conductive substrate 10 is a closed annular pattern, covering the edge region of the epitaxial layer 15; in step S5, the bonding metal layer 11 completely covers the reflective layer 12, and the bonding metal layer 11 covers the area of ​​the current blocking layer 14 not covered by the reflective layer 12; in step S8, the periphery of the epitaxial layer 15 is etched away to obtain the epitaxial layer mesa structure, exposing a portion of the current blocking layer 14; the projection of the epitaxial layer mesa structure onto the plane of the conductive substrate 10 completely covers the vertical projection of the reflective layer 12 onto the plane of the conductive substrate 10. It should be noted that after the epitaxial layer 15 forms a mesa structure, the PN junction in the epitaxial layer is exposed. During chip fabrication and subsequent use, metal particles and other conductors can easily come into contact with the PN junction, causing LED chip leakage, affecting LED chip yield and reliability. The main function of the current blocking layer 14 is to block the direct connection between the metal particles and other conductors adhering to the sidewalls of the PN junction and the metal layer, avoiding the formation of leakage paths and improving chip manufacturing yield. The bonding metal layer needs to undergo eutectic reaction, diffusion, or interatomic bonding with the metal layer on the conductive substrate under specific process conditions (such as heating and pressurization) to form a strong, dense, and uniform bonding interface. The reflective layer is made of Ag or NiAg alloy. When used in harsh environments such as high temperature and high humidity, Ag is prone to metal migration. The epitaxial mesa structure completely covers the reflective layer, which can prevent migrating Ag ions from climbing to the sidewalls of the epitaxial mesa and causing a short circuit in the PN junction.

[0049] The following are some embodiments of this application. The embodiments of the present invention will further describe in detail each technical step and process parameter in the preparation process. Example 1

[0050] This embodiment provides a method for fabricating a vertical structure LED chip, including the following steps: Step S1: Provide a growth substrate 16, and form an epitaxial layer 15 on the growth substrate 16 using a metal-organic chemical vapor deposition (MOCVD) apparatus. The epitaxial layer 15 includes an N-type layer 153, a quantum well layer 152, and a P-type layer 151 sequentially stacked on the growth substrate 16, such as... Figure 2 As shown. Among them, the growth substrate 16 is a 4-inch silicon substrate with a thickness of 1030µm; the N-type layer 153 is N-type GaN, the quantum well layer 152 is InGaN / GaN multiple quantum well, and the P-type layer 151 is P-type GaN.

[0051] Step S2: A current blocking layer 14 is formed on the P-type layer 151 using plasma-enhanced chemical vapor deposition (PECVD), such as... Figure 3 As shown. The deposition rate is 10 Å / s, the material of the current blocking layer 14 is SiO2, and the thickness of the current blocking layer 14 is 1500 Å. A photolithography patterning method, combined with wet etching or dry etching processes, is used to expose a portion of the P-type layer 151, forming a patterned current blocking layer 14, as shown. Figure 4 As shown. The vertical projection of the current blocking layer 14 onto the conductive substrate plane is a closed annular pattern, covering the edge region of the epitaxial layer. In this embodiment, the top view of the current blocking layer and the mesa structure of the epitaxial layer is as follows. Figure 12 As shown.

[0052] Step S3: An ITO thin film layer 13 is formed by sputtering a magnetron sputtering stage onto the P-type layer 151 and the current blocking layer 14. A photolithography patterning method, combined with wet etching or dry etching processes, is used to etch and remove the ITO thin film at the chip edges. This exposes part of the current blocking layer 14, forming a patterned ITO thin film layer 13. Part of the ITO thin film layer contacts the P-type layer 151, and part contacts the current blocking layer 14, as shown below. Figure 5 As shown, in the ITO thin film layer, the weight ratio of indium oxide to tin oxide is 90%:10%, and the thickness of the ITO thin film is 700 Å.

[0053] Step S4: A metal material is deposited on the ITO thin film layer 13 using an electron beam evaporation deposition apparatus to form a reflective layer 12. A photolithography lift-off or photolithography patterning and wet etching process is then used to expose part of the current blocking layer 14, forming the patterned reflective layer 12. Figure 6 As shown. The reflective layer material is a NiAg alloy with a thickness of 2000 Å.

[0054] Step S5: A metal material is deposited on the reflective layer 12 using an electron beam evaporation deposition apparatus to form a bonding metal layer 11; the bonding metal layer 11 completely covers the reflective layer 12, and covers the area of ​​the current blocking layer 14 not covered by the reflective layer 12, such as... Figure 7 As shown. The material of the bonding metal layer 11 is a CuIn alloy.

[0055] Step S6: Bond the conductive substrate 10 onto the bonding metal layer 11 using a high-temperature bonding process, such as... Figure 8 As shown. The conductive substrate 10 is a silicon substrate with a thickness of 170µm.

[0056] Step S7: The growth substrate 16 is removed using a chemical etching process to expose the N-type layer 153, as shown below. Figure 9 As shown, the surface of the N-type layer 153 is roughened using an ICP etching and humidification process, making the surface of the N-type layer 153 rough (not shown in the figure), increasing the light-emitting area, and thus improving the light-emitting efficiency of the LED.

[0057] Step S8: Using a spin coating, exposure, and development process, combined with dry etching and wet etching processes, the edges of the epitaxial layer 15 are removed to form a mesa structure, such as... Figure 10 As shown, a portion of the current blocking layer 14 is exposed, and the projection of the epitaxial mesa structure 15 onto the plane of the conductive substrate 10 completely covers the vertical projection of the reflective layer 12 onto the plane of the conductive substrate 10.

[0058] Step S9: An N-electrode 17 is formed on the surface of the N-type layer 153 using a vapor deposition process and a metal stripping process, such as... Figure 11 As shown. The N electrode is made of CrPtAu and consists of pads and electrode lines. Example 2

[0059] This embodiment provides a vertical structure LED chip, which is prepared using the method provided in Embodiment 1, such as... Figure 11 As shown, from bottom to top, it includes a conductive substrate 10, a bonding metal layer 11, a reflective layer 12, an ITO thin film layer 13, a current blocking layer 14, an epitaxial layer 15, and an N-electrode 17; the ITO thin film layer 13 is formed on the epitaxial layer 15 and the current blocking layer 14, and the reflective layer 12 is connected to the ITO thin film layer 13, the current blocking layer 14, and the bonding metal layer 11.

[0060] The epitaxial layer 15 includes a P-type layer 151, a quantum well layer 152, and an N-type layer 153. The epitaxial layer 15 can be made of various material systems, such as GaAs, GaN, and ZnO.

[0061] The current blocking layer 14 is in direct contact with the P-type layer 151. The vertical projection of the current blocking layer 14 onto the plane of the conductive substrate 10 is a closed ring, and the closed ring pattern corresponds to the outer edge of the epitaxial layer 15, such as... Figure 12 As shown. The current blocking layer 14 is 1500 Å SiO2. The vertical projection of the epitaxial layer 15 onto the plane of the conductive substrate 10 completely covers the vertical projection of the reflective layer 12 onto the plane of the conductive substrate 10.

[0062] The ITO thin film layer is an indium tin oxide thin film with an indium oxide to tin oxide weight ratio of 90%:10% and an ITO film thickness of 700 Å.

[0063] The reflective layer 12 is a NiAg alloy with a thickness of 2000 Å.

[0064] The vertical LED chip with an ITO thin film provided in this embodiment has an ITO thin film layer inserted between the epitaxial layer and the reflective layer. ITO is fabricated through processes such as sputtering, forming a very dense and continuous thin film. This structure physically isolates the reflective layer from the epitaxial layer. Because the melting point and recrystallization temperature of ITO are much higher than those of commonly used reflective layer metals such as Ag and Al, its chemical bonds are very strong and it is very stable at LED operating temperatures, effectively preventing Ag and Al atoms from diffusing into the epitaxial layer through lattice gaps or grain boundaries. Even if a small amount of Ag... + Al + Once metal ions are generated, the dense ITO thin film layer also changes their migration path and dynamics, greatly increasing the difficulty of metal migration and improving the problem of electrical instability and abnormal reliability of LED chips caused by the migration of metal from the reflective layer to the epitaxial layer.

[0065] The above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A vertical LED chip, comprising, from bottom to top, a conductive substrate, a bonding metal layer, a reflective layer, an epitaxial layer, and an N-electrode, characterized in that: It also includes an ITO thin film layer sandwiched between the reflective layer and the epitaxial layer.

2. The vertical structure LED chip according to claim 1, characterized in that: The ITO thin film layer is an indium tin oxide thin film, with an indium oxide to tin oxide weight ratio of 85%:15% to 95%:5%, and the thickness of the ITO thin film layer is 300Å to 6000Å.

3. The vertical structure LED chip according to claim 1, characterized in that: The material of the reflective layer is Ag or NiAg alloy, and the thickness of the reflective layer is 200 Å to 10000 Å.

4. The vertical structure LED chip according to claim 1, characterized in that: The vertical projection of the epitaxial layer onto the conductive substrate plane completely covers the vertical projection of the reflective layer onto the conductive substrate plane; the vertical projection of the reflective layer onto the conductive substrate plane completely covers the vertical projection of the ITO thin film layer onto the conductive substrate plane.

5. The vertical structure LED chip according to claim 1, characterized in that: The epitaxial layer consists of a P-type layer, a quantum well layer, and an N-type layer from bottom to top; the epitaxial layer is composed of at least one selected from GaAs-based compound semiconductors, GaN-based compound semiconductors, and ZnO-based compound semiconductors.

6. The vertical structure LED chip according to claim 1, characterized in that: The LED chip also includes a current blocking layer, which is in contact with the epitaxial layer above and with the bonding metal layer, reflective layer and ITO thin film layer below. The vertical projection of the current blocking layer on the conductive substrate plane is a closed ring, and the closed ring pattern corresponds to the outer edge of the epitaxial layer.

7. A method for fabricating a vertically structured LED chip, characterized in that, Includes the following steps: S1. A growth substrate is provided, and an epitaxial layer is formed on the growth substrate; the epitaxial layer includes an N-type layer, a quantum well layer and a P-type layer sequentially stacked on the growth substrate. S2. Form a current blocking layer on the P-type layer; pattern the current blocking layer to expose a portion of the P-type layer; S3. An ITO thin film layer is formed on the P-type layer and the current blocking layer; The ITO thin film layer is patterned to expose a portion of the current blocking layer; S4. A reflective layer is formed on the ITO thin film layer and the current blocking layer; the reflective layer is patterned to expose a portion of the current blocking layer; S5. A bonding metal layer is formed on the reflective layer; S6. Bond a conductive substrate onto the bonding metal layer; S7. Remove the growth substrate to expose the N-type layer; S8. Etch away the periphery of the epitaxial layer to form an epitaxial layer mesa structure; S9. An N-electrode is formed on the surface of the N-type layer.

8. The method for fabricating a vertical structure LED chip according to claim 7, characterized in that: The method for forming the ITO thin film layer in step S3 is to sputter or vapor deposit an ITO thin film on the surface of the P-type layer and the current blocking layer. The method for patterning the ITO thin film layer is to etch away the edges of the ITO thin film; The formed ITO thin film layer is in contact with the P-type layer in part and with the current blocking layer in part.

9. The method for fabricating a vertical structure LED chip according to claim 7, characterized in that: The method for forming the reflective layer in step S4 is to sputter or vapor-deposit the reflective layer on the surface of the ITO thin film layer and the current blocking layer; the method for patterning the reflective layer is to etch or strip away the reflective layer at the edges; the formed reflective layer completely covers the ITO thin film layer and covers a portion of the current blocking layer.

10. The method for fabricating a vertical structure LED chip according to claim 7, characterized in that: In step S2, the vertical projection of the current blocking layer on the conductive substrate plane is a closed annular pattern, and it covers the edge region of the epitaxial layer; in step S5, the bonding metal layer completely covers the reflective layer, and the bonding metal layer covers the area of ​​the current blocking layer not covered by the reflective layer; in step S8, the edges of the epitaxial layer are etched away to obtain the epitaxial layer mesa structure, exposing part of the current blocking layer; the projection of the epitaxial layer mesa structure on the conductive substrate plane completely covers the vertical projection of the reflective layer on the conductive substrate plane.

Images