Piezoelectric substrate on insulator and preparation method thereof

Abstract

The invention provides a piezoelectric substrate on an insulator and a preparation method of the piezoelectric substrate on the insulator, the piezoelectric substrate on the insulator comprises a supporting layer, a polycrystalline silicon layer, a temperature compensation layer, an isolation layer and a piezoelectric material layer which are stacked in sequence from bottom to top, the support is used for supporting an upper-layer structure; the polycrystalline silicon layer is used for improving the quality of a bonding interface; the temperature compensation layer is used for compensating frequency temperature excursion generated by the piezoelectric material layer; the isolation layer is used for limiting surface acoustic wave energy generated by the piezoelectric material layer from leaking to a lower layer structure; and the piezoelectric material layer is used for realizing conversion and propagation of electric signals and surface acoustic waves. According to the substrate provided by the invention, through the combination of the temperature compensation layer and the isolation layer, the dielectric constant can be reduced, the coupling efficiency of the piezoelectric material is redistributed, the temperature coefficient is improved, the stray mode induced by temperature drift is reduced, and the harmonic performance of the piezoelectric substrate on the insulator is further improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a piezoelectric substrate on an insulator and its preparation method. Background Technology

[0002] With the maturity of fifth-generation wireless communication technology, smartphones are increasingly demanding higher frequency band support, leading to prominent uplink interference issues due to dense frequency bands. To ensure high-quality data communication across spectrums, a typical high-end smartphone needs to be equipped with at least 50 RF front-end filters. Furthermore, with the upgrade to 5G technology and the deployment of new technologies such as Carrier Aggregation (CA) and Multiple Input Multiple Output (MIMO), the number of communication frequency bands continues to increase, resulting in a rapid growth in filter demand. At the same time, new technologies place higher demands on filter performance, requiring them to meet core indicators such as low insertion loss, large bandwidth, high rectangularity, and high isolation.

[0003] The advent of piezoelectric on insulator (POI) substrate technology has provided a feasible solution for surface acoustic wave (SAW) filters to meet high-end requirements. This technology, by bonding a silicon oxide layer, polycrystalline silicon, and high-resistivity silicon multilayer structure to the bottom of the piezoelectric layer, enables the filter to possess advantages such as low temperature drift, high Q value, and low insertion loss, making it a key development direction for future filters. The existing POI wafer substrate structure, from bottom to top, consists of high-resistivity silicon, polycrystalline silicon, silicon dioxide, and the piezoelectric layer. The core function of the silicon dioxide layer is to compensate for the inherent temperature drift effect of the lithium tantalate piezoelectric material, ensuring the substrate's temperature stability.

[0004] However, existing POI substrate designs have significant technical defects: the silicon dioxide layer is prone to generating standing wave effects, which couple to the master mode, causing plate mode noise in the high-frequency region of the resonator. This severely affects the second and third harmonic performance of the filter, making it unable to fully meet the stringent requirements of 5G communication and various new technologies for the high-frequency performance of the filter, thus limiting the application of POI substrates in high-end RF front-end filters.

[0005] Therefore, it is urgent to improve the existing POI substrate structure to address the aforementioned defects. Summary of the Invention

[0006] This invention provides a piezoelectric substrate on an insulator and its preparation method, aiming to solve the technical problem that the existing POI substrate structure is prone to standing wave effect, which affects harmonic performance.

[0007] To address the aforementioned technical problems, in a first aspect, the present invention provides a piezoelectric substrate on an insulator, wherein the piezoelectric substrate on an insulator comprises, from bottom to top, a support layer, a polysilicon layer, a temperature compensation layer, an isolation layer, and a piezoelectric material layer stacked sequentially, wherein:

[0008] The support layer serves as the substrate of the piezoelectric substrate on the insulator and is used to provide support for the upper structure. The polycrystalline silicon layer is used to improve the bonding interface quality; The temperature compensation layer is used to compensate for the frequency temperature drift generated by the piezoelectric material layer; The isolation layer is used to limit the leakage of surface acoustic wave energy generated by the piezoelectric material layer into the lower layer structure; The piezoelectric material layer is used to convert electrical signals into surface acoustic waves and to propagate surface acoustic waves.

[0009] Furthermore, the temperature compensation layer is made of fluorine-doped silicon oxide material.

[0010] Furthermore, the insulating layer is made of alumina.

[0011] Furthermore, the support layer is made of a high-resistivity silicon material.

[0012] Secondly, the present invention also provides a method for preparing a substrate for preparing the piezoelectric substrate on an insulator as described above, the method comprising the following steps: S1. The fabrication process begins with a composite wafer containing the support layer and the polysilicon layer as the basic structure of the piezoelectric substrate on the insulator. S2. A low-pressure plasma-enhanced chemical vapor deposition process is used to deposit fluorine-doped silicon oxide on the surface of the polycrystalline silicon layer to form the temperature compensation layer. S3. Using atomic layer deposition (ALD) technology, aluminum oxide is deposited on the surface of the temperature compensation layer to form the isolation layer; S4. A wafer containing the piezoelectric material layer is bonded to the surface of the isolation layer to form the piezoelectric substrate on the insulator.

[0013] Furthermore, step S2 also includes the following steps: The temperature compensation layer is subjected to chemical mechanical polishing, and the polished temperature compensation layer is etched and adjusted based on a dry etching process to make the thickness of the temperature compensation layer uniform.

[0014] Furthermore, step S4 also includes the following steps: The piezoelectric material layer is subjected to annealing, grinding and chemical mechanical polishing in sequence, and then the piezoelectric material layer is thinned to a preset thickness.

[0015] The beneficial effects achieved by this invention are that it proposes a novel layered structure of piezoelectric substrate on insulator. This substrate can reduce the dielectric constant by combining a temperature compensation layer and an isolation layer, thereby redistributing the coupling efficiency of the piezoelectric material and improving the temperature coefficient. It also reduces stray modes induced by temperature drift, thereby improving the harmonic performance of the piezoelectric substrate on insulator. Attached Figure Description

[0016] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings: Figure 1 This is a layer structure diagram of the piezoelectric substrate on an insulator provided in an embodiment of the present invention; Figure 2 This is a diagram of the hierarchical structure of a piezoelectric substrate on an insulator in the prior art; Figure 3 This is a comparison diagram of the transfer admittance waveforms of resonators implemented based on piezoelectric substrates on insulators in the prior art and embodiments of the present invention, respectively; Figure 4 This is a flowchart illustrating the preparation method proposed in the embodiments of the present invention. Detailed Implementation

[0017] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0018] The specific embodiments / examples described herein are specific implementations of the present invention, used to illustrate the concept of the invention, and are illustrative and exemplary, and should not be construed as limiting the implementation methods or scope of the present invention. In addition to the embodiments described herein, those skilled in the art can employ other obvious technical solutions based on the content disclosed in the claims and specification of this application. These technical solutions include those that make any obvious substitutions and modifications to the embodiments described herein, all of which are within the protection scope of the present invention.

[0019] Example 1 Please refer to Figure 1 , Figure 1 This is a layer structure diagram of the piezoelectric substrate on an insulator provided in an embodiment of the present invention. The piezoelectric substrate on an insulator 100 includes, from bottom to top, a support layer 1, a polysilicon layer 2, a temperature compensation layer 3, an isolation layer 4, and a piezoelectric material layer 5, which are stacked sequentially. The support layer 1 serves as the substrate of the piezoelectric substrate on the insulator and is used to provide support for the upper structure. The polycrystalline silicon layer 2 is used to improve the bonding interface quality; The temperature compensation layer 3 is used to compensate for the frequency temperature drift generated by the piezoelectric material layer 5. The isolation layer 4 is used to limit the leakage of surface acoustic wave energy generated by the piezoelectric material layer 5 into the lower layer structure; The piezoelectric material layer 5 is used to convert electrical signals into surface acoustic waves and to propagate surface acoustic waves.

[0020] The temperature compensation layer 3 is made of fluorine-doped silicon oxide (SiOF), the isolation layer 4 is made of aluminum oxide (Al2O3), and the support layer 1 is made of high-resistivity silicon material.

[0021] For comparison, please refer to Figure 2 , Figure 2 This is a layer structure diagram of a prior art piezoelectric substrate on an insulator. The prior art piezoelectric substrate on an insulator 200 includes, from bottom to top, a support layer a, a polycrystalline silicon layer b, a temperature compensation layer c, and a piezoelectric material layer d stacked sequentially. The temperature compensation layer c in the prior art is made of silicon dioxide (SiO2).

[0022] Compared to silicon dioxide, fluorine-doped silicon oxide exhibits a positive shift in its temperature coefficient of frequency (TCF) by 5-8 ppm / K, along with a lower temperature slope for its elastic constant. Substrates made from this material not only reduce master mode temperature drift but also push plate modes that would otherwise enter the passband due to temperature variations away from the operating window, resulting in more stable operating modes.

[0023] Figure 3 The diagram shows a comparison of the transfer admittance (Y21) waveforms of resonators based on the proposed piezoelectric substrate on insulators in the prior art and embodiments of the present invention. It can be seen that in the low-frequency range (1.5GHz-2.0GHz), the piezoelectric substrate on insulator 100 proposed in the embodiments of the present invention has a deeper suppression depth and better isolation than the prior art; while in the high-frequency range (2.0GHz-4.5GHz), especially at about 3.8GHz, the parasitic resonance is smoother than the prior art, demonstrating better harmonic performance.

[0024] The beneficial effects achieved by this invention are that it proposes a novel layered structure of piezoelectric substrate on insulator. This substrate can reduce the dielectric constant by combining a temperature compensation layer and an isolation layer, thereby redistributing the coupling efficiency of the piezoelectric material and improving the temperature coefficient. It also reduces stray modes induced by temperature drift, thereby improving the harmonic performance of the piezoelectric substrate on insulator.

[0025] Example 2 This invention also provides a preparation method for preparing the piezoelectric substrate 100 on an insulator as described in Embodiment 1 above. Please refer to... Figure 4 , Figure 4 This is a flowchart illustrating the preparation method proposed in this embodiment of the invention. The preparation method includes the following steps: S1. The fabrication process begins with a composite wafer containing the support layer 1 and the polycrystalline silicon layer 2 as the basic structure of the piezoelectric substrate on the insulator.

[0026] S2. Fluorine-doped silicon oxide is deposited on the surface of the polycrystalline silicon layer 2 using a low-pressure plasma-enhanced chemical vapor deposition (PECVD) process to form the temperature compensation layer 3.

[0027] S3. Using atomic layer deposition (ALD) technology, aluminum oxide is deposited on the surface of the temperature compensation layer 3 to form the isolation layer 4.

[0028] S4. The wafer containing the piezoelectric material layer 5 is bonded to the surface of the isolation layer 4 to form the piezoelectric substrate on insulator 100.

[0029] Furthermore, step S2 also includes the following steps: The temperature compensation layer 3 is subjected to chemical mechanical polishing, and the polished temperature compensation layer is etched and adjusted based on a dry etching process to make the thickness of the temperature compensation layer 3 uniform.

[0030] By eliminating the non-uniformity of the surface and thickness of the fluorine-doped silicon oxide film, the formation of local acoustic resonant cavities due to film thickness non-uniformity is avoided, thereby reducing the excitation of clutter waves at the source. Furthermore, the treatment of thickness uniformity ensures that the film thickness does not form a matching resonance with the high-frequency acoustic wavelength, further preventing the standing wave coupling of the plate mode.

[0031] Furthermore, step S4 also includes the following steps: The piezoelectric material layer 5 is subjected to annealing, grinding and chemical mechanical polishing in sequence, and then the piezoelectric material layer 5 is thinned to a preset thickness.

[0032] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0033] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form under the guidance of the present invention without departing from the spirit and scope of the claims. All such changes are within the protection scope of the present invention.

Claims

1. A piezoelectric substrate on an insulator, characterized in that, The piezoelectric substrate on the insulator comprises, in a bottom-up layered order, a support layer, a polysilicon layer, a temperature compensation layer, an isolation layer, and a piezoelectric material layer, wherein: The support layer serves as the substrate of the piezoelectric substrate on the insulator and is used to provide support for the upper structure. The polycrystalline silicon layer is used to improve the bonding interface quality; The temperature compensation layer is used to compensate for the frequency temperature drift generated by the piezoelectric material layer; The isolation layer is used to limit the leakage of surface acoustic wave energy generated by the piezoelectric material layer into the lower layer structure; The piezoelectric material layer is used to convert electrical signals into surface acoustic waves and to propagate surface acoustic waves.

2. The piezoelectric substrate on an insulator according to claim 1, characterized in that, The temperature compensation layer is made of fluorine-doped silicon oxide material.

3. The piezoelectric substrate on an insulator according to claim 1, characterized in that, The insulating layer is made of alumina.

4. The piezoelectric substrate on an insulator according to claim 1, characterized in that, The support layer is made of high-resistivity silicon material.

5. A method for preparing a substrate, used to prepare a piezoelectric substrate on an insulator as described in any one of claims 1 to 4, characterized in that, The preparation method includes the following steps: S1. A composite wafer containing the support layer and the polysilicon layer is used as the basic structure of the piezoelectric substrate on the insulator. S2. A low-pressure plasma-enhanced chemical vapor deposition process is used to deposit fluorine-doped silicon oxide on the surface of the polycrystalline silicon layer to form the temperature compensation layer. S3. Using atomic layer deposition (ALD) technology, aluminum oxide is deposited on the surface of the temperature compensation layer to form the isolation layer; S4. A wafer containing the piezoelectric material layer is bonded to the surface of the isolation layer to form the piezoelectric substrate on the insulator.

6. The preparation method according to claim 5, characterized in that, Step S2 also includes: The temperature compensation layer is subjected to chemical mechanical polishing, and the polished temperature compensation layer is etched and adjusted based on a dry etching process to make the thickness of the temperature compensation layer uniform.

7. The preparation method according to claim 5, characterized in that, Step S4 also includes: The piezoelectric material layer is subjected to annealing, grinding and chemical mechanical polishing in sequence, and then the piezoelectric material layer is thinned to a preset thickness.

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