Power electronic circuit device and method of manufacturing

Abstract

The invention relates to a power electronic circuit arrangement having a first substrate conductor track on which a power semiconductor component is arranged and having a component contact region on a surface facing away from the first substrate conductor track, and a second substrate conductor track on which the power semiconductor component is arranged, the power electronic circuit arrangement has a plurality of uninterrupted wire-bonding connections, each wire-bonding connection having a first bonding leg on the second conductor track, a second bonding leg on the component contact region, and a third bonding leg on the second conductor track, wherein the first engaging leg and the third engaging leg are arranged adjacent to each other.

Description

Technical Field

[0001] The present invention describes a power electronic circuit device having a first substrate conductor track and a second substrate conductor track, wherein a power semiconductor component is disposed on the first substrate conductor track and has a component contact area on a surface opposite to the first substrate conductor track. The power electronic circuit device has a plurality of uninterrupted wire bonding connections, each wire bonding connection having a first bonding pin on the second conductor track, a second bonding pin on the component contact area, and a third bonding pin on the second conductor track. Background Technology

[0002] DE 10 201 5 120 157 A1 discloses a power electronic switching device having a substrate comprising a plurality of potential surfaces, wherein at least two different potentials are each assigned to at least one of these potential surfaces, wherein a plurality of semiconductor components are arranged in an n×m matrix oriented along the xy direction on a first conductor track formed by at least one potential surface of the first potential, and the semiconductor components are connected in parallel to each other to form a current valve. In this case, the semiconductor components can be distributed to the plurality of potential surfaces of the first potential, which form the first conductor track.

[0003] In light of the above situation, the present invention aims to improve the design of power electronic circuit devices (particularly individual lead-connected joints) and to specify a method for manufacturing such power electronic circuit devices.

[0004] According to the present invention, this objective is achieved by a power electronic circuit device having a first substrate conductor track and a second substrate conductor track, wherein a power semiconductor component is arranged on the first substrate conductor track and has a component contact area on a surface opposite to the first substrate conductor track, the power electronic circuit device having a plurality of uninterrupted lead-connection joints, each lead-connection joint having a first engagement pin on the first contact area (preferably on the second conductor track), a second engagement pin on the second contact area (preferably on the component contact area), and a third engagement pin on the first contact area (preferably on the second conductor track), wherein the first engagement pin and the third engagement pin are arranged adjacent to each other.

[0005] Here, the term "arranged adjacent to each other" is intended to specifically mean that the first and third terminals are not arranged on two different sides of the power semiconductor component. In other words, the area where the first and second terminals are located is only slightly larger than the area of ​​the power semiconductor component.

[0006] In principle, the first contact area and the second contact area can be arranged on any desired component, that is, in particular the power semiconductor component of a power electronic circuit device, the substrate conductor track, another conductor track, or the contact component.

[0007] First, if there is an odd number of lead-connected joints, it is preferable that the first to third connectors are arranged in a row in the intermediate lead-connected joints. Second, if there is an even number of lead-connected joints, it is preferable that the first to third connectors are arranged in a row in the two intermediate lead-connected joints.

[0008] Also preferably, in the case of multiple lead-connected joints, the first and second connecting feet of the respective lead-connected joints are arranged in a straight line, and the corresponding third connecting feet are arranged off-line. In this case, it is particularly preferred that the offset of the intermediate lead-connected joints or multiple intermediate lead-connected joints increases outward.

[0009] It may be advantageous that the maximum first height from the surface of the first conductor track to the first portion of the lead wire (which extends from the first joint foot to the second joint foot) is between 30% and 90% of the maximum second height from the surface of the first conductor track to the second portion of the lead wire (which extends from the second joint foot to the third joint foot), preferably between 50% and 80%.

[0010] Alternatively, another coupling pin is disposed on the component contact area, and a corresponding lead-connected portion extends from the first coupling pin to the second coupling pin, then to the other coupling pin, and then to the third coupling pin.

[0011] Preferably, the distance between the first and third terminals of the corresponding lead bonding connection is less than the diagonal of the power semiconductor component, particularly less than 0.8 times the diagonal.

[0012] Furthermore, it may be preferable that the distance between the first and third joints of the corresponding lead joint is less than 15 times the diameter of the joint lead of the lead joint, and particularly less than 10 times the diameter of the joint lead of the lead joint.

[0013] According to the present invention, the above objective is also achieved by a method for forming a power electronic circuit device according to the present invention, the method comprising the following steps: a) Forming a power electronic substrate having a first substrate conductor track and a second substrate conductor track, wherein power semiconductor components are arranged on the first substrate conductor track and have component contact areas on a surface opposite to the first substrate conductor track; b) Multiple uninterrupted lead-connected joints are formed sequentially, in each case by forming a first joint foot of a single lead-connected joint, followed by forming a second joint foot, and then forming a third joint foot.

[0014] It may be advantageous here that the first formed lead-connection is an intermediate lead-connection.

[0015] It goes without saying that features or groups of features mentioned in the singular may appear multiple times in the power electronic circuit device according to the invention, unless explicitly excluded or excluded on their own or inconsistent with the concept of the invention.

[0016] It should be understood that various improvements to the present invention, whether they are combined with power electronic circuit devices or method references, can be implemented individually or in any desired combination to achieve the improvement. In particular, the features presented and explained above and below can be used not only in the given combinations, but also in other combinations or individually, without departing from the scope of the invention. Attached Figure Description

[0017] Further explanation, advantageous details and features of the invention are derived from Figures 1 to 9 The following description illustrates exemplary embodiments of the invention or corresponding portions thereof.

[0018] Figure 1 A side view of a first improvement of the power electronic circuit device according to the present invention is shown.

[0019] Figures 2 to 4 A top view showing different configurations of the joint foot position of the first improvement.

[0020] Figure 5 A top view showing the location of the engagement pins in a first improved variant of the power electronic circuit device.

[0021] Figure 6 A top view showing the dimensional specifications of a power electronic circuit device according to the present invention.

[0022] Figure 7 A side view of a second improvement to the power electronic circuit device according to the present invention is shown.

[0023] Figure 8 and Figure 9 A top view showing different configurations of the joint foot position of the second improvement. Detailed Implementation

[0024] Figure 1A side view of a first improvement of a power electronic circuit device according to the present invention is shown. The figure shows the substrate of the circuit device, which has an electrically insulating layer 1 formed of industrial ceramic (such as alumina), purely by way of example. A first substrate conductor track 2 and a second substrate conductor track 3 are arranged on the electrically insulating layer 1. A power semiconductor component 4 is arranged on the first substrate conductor track 2, and the power semiconductor component 4 has a component contact region 5 on a surface facing away from the first substrate conductor track 2. Furthermore, the power semiconductor component 4 has additional component contact regions on a surface facing the first substrate conductor track 2, which are conductively connected to the first substrate conductor track 2. Purely by way of example, a connection component 300 of the power electronic circuit device is also arranged on the second substrate conductor track 3 and is conductively connected to the second substrate conductor track 3.

[0025] To electrically connect the component contact area 5 of the power semiconductor component 4 to the second substrate conductor track 3, the circuit arrangement in each case has a plurality of uninterrupted lead-bonding connections 6. Each of these lead-bonding connections 6 has a first bonding pin 61 on the second conductor track 3, a second bonding pin 62 on the component contact area 5, and a third bonding pin 63 on the second conductor track 3, which are formed in this order during production without interrupting the bonding leads. According to the invention, the first bonding pin 61 and the third bonding pin 63 are arranged adjacent to each other, in this embodiment on the same side of the power semiconductor component 4. This forms a first portion of lead 65 (extending from the first bonding pin 61 to the second bonding pin 62) and a second portion of lead 66 (extending from the second bonding pin 62 to the third bonding pin 63) continuously connected thereto in the lead-bonding connection 6.

[0026] Here, the maximum first height 650 of the first portion of the lead 65 to the lead joint connection 6 (which is measured in the z direction, i.e., the normal direction of the first base conductor track 2) is approximately 50% of the maximum second height 660. The second height 660 is measured from the surface of the first conductor track 2 to the second portion of the lead 66 in the same manner.

[0027] Figures 2 to 4 A top view showing different configurations of the position of the first improved coupling foot. In the following text, the third number of the reference numerals for the coupling foot indicates the ordinal number of the lead-wire coupling connection in each case.

[0028] Figure 2An odd number of lead-connected joints 6 are shown. Three lead-connected joints 6 are shown here purely by way of example, with only their connecting pins shown. The first connecting pins 611, 612, 613 and the third connecting pins 631, 632, 633 of each individual lead-connected joint are arranged here and in all other figures on the second substrate conductor track 3, while the second connecting pins 621, 622, 623 are arranged on the component contact area 5 of the power semiconductor component 4. In this improvement, the first to third connecting pins 611, 621, 631 are arranged in a row in the intermediate lead-connected joint, i.e., in a straight line. Similarly, all the first to third connecting pins 612, 622, 632, 613, 623, 633 of the other lead-connected joints are also arranged in a row.

[0029] and Figure 2 Conversely, the corresponding third engagement pins 631, 632, and 633 of all lead wire connection portions are not connected to... Figure 3 The first connecting pins 611, 612, 613 and the second connecting pins 621, 622, 623 are arranged in a row. These connecting pins are offset from the corresponding straight line arrangement.

[0030] and Figure 2 Conversely, the first to third coupling pins 611, 621, and 631 are only... Figure 4 The intermediate lead joints are arranged in a row. Conversely, the corresponding third joints 632, 633 of the other external lead joints are not arranged in a row with the first joints 612, 613 and the second joints 622, 623. These joints are offset from the corresponding straight line that defines the row, here away from the intermediate joint.

[0031] Figure 5 This is a top view showing the position of the connector pins of a first improved variant of a power electronic circuit device. The figure shows an even number of lead-connected joints 6; here, only four lead-connected joints 6 are shown as an example, with their connector pins only shown again. Here, the first to third connector pins 611, 621, 631, 614, 624, 634 are each arranged in a row in two intermediate lead-connected joints. Conversely, the corresponding third connector pins 632, 633 of the additional outer lead-connected joints are not arranged in a row with the first connector pins 612, 613 and the second connector pins 622, 623. They are arranged off-center from the corresponding straight line defining the row, here away from the intermediate connectors.

[0032] Figure 6A top view showing the dimensional specifications of a power electronic circuit device according to the present invention is provided. The figure shows a distance 670 between the first and third terminals 61 and 63 of the lead-connector, the distance being determined from the center of the respective terminals 61 and 63. Furthermore, a diagonal 672 of the power semiconductor component 4 is shown. Here, according to the present invention, this diagonal 672 is greater than the distance 670 between the first and third terminals 61 and 63 of the lead-connector.

[0033] Figure 7 A side view of a second improvement to the power electronic circuit device according to the invention is shown. This differs from the first improvement in that another bonding pin 64 is arranged next to the second bonding pin 62 along a corresponding uninterrupted lead bonding connection 6 on the component contact region 5 of the power semiconductor component 4. This lead bonding connection 6 is formed as follows: first, a first bonding pin 61 is formed on the second substrate conductor track 3; then, a second bonding pin 62 is formed on the component contact region 5; then, another bonding pin 64 is formed on the component contact region 5; and finally, a third bonding pin 63 is formed on the second substrate conductor track 3. According to the invention, this is accomplished without interrupting the bonding leads of each lead bonding connection 6.

[0034] Figure 8 and Figure 9 A top view showing different configurations of the engagement foot position in this second improvement. Figure 8 and Figure 2 The difference lies in that, in each case, another engagement foot 641, 642, 643 is arranged on the component contact area 5. Furthermore, the orientations of the first engagement feet 611, 612, 613 and the third engagement feet 631, 632, 633, arranged to be twisted into a straight line, are different. Here, purely as an example, the first engagement feet 611, 612, 613 are twisted in a first direction, while the third engagement feet 631, 632, 633 are twisted in the opposite direction to the first direction.

Claims

1. A power electronic circuit device having a first substrate conductor track (2) and a second substrate conductor track (3), wherein a power semiconductor component (4) is disposed on the first substrate conductor track (2), the power semiconductor component (4) having a component contact area (5) on a surface opposite to the first substrate conductor track (2), and the power electronic circuit device having uninterrupted wire bonding connections (6), each uninterrupted wire bonding connection (6) having a first bonding foot (61) on a first contact area, a second bonding foot (62) on a second contact area, and a third bonding foot (63) on the first contact area, wherein the first bonding foot (61) and the third bonding foot (63) are arranged adjacent to each other.

2. The power electronic circuit device according to claim 1, characterized in that: In the case of an odd number of lead-connected joints (6), the first to the third joints (611, 621, 631) are arranged in a row in the middle lead-connected joint.

3. The power electronic circuit device according to claim 1, characterized in that: In the case of an even number of lead-connected joints (6), the first to third joints (611, 621, 631, 614, 624, 634) are arranged in a row in the two intermediate lead-connected joints.

4. The power electronic circuit device according to any one of claims 1-3, characterized in that: In the case of multiple lead-connected joints (6), the first joint pins (611, 612, 613) and the second joint pins (621, 622, 623) of the corresponding lead-connected joints are arranged in a straight line, and the corresponding third joint pins (631, 632, 633) are arranged off-line.

5. The power electronic circuit device according to claim 4, characterized in that: The deviation of the middle lead wire joint connection (6) increases towards the outside.

6. The power electronic circuit device according to any one of claims 1-3, characterized in that: The maximum first height (650) of the first portion of the lead wire (65) from the surface of the first base conductor track (2) to the first portion of the lead wire (65) of the lead wire joint connection (6) is between 30% and 90% of the maximum second height (660) of the second portion of the lead wire (66) from the surface of the first base conductor track (2) to the second portion of the lead wire joint connection (6), the first portion of the lead wire extending from the first joint foot (61) to the second joint foot (62), and the second portion of the lead wire extending from the second joint foot (62) to the third joint foot (63).

7. The power electronic circuit device according to any one of claims 1-3, characterized in that: Another coupling pin (64) is arranged on the component contact area (5), and a corresponding lead-connected connection (6) extends from the first coupling pin (61) to the second coupling pin (62), then to the other coupling pin (64), and then to the third coupling pin (63).

8. The power electronic circuit device according to any one of claims 1-3, characterized in that: The distance (670) between the first and third joints of the corresponding lead-connected joint is less than the diagonal (672) of the power semiconductor component (4).

9. The power electronic circuit device according to any one of claims 1-3, characterized in that: The distance (670) between the first and third joints of the corresponding lead joint is less than 15 times the diameter of the joint lead of the lead joint.

10. The power electronic circuit device according to claim 1, characterized in that: The power electronic circuit device has multiple uninterrupted lead-connected joints (6).

11. The power electronic circuit device according to claim 1, characterized in that: The first connecting pin (61) is on the second base conductor track (3).

12. The power electronic circuit device according to claim 1, characterized in that: The second engagement foot (62) is on the component contact area (5).

13. The power electronic circuit device according to claim 1, characterized in that: The third coupling pin (63) is on the second base conductor track (3).

14. The power electronic circuit device according to claim 6, characterized in that: The maximum first height (650) is between 50% and 80% of the maximum second height (660).

15. The power electronic circuit device according to claim 8, characterized in that: The distance (670) is less than 0.8 times the diagonal (672) of the power semiconductor component (4).

16. The power electronic circuit device according to claim 9, characterized in that: The distance (670) is less than 10 times the diameter of the connecting lead of the lead joint.

17. A method for forming a power electronic circuit device according to any one of the preceding claims, comprising the following method steps: a. Forming a power electronic substrate having a first substrate conductor track (2) and a second substrate conductor track (3), wherein a power semiconductor component (4) is arranged on the first substrate conductor track (2), and the power semiconductor component (4) has a component contact area (5) on a surface opposite to the first substrate conductor track (2). b. Sequentially form multiple uninterrupted lead-connected joints (6). In each case, multiple uninterrupted lead-connected joints (6) are formed sequentially by forming a first joint foot (61) of a single lead-connected joint, followed by forming a second joint foot (62), followed by forming a third joint foot (63).

18. The method according to claim 17, characterized in that: The first formed lead-connection joint (6) is the middle lead-connection joint.

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