Selective multiplexing in analog simulation of integrated circuits

Abstract

A computing system may identify result data (302) corresponding to a simulation of a first circuit design (301) with a set of samples from a distribution describing manufacturing variations of an integrated circuit, determining that a second circuit design describing the integrated circuit is compatible with the first circuit design based on a comparison of a variable of the manufacturing variation in the first circuit design and a variable of the manufacturing variation in the second circuit design (342), and when simulating the second circuit design with values from a distribution describing manufacturing variations identified based at least in part on the result data corresponding to the simulation of the first circuit design, multiplexing at least a portion of the result data. The computing system may estimate a yield of the output of the integrated circuit described by the second circuit design based on the response of the second circuit design to the simulation (306).

Description

Technical Field

[0001] This application generally relates to electronic design automation, and more specifically to selective reuse in the simulation of integrated circuits. Background Technology

[0002] In circuit design verification, the conditions used to manufacture integrated circuits can be included in a foundry model, such as a SPICE model of various manufacturing parameters. A foundry model can describe the distribution of parameters that can vary during manufacturing (e.g., oxide thickness, oxide length, etc.).

[0003] Design verification tools can be used to evaluate circuit designs describing integrated circuits relative to manufacturing variability described in a foundry model. Designers can define the output of the circuit design and its performance specifications, which can be used during evaluation. Design verification tools can leverage this evaluation to determine the probability that a particular manufacturing variation described in the foundry model might cause the circuit design to fail to meet performance specifications.

[0004] When integrated circuit designers are concerned about rare failure events, such as when designing computer storage devices, popular techniques may include: performing Monte Carlo sampling of variable parameters in a foundry model, selecting a subset of samples furthest from the nominal parameter values, and then performing simulations of the circuit design at one or more process, voltage, and temperature (PVT) angles using the selected subset of samples. Design verification tools can then compare the simulation results to performance specifications to determine if a failure has occurred. This can inform designers whether the worst sample from the Monte Carlo sampling of the foundry model will cause the circuit design's output to fail to meet performance specifications. While this sampling and simulation technique can be effective, design verification tools typically run thousands of simulations per circuit design, which can be time- and resource-intensive. When integrated circuit manufacturers release new versions of foundry models, rerunning the analysis of the circuit design library may become impractical given the time and resource constraints. This forces many designers to make trade-offs, such as extending their design schedules, acquiring more computational resources, and allowing for margins in the circuit design, such as increasing circuit size or die area, increasing power, or reducing clock speed. Summary of the Invention

[0005] This application discloses a computational system that implements a design verification tool to identify resulting data corresponding to simulations of a first circuit design using a sample set from a distribution describing manufacturing variations of an integrated circuit. In some embodiments, the computational system implementing the design verification tool may utilize a machine learning model of the first circuit design to select a sample set from the distribution describing manufacturing variations. The computational system implementing the design verification tool may determine, at least in part, that a second circuit design describing the integrated circuit is compatible with the first circuit design based on a comparison of manufacturing variation variables in the first circuit design and in a second circuit design, and reuse at least a portion of the resulting data when simulating the second circuit design. In some embodiments, the simulation of the second circuit design may reuse values ​​from a distribution describing the manufacturing variations identified from the simulation of the first circuit design. The computational system implementing the design verification tool may estimate the yield of the output of the integrated circuit described by the second circuit design based on the second circuit design's response to the simulation. The computational system implementing the design verification tool may also compare the estimated yield associated with the second circuit design with the estimated yield in the resulting data associated with the first circuit design. The computational system implementing the design verification tool can select different sample sets from a distribution describing manufacturing variation based on a comparison of the yield associated with a second circuit design and the yield associated with a first circuit design. The computational system implementing the design verification tool can then use these different sample sets from the distribution describing manufacturing variation to simulate the second circuit design. In some embodiments, the computational system implementing the design verification tool can use a machine learning model of the first circuit design to select different sample sets from the distribution describing manufacturing variation. Embodiments will be described in more detail below. Attached Figure Description

[0006] Figure 1 and Figure 2 Examples of computer systems of various types that can be used to implement the various embodiments are illustrated.

[0007] Figure 3 Examples of design verification tools for additive learning by selectively reusing simulation data from previous circuit designs, which can be implemented according to various embodiments, are illustrated.

[0008] Figure 4 The flowchart illustrates an example implementation of estimating integrated circuit yield by sampling the distribution of manufacturing variability, based on various examples.

[0009] Figure 5 Flowcharts illustrating example implementations of additive learning by selectively reusing existing circuit design simulation data are provided, based on various examples. Detailed Implementation

[0010] Explanatory operating environment

[0011] Various examples can be implemented by executing software instructions by computing device 101 (e.g., a programmable computer). Therefore, Figure 1 An illustrative example of a computing device 101 is shown. As seen in the figure, the computing device 101 includes a computing unit 103 having a processor unit 105 and a system memory 107. The processor unit 105 can be any type of programmable electronic device for executing software instructions, but will typically be a microprocessor. The system memory 107 may include a read-only memory (ROM) 109 and a random access memory (RAM) 111. As will be understood by those skilled in the art, both the read-only memory (ROM) 109 and the random access memory (RAM) 111 can store software instructions for execution by the processor unit 105.

[0012] Processor unit 105 and system memory 107 are connected directly or indirectly, via bus 113 or alternative communication structures, to one or more peripheral devices 115-123. For example, processor unit 105 or system memory 107 may be directly or indirectly connected to one or more additional storage devices, such as magnetic and / or removable hard disk drives 117, removable optical disk drives 119, and / or flash memory cards. Processor unit 105 and system memory 107 may also be directly or indirectly connected to one or more input devices 121 and one or more output devices 123. Input devices 121 may include, for example, a keyboard, pointing devices (e.g., a mouse, touchpad, stylus, trackball, or joystick), scanners, cameras, and microphones. Output devices 123 may include, for example, monitor displays, printers, and speakers. For various examples of computing device 101, one or more peripheral devices 115-123 may be housed internally with computing unit 103. Alternatively, one or more peripheral devices 115-123 may be located outside the housing of computing unit 103 and connected to bus 113 via, for example, a Universal Serial Bus (USB) connection.

[0013] In some implementations, computing unit 103 may be directly or indirectly connected to network interface 115 to communicate with other devices comprising the network. Network interface 115 may convert data and control signals from computing unit 103 into network messages according to one or more communication protocols, such as Transmission Control Protocol (TCP) and Internet Protocol (IP). Furthermore, network interface 115 may employ any suitable connection proxy (or combination of proxies) to connect to the network, including, for example, a wireless transceiver, modem, or Ethernet connection. Such network interfaces and protocols are well known in the art and will not be discussed in further detail here.

[0014] It should be understood that computing device 101 is merely illustrative and is not intended to be limiting. Various embodiments may be implemented using one or more computing devices, including... Figure 1 The components of the computing device 101 illustrated herein include only... Figure 1 A subset of the components illustrated, or including alternative combinations of components, including Figure 1 Components not shown. For example, various embodiments may be implemented using a multiprocessor computer, multiple single-processor and / or multiprocessor computers arranged in a network, or some combination of both.

[0015] In some implementations, processor unit 105 may have more than one processor core. Therefore, Figure 2 An example of a multi-core processor unit 105 that can be used with various embodiments is illustrated. As seen in the figure, the processor unit 105 includes a plurality of processor cores 201A and 201B. Each processor core 201A and 201B includes a compute engine 203A and a compute engine 203B, as well as a memory cache 205A and a memory cache 205B, respectively. As will be known to those skilled in the art, compute engines 203A and 203B may include logic devices for performing various computational functions, such as fetching software instructions and then executing actions specified in the fetched instructions. These actions may include, for example, adding, subtracting, multiplying, and comparing numbers, performing logical operations (e.g., AND, OR, NOR, and XOR), and retrieving data. Each compute engine 203A and 203B may then use its corresponding memory cache 205A and 205B, respectively, to quickly store and retrieve data and / or instructions for execution.

[0016] Each processor core 201A and 201B is connected to interconnect 207. The specific configuration of interconnect 207 can vary depending on the architecture of processor unit 105. For some processor cores 201A and 201B (e.g., Cell microprocessors created by Sony, Toshiba, and IBM), interconnect 207 can be implemented as an interconnect bus. However, for other processor units 201A and 201B (e.g., Opteron™ and Athlon™ dual-core processors available from Advanced Micro Devices, Sunnyvale, California), interconnect 207 can be implemented as a system request interface device. In any case, processor cores 201A and 201B communicate with input / output interface 209 and memory controller 210 via interconnect 207. Input / output interface 209 provides a communication interface to bus 113. Similarly, memory controller 210 controls the exchange of information to system memory 107. In some implementations, processor unit 105 may include additional components, such as an advanced cache memory accessible by processor cores 201A and 201B. It should also be understood that... Figure 1 and Figure 2 The description of the illustrated computer networks is provided by way of example only and is not intended to impose any limitation on the scope or functionality of alternative embodiments.

[0017] Selective multiplexing in integrated circuit simulation

[0018] Figure 3 An example design verification tool 300 is illustrated, which can be implemented according to various embodiments to perform additive learning by selectively reusing simulation data from previous circuit designs. Figure 4 Flowcharts illustrating example implementations of estimating integrated circuit yield by sampling the distribution of manufacturing variability are provided, based on various examples. (Reference) Figure 3 and Figure 4 For example, using Figure 1 The design verification tool 300 implemented in the computing device 101 described herein can receive circuit designs 301 that describe electronic devices (e.g., integrated circuits) in a transistor-level netlist format. The circuit design 301 may correspond to transistor-level netlists, which describe electronic circuits using, for example, metal-oxide-semiconductor (MOS) transistors, resistors, capacitors, inductors, etc., in a Simulation Program with Integrated Circuit Emphasis (SPICE) file format. In some embodiments, the circuit design 301 may be a standard cell design, for example, within a standard cell library used by the design verification tool 300 to characterize or estimate yield.

[0019] Design verification tool 300 may receive foundry model 302 to describe manufacturing parameters (e.g., oxide thickness, oxide length, etc.) and how these parameters may vary during manufacturing. In some embodiments, foundry model 302 may describe the statistical conditions used to manufacture circuit design 301 (e.g., defining the distribution of values ​​for manufacturing parameters). In some embodiments, foundry model 302 may be specified in SPICE file format.

[0020] Design verification tool 300 may receive specifications 303 for the performance or operation of circuit design 301. In some embodiments, specifications 303 may define outputs associated with circuit design 301 and define when the values ​​of the outputs will correspond to a failure. For example, specifications 303 may define minimum and maximum values ​​for the outputs in circuit design 301, and consider the performance of circuit design 301 to have failed when the output value drops below the minimum or exceeds the maximum. Design verification tool 300 may also receive process corners, which define a combination of factors (e.g., process, voltage, and temperature (PVT)) used to manufacture and / or operate the integrated circuit described by circuit design 301.

[0021] Design verification tool 300 may include surrogate modeling system 310 to construct a surrogate model that approximates the output response of circuit design 301 to variability in manufacturing parameters described in foundry model 302. When simulated with different sets of manufacturing variations, the surrogate model can provide an output response similar to that of circuit design 301 simulated with the same set of manufacturing variations, and simulation system 350 can simulate the surrogate model faster than circuit design 301. In some embodiments, the surrogate model may be a machine learning model of circuit design 301, a simple linear regression model, a multinomial model, a piecewise linear regression model, etc.

[0022] The surrogate modeling system 310 may, for example, receive training samples of the manufacturing variation distribution from the sampling system 320. The sampling system 320 may include a sample generator to sample the distribution of the values ​​of manufacturing parameters in the foundry model 302. In some embodiments, each training sample may be a Monte Carlo sample randomly drawn from the distribution of the values ​​of the manufacturing parameters.

[0023] The proxy modeling system 310 can guide the simulation system 350 to iteratively set the manufacturing parameters of the circuit design 301 to correspond to different training samples, and... Figure 4In block 401, a test bench is used to simulate a circuit design 301 configured with different training samples. The test bench can define test stimuli, such as clock signals, activation signals, power signals, control signals, data signals, etc., which, when grouped, can form test bench transactions that facilitate the operation of the circuit design 301 in a simulation environment. In some embodiments, the test bench can be written in an object-oriented programming language (e.g., SystemVerilog), which can dynamically generate test bench components for verifying the circuit design 301 when executed during refinement. Method libraries (e.g., Universal Verification Method (UVM) library, Open Verification Method (OVM) library, Advanced Verification Method (AVM) library, Verification Method Manual (VMM) library, etc.) can be used as the basis for creating the test bench. Figure 4 In box 402, the surrogate modeling system 310 can generate a surrogate model of the circuit design 301 based at least in part on the simulation results of the circuit design 301 set with different training samples.

[0024] After the surrogate model of circuit design 301 has been generated by surrogate modeling system 310, sampling system 320 can perform sampling of parameter values ​​in foundry model 302, which describes the variations in parameter values ​​used in the manufacturing process. For example, in Figure 4 In box 403, sampling system 320 can select samples from a manufacturing variation distribution for use in a surrogate model of simulation circuit design 301. Sampling of the distribution can be performed by randomly selecting parameter values ​​from the distribution (e.g., Monte Carlo samples randomly drawn from a distribution of manufacturing parameter values).

[0025] exist Figure 4 In box 404, the simulation system 350 can use samples to simulate the surrogate model to generate simulation results and identify outlier samples 305. Since the operation of the circuit design 301 modeled by the surrogate model can vary based on parameter values, the simulation system 350 simulating the surrogate model can generate output values ​​defined in specification 303, which also vary. The design verification tool 300 can determine whether any output value determined during simulation falls outside specification 303, for example, exceeding the maximum value of the output or falling below the minimum value of the output. The design verification tool 300 can identify outlier samples 305 as those samples that cause the output determined during the simulation of the surrogate model to fall outside specification 303.

[0026] exist Figure 4In block 405, design verification tool 300 can guide simulation system 350 to simulate circuit design 301 using outlier samples 305 corresponding to parameter values ​​within foundry model 302. Simulation system 350 can generate simulation results 351, which may include the values ​​of the parameters used during simulation and the values ​​of the output generated using the parameter values. In some embodiments, simulation system 350 can perform simulation of circuit design 301 using multiple process corners (e.g., integrated circuits manufactured using different processes, operating at different drive voltages, and / or operating under different environmental conditions (e.g., temperature)).

[0027] Design verification tool 300 may include yield estimation system 330, which in Figure 4 In box 406, the yield of the output in the circuit design 301 describing the integrated circuit can be estimated at least in part based on simulation results 351. The yield estimation system 330 can determine when the value of the output in the simulation results 351 falls outside specification 303, and estimates the yield at least in part based on this determination. The yield estimation system 330 can output a yield estimate 306 that predicts the yield of the output defined in specification 303 given the parameter distribution described in foundry model 302. The yield estimation system 330 can determine the output yield estimate 306 based on the estimated failure probability of the output for the parameter distribution. The design verification tool 300 and the simulation system 350 can record the simulation results 351, along with the circuit design 301, foundry model 302, specification 303, surrogate model, outlier samples 305, and yield estimate 306, in the results database 360.

[0028] Design verification tool 300 may include simulation reuse system 340 to identify when design verification tool 300 can reuse simulation data from previous circuit design simulations to accelerate the simulation process of circuit design 301, for example by skipping the above references. Figure 4 At least a portion of the simulation process described, such as generating a surrogate model or identifying outlier samples 305. References will follow. Figure 3 and Figure 5 An embodiment of circuit simulation multiplexing implemented by simulation multiplexing system 340 is described.

[0029] Figure 5 Flowcharts illustrating example implementations of additive learning by selectively reusing simulation data from existing circuit designs are provided, based on various examples. (Reference) Figure 3 and Figure 5 ,exist Figure 5 In block 501, simulation multiplexing system 340 can receive circuit design 301 describing an integrated circuit to perform simulation using a distribution of manufacturing variations (e.g., from foundry model 302). In some embodiments, not as referenced above... Figure 4 Instead of directly performing the entire yield estimation analysis on the circuit design 301 as described above, the design verification tool 300 can first allow the simulation reuse system 340 to analyze the circuit design 301 to determine whether any previous circuit design simulation can include information such as previously identified outliers, previously generated surrogate models, etc., which can be reused in the simulation of the circuit design 301, for example, to accelerate the entire simulation process.

[0030] The simulation reuse system 340 may include a compatibility system 342, which in Figure 5 In box 502, a compatibility check can be performed between circuit design 301 and at least one other circuit design previously simulated using manufacturing variations. When compatibility system 342 determines that circuit design 301 is compatible with at least one other previously simulated circuit design, design verification tool 300 can access result data 307 corresponding to the previously simulated circuit design (which is stored, for example, in result database 360), and selectively reuse some of the result data 307 in the analysis of circuit design 301.

[0031] The compatibility system 342 may include a circuit topology system 343 to identify variables of manufacturing variation input to circuit design 301 and to previously simulated circuit designs, such as those stored in a results database 360. In some embodiments, the circuit topology system 343 may identify the variables of manufacturing variation as statistical variables having an associated distribution of manufacturing variation, for example, in a netlist associated with circuit design 301 or a previously simulated circuit design. The circuit topology system 343 may compare the identified variables of manufacturing variation associated with circuit design 301 and the previously simulated circuit design with each other. In some embodiments, when circuit design 301 and the previously simulated circuit design have the same or substantially similar variables of manufacturing variation, the circuit topology system 343 may determine that circuit design 301 is compatible with at least one of the previously simulated circuit designs.

[0032] The circuit topology system 343 can also identify the topology of circuit design 301 and (e.g., stored in the results database 360) previously simulated circuit designs. In some embodiments, the circuit topology system 343 can identify the topology by identifying transistors within circuit design 301 and previously simulated circuit designs and their possible corresponding parameter values. The circuit topology system 343 can compare the identified circuit design 301 and the previously simulated circuit designs with each other. In some embodiments, the circuit topology system 343 can determine that circuit design 301 is compatible with at least one of the previously simulated circuit designs based on the comparison of transistors within circuit design 301 and previously simulated circuit designs and their possible corresponding parameter values. For example, when circuit design 301 has the same transistors as a previously simulated circuit design, the circuit topology system 343 can consider circuit design 301 and the previously simulated circuit design to be compatible.

[0033] The compatibility system 342 may include a sequence consistency system 344 to confirm the compatibility determination made by the circuit topology system 343. The sequence consistency system 344 may instruct the simulation system 350 to simulate circuit design 301 using samples from a previously simulated circuit design, and to determine the order of samples based on the outputs from circuit design 301 during simulation. The sequence consistency system 344 may access a results database 360 ​​to obtain results data 307 including the sample order of previously simulated circuit designs, and compare the sample order between circuit design 301 and the previously simulated circuit design. In some embodiments, the sequence consistency system 344 may confirm the compatibility of circuit design 301 with the previously simulated circuit design when the sample order is the same and / or when the ordered samples corresponding to failed outputs are the same in circuit design 301 and the previously simulated circuit design.

[0034] When the compatibility system 342 determines in block 503 of the figure that the circuit design 301 is incompatible with the previously simulated circuit design, execution can proceed to... Figure 5 Box 510, where the design verification tool 300 performs the operation as described above (see reference above). Figure 4 The complete yield analysis is performed, and the simulation results are stored in the results database 360. In some embodiments, the stored simulation results can be reused by the simulation multiplexing system 340 when analyzing different circuit designs in the future.

[0035] When the compatibility system 342 in block 503 of the figure determines that the circuit design 301 is compatible with the previously simulated circuit design, execution can proceed to... Figure 5 Box 504, wherein the simulation system 350 uses outlier samples used in previous simulations of the compatible circuit design to simulate the circuit design 301.

[0036] exist Figure 5 In block 505, yield estimation system 330 can estimate the yield of the output in circuit design 301, which describes an integrated circuit used in outlier sample simulations of previous simulations of a compatible circuit design. Yield estimation system 330 can determine when the value of the output in the simulation results falls outside specification 303, and estimate the yield at least in part based on that determination.

[0037] The simulation reuse system 340 can compare the estimated yield of the circuit design 301 simulated using outlier samples from previous simulations of the compatible circuit design with the estimated yield for the compatible circuit design. When in Figure 5 In block 506, when the estimated yield of simulation multiplexing system 340 has been determined to be unchanged between the simulation of circuit design 301 and the simulation of compatible circuit design, execution can proceed to... Figure 5 Box 509 in the diagram shows that the verification tool 300 can record simulation results, along with circuit designs 301, foundry models 302, specifications 303, yield estimates, and outlier samples used for yield estimation, in the results database 360.

[0038] When in Figure 5 In block 506, when the simulation multiplexing system 340 has determined that the estimated yield does indeed vary between the simulation of circuit design 301 and the simulation of compatible circuit design, execution can proceed to... Figure 5 In box 507, the sampling system 320 can utilize a surrogate model associated with the compatible circuit design to identify distinct outlier sets from the distribution of manufacturing variations (e.g., in foundry model 302). By reusing the surrogate model associated with the compatible circuit design, the design verification tool 300 can skip generating a new surrogate model for the circuit design 301, which can accelerate throughput and reduce processing and simulation resource consumption. In some embodiments, such as where the yield estimation process does not include a surrogate model, execution can instead proceed to box 510, where the design verification tool 300 performs a full yield analysis and stores the simulation results in the results database 360. In some embodiments, instead of performing a yield analysis, the design verification tool 300 can use samples of manufacturing variations from the simulation of the circuit design 301 to construct the output distribution of the circuit design 301.

[0039] In some embodiments, instead of execution blocks 504 to 506, the simulation multiplexing system 340 may perform compatibility verification between circuit design 301 and previously simulated circuit designs by: simulating circuit design 301 using samples from the manufacturing variation distribution; determining the order of samples based on the outputs from circuit design 301 during simulation; and comparing the order of samples between circuit design 301 and previously simulated circuit designs. When the simulation multiplexing system 340 determines that the sample order is consistent, it may construct the output distribution of circuit design 301 based on the simulation samples and result data 307. When the simulation multiplexing system 340 determines that the sample order lacks consistency, execution may proceed to block 510, where a full analysis is performed to generate the output distribution of circuit design 301.

[0040] exist Figure 5 In block 508, the simulation system 350 simulates circuit design 301 using different sets of outliers used in previous simulations of the compatible circuit design. In some embodiments, before simulation by the simulation system 350, the simulation multiplexing system 340 may determine whether the different sets of outliers have an order consistency with the outliers used in previous simulations of the compatible circuit design, and the simulation system 350 may use different sets of outliers to simulate circuit design 301 if the different sets of outliers have an order consistency with the outliers used in previous simulations of the compatible circuit design. When the different sets of outliers do not have an order consistency with the outliers used in previous simulations of the compatible circuit design, execution proceeds to block 510, where the design verification tool 300 performs a full yield analysis and stores the simulation results in the results database 360.

[0041] After the simulation system 350 simulates the circuit design using different sets of outliers, execution returns to block 505, where the yield estimation system 330 estimates the yield of the output in the circuit design, which describes the integrated circuit simulated using different sets of outliers. The yield estimation system 330 can determine when the output value in the simulation results falls outside specification 303, and estimates the yield at least in part based on this determination.

[0042] Then, execution can proceed to decision box 506, where the simulation reuse system 340 can compare the estimated yield of the circuit design simulated using different outlier sample sets with the estimated yield for a compatible circuit design. When in Figure 5 In box 506, simulation multiplexing system 340 has determined that the estimated yield does not change between the simulation of the circuit design and the simulation of the compatible circuit design, and execution can proceed to... Figure 5Box 509 in the diagram shows that the verification tool 300 can record simulation results, along with circuit designs 301, foundry models 302, specifications 303, yield estimates, and outlier samples used for yield estimation, in the results database 360.

[0043] When in Figure 5 In box 506, when the simulation multiplexing system 340 has determined that the estimated yield does indeed vary between the simulation of the circuit design and the simulation of the compatible circuit design, execution can proceed to... Figure 5 In box 510, the verification tool 300 is designed to perform a full yield analysis and store the simulation results in the results database 360.

[0044] The systems and apparatuses described herein may use dedicated processor systems, microcontrollers, programmable logic devices, microprocessors, or any combination thereof to perform some or all of the operations described herein. Some of the operations may be implemented in software, while others may be implemented in hardware. Any operations, processes, and / or methods described herein may be performed by apparatus, devices, and / or systems substantially similar to those described herein and with reference to the illustrated figures.

[0045] A processing device can execute instructions or "code" stored in memory. Memory can also store data. A processing device can be, but is not limited to, analog processors, digital processors, microprocessors, multi-core processors, processor arrays, network processors, etc. A processing device can be part of an integrated control system or system manager, or it can be provided as a portable electronic device configured to interface locally or remotely with a networked system via wireless transmission.

[0046] Processor memory can be integrated with the processing device, such as RAM or flash memory disposed within an integrated circuit microprocessor. In other examples, memory can include separate devices, such as external disk drives, storage arrays, portable flash key cards, etc. Memory and processing devices can be operatively coupled together or communicate with each other, for example, via I / O ports, network connections, etc., and the processing device can read files stored on the memory. Depending on access settings, associated memory may be designed to be "read-only" (ROM) or not. Other examples of memory may include, but are not limited to, WORM, EPROM, EEPROM, flash memory, etc., which can be implemented in solid-state semiconductor devices. Other memory may include moving parts, such as known spinning disk drives. All of these memories can be "machine-readable" and can be read by the processing device.

[0047] Operating instructions or commands may be implemented or embodied in the tangible form of stored computer software (also known as a “computer program” or “code”). The program or code may be stored in digital memory and may be read by a processing device. A “computer-readable storage medium” (or alternatively, a “machine-readable storage medium”) may include all of the aforementioned types of memory as well as future technologies, provided that the memory is capable of storing digital information having the nature of a computer program or other data, at least temporarily, and provided that the stored information can be “read” by a suitable processing device. The term “computer-readable” may not be limited to the historical use of “computer” to imply the complete use of mainframes, minicomputers, desktops, or even laptop computers. Rather, “computer-readable” may include storage media that can be read by a processor, processing device, or any computing system. Such media may be any available media that can be accessed locally and / or remotely by a computer or processor, and may include volatile and non-volatile media, removable and non-removable media, or any combination thereof.

[0048] A program stored in a computer-readable storage medium may include a computer program product. For example, the storage medium can serve as a convenient means of storing or transmitting a computer program. For convenience, operations may be described as various interconnected or coupled functional blocks or diagrams. However, there may be situations where these functional blocks or diagrams can be equivalently aggregated into a single logic device, program, or operation without clear boundaries.

[0049] in conclusion

[0050] While this application describes specific examples of embodiments of the invention, those skilled in the art will understand that many variations and substitutions of the systems and techniques described above fall within the spirit and scope of the invention as set forth in the appended claims. For example, although specific terms have been used above to refer to the design process, it should be understood that various examples of the invention can be implemented using any desired combination of electronic design automation processes.

[0051] Those skilled in the art will also recognize that the concepts taught herein can be adapted to a particular application in many other ways. In particular, those skilled in the art will recognize that the illustrated examples are merely one of many alternative implementations that will become apparent upon reading this disclosure.

[0052] Although the specification may mention “one,” “an,” “another,” or “some” examples in several places, this does not necessarily mean that each such reference refers to the same one or more examples or that the feature applies only to a single example.

Claims

1. A method comprising: The computing system identifies and uses the corresponding simulation results of a first circuit design based on a sample set from a distribution that describes the manufacturing variations of the integrated circuit described by the first circuit design; The computing system determines, at least in part, that the second circuit design describing the integrated circuit is compatible with the first circuit design by comparing the variables of manufacturing variation in the first circuit design with the variables of manufacturing variation in the second circuit design. as well as The computing system uses values ​​from the distribution to simulate the second circuit design, the distribution describing the manufacturing variations identified at least in part based on the resulting data corresponding to the simulation of the first circuit design.

2. The method according to claim 1, wherein, Determining that the second circuit design is compatible with the first circuit design is based, at least in part, on a comparison of the topology and parameter values ​​between the first and second circuit designs.

3. The method according to claim 1, wherein, Determining that the second circuit design is compatible with the first circuit design also includes: The second circuit design was simulated using compatibility samples obtained from the distribution that produced the variation; The order of the compatibility samples associated with the simulation of the second circuit design is compared with the order of the sample set in the result data corresponding to the simulation of the first circuit design; and The second circuit design is determined to be compatible with the first circuit design, at least in part, based on the comparison.

4. The method according to claim 1, further comprising: The computing system estimates the yield of the output of the integrated circuit described by the second circuit design based on the response of the second circuit design to the sample set of the distribution describing the manufacturing variations of the integrated circuit described by the first circuit design.

5. The method according to claim 4, further comprising: The computing system compares the yield associated with the second circuit design with the yield in the result data corresponding to the simulation of the first circuit design; The computing system selects different sample sets from the distribution describing the manufacturing variation based on the comparison between the yield associated with the second circuit design and the yield associated with the first circuit design. as well as The computing system uses the different sets of samples from the distribution describing the manufacturing variation to simulate the second circuit design.

6. The method according to claim 5, wherein, The simulation of the first circuit design includes selecting the sample set from the distribution describing the manufacturing variation using a machine learning model of the first circuit design, wherein the selection of the different sample sets from the distribution describing the manufacturing variation uses the machine learning model of the first circuit design.

7. The method according to claim 1, wherein, The distribution describing the manufacturing variation of the integrated circuit is the distribution of parameter values ​​in the foundry model, which describes the parameter variations of the manufacturing process capable of manufacturing the integrated circuit described in the first circuit design.

8. A system comprising: A storage system configured to store computer-executable instructions; as well as A computing system, which responds to the execution of said computer-executable instructions, is configured to: Identify and utilize the result data corresponding to the simulation of the first circuit design using a sample set from a distribution that describes the manufacturing variations of the integrated circuit described by the first circuit design; The second circuit design describing the integrated circuit is determined to be compatible with the first circuit design based at least in part on a comparison of manufacturing variation variables in the first circuit design and manufacturing variation variables in the second circuit design. as well as The second circuit design is simulated using values ​​from the distribution, which describes the manufacturing variations identified at least in part based on the resulting data corresponding to the simulation of the first circuit design.

9. The system according to claim 8, wherein, The computing system, in response to the execution of the computer-executable instructions, is further configured to determine, at least in part, that the second circuit design is compatible with the first circuit design based on a comparison of topology and parameter values ​​between the first circuit design and the second circuit design.

10. The system according to claim 8, wherein, In response to the execution of the computer-executable instructions, the computing system is further configured to determine that the second circuit design is compatible with the first circuit design by: The second circuit design was simulated using compatibility samples obtained from the distribution that produced the variation; The order of the compatibility samples associated with the simulation of the second circuit design is compared with the order of the sample set in the result data corresponding to the simulation of the first circuit design; as well as The second circuit design is determined to be compatible with the first circuit design, at least in part, based on the comparison.

11. The system according to claim 8, wherein, The computing system, in response to the execution of the computer-executable instructions, is further configured to: estimate the yield of the output of the integrated circuit described by the second circuit design based on the response of the second circuit design to the sample set of the distribution describing the manufacturing variations of the integrated circuit described by the first circuit design.

12. The system according to claim 11, wherein, The computing system, in response to the execution of the computer-executable instructions, is further configured to: The yield associated with the second circuit design is compared with the yield in the result data corresponding to the simulation of the first circuit design; Based on the comparison between the yield associated with the second circuit design and the yield associated with the first circuit design, different sample sets are selected from the distribution describing the manufacturing variation; as well as The second circuit design is simulated using the different sample sets from the distribution describing the manufacturing variation.

13. The system according to claim 12, wherein, The simulation of the first circuit design includes selecting the sample set from the distribution describing the manufacturing variation using a machine learning model of the first circuit design, and wherein the computing system is further configured to select the different sample sets from the distribution describing the manufacturing variation using the machine learning model of the first circuit design in response to the execution of the computer-executable instructions.

14. An apparatus for at least one computer-readable storage device including storage instructions, the instructions being configured to cause one or more processing devices to perform an operation, the operation comprising: Identify and utilize the result data corresponding to the simulation of the first circuit design using a sample set from a distribution that describes the manufacturing variations of the integrated circuit described by the first circuit design; The second circuit design describing the integrated circuit is determined to be compatible with the first circuit design based at least in part on a comparison of manufacturing variation variables in the first circuit design and manufacturing variation variables in the second circuit design. as well as The second circuit design is simulated using values ​​from the distribution, which describes the manufacturing variations identified at least in part based on the resulting data corresponding to the simulation of the first circuit design.

15. The apparatus according to claim 14, wherein, Determining that the second circuit design is compatible with the first circuit design is based, at least in part, on a comparison of the topology and parameter values ​​between the first and second circuit designs.

16. The apparatus according to claim 14, wherein, Determining that the second circuit design is compatible with the first circuit design also includes: The second circuit design was simulated using compatibility samples obtained from the distribution that produced the variation; The order of the compatibility samples associated with the simulation of the second circuit design is compared with the order of the sample set in the result data corresponding to the simulation of the first circuit design; and The second circuit design is determined to be compatible with the first circuit design, at least in part, based on the comparison.

17. The apparatus according to claim 14, wherein, The instructions are configured to cause one or more processing devices to perform an operation, the operation further comprising: estimating the yield of the output of the integrated circuit described by the second circuit design based on the response of the second circuit design to a sample set of a distribution describing manufacturing variations of the integrated circuit described by the first circuit design.

18. The apparatus according to claim 17, wherein, The instructions are configured to cause one or more processing devices to perform an operation, the operation further comprising: The yield associated with the second circuit design is compared with the yield in the result data corresponding to the simulation of the first circuit design; Based on the comparison of the yield associated with the second circuit design and the yield associated with the first circuit design, different sample sets are selected from the distribution describing the manufacturing variation; and The second circuit design is simulated using the different sample sets from the distribution describing the manufacturing variation.

19. The apparatus according to claim 18, wherein, The simulation of the first circuit design includes selecting the sample set from the distribution describing the manufacturing variation using a machine learning model of the first circuit design, wherein the selection of the different sample sets from the distribution describing the manufacturing variation uses the machine learning model of the first circuit design.

20. The apparatus according to claim 14, wherein, The distribution describing the manufacturing variation of the integrated circuit is the distribution of parameter values ​​in the foundry model, which describes the parameter variations of the manufacturing process capable of manufacturing the integrated circuit described in the first circuit design.

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