Phase reconfigurable circuit with dynamic phase modulation for broadband dual input power amplifiers

Abstract

A phase reconfigurable circuit (100) for a dual input power amplifier is provided. The circuit (100) includes an envelope detector (120) configured to process an envelope of the RF input signal into an envelope signal. A first vector and phase shifter (140) and a second vector and phase shifter (145) process an in-phase version and a quadrature-phase version of the RF input signal and the envelope signal to produce a first differential output signal having a dynamically modulated phase difference from the second differential output signal.

Description

Cross-references to related applications

[0001] This application claims priority and benefit to U.S. nonprovisional patent application No. 18 / 471,231, filed September 20, 2023, the entire contents of which are incorporated herein by reference as fully set forth herein and for all applicable purposes. Technical Field

[0002] This disclosure relates generally to wireless communication, and more specifically to a phase-reconfigurable circuit with dynamic phase modulation for a broadband dual-input power amplifier. Background Technology

[0003] Orthogonal Frequency Division Modulation (OFDM), used in modern telecommunications systems such as 5G, makes efficient use of bandwidth, but at the cost of a relatively high peak-to-average power ratio (PAPR). This high PAPR complicates the design of power amplifiers for such systems. For example, if a power amplifier is biased to achieve good efficiency at the average power of the transmitted signal, it may clip or saturate at peak power, resulting in nonlinearity. Conversely, if a power amplifier is biased to achieve good efficiency at peak power, it will be inefficient at the average power level. Therefore, conventional power amplifiers used for OFDM signals must be chosen between those with good linearity but poor efficiency, or those with high efficiency but poor linearity.

[0004] To achieve both high efficiency and high linearity within the same system, dual-input amplifiers, such as the Doherty amplifier, have been developed, which comprises both a carrier amplifier and a peak amplifier. Doherty amplifiers require phase-reconfigurable circuitry to separate and phase-shift the input signal to drive both the peak and carrier amplifiers, and also require an output network to combine the output signals from the peak and carrier amplifiers. In a conventional Doherty amplifier, the phase-reconfigurable circuitry phase-shifts the input signal to the peak amplifier by -90° compared to the input signal to the carrier amplifier. To enhance performance, generalized Doherty amplifiers have been developed, in which the phase shift is no longer set to -90° but can be tuned to any suitable value. Summary of the Invention

[0005] The following summary discusses some aspects of this disclosure to provide a basic understanding of the techniques under discussion. This summary is not an exhaustive overview of all the intended features of this disclosure, and is neither intended to identify key or essential elements of all aspects of this disclosure, nor to define the scope of any or all aspects of this disclosure. The sole purpose of this summary is to present, in a general form, some concepts of one or more aspects of this disclosure as a prelude to the more detailed description that follows.

[0006] According to one aspect of this disclosure, a dual-input amplifier with dynamic phase modulation is provided, the dual-input amplifier comprising: an envelope detector configured to process an envelope of an RF input signal to form an envelope signal; a single-ended to differential converter configured to convert a version of the RF input signal into a differential RF input signal; an I / Q generator circuit configured to convert the differential RF input signal into a differential in-phase signal and a differential quadrature-phase signal; a first vector and phase shifter; a second vector and phase shifter; a first pair of output terminals; and a second pair of output terminals, wherein the first vector and phase shifter and the second vector and phase shifter are configured to process the differential in-phase signal and the differential quadrature-phase signal to form a first differential output signal at the first pair of output terminals and a second differential output signal at the second pair of output terminals, and to adjust the phase difference between the first differential output signal and the second differential output signal in response to the envelope signal.

[0007] According to another aspect of this disclosure, a dual-input amplifier method is provided, the dual-input amplifier method comprising: converting an RF input signal into a differential in-phase signal and a differential quadrature-phase signal; processing the differential in-phase signal and the differential quadrature-phase signal to form a first differential output signal and a second differential output signal, wherein the first differential output signal has a phase difference relative to the second differential output signal; and adjusting the phase difference in response to the power of the RF input signal.

[0008] According to another aspect of this disclosure, a dual-input amplifier is provided, comprising: a pair of vector and phase shifters configured to dynamically modulate a phase difference between a first differential output signal and a second differential output signal in response to the power of an input RF signal; a first differential-to-single-ended converter configured to convert the first differential output signal into a first single-ended output signal; a first driver amplifier configured to amplify the first single-ended output signal to form a first driver output signal; and a first power amplifier configured to amplify the first driver output signal to form a first power amplifier output signal.

[0009] Finally, according to another aspect of this disclosure, a transmitter is provided, comprising: a delay and impedance matching circuit configured to delay an RF input signal to a delayed matched signal; a preamplifier configured to amplify the delayed matched signal to form an amplified input signal; a single-ended to differential converter configured to convert the amplified input signal into a differential input signal; a polyphase filter configured to convert the differential input signal into a differential in-phase signal and a differential quadrature-phase signal; a first vector and phase shifter and a second vector and phase shifter both configured to process the differential in-phase signal and the differential quadrature-phase signal to form a first differential output signal and a second differential output signal, and responsive to the RF input. The signal power is used to dynamically modulate the phase difference between the first differential output signal and the second differential output signal; a first differential-to-single-ended converter circuit configured to convert the first differential output signal to form a first single-ended output signal; a second differential-to-single-ended converter circuit configured to convert the second differential output signal to form a second single-ended output signal; one or more first amplifiers configured to amplify the first single-ended output signal to form a first amplified RF signal; one or more second amplifiers configured to amplify the second single-ended output signal to form a second amplified RF signal; and a combiner configured to combine the first amplified RF signal and the second amplified RF signal to form a combined RF output signal.

[0010] Other aspects, features, and embodiments of this disclosure will be apparent to those skilled in the art after reading the following description of specific exemplary embodiments of the disclosure in conjunction with the accompanying drawings. Although features of this disclosure may be discussed below with respect to certain embodiments and drawings, all embodiments of this disclosure may include one or more of the advantageous features discussed herein. In other words, while one or more embodiments are discussed as having certain advantageous features, one or more such features may also be used according to the various embodiments of this disclosure discussed herein. Similarly, although exemplary embodiments may be discussed below as embodiments of an apparatus, system, or method, it should be understood that such exemplary embodiments may be implemented in various apparatuses, systems, and methods. Attached Figure Description

[0011] The accompanying drawings are used to further illustrate various specific embodiments and explain the various principles and advantages of this disclosure. In the drawings, the same reference numerals are used throughout individual views to refer to the same or functionally similar elements, and the drawings, together with the following detailed description, are incorporated in and form part of the specification.

[0012] Figure 1A An example is illustrated of a phase-reconfigurable circuit with dynamic phase modulation for a dual-input amplifier according to one aspect of the present disclosure.

[0013] Figure 1B An example is illustrated for amplifying from one aspect of this disclosure. Figure 1A It is part of the Dougherty amplifier system for the output signal of the phase reconfigurable circuit.

[0014] Figure 2 It is a phasor diagram of a carrier and a peak input signal with dynamic phase modulation according to one aspect of this disclosure.

[0015] Figure 3 It is based on one aspect of this disclosure. Figure 1A A conceptual diagram of vectors and phase shifters in a phase-reconfigurable circuit.

[0016] Figure 4 Examples of multiple circuits for forming a portion of a vector and phase shifter having dynamic phase modulation, according to one aspect of the present disclosure, are illustrated.

[0017] Figure 5 An example circuit for a vector and phase shifter with dynamic phase modulation is illustrated according to one aspect of this disclosure.

[0018] Figure 6 An example is illustrated of a vector and phase shifter with dynamic phase modulation according to one aspect of this disclosure.

[0019] Figure 7 It is based on one aspect of this disclosure. Figure 1A The circuit diagrams illustrate specific implementations of delay and impedance matching circuits, as well as transformers and matching circuits, in phase-reconfigurable circuits.

[0020] Figure 8A It is for use in accordance with one aspect of this disclosure Figure 1A The circuit diagram of a two-stage RC multiphase filter generated by I / Q in a phase reconfigurable circuit.

[0021] Figure 8B It is for use in accordance with one aspect of this disclosure Figure 1A The circuit diagram of a two-stage gm-C polyphase filter generated by I / Q in a phase reconfigurable circuit.

[0022] Figure 9It is based on one aspect of this disclosure. Figure 1A The circuit diagram of the envelope detector and processing circuit.

[0023] Figure 10 This is a flowchart of a phase reconfigurable circuit operation method according to one aspect of this disclosure.

[0024] The specific embodiments of this disclosure and its advantages can be best understood by referring to the following detailed description. It should be understood that the same reference numerals are used to identify the same elements illustrated in one or more of the figures. Detailed Implementation

[0025] To improve the efficiency and linearity of Dougherty amplifiers, phase-reconfigurable circuits have been developed, in which the phase difference between the input signal of the carrier amplifier and the input signal of the peak amplifier can be set to an arbitrary value. While such variable input phase differences are beneficial, challenges remain regarding the linearity of Dougherty amplifiers. The linearity of a Dougherty power amplifier can be characterized in several ways. For example, the first measure of linearity is called the AM-AM measurement, where AM stands for amplitude modulation. In the AM-AM characterization of the amplifier, the input signal is an unmodulated sine wave. The output sine wave should have a linear relationship with this input sine wave, but as the input signal power increases, the final output sine wave will have nonlinear distortion relative to the input sine wave. The AM-AM measurement characterizes this nonlinear distortion. Another measure of linearity is called the AM-PM measurement, where PM stands for phase modulation. A sine wave is input to the power amplifier again, and the input power is gradually increased. The phase of the output signal should remain stable, but it will inevitably begin to change as the input power increases. AM-PM measurements characterize the output phase linearly as it varies with the input signal power.

[0026] Despite the use of a phase-reconfigurable input circuit that provides an arbitrary phase difference between the carrier input signal and the peak input signal, load modulation still perturbs the desired flatness of the AM-AM and AM-PM performance of the Dougherty amplifier. Furthermore, the instantaneous peak power of the Dougherty amplifier is reduced due to the Class C bias of the peak amplifier, which facilitates load modulation. Therefore, this paper discloses a Dougherty amplifier with an improved phase-reconfigurable input circuit to provide enhanced linearity. For brevity, the phase-reconfigurable input circuit disclosed herein will be simply referred to as the "input circuit" in the following discussion. To provide improved linearity, the input circuit not only introduces an arbitrary static phase difference between the carrier input signal and the peak input signal, but also dynamically modulates this phase difference in response to the power of the input signal. The resulting dynamic modulation of the phase difference improves the linearity of the Dougherty amplifier. Although the following discussion is directed to a specific implementation of a Dougherty amplifier, it should be understood that the input circuit disclosed herein can be readily applied to any suitable dual-input power amplifier, such as a balanced amplifier or a load-modulated balanced amplifier.

[0027] Figure 1A Example input circuit 100 is shown in the figure, while Figure 1B The remaining portion 105 of the Dougherty amplifier transceiver is shown. In the input circuit 100, the input radio frequency (RF) signal is delayed and impedance matched in the delay and matching circuit 110 to produce a delayed and matched signal. The pre-amplifier 125 amplifies this delayed and matched signal to produce a pre-amplified signal, which is processed by a single-ended to differential converter, such as a transformer and impedance matching circuit 130, to produce a transformed signal. The single-ended to differential converter thus converts the version of the RF input signal processed by the delay and matching circuit 110 and the pre-amplifier 125. For clarity, the transformed signal produced by the transformer and matching circuit 130 is... Figure 1A The differential signal is shown in single-ended form. Next, the differential signal can be converted into in-phase and quadrature-phase signals in the I / Q signal generator 135 to generate differential in-phase and differential quadrature-phase output signals. For clarity, the differential in-phase and quadrature-phase output signals from the I / Q signal generator 135 are... Figure 1A The example below is again shown as a single-ended signal.

[0028] To determine the input signal power used for dynamic phase modulation, envelope detection and processing circuit 120 detects the envelope of the input signal and processes it into a differential envelope signal that varies with the input signal envelope. For clarity, Figure 1AThe differential envelope signal is also illustrated as a single-ended signal. Next, the differential in-phase and quadrature phase signals and the differential envelope signal are processed in a pair of vector and phase shifter circuits 140 and 145 to form a differential carrier branch signal and a peak branch signal, which are again illustrated in single-ended form for clarity. The differential carrier branch signal can also be represented herein as a first differential output signal. Similarly, the differential peak branch signal can also be represented herein as a second differential output signal. The differential carrier branch signal is converted to single-ended form in a first differential-to-single-ended converter circuit, such as a transformer and impedance matching circuit 150, to drive the first driver amplifier 151 in section 105. Figure 1B The first driver amplifier 151 then drives the carrier amplifier 160.

[0029] Referring again to input circuitry 100, the differential peak branch signal is converted to single-ended form in a second differential-to-single-ended converter circuit, such as a transformer and impedance matching circuitry 155, to drive a second driver amplifier 161 in section 105. The second driver amplifier 161 then drives a peak amplifier 165. The amplified output signals from carrier amplifier 160 and peak amplifier 165 are combined in combiner 170 to produce a combined output signal. A combined duplexer, filter, and antenna switch 175 processes the combined output signal to drive one or more antennas 180. The received signal from antenna 180 is coupled through duplexer 175 before being amplified by a low-noise amplifier (LNA) (not illustrated).

[0030] To provide a better understanding of the dynamic phase modulation provided by input circuit 100, some basic concepts will now be discussed, followed by a more detailed discussion of the various components of the input circuit. Recall that conventional phase-reconfigurable circuits may introduce an arbitrary static phase difference between the carrier input signal and the peak input signal. This phase difference can be represented using the phasor representations of the resulting carrier input signal and the peak input signal. It can be seen that the carrier input signal (e.g., the carrier input signal voltage) can be represented in phasor form as (1 + j)exp(+j / 2), while the peak input signal can be expressed as (1 + j)exp(-j / 2), where j is an imaginary number equal to the square root of -1. These phasors are used as follows: Figure 2 The unit circle shown is used as an example, where the y-axis represents the imaginary part and the x-axis represents the real part. The phase of the carrier phasor is advanced relative to an angle of π / 4. The angle is π / 2, while the phase of the peak phasor decreases from π / 4. An angle of 2 / 2. It can be seen that if / 2 itself is equal to π / 4, so a typical phase difference of 90 degrees between the carrier input signal and the peak input signal can be achieved.

[0031] Regardless of the static phase difference between the carrier input signal and the peak input signal The dynamic phase modulation disclosed in this paper can increase or decrease the phase difference depending on the power of the input signal. In this regard, the dependence of phase modulation on the input signal power can be characterized by a factor x, where x varies with the input signal power. Depending on its application, the factor x can represent the phase divergence (relative to the static phase difference) between the carrier input signal and the peak input signal. (increase) or phase convergence (relative to static phase difference) (reduction). For example, suppose we apply x to cause phase divergence. In the phasor representation of phase divergence as a function of input signal power x, it can be seen that the carrier input signal voltage can be expressed in phasor form as (1 + j)exp((+j) / 2 + x). Assume x is more than 2 + x. If the value is less than 2, then the phasor form can be expanded as shown in the following equation (1): Vcarrier = cos( / 2)(1-x) – sin( / 2)(1+x) + j(sin( / 2)(1-x) + cos( / 2)(1+x)) Equation (1) Where Vcarrier is the carrier input signal voltage waveform. Similarly, the expanded peak input signal voltage can be represented by the following equation (2): Vpeaking = cos( / 2)(1+x) + sin( / 2)(1-x) + j(-sin( / 2)(1+x) + cos( / 2)(1-x)) Equation (2) Where Vpeaking is the peak input signal voltage waveform.

[0032] Regarding these extended behaviors of the carrier input signal and the peak input signal, it can be seen that, depending on how the envelope modulation signal is derived from the envelope detection and processing circuit 120, the phase difference between the carrier input signal and the peak input signal can be increased (divergent phase modulation) or decreased (convergent phase modulation). Figure 2 Examples of carrier input signals and peak input signals with both divergent and convergent phase modulation are also shown.

[0033] Figure 3The pair of vectors and phase shifters 140 and 145 are shown conceptually to realize the phasor representations of equations (1) and (2). As previously noted, the I / Q signal generator 135 in Figure 1 generates... Figure 3 The differential in-phase output signals are designated as I+ and I-. Similarly, the differential quadrature output signals from the I / Q signal generator 135 are... Figure 3 The values ​​are designated as Q+ and Q-. The differential envelope signal in Figure 1 is... Figure 3 Vg+ and Vg- are denoted by Vg+ and Vg-, respectively. The pair of vector and phase shifters 140 and 145 function to drive the transformer and impedance matching circuit 150 with a differential version of the carrier input signal defined by equation (1), which can also be represented herein as a first differential output signal. Vector and phase shifters 140 and 145 are therefore coupled to a first pair of output terminals 149 to drive the transformer and impedance matching circuit 150 with the first differential output signal.

[0034] In the vector and phase shifter 140, the variable transconductance amplifier 305 is at cos( The gain transconductance differential in-phase signals I+ and I- from the variable transconductance amplifier 305 are used to generate a differential output signal. Circuit 325 mixes the differential output signal from the variable transconductance amplifier 305 with the differential envelope signal to multiply the differential output signal by a factor (1-x). Therefore, circuit 325 generates cos(1-x) according to equation (1). The differential version of ( / 2)(1-x). This signal drives the transformer and impedance matching circuit 150, which will be discussed further below.

[0035] Variable transconductance amplifier 310 with sin( The gain transconductance differential in-phase signals I+ and I- from the variable transconductance amplifier 310 are used to generate a differential output signal. Circuit 340 mixes the differential output signal from the variable transconductance amplifier 310 with the differential envelope signal to multiply the pair of differential output signals by a factor (1+x). Therefore, circuit 340 generates sin( The difference version of / 2)(1+x). sin( The differential version of / 2)(1+x) is coupled to the transformer and impedance matching circuit 150 in a complementary manner, so as to use -sin( from equation (1) The differential version of ( / 2)(1+x) is used to drive circuit 150.

[0036] In the vector and phase shifter 145, the variable transconductance amplifier 315 uses sin( The gain transconductance differential in-phase signals Q+ and Q- of the variable transconductance amplifier 315 are used to generate a differential output signal. Circuit 350 mixes the differential output signal from the variable transconductance amplifier 315 with the differential envelope signal to multiply the differential output signal by a factor (1-x). Therefore, circuit 350 generates j sin( The difference version of ( / 2)(1-x). jsin( The differential version of / 2)(1-x) is coupled to the transformer and impedance matching circuit 150 to use jsin( from equation (1) The differential version of ( / 2)(1-x) is used to drive circuit 150.

[0037] To complete equation (1), the variable transconductance amplifier 320 in the vector and phase shifter 145 is at cos( The gain transconductance differential in-phase signals Q+ and Q- of the variable transconductance amplifier 320 are used to generate a differential output signal. Circuit 355 mixes the differential output signal from the variable transconductance amplifier 320 with the differential envelope signal to multiply the differential output signal by a factor (1+x). Therefore, circuit 350 generates jcos( The difference version of / 2)(1+x). jcos( The differential version of ( / 2)(1+x) is coupled to the transformer and impedance matching circuit 150 to use jcos( from equation (1) The differential version of (1+x) is used to drive circuit 150. Therefore, vector and phase shifters 140 and 150 drive circuit 150 with a differential version of the carrier input signal defined by equation (1).

[0038] Vectors and phase shifters 140 and 145 are similarly constructed such that the transformer and impedance matching circuit 155 is driven by a differential version of the peak input signal defined by equation (2), which can also be represented herein as a second differential output signal. Therefore, vectors and phase shifters 140 and 145 are coupled to a second pair of output terminals 148 to drive the transformer and impedance matching circuit 150 with the second differential output signal. Specifically, circuit 330 mixes the differential output signal from the variable transconductance amplifier 305 with the differential envelope signal to multiply the differential output signal by a factor (1+x). Therefore, circuit 330 generates cos( The difference version of / 2)(1+x). cos( The differential version of ( / 2)(1+x) is coupled to the transformer and impedance matching circuit 155 to use cos( from equation (2) The differential version of ( / 2)(1+x) is used to drive circuit 155.

[0039] Circuit 335 mixes the differential output signal from the variable transconductance amplifier 310 with the differential envelope signal to multiply the differential output signal by a factor (1-x). Therefore, circuit 335 generates sin( The difference version of / 2)(1-x). sin( The differential version of (2)(1-x) is coupled to the transformer and impedance matching circuit 155 to use sin( from equation (2) The differential version of ( / 2)(1-x) is used to drive circuit 155.

[0040] Furthermore, circuit 345 mixes the differential output signal from variable transconductance amplifier 315 with the differential envelope signal to multiply the differential output signal by a factor (1+x). Therefore, circuit 345 generates jsin( The difference version of / 2)(1+x). jsin( The differential version of / 2)(1+x) is coupled to the transformer and impedance matching circuit 155 in a complementary manner, so as to use -j sin( from equation (2). The differential version of ( / 2)(1+x) is used to drive circuit 155.

[0041] Finally, circuit 360 mixes the differential output signal from variable transconductance amplifier 320 with the differential envelope signal to multiply the differential output signal by a factor (1-x). Therefore, circuit 360 generates jcos( The difference version of / 2)(1-x). jcos( The differential version of (2)(1-x) is coupled to the transformer and impedance matching circuit 155 to use jcos( from equation (2) The differential version of (1-x) is used to drive circuit 155. Therefore, vector and phase shifters 140 and 150 drive circuit 155 using the differential version of the peak input signal defined by equation (2).

[0042] In the following discussion, assumptions will be made such as Figure 1B The antenna 180 is driven by a single-ended signal. Therefore, transformers and matching circuits 150 and 155 serve as differential-to-single-ended converter circuits to convert the differential signals from vector and phase shifters 140 and 145 into single-ended signals. However, it should be understood that differential signals can be used to drive the antenna in alternative embodiments. To perform the differential-to-single-ended conversion, each transformer and matching circuit 150 and 155 includes a center-tapped transformer T. To match the input and output impedances, the primary winding of each transformer T is coupled in parallel with a variable capacitor C1. Similarly, the secondary winding of each transformer T is coupled in parallel with a variable capacitor C2.

[0043] Vector and phase shifters 140 and 145 can each be implemented using suitable circuits with mixer-like topologies. Therefore, without loss of generality, the following discussion will focus on mixer-like implementations of vector and phase shifters 140 and 145. As defined herein, a circuit is considered a “mixer-like” circuit when it has a mixer topology but does not perform frequency transformation on its output signal. It should be noted that equations (1) and (2) each have four terms, two cosine terms and two sine terms. Each term can be formed by a corresponding plurality of mixer-like circuits. Figure 4 The diagram shows an example of multiple N class mixer circuits 400, from the first circuit 405 to the Nth circuit, where N is a complex positive integer. Each circuit is digitally controlled to provide the desired cosine or sine ratio. Referring again to the cosine and sine terms in equations (1) and (2), it can be seen that there are two real terms and two imaginary terms. The real terms depend on the I / Q signal generator 135 ( Figure 1A The in-phase signal is used to generate the real term, while the imaginary term depends on the quadrature-phase differential signal from the I / Q signal generator 135. The plurality of circuits 400 respond to the in-phase differential signal to generate one of the real terms, but it should be understood that in alternative embodiments, the plurality of circuits 400 may alternatively respond to the quadrature-phase differential signal. The function of each circuit is to multiply the in-phase differential signal with the envelope differential signal to generate the desired (1+x) or (1-x) term. For example, suppose the generated term is cos(...). / 2)(1+x). Within these multiple N circuits, a corresponding number of circuits are activated to each generate (1+x) terms, where N is a positive complex integer. Therefore, the combination of circuits in the operation of these multiple circuits 400 produces the desired cos( / 2)(1+x). / 2)(1+x) terms.

[0044] Regarding the activation of individual circuits among the plurality of circuits 400, an N-bit wide digital control word cos_mag controls which circuits are active. The N circuits are arranged from the first circuit 405 to the Nth circuit 410. The first bit of the digital control word, cos_mag(1), controls switch 415 of the first circuit 405. If switch 415 is closed, its gated differential envelope signal Vg is prevented from mixing in circuit 405. However, if switch 415 is open, circuit 405 is active and mixes the envelope differential signal Vg with the in-phase differential signal. Similarly, switch 420, controlled by the Nth bit of the digital control word cos_mag(N), controls whether the Nth circuit 410 is active. Each of the remaining circuits has its own corresponding switch, similar to switches 415 and 420. A combination network 425 combines the output signals from the active circuits to drive peak and carrier branches, as will be further explained herein.

[0045] The mixer-like circuit disclosed in this article can be constructed similarly to the Gilbert unit mixer. Figure 5 The example Gilbert unit mixer circuit 500 is shown in more detail below. Circuit 500 is the i-th circuit in a plurality of N circuits, where i is an integer ranging from 1 to N. Therefore, circuit 500 is controlled by the i-th bit of the corresponding digital control word represented by the i-th digital control bit. In circuit 500, the switch is formed by a pair of transmit gates 505 and 515, which in turn are formed by a pair of n-type metal-oxide-semiconductor (NMOS) transistors M1 and M2 and a pair of p-type metal-oxide-semiconductor (PMOS) transistors P1 and P2. Transmit gates 505 and 515 are turned on if the i-th digital control bit is asserted as the supply voltage. Specifically, the i-th digital control bit drives the gates of transistors M1 and M2 such that these transistors are turned on when the i-th digital control bit is asserted as the supply voltage. Inverter 515 inverts the i-th digital control bit to drive the gates of transistors P1 and P2. Therefore, when the i-th digital control bit is asserted as the power supply voltage, transistors P1 and P2 are also turned on.

[0046] Circuit 500 also includes a differential pair of NMOS transistors M5 and M6 and another differential pair of NMOS transistors M7 and M8. The sources of transistors M5 and M6 are coupled to ground via NMOS transistor M3. Similarly, the sources of transistors M7 and M8 are coupled to ground via NMOS transistor M4. Depending on the implemented sinusoidal term, the in-phase or quadrature-phase signal from the I / Q signal generator 135 (FIG. 1) drives the gates of transistors M3 and M4. Specifically, the positive component drives the gate of transistor M3, while the negative component drives the gate of transistor M4.

[0047] Assuming circuit 500 is in operation, the positive component Vg+ of the envelope differential signal is coupled through transmit gate 510 to drive the gates of transistors M6 and M8. Similarly, the negative component Vg- of the envelope differential signal is coupled through transmit gate 515 to drive the gates of transistors M5 and M8. The drains of transistors M5, M6, M7, and M8 are coupled to a combinational network (not illustrated).

[0048] Figure 6Example vector and phase shifter 600 is shown. As previously discussed with respect to the four terms of equations (1) and (2), vector and phase shifter 600 comprises four corresponding plurality of N-type mixer circuits. Specifically, a first plurality of N-type mixer circuits 605 and a second plurality of N-type mixer circuits 610 each respond to in-phase differential signals. The first plurality of 605 is gated by a cosine magnitude digital word (which may also be designated herein as a first digital word), such that the first plurality of 605 produces a real cosine term of equation (1) or equation (2), as coupled via combination network 425. Similarly, the second plurality of 610 is gated by a sinine magnitude digital word (which may also be designated herein as a second digital word), such that the second plurality of 610 produces a real sine term of equation (1) or equation (2). A third plurality of N-type mixer circuits 615 and a fourth plurality of N-type mixer circuits 620 each respond to quadrature differential signals to form imaginary terms. Specifically, the third plurality of 615s is gated by a cosine value digit (which may also be designated as the third digit in this document) to produce an imaginary cosine term of equation (1) or equation (2), as coupled via the combination network 425. Similarly, the fourth plurality of 620s is gated by a sinine value digit (which may also be designated as the fourth digit in this document), such that the fourth plurality of 620s produces an imaginary sine term of equation (1) or equation (2). The combination network 425 combines the corresponding output signals from the multiple mixer-like circuits to produce a differential carrier signal to drive the transformer and impedance matching circuit 150 ( Figure 3 Similarly, the combination network 425 combines corresponding output signals from multiple mixer-like circuits to generate a differential peak signal to drive the transformer and impedance matching circuit 155. Figure 3 ).

[0049] Refer again Figure 1A The input circuit 100, in Figure 7The following diagram illustrates a more detailed example implementation of the delay and matching circuit 110, the preamplifier 125, and the transformer and matching circuit 130. The delay and matching circuit 110 can be formed using one or more inductor-capacitor (LC) stages. For example, a first LC stage includes a variable capacitor CD1 and an inductor LD1. Similarly, a second LC stage includes a variable capacitor CD2 and an inductor LD2. To provide the desired amount of delay, the delay and matching circuit 110 can include multiple N LC stages, ending with an Nth LC stage including a variable capacitor CDN and an inductor LDN, where N is a complex positive integer. The final capacitor CD(N+1) completes the delay and matching circuit 110, which provides the delayed and matched output signal to the preamplifier 125. As an alternative to the LC stages, other circuitry can be used to introduce the desired delay, such as delay lines or external filters. The transformer and impedance matching circuit 130 includes a transformer T1 that converts the single-ended output signal from the preamplifier 125 into a signal that drives the I / Q signal generator 135. Figure 1A The differential output signal is generated by a variable capacitor C5 coupled in parallel with the primary winding of transformer T1 for matching. Similarly, the variable capacitor C6 is coupled in parallel with the secondary winding of transformer T1 for matching. Furthermore, the center tap of the secondary winding can be biased using a bias voltage Vbias to control the common-mode voltage of the differential output signal.

[0050] I / Q signal generator 135 is used to convert differential signals from transformer and impedance matching circuit 130 into differential in-phase and quadrature phase signals. In some implementations, I / Q signal generator 135 may be formed by two stages of multiphase filters. Each stage of the two-stage multiphase filter may be formed using a transconductance-capacitance (gm-C) topology or a resistor-capacitor (RC) topology. Figure 8A An example RC two-stage polyphase filter 800 for implementing an I / Q signal generator 135 is shown, comprising a first stage 805 and a second stage 810. The first stage 805 includes four resistors R1 arranged with four corresponding capacitors C7 to provide a first pole frequency that varies with the resistors R1 and capacitors C7. Similarly, the second stage 810 includes four resistors R2 arranged with four corresponding capacitors C8 to provide a second pole frequency that varies with the resistors R2 and capacitors C8. Properly setting the two pole frequencies of the RC polyphase filter 800 results in high-quality differential signals I+, I-, Q+, and Q- with satisfactory phase and gain matching. Compared to a gm-C polyphase filter, the RC polyphase filter 800 consumes no current and is highly linear. However, it should be understood that a gm-C polyphase filter can be used in alternative implementations.

[0051] Figure 8BThe diagram illustrates an example two-stage gm-C polyphase filter 820 for implementing the I / Q signal generator 135, comprising a first stage 825 and a second stage 830. In the first stage 825, four transconductance amplifiers 835 each provide a first transconductance and are arranged with four corresponding capacitors C9 to generate a first pole frequency that varies with the first transconductance and capacitor C9. Similarly, the second stage 830 includes four transconductance amplifiers 840, each providing a second transconductance and being arranged with four corresponding capacitors C10 to generate a second pole frequency that varies with the second transconductance and capacitor C10. By appropriately setting the two pole frequencies, the polyphase filter 820 provides high-quality differential signals I+, I-, Q+, and Q- with satisfactory phase and gain matching. In another passive embodiment, a transformer-based differential I / Q generation circuit can be used instead of the polyphase filter to form the I / Q generator 135 to generate in-phase and quadrature RF signals. Alternatively, in an alternative implementation, a three-stage RC (or Gm-C) polyphase filter can be used to perform the I and Q conversion.

[0052] Preamplifiers can alternatively be inserted between vector and phase shifters 140 and 145 and their corresponding transformers and impedance matching circuits 150 and 155. In such embodiments, four single-ended preamplifiers may be present, such that the positive carrier branch input signal, the load wave branch input signal, the positive peak branch input signal, and the negative peak branch input signal are each preamplified by their respective preamplifiers. Alternatively, such preamplifiers may be other than preamplifier 125. In other embodiments, preamplifiers can alternatively be inserted between the transformer and impedance matching portions of each of the transformers and impedance matching circuits 150 and 155. Note that in alternative embodiments, these various preamplifier configurations may replace preamplifier 125, or may be combined with preamplifier 125 in part or in whole.

[0053] Figure 9Example envelope detection and processing circuitry 120 is shown in more detail below. Envelope detector 900 detects the envelope of the RF input signal and outputs a signal representing the envelope to the positive input terminal of transconductance amplifier 905. A voltage reference signal (Vref) biases the negative input terminal of transconductance amplifier 905 such that the differential output signal from the transconductance amplifier is proportional to the difference between the envelope and the voltage reference signal. To provide improved drive capability, the differential output signal from the transconductance amplifier is amplified by differential amplifier 910, which outputs the amplified differential signal. To provide tunability of low-frequency gain to align with the voltage swing of the amplified differential output signal, and to adjust the group delay to reduce the group delay difference between the forward path through I / Q generator circuitry 135 and the path through envelope and processing circuitry 120, differential amplifier 910 is coupled to variable resistors R3 and R4 (note that variable resistors R3 and R4 can be set to the same resistance, since differential amplifier 910 can be a differential transimpedance amplifier). A variable resistor R3 is coupled between the negative output terminal and the positive input terminal of the differential amplifier 910. Similarly, a variable resistor R4 is coupled between the positive output terminal and the negative input terminal of the differential amplifier 910. An optional double-pole double-throw switch 915 is coupled between the output terminal of the differential amplifier 910 and vector and phase shifters 140 and 145. Figure 1A Depending on the configuration of switch 915, the dynamic phase modulation in vector and phase shifters 140 and 145 can switch from divergent phase difference (the phase difference between the carrier input signal and the peak input signal increases from its static value) to convergent phase difference (the phase difference between the carrier input signal and the peak input signal decreases from its static value), and vice versa. The bias voltage Vbias controls the common-mode voltage of the differential envelope signal.

[0054] Now see Figure 10 The flowchart discusses a dual-input amplifier method. This method includes action 1000, which converts an RF input signal into a differential in-phase signal and a differential quadrature-phase signal. An example of action 1000 is the conversion of the RF input signal to form differential I and Q signals via a delay and matching circuit 110, a transformer and impedance matching circuit 130, and an I / Q generator circuit 135. Furthermore, the method includes action 1005, which processes the differential in-phase signal and the differential quadrature-phase signal to form a first differential output signal and a second differential output signal, wherein the first differential output signal has a phase difference relative to the second differential output signal, and action 1010, which adjusts the phase difference in response to the power of the RF input signal. Examples of actions 1005 and 1010 are the dynamic modulation of the phase difference between the carrier branch input signal and the peak branch input signal by a first vector and phase shifter 140 and a second vector and phase shifter 145.

[0055] This disclosure will now be outlined in the following exemplary terms: Clause 1. A dual-input amplifier with dynamic phase modulation, the dual-input amplifier comprising: An envelope detector configured to process the envelope of an RF input signal to form an envelope signal; A single-ended to differential converter, the single-ended to differential converter being configured to convert a version of the RF input signal into a differential RF input signal; I / Q generator circuit, the I / Q generator circuit being configured to convert the differential RF input signal into a differential in-phase signal and into a differential quadrature-phase signal; First vector and phase shifter; Second vector and phase shifter; The first pair of output terminals; and The second pair of output terminals, wherein both the first vector and phase shifter and the second vector and phase shifter are configured to process the differential in-phase signal and the differential quadrature-phase signal to form a first differential output signal at the first pair of output terminals and a second differential output signal at the second pair of output terminals, and to adjust the phase difference between the first differential output signal and the second differential output signal in response to the envelope signal.

[0056] Clause 2. The dual-input amplifier as described in Clause 1, wherein the I / Q generator circuitry includes a polyphase filter.

[0057] Clause 3. The dual-input amplifier as described in Clause 2, wherein the polyphase filter comprises a transconductance-capacitor (gm-C) polyphase filter.

[0058] Clause 4. The dual-input amplifier as described in Clause 2, wherein the polyphase filter comprises a resistor-capacitor (RC) polyphase filter.

[0059] Clause 5. The dual-input amplifier as described in Clause 4, wherein the polyphase filter comprises a two-stage RC polyphase filter.

[0060] Clause 6. The dual-input amplifier as described in Clause 3, wherein the gm-C polyphase filter comprises a two-stage gm-C polyphase filter.

[0061] Clause 7. A dual-input amplifier according to any one of Clauses 1 to 6, wherein the envelope signal is a differential envelope signal, and wherein the dual-input amplifier further comprises: A double-pole double-throw switch, configured to couple the differential envelope signal from the envelope detector to the first vector and phase shifter and the second vector and phase shifter.

[0062] Clause 8. The dual-input amplifier according to Clause 7, wherein the envelope signal is a differential envelope signal, and the first vector and phase shifter comprises: A plurality of circuits, each of which is configured to respond to an assertion of a corresponding digital bit from a first digital word to mix the differential in-phase signal with the differential envelope signal; The second plurality of circuits, each of which is configured to respond to an assertion of a corresponding digital bit from the second digital word to mix the differential in-phase signal with the differential envelope signal; A third plurality of circuits, each of which is configured to respond to an assertion of a corresponding digital bit from a third digital word to mix the differential quadrature phase signal with the differential envelope signal; and A fourth plurality of circuits, each of which is configured to respond to an assertion of a corresponding digital bit from a fourth digital word to mix the differential quadrature phase signal with the differential envelope signal.

[0063] Clause 9. The dual-input amplifier as described in Clause 8, further comprising: A combined network configured to couple the first plurality of circuits, the second plurality of circuits, the third plurality of circuits, and the fourth plurality of circuits to the first pair of output terminals and the second pair of output terminals.

[0064] Clause 10. The dual-input amplifier as described in Clause 8, wherein the second vector and phase shifter further comprises four sets of multiple-class mixer circuits.

[0065] Clause 11. A dual-input amplifier according to any one of Clauses 1 to 10, wherein phase-reconfigurable circuitry is incorporated into a Dougherty amplifier, the Dougherty amplifier comprising: A first differential-to-single-ended converter, coupled to the first pair of output terminals and configured to convert the first differential output signal into a first single-ended output signal; A first driver amplifier, configured to amplify a first single-ended RF output signal to form a first driver output signal; and A carrier amplifier configured to amplify the output signal of the first driver.

[0066] Clause 12. The dual-input amplifier as described in Clause 11, wherein the Dougherty amplifier further comprises: A second differential-to-single-ended converter is coupled to the second pair of output terminals and configured to convert the second differential output signal into a second single-ended output signal; A second driver amplifier, configured to amplify the second single-ended output signal to form a second driver output signal; and A peak amplifier configured to amplify the output signal of the second driver.

[0067] Clause 13. The dual-input amplifier according to Clause 12, further comprising: A combiner configured to combine a carrier output signal from the carrier amplifier with a peak output signal from the peak amplifier to form a combined output signal.

[0068] Clause 14. The dual-input amplifier according to any one of Clauses 1 to 13, wherein the dual-input amplifier further comprises: Delay and impedance matching circuitry, the delay and impedance matching circuitry being configured to delay the RF input signal to a delayed matched signal; and A preamplifier configured to preamplify the delayed matched signal to form the version of the RF input signal.

[0069] Clause 15. The dual-input amplifier according to any one of Clauses 7, wherein the envelope detector further comprises a transconductance amplifier configured to form the differential envelope signal in response to the difference between the envelope of the RF input signal and a reference voltage signal.

[0070] Clause 16. A dual-input amplifier method, the dual-input amplifier method comprising: The RF input signal is converted into a differential in-phase signal and a differential quadrature-phase signal; Processing the differential in-phase signal and the differential quadrature-phase signal to form a first differential output signal and a second differential output signal, wherein the first differential output signal has a phase difference with respect to the second differential output signal; and The phase difference is adjusted in response to the power of the RF input signal.

[0071] Clause 17. The dual-input amplifier method according to Clause 16, further comprising: Pre-amplify the first differential output signal to form a pre-amplified first differential output signal; and The second differential output signal is pre-amplified to form a pre-amplified second differential output signal.

[0072] Clause 18. The dual-input amplifier method of claim 16, further comprising: The first differential output signal is converted into a first single-ended output signal; The first single-ended output signal is pre-amplified to form a pre-amplified first output signal; Convert the second differential output signal into a second single-ended output signal; and The second single-ended output signal is pre-amplified to form a pre-amplified second output signal.

[0073] Clause 19. The dual-input amplifier method according to Clause 18, further comprising: The pre-amplified first output signal is amplified in the first driver amplifier and carrier amplifier of the first series to form an amplified first output signal; and The pre-amplified second output signal is amplified in the second driver amplifier and peak amplifier of the second series to form an amplified second output signal; The amplified first output signal and the amplified second output signal are combined to form a combined RF output signal; and The combined RF output signal is transmitted through at least one antenna.

[0074] Clause 20. A dual-input amplifier, the dual-input amplifier comprising: A pair of vector and phase shifters, the pair of vector and phase shifters being configured to dynamically modulate the phase difference between a first differential output signal and a second differential output signal in response to the power of an input RF signal; A first differential-to-single-ended converter is configured to convert the first differential output signal into a first single-ended output signal. A first driver amplifier, configured to amplify the first single-ended output signal to form a first driver output signal; and A first power amplifier is configured to amplify the output signal of the first driver to form a first power amplifier output signal.

[0075] Clause 21. The dual-input amplifier according to Clause 20, further comprising: A second differential-to-single-ended converter is configured to convert the second differential output signal into a second single-ended output signal. A second driver amplifier, configured to amplify the second single-ended output signal to form a second driver output signal; and A second power amplifier is configured to amplify the output signal of the second driver to form a second power amplifier output signal.

[0076] Clause 22. The dual-input amplifier according to Clause 21, further comprising: A combiner configured to combine the output signal of the first power amplifier with the output signal of the second power amplifier to form a combined RF output signal.

[0077] Clause 23. The dual-input amplifier as described in Clause 22, wherein the dual-input amplifier is integrated into a transmitter, the transmitter including at least one antenna configured to transmit the combined RF output signal.

[0078] Clause 24. The dual-input amplifier as described in Clause 22, wherein the dual-input amplifier includes a Dougherty amplifier, wherein the first power amplifier is a carrier amplifier and wherein the second power amplifier is a peak amplifier.

[0079] Clause 25. A transmitter comprising: A delay and impedance matching circuit, the delay and impedance matching circuit being configured to delay an RF input signal to a delayed matched signal; A preamplifier configured to amplify the delayed matched signal to form an amplified input signal; A single-ended to differential conversion circuit, configured to convert the amplified input signal into a differential input signal; A polyphase filter configured to convert the differential input signal into a differential in-phase signal and a differential quadrature-phase signal; A first vector and a phase shifter and a second vector and a phase shifter are both configured to process the differential in-phase signal and the differential quadrature-phase signal to form a first differential output signal and a second differential output signal, and to dynamically modulate the phase difference between the first differential output signal and the second differential output signal in response to the power of the RF input signal. A first differential-to-single-ended converter circuit is configured to convert the first differential output signal to form a first single-ended output signal. The second differential-to-single-ended converter circuit is configured to convert the second differential output signal to form a second single-ended output signal. One or more first amplifiers, the one or more first amplifiers being configured to amplify the first single-ended output signal to form a first amplified RF signal; One or more second amplifiers, the one or more second amplifiers being configured to amplify the second single-ended output signal to form a second amplified RF signal; and A combiner configured to combine a first amplified RF signal with a second amplified RF signal to form a combined RF output signal.

[0080] Clause 26. The transmitter according to Clause 25, wherein the one or more first amplifiers comprise a first series of first driver amplifiers and first power amplifiers, and wherein the one or more second amplifiers comprise a second series of second driver amplifiers and second power amplifiers.

[0081] Clause 27. The transmitter as described in Clause 25, wherein the polyphase filter is a two-stage polyphase filter.

[0082] Clause 28. The transmitter as described in Clause 27, wherein the two-stage polyphase filter is a two-stage transconductance-capacitor (gm-C) polyphase filter.

[0083] Clause 29. The transmitter as described in Clause 27, wherein the two-stage multiphase filter is a two-stage resistor-capacitor (RC) multiphase filter.

[0084] Clause 30. A transmitter according to any one of Clauses 25 to 30, wherein the one or more first amplifiers comprises a carrier amplifier of a Dougherty amplifier, and wherein the one or more second amplifiers comprises a peak amplifier of the Dougherty amplifier.

[0085] The description herein is provided to enable those skilled in the art to implement or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be granted the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A dual-input amplifier with dynamic phase modulation, the dual-input amplifier comprising: An envelope detector configured to process the envelope of an RF input signal to form an envelope signal; A single-ended to differential converter, the single-ended to differential converter being configured to convert a version of the RF input signal into a differential RF input signal; I / Q generator circuit, the I / Q generator circuit being configured to convert the differential RF input signal into a differential in-phase signal and into a differential quadrature-phase signal; First vector and phase shifter; Second vector and phase shifter; The first pair of output terminals; and The second pair of output terminals, wherein the first vector and phase shifter and the second vector and phase shifter are configured to process the differential in-phase signal and the differential quadrature-phase signal to form a first differential output signal at the first pair of output terminals and a second differential output signal at the second pair of output terminals, and to adjust the phase difference between the first differential output signal and the second differential output signal in response to the envelope signal.

2. The dual-input amplifier according to claim 1, wherein the I / Q generator circuit includes a polyphase filter.

3. The dual-input amplifier according to claim 2, wherein the polyphase filter comprises a transconductance-capacitor (gm-C) polyphase filter.

4. The dual-input amplifier of claim 2, wherein the polyphase filter comprises a resistor-capacitor (RC) polyphase filter.

5. The dual-input amplifier according to claim 4, wherein the polyphase filter comprises a two-stage RC polyphase filter.

6. The dual-input amplifier according to claim 3, wherein the gm-C polyphase filter comprises a two-stage gm-C polyphase filter.

7. The dual-input amplifier of claim 1, wherein the envelope signal is a differential envelope signal, and wherein the dual-input amplifier further comprises: A double-pole double-throw switch, configured to couple the differential envelope signal from the envelope detector to the first vector and phase shifter and the second vector and phase shifter.

8. The dual-input amplifier of claim 7, wherein the envelope signal is a differential envelope signal, and the first vector and phase shifter comprises: A plurality of circuits, each of which is configured to respond to an assertion of a corresponding digital bit from a first digital word to mix the differential in-phase signal with the differential envelope signal; The second plurality of circuits, each of which is configured to respond to an assertion of a corresponding digital bit from the second digital word to mix the differential in-phase signal with the differential envelope signal; A third plurality of circuits, each of which is configured to respond to an assertion of a corresponding digital bit from a third digital word to mix the differential quadrature phase signal with the differential envelope signal; and A fourth plurality of circuits, each of which is configured to respond to an assertion of a corresponding digital bit from a fourth digital word to mix the differential quadrature phase signal with the differential envelope signal.

9. The dual-input amplifier according to claim 8, further comprising: A combined network configured to couple the first plurality of circuits, the second plurality of circuits, the third plurality of circuits, and the fourth plurality of circuits to the first pair of output terminals and the second pair of output terminals.

10. The dual-input amplifier of claim 8, wherein the second vector and phase shifter further comprises four sets of multiple mixer-like circuits.

11. The dual-input amplifier of claim 1, wherein the dual-input amplifier comprises a Dougherty amplifier, the Dougherty amplifier comprising: A first differential-to-single-ended converter, coupled to the first pair of output terminals and configured to convert the first differential output signal into a first single-ended output signal; A first driver amplifier, configured to amplify a first single-ended RF output signal to form a first driver output signal; and A carrier amplifier configured to amplify the output signal of the first driver.

12. The dual-input amplifier of claim 11, wherein the Dougherty amplifier further comprises: A second differential-to-single-ended converter is coupled to the first pair of output terminals and configured to convert the first differential output signal into a first single-ended output signal. A first driver amplifier, configured to amplify the first single-ended RF output signal to form a first driver output signal; and A carrier amplifier configured to amplify the output signal of the first driver.

13. The dual-input amplifier of claim 12, wherein the Dougherty amplifier further comprises: A combiner configured to combine a carrier output signal from the carrier amplifier with a peak output signal from the peak amplifier to form a combined output signal.

14. The dual-input amplifier according to claim 1, further comprising: A delay and impedance matching circuit, the delay and impedance matching circuit being configured to delay the RF input signal into a delayed matched signal; and A preamplifier configured to preamplify the delayed matched signal to form the version of the RF input signal.

15. The dual-input amplifier of claim 7, wherein the envelope detector further comprises a transconductance amplifier configured to form the differential envelope signal in response to the difference between the envelope of the RF input signal and a reference voltage signal.

16. A dual-input amplifier method, the dual-input amplifier method comprising: The RF input signal is converted into a differential in-phase signal and a differential quadrature-phase signal; Processing the differential in-phase signal and the differential quadrature-phase signal to form a first differential output signal and a second differential output signal, wherein the first differential output signal has a phase difference with respect to the second differential output signal; and The phase difference is adjusted in response to the power of the RF input signal.

17. The dual-input amplifier method of claim 16, further comprising: The first differential output signal is pre-amplified to form a pre-amplified first differential output signal; as well as The second differential output signal is pre-amplified to form a pre-amplified second differential output signal.

18. The dual-input amplifier method according to claim 16, further comprising: The first differential output signal is converted into a first single-ended output signal; The first single-ended output signal is pre-amplified to form a pre-amplified first output signal; The second differential output signal is converted into a second single-ended output signal; as well as The second single-ended output signal is pre-amplified to form a pre-amplified second output signal.

19. The dual-input amplifier method according to claim 16, further comprising: The pre-amplified first output signal is amplified in the first driver amplifier and carrier amplifier of the first series to form an amplified first output signal; The pre-amplified second output signal is amplified in the second driver amplifier and peak amplifier of the second series to form an amplified second output signal; The amplified first output signal and the amplified second output signal are combined to form a combined RF output signal; and The combined RF output signal is transmitted through at least one antenna.

20. A dual-input amplifier, the dual-input amplifier comprising: A first vector and a phase shifter and a second vector and a phase shifter are configured to dynamically modulate the phase difference between a first differential output signal and a second differential output signal in response to the power of the input RF signal. A first differential-to-single-ended converter is configured to convert the first differential output signal into a first single-ended output signal. A first driver amplifier, configured to amplify the first single-ended output signal to form a first driver output signal; and A first power amplifier is configured to amplify the output signal of the first driver to form a first power amplifier output signal.

21. The dual-input amplifier of claim 20, further comprising: A second differential-to-single-ended converter is configured to convert the second differential output signal into a second single-ended output signal. A second driver amplifier is configured to amplify the second single-ended output signal to form a second driver output signal; and A second power amplifier is configured to amplify the output signal of the second driver to form a second power amplifier output signal.

22. The dual-input amplifier of claim 21, further comprising: A combiner configured to combine the output signal of the first power amplifier with the output signal of the second power amplifier to form a combined RF output signal.

23. The dual-input amplifier of claim 22, wherein the dual-input amplifier is integrated into a transmitter, the transmitter including at least one antenna configured to transmit the combined RF output signal.

24. The dual-input amplifier of claim 22, wherein the dual-input amplifier comprises a Dougherty amplifier, wherein the first power amplifier is a carrier amplifier and wherein the second power amplifier is a peak amplifier.

25. A transmitter, the transmitter comprising: A delay and impedance matching circuit, configured to delay an RF input signal to a delayed matched signal; A preamplifier configured to amplify the delayed matched signal to form an amplified input signal; A single-ended to differential conversion circuit, configured to convert the amplified input signal into a differential input signal; A polyphase filter configured to convert the differential input signal into a differential in-phase signal and a differential quadrature-phase signal; A first vector and a phase shifter and a second vector and a phase shifter are both configured to process the differential in-phase signal and the differential quadrature-phase signal to form a first differential output signal and a second differential output signal, and to dynamically modulate the phase difference between the first differential output signal and the second differential output signal in response to the power of the RF input signal. A first differential-to-single-ended converter circuit is configured to convert the first differential output signal to form a first single-ended output signal. The second differential-to-single-ended converter circuit is configured to convert the second differential output signal to form a second single-ended output signal. One or more first amplifiers, the one or more first amplifiers being configured to amplify the first single-ended output signal to form a first amplified RF signal; One or more second amplifiers, the one or more second amplifiers being configured to amplify the second single-ended output signal to form a second amplified RF signal; and A combiner configured to combine a first amplified RF signal with a second amplified RF signal to form a combined RF output signal.

26. The transmitter of claim 25, wherein the one or more first amplifiers comprise a first series of first driver amplifiers and first power amplifiers, and wherein the one or more second amplifiers comprise a second series of second driver amplifiers and second power amplifiers.

27. The transmitter of claim 25, wherein the polyphase filter comprises a two-stage polyphase filter.

28. The transmitter of claim 27, wherein the two-stage polyphase filter is a two-stage transconductance-capacitor (gm-C) polyphase filter.

29. The transmitter of claim 27, wherein the two-stage multiphase filter is a two-stage resistor-capacitor (RC) multiphase filter.

30. The transmitter of claim 25, wherein the one or more first amplifiers comprise a carrier amplifier of a Dougherty amplifier, and wherein the one or more second amplifiers comprise a peak amplifier of the Dougherty amplifier.

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