Semiconductor device and method of manufacturing the same

Abstract

Methods, devices, systems, and techniques are provided for managing conductive structures in semiconductor devices. In one aspect, a semiconductor device includes a memory cell. Each of the memory cells includes a transistor having a gate structure extending in a first direction in a first trench structure. The semiconductor device further includes a conductive structure in the second trench structure between the transistors of the first memory cell and the second memory cell. The transistors of the first and second memory cells have corresponding first terminal structures, identical semiconductor bodies, and identical second terminal structures. The conductive structure is in contact with the semiconductor bodies of the transistors of the first and second memory cells. In the first direction, the first trench structure has a greater length than the second trench structure.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and processes for manufacturing semiconductor devices. Background Technology

[0002] Semiconductor devices (e.g., memory devices) can have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices are attractive due to their ability to increase array density by stacking more layers within a similar footprint. 3D memory devices typically include a memory array of memory cells and peripheral circuitry for facilitating operation of the memory array. Memory cells may include vertical structures, such as vertical transistors. Summary of the Invention

[0003] This disclosure describes methods, apparatus, systems, and techniques for managing vertical structures in three-dimensional (3D) semiconductor devices.

[0004] One aspect of this disclosure is a semiconductor device. The semiconductor device includes: a plurality of memory cells, wherein each memory cell includes a transistor having a gate structure extending along a first direction in a first trench structure; and a conductive structure located in a second trench structure between the transistors of the first and second memory cells, wherein the transistors of the first and second memory cells have corresponding first terminal structures, identical semiconductor bodies, and identical second terminal structures, and wherein the conductive structure contacts the semiconductor bodies of the transistors of the first and second memory cells, wherein the first trench structure has a longer length than the second trench structure along the first direction.

[0005] In some embodiments, along the first direction, the end of the gate structure of the transistor of the memory cell is farther from the first terminal structure of the transistor of the memory cell than the end of the second trench structure.

[0006] In some embodiments, the length of the first trench structure is greater than the length of the second trench structure along a second direction perpendicular to the first direction.

[0007] In some embodiments, the semiconductor body of the memory cell includes opposing ends along a first direction, wherein a first terminal structure and a second terminal structure are respectively located at opposing ends of the semiconductor body of the memory cell, and wherein a second trench structure is located between two adjacent first trench structures along a second direction perpendicular to the first direction.

[0008] In some embodiments, the semiconductor device includes a third memory cell, wherein a first memory cell is located between the second and third memory cells along a second direction perpendicular to the first direction, and wherein a first trench structure includes two gate structures of two transistors of the first and third memory cells, wherein the two gate structures are separated by an insulating material filled in the first trench structure.

[0009] In some embodiments, the conductive structure is isolated from the first terminal structure by a dielectric material along a second direction perpendicular to the first direction.

[0010] In some embodiments, the conductive structure includes a semiconductor material, and wherein the second trench structure further includes a dielectric body stacked on the conductive structure along a first direction.

[0011] In some embodiments, the conductive structure includes a metallic material, wherein the second trench structure further includes a dielectric body stacked on the conductive structure along a first direction, and wherein the semiconductor device further includes an ohmic contact between the metallic material and the semiconductor body.

[0012] In some implementations, the conductive structure in the second trench structure is coupled to the interconnect structure via a coupling output structure.

[0013] In some embodiments, the first trench structure and the second trench structure extend along a second direction perpendicular to the first direction, and wherein the semiconductor device further includes one or more third trench structures extending through the semiconductor device along the first direction and spaced apart from each other along a third direction perpendicular to the first and second directions.

[0014] In some embodiments, one or more third trench structures are filled with an isolation material, wherein the first trench structure includes an isolation material filled around the gate structure, and the second trench structure includes an isolation material stacked on the conductive structure along a first direction.

[0015] Another aspect of this disclosure features a method for forming a semiconductor device. The method includes: forming a plurality of memory cells in a semiconductor substrate, wherein each memory cell includes a transistor having a gate structure extending along a first direction in a first trench structure. The method further includes: forming a conductive structure in a second trench structure between the transistors of the first and second memory cells, wherein the transistors of the first and second memory cells have corresponding first terminal structures, identical semiconductor bodies, and identical second terminal structures, and wherein the conductive structure contacts the semiconductor bodies of the transistors of the first and second memory cells, wherein the first trench structure has a longer length than the second trench structure along the first direction.

[0016] In some embodiments, the semiconductor body of the memory cell includes opposing ends along a first direction, wherein a first terminal structure and a second terminal structure are respectively located at opposing ends of the semiconductor body of the memory cell, and wherein a second trench structure is located between two adjacent first trench structures along a second direction perpendicular to the first direction.

[0017] In some embodiments, forming a conductive structure includes: etching a semiconductor substrate along a first direction to form a trench, and depositing a semiconductor material in the trench along the first direction, wherein the length of the semiconductor material along the first direction is not greater than the length of the semiconductor body.

[0018] In some embodiments, a portion of the semiconductor material diffuses into the semiconductor body to form a conductive contact between the semiconductor material and the semiconductor body, and wherein the conductive structure contacts a portion of the semiconductor body that is closer to the second terminal structure than the first terminal structure along a first direction.

[0019] In some embodiments, forming a conductive structure includes: etching a semiconductor substrate along a first direction to form a trench, implanting conductive ions into a semiconductor body at the bottom of the trench to form a conductive contact, and depositing a metal material on the conductive contact in the trench to form a conductive structure, wherein the length of the metal material along the first direction is not greater than the length of the semiconductor body.

[0020] In some embodiments, the method further includes: forming a first trench structure including a gate structure, wherein the first trench structure and the second trench structure are located at different positions along a second direction perpendicular to the first direction, and wherein the gate structure extends in the first trench structure along the first direction, and wherein, along the first direction, the end of the gate structure of the transistor of the memory cell is farther from the first terminal structure of the transistor of the memory cell than the end of the second trench structure.

[0021] In some embodiments, the first trench structure and the second trench structure extend along a second direction perpendicular to the first direction, and the method further includes: forming one or more third trench structures that extend through the semiconductor substrate along the first direction and are spaced apart from each other along a third direction perpendicular to the first and second directions.

[0022] In some embodiments, one or more third trench structures are filled with an isolation material, wherein the first trench structure includes an isolation material filled around the gate structure, and the second trench structure includes an isolation material stacked on the conductive structure along a first direction.

[0023] In some embodiments, the method further includes forming a coupled output structure, wherein the conductive structure in the second trench structure is coupled to the interconnect structure through the coupled output structure.

[0024] Another aspect of this disclosure features a memory system. The memory system includes a memory device and a memory controller coupled to and configured to control the memory device. The memory device includes: a plurality of memory cells, wherein each memory cell includes a transistor having a gate structure extending along a first direction in a first trench structure; and a conductive structure in a second trench structure located between the transistors of the first and second memory cells, wherein the transistors of the first and second memory cells have corresponding first terminal structures, identical semiconductor bodies, and identical second terminal structures, and wherein the conductive structure contacts the semiconductor bodies of the transistors of the first and second memory cells, wherein the first trench structure has a greater length than the second trench structure along the first direction.

[0025] Details of one or more embodiments of the subject matter of this disclosure are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will be apparent from the specification, drawings, and claims. Attached Figure Description

[0026] The accompanying drawings, which are incorporated herein and form a part of this disclosure, illustrate various aspects of this disclosure and, together with the description, further serve to explain the principles of this disclosure and enable those skilled in the art to implement and use this disclosure.

[0027] Figure 1 A cross-sectional view of an exemplary 3D semiconductor device is shown.

[0028] Figure 2 A perspective view of an exemplary 3D semiconductor device is shown.

[0029] Figure 3A A cross-sectional view of an exemplary 3D semiconductor device including a semiconductor conductive structure is shown.

[0030] Figure 3B It shows Figure 3A A top view of an exemplary 3D semiconductor device.

[0031] Figure 3C This is a cross-sectional view of an exemplary 3D semiconductor device including a metallic conductive structure.

[0032] Figure 3D It shows Figure 3C A top view of an exemplary 3D semiconductor device.

[0033] Figures 4A to 4D This illustrates the various stages of the manufacturing process. Figure 3A A cross-sectional view of the structure of a 3D semiconductor device.

[0034] Figures 5A to 5D This illustrates the various stages of the manufacturing process. Figure 3B A cross-sectional view of the structure of a 3D semiconductor device.

[0035] Figures 6A-6B A perspective view of an exemplary 3D semiconductor device is shown.

[0036] Figure 7 A flowchart illustrating an exemplary process for manufacturing semiconductor structures is shown.

[0037] Figure 8 A block diagram of an exemplary system having one or more semiconductor devices is shown.

[0038] The same reference numerals and names in the various figures indicate the same elements. It should also be understood that the various exemplary embodiments shown in the figures are merely illustrative representations and are not necessarily drawn to scale. Detailed Implementation

[0039] Due to the need for higher-density and cheaper memory devices, memory devices (e.g., DRAM) can be configured with vertical-channel selectors and high aspect ratios. The vertical-channel selectors and high aspect ratios of such memory devices can present manufacturing challenges. For example, vertical-channel selectors typically have a floating body, which leads to charge accumulation in the source-drain junction in the bulk region of the transistor body. In other words, vertical-channel selectors can increase channel leakage current. In another example, the high aspect ratio can pose challenges in controlling leakage current. Therefore, a vertical-channel structure capable of addressing these issues is needed.

[0040] In one or more embodiments of this disclosure, an exemplary semiconductor device is provided. The semiconductor device includes a plurality of memory cells, wherein one of the memory cells includes a transistor having a semiconductor body, a first terminal structure, a second terminal structure, and a gate structure, wherein the gate structure extends in a first trench structure along a first direction. The semiconductor device also includes a conductive structure located in a second trench structure between the transistors of the first and second memory cells, the conductive structure contacting the semiconductor body of the transistors of the first and second memory cells, wherein, along the first direction, the first trench structure has a longer length than the second trench structure.

[0041] The embodiments of this disclosure can provide one or more of the following advantages and / or benefits. For example, by using a conductive structure between two adjacent memory cells, charge accumulation in the float can be reduced, thereby mitigating the float effect in a vertical channel selector transistor. By reducing the length of the second trench between the first and second memory cells, the semiconductor bodies of the two transistors in the first and second memory cells are connected together, thereby reducing overall manufacturing complexity and cost, and improving the reliability of the memory cells. Furthermore, by arranging the gate structure and conductive structure in two different trenches on opposite sides of the semiconductor body of the transistor, the overall manufacturing complexity of the semiconductor structure can be reduced.

[0042] This technology can be applied to various types of semiconductor devices, volatile memory devices (e.g., DRAM memory devices), non-volatile memory (NVM) devices (e.g., NAND flash memory, NOR flash memory), resistive random access memory (RRAM), phase-change memory (PCM) (e.g., PCRAM), spin-transfer torque (STT) magnetoresistive random access memory (MRAM), etc. It can also be applied to charge-trap-based memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices and floating-gate-based memory devices. This technology can be applied to three-dimensional (3D) memory devices. It can be applied to various memory types, such as SLC (single-cell) devices, MLC (multi-cell) devices (e.g., 2-cell devices, TLC (triple-cell) devices, QLC (quadruple-cell) devices, or PLC (five-cell) devices). Alternatively, this technology can be applied to various types of devices and systems, such as secure digital cards (SD cards), embedded multimedia cards (eMMC) or solid-state drives (SSDs), embedded systems, etc.

[0043] Notice, Figure 1 The disclosure includes X, Y, and Z axes (also referred to as the X, Y, and Z directions) to further illustrate the spatial relationships of the various components in the semiconductor device. The substrate of the semiconductor device may include two lateral surfaces extending laterally in the XY plane: a top surface on the front side of the substrate on which components of the semiconductor device may be formed; and a bottom surface on the back side opposite the front side of the substrate. The Z direction is perpendicular to both the X and Y directions. As used in this disclosure, when the substrate is located in the lowest plane of the semiconductor device in the Z direction, whether one component (e.g., a layer or device) of the semiconductor device is “on,” “above,” or “below” another component (e.g., a layer or device) is determined relative to the substrate of the semiconductor device in the Z direction (a direction perpendicular to the XY plane, such as the thickness direction of the substrate). The same concepts used to describe spatial relationships are applied throughout this disclosure.

[0044] Figure 1 A side view of a cross-section of an exemplary 3D semiconductor device 100 is shown. The 3D semiconductor device 100 may be a 3D dynamic random access memory (DRAM). It should be understood that... Figure 1 For illustrative purposes only and may not necessarily reflect actual device structures (e.g., interconnections) in practice. In some embodiments, the 3D semiconductor device 100 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104 stacked on top of the first semiconductor structure 102. The first semiconductor structure 102 and the second semiconductor structure 104 may be connected at a bonding interface 106 located between them.

[0045] like Figure 1 As shown, the first semiconductor structure 102 may include a substrate 110, which may include silicon (e.g., single-crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material. The first semiconductor structure 102 may include peripheral circuitry 112 located on and / or within the substrate 110. In some embodiments, the peripheral circuitry 112 includes a plurality of transistors 114 (e.g., planar transistors and / or 3D transistors). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions (e.g., wells, sources, and drains of transistors 114) may also be formed on or within the substrate 110. In some examples, the peripheral circuitry 112 is formed using complementary metal-oxide-semiconductor (CMOS) technology, and the first semiconductor structure 102 may also be formed on a semiconductor die, which may be referred to as a control die or CMOS die 102.

[0046] In some embodiments, the first semiconductor structure 102 further includes an interconnect layer 116 above the peripheral circuitry 112 for transmitting electrical signals to and from the peripheral circuitry 112. The interconnect layer 116 may include a plurality of interconnects (also referred to herein as “contacts”), including lateral interconnects and via contacts. The interconnect layer 116 may also include one or more interlayer dielectric (ILD) layers in which the interconnects and via contacts can be formed. That is, the interconnect layer 116 may include interconnects and via contacts located in a plurality of ILD layers. In some embodiments, the peripheral circuitry 112 is coupled to each other via interconnects in the interconnect layer 116. The interconnects in the interconnect layer 116 may include conductive materials, including but not limited to: W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. Dielectric materials may be used to form the ILD layers, including but not limited to: silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0047] like Figure 1As shown, the first semiconductor structure 102 has a front side and a back side, and the first semiconductor structure 102 may further include a bonding layer 118 on the back side of the bonding interface 106 and above the interconnect layer 116 and the peripheral circuitry 112. The bonding layer 118 may include a plurality of bonding contacts 119 and a dielectric that electrically isolates the bonding contacts 119. The bonding contacts 119 may include a conductive material, such as Cu. A dielectric material (e.g., silicon oxide) may be used to form the remaining area of ​​the bonding layer 118. The bonding contacts 119 in the bonding layer 118 and the surrounding dielectric may be used for hybrid bonding. Similarly, as Figure 1 As shown, the second semiconductor structure 104 may also include a bonding layer 120 at the bonding interface 106 and above the bonding layer 118 of the first semiconductor structure 102. The bonding layer 120 may include a plurality of bonding contacts 121 and a dielectric that electrically isolates the bonding contacts 121. The bonding contacts 121 may include a conductive material, such as Cu. The remaining area of ​​the bonding layer 120 may be formed using a dielectric material (e.g., silicon oxide). The bonding contacts 121 in the bonding layer 120 and the surrounding dielectric may be used for hybrid bonding. The bonding contacts 121 may contact the bonding contacts 119 at the bonding interface 106. In some embodiments, such as Figure 1 As shown, the bonding layer 120 includes a dielectric layer opposite to a memory cell (e.g., a DRAM cell) 124, wherein bit lines 123 are located between the dielectric layer and the memory cell 124. The dielectric layer may include a bonding interface 106 having bonding contacts 121.

[0048] The second semiconductor structure 104 can be bonded face-to-face to the top of the first semiconductor structure 102 at the bonding interface 106. In some embodiments, as a result of hybrid bonding (also referred to as “metal / dielectric hybrid bonding”), the bonding interface 106 is disposed between the bonding layers 120 and 118. Hybrid bonding is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer such as solder or adhesive) and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, the bonding interface 106 is where the bonding layers 120 and 118 meet and bond. In some examples, the bonding interface 106 can be a layer of a specific thickness, comprising the top surface of the bonding layer 118 of the first semiconductor structure 102 and the bottom surface of the bonding layer 120 of the second semiconductor structure 104.

[0049] In some embodiments, the second semiconductor structure 104 further includes an interconnect layer 122 for transmitting electrical signals, the interconnect layer 122 including bit lines 123 located above the bonding layer 120. The interconnect layer 122 may include multiple interconnects, such as mid-stage (MEOL) interconnects and back-end stage (BEOL) interconnects. In some embodiments, the interconnects in the interconnect layer 122 also include local interconnects, such as bit lines 123 and word line contacts (not shown). The interconnect layer 122 may also include one or more ILD layers, in which interconnect lines and via contacts can be formed. The interconnects in the interconnect layer 122 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers may be formed using dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0050] In some embodiments, peripheral circuitry 112 includes a word line driver / row decoder coupled to word line contacts in interconnect layer 122 via bonding contacts 121 and 119 in bonding layers 120 and 118 and interconnect layer 116. In some embodiments, peripheral circuitry 112 includes a bit line driver / column decoder coupled to bit lines 123 and bit line contacts in interconnect layer 122 via bonding contacts 121 and 119 in bonding layers 120 and 118 and interconnect layer 116. In some embodiments, bit line 123 is a metal bit line opposite to a semiconductor bit line (e.g., a doped silicon bit line). For example, bit line 123 may include W, Co, Cu, Al, or any other suitable metal having a higher conductivity than doped silicon. In some embodiments, the bit line contacts are ohmic contacts instead of Schottky contacts.

[0051] In some embodiments, bit line 123 is made of a composite conductive material, which may be based on a metallic material (e.g., W, Co, Cu, Al) and a semiconductor material (e.g., Si). For example, the composite conductive material may include metal silicides such as WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a higher conductivity than doped silicon.

[0052] In some embodiments, the second semiconductor structure 104 includes a DRAM device, wherein memory cells are provided in the form of an array of DRAM cells 124 over the interconnect layer 122 and the bonding layer 120. That is, the interconnect layer 122, including bit lines 123, may be disposed between the bonding layer 120 and the array of DRAM cells 124. The bit lines 123 in the interconnect layer 122 may be coupled to a string of DRAM cells 124. In some embodiments, the second semiconductor structure 104 is formed on a semiconductor die and may be referred to as an array die 104.

[0053] In some embodiments, a semiconductor device may include a plurality of array dies (e.g., array die 104) and a CMOS die (e.g., CMOS die 102). The array dies and CMOS dies may be stacked and bonded together. A CMOS die may be coupled to each of the array dies individually and may drive each of the array dies individually to operate in a manner similar to that of the semiconductor device. The semiconductor device may be any suitable device. In some examples, the semiconductor device includes at least a first wafer and a second wafer face-to-face bonded. Array dies may be disposed on the first wafer along with other array dies, and CMOS dies may be disposed on the second wafer along with other CMOS dies. The first and second wafers may be bonded together, so that an array die on the first wafer may be bonded to a corresponding CMOS die on the second wafer. In some examples, the semiconductor device is a chip having at least array dies and CMOS dies bonded together. In this example, the chip is diced from the bonded wafer. In another example, the semiconductor device is a semiconductor package including one or more semiconductor chips assembled on a packaging substrate.

[0054] Each DRAM cell 124 may include a vertical transistor 126 and a capacitor 128 coupled to the vertical transistor 126. The DRAM cell 124 may be a 1T1C cell consisting of a transistor (T) and a capacitor (C). It should be understood that the DRAM cell 124 may be any suitable configuration, such as a 2T1C cell, a 3T1C cell, etc. The vertical transistor 126 may be a MOSFET for switching the corresponding DRAM cell 124. In some embodiments, the vertical transistor 126 includes a semiconductor body 130 extending vertically (in the Z direction), and a gate structure 136 extending in the Z direction within a first trench structure 132. The first trench structure 132 contacts one side of the semiconductor body 130. In some embodiments, the first trench structure 132 is filled with a dielectric material. In a single-gate vertical transistor, the semiconductor body 130 may have a cuboid or cylindrical shape. In some embodiments, the vertical transistor 126 has a structure including two or more gates, such as a dual-gate structure, a tri-gate structure, or a gate all-around (GAA) structure. In some embodiments, the gate structure 136 includes a gate electrode and a gate dielectric laterally located between the gate electrode and the semiconductor body 130 in the bit line direction (e.g., in the Y direction). In some embodiments, such as Figure 1As shown, the vertical transistor 126 may have a first terminal structure 156 in the positive z-direction and a second terminal structure 158 opposite to the first terminal structure 156 in the negative z-direction. Each vertical transistor 126 of the DRAM cell 124 may include a conductive structure 160 in a second trench structure 164. The second trench structure 164 is located between the first vertical transistor 126a of the first memory cell 124a and the second vertical transistor 126b of the second memory cell 124b.

[0055] The conductive structure 160 is connected to the semiconductor bodies 130 of the vertical transistors 126a and 126b of the first memory cell 124a and the second memory cell 124b. In some embodiments, the transistors 126a and 126b of the first memory cell 124a and the second memory cell 124b have corresponding first terminal structures 156, the same semiconductor bodies 130, and the same second terminal structures 158, and the conductive structure 160 is in contact with the semiconductor bodies 130 of the transistors 126a and 126b of the first memory cell 124a and the second memory cell 124b. In some embodiments, the second trench structure 164 may be filled with an insulating material. In some embodiments, such as Figure 1 As shown, the first trench structure 132 has a longer length along the Z-direction than the second trench structure 164. In some embodiments, the semiconductor bodies 130 of the vertical transistors 126a and 126b of the first memory cell 124a and the second memory cell 124b are connected together along a horizontal direction perpendicular to the Z-direction (e.g., the X-direction). In some embodiments, such as Figure 1 As shown, the length of end 132-1 of the first groove structure 132 and the length of end 164-1 of the second groove structure 164 are the same along the X direction.

[0056] like Figure 1 As shown, in some embodiments, the semiconductor body 130 of the vertical transistor 126 of each memory cell 124 includes opposing ends along the Z direction. In some embodiments, the first terminal structure 156 and the second terminal structure 158 of the vertical transistor 126 are located along the Z direction at opposing ends of the semiconductor body 130 of the memory cell 124, and the second trench structure 164 is located along the X direction between two adjacent first trench structures 132. In some embodiments, as... Figure 1 As shown, the end 136-1 of the gate structure 136 of the vertical transistor 126 of the memory cell 124 is farther from the first terminal structure 156 of the vertical transistor 126 than the end 164-2 of the second trench structure 164.

[0057] like Figure 1As shown, the semiconductor device 100 may include a third memory cell 124c. In some embodiments, the first memory cell 124a is located along the X direction between the second memory cell 124b and the third memory cell 124c. In some embodiments, such as Figure 1 As shown, the first trench structure 132 may include two gate structures 136 of two vertical transistors 126a and 126c of the first memory cell 124a and the third memory cell 124c. In some embodiments, such as Figure 1 As shown, the thickness of the conductive structure 160 along the Z-direction is no greater than the thickness of the semiconductor body 130, and wherein the conductive structure 160 is connected to the portion of the semiconductor body 130 along the Z-direction that is closer to the second terminal structure 158 than the first terminal structure 156. In some embodiments, the thickness of the conductive structure 160 along the Z-direction is no greater than the thickness of the semiconductor body 130, and the conductive structure 160 is connected to the portion of the semiconductor body 130 along the Z-direction that is closer to the second terminal structure 158 than the first terminal structure 156. In some embodiments, the conductive structure 160 is isolated from the first terminal structure 156 along the X-direction by a dielectric material. In some embodiments, such as Figure 1 As shown, a first terminal structure 156 is coupled to a capacitor 128 and a second terminal structure 158 is coupled to a bit line 123. In some embodiments, the first terminal structure 156 may be a source structure and the second terminal structure 158 may be a drain structure. In some embodiments, the semiconductor bodies 130 of the first memory cell 124a and the second memory cell 124b form a single semiconductor body 130. In some embodiments, a second trench structure 164 is surrounded by the single semiconductor body 130. In some embodiments, the second terminal structure 158 of the memory cell 124 forms a single second terminal structure 158. The second terminal structure 158 is connected to the corresponding bit line 123. In some embodiments, the transistors 126 of two adjacent memory cells 124a and 124b have corresponding first terminal structures 156 coupled to the corresponding capacitors 128b, the same semiconductor body 210, and the same second terminal structure 158.

[0058] In some embodiments, the semiconductor body 130 comprises a semiconductor material, such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, Ge, any other semiconductor material, or any combination thereof. In one example, the semiconductor body 130 may comprise monocrystalline silicon. The first terminal structure 156 and the second terminal structure 158 may be doped with an N+ type dopant (e.g., phosphorus (P) or arsenic (As)) or a P type dopant (e.g., boron (B) or gallium (Ga)) at a desired doping level. In some embodiments, a silicide layer (e.g., a metal silicide layer) is formed between the second terminal structure 158 of the vertical transistor 126 and the bit line 123 as a bit line contact, or formed between the first terminal structure 156 of the vertical transistor 126 and the first electrode of the capacitor 128 as a capacitor contact 142, thereby reducing contact resistance. In some embodiments, the gate dielectric comprises a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some embodiments, the gate electrode comprises a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the gate electrode comprises multiple conductive layers, such as a W layer over a TiN layer. In one example, the gate structure 136 may be a "gate oxide / gate polysilicon" gate, wherein the gate dielectric comprises silicon oxide and the gate electrode comprises doped polysilicon. In another example, the gate structure 136 may be an HKMG, wherein the gate dielectric comprises a high-k dielectric and the gate electrode comprises a metal.

[0059] As described above, since the gate structure 136 can be part of a word line or extend as a word line in the word line direction (e.g., the X direction), the second semiconductor structure 104 of the 3D semiconductor device 100 can also include multiple word lines, each extending in the word line direction. Each word line can be coupled to a row of DRAM cells 124. That is, the bit line 123 and the word line can extend in two perpendicular lateral directions, and the semiconductor body 130 of the vertical transistor 126 can extend in a vertical direction perpendicular to the two lateral directions in which the bit line 123 and the word line extend. The word lines are in contact with word line contacts (not shown). In some embodiments, the word lines comprise conductive materials, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicides, or any combination thereof. In some embodiments, such as Figure 1 As shown, the word line includes multiple conductive layers, such as a W layer located above the TiN layer.

[0060] In some implementations, such as Figure 1As shown, the vertical transistors 126 can be arranged in a mirror-symmetric manner to increase the density of memory cells 124 in the bit line direction (Y direction). Figure 1 As shown, two adjacent vertical transistors 126 in the bit line direction are mirror-symmetrical with respect to the second trench structure 164. That is, the second semiconductor structure 104 may include a plurality of second trench structures 160, each extending parallel to the word line in the X direction and disposed between the vertical gates of two adjacent rows of vertical transistors 126. Each first trench structure may include two gate structures 136 for two memory cells. In some embodiments, rows of vertical transistors 126 separated by the second trench structure 164 are mirror-symmetrical with respect to the second trench structure 164. The second trench structure 164 may include conductive structures 160 in contact with the semiconductor body and filled with a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0061] like Figure 1 As shown, in some embodiments, capacitor 128 includes a first electrode 144 located above and coupled to the first terminal structure 156 of vertical transistor 126 via capacitor contact 142. In some embodiments, capacitor contact 142 is an ohmic contact, such as a metal silicide contact, rather than a Schottky contact. For example, capacitor contact 142 may include a metal silicide, such as WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having higher conductivity than doped silicon. Capacitor 128 may also include a capacitor dielectric located above and in contact with the first electrode 144, and a second electrode located above and in contact with the capacitor dielectric. That is, capacitor 128 may be a vertical capacitor, wherein the electrodes and capacitor dielectric are stacked vertically (in the z-direction), and the capacitor dielectric may be sandwiched between the electrodes. In some embodiments, each first electrode is coupled to a first terminal structure 156 of a corresponding vertical transistor 126 in the same memory cell 124, while all second electrodes are coupled to a common plate 146, which is coupled to ground (e.g., a common ground). Figure 1 As shown, capacitor 128 may have a first end in the negative z-direction and a second end in the positive z-direction opposite to the first end. Figure 1 As shown, the second semiconductor structure 104 may further include capacitor contacts 147 (e.g., conductors) in contact with the common plate 146 to couple capacitor 128 to peripheral circuitry 112 or directly to ground. In some embodiments, such as Figure 1As shown, capacitor contacts 147 (e.g., conductors) extend in the z-direction from the dielectric layer of bonding layer 120 to be coupled to a second end of capacitor 128 via common plate 146. In some embodiments, the ILD layer in which capacitor 128 is formed has the same dielectric material, such as silicon oxide, as the two ILD layers into which semiconductor body 130 extends.

[0062] It should be understood that the structure and construction of capacitor 128 are not limited to... Figure 1 Examples are provided, and any suitable structure and construction may be included, such as planar capacitors, stacked capacitors, multi-fin capacitors, cylindrical capacitors, trench capacitors, or substrate-plate capacitors. In some embodiments, the capacitor dielectric comprises a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to: Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. It should be understood that in some examples, capacitor 128 may be a ferroelectric capacitor used in FRAM cells, and the capacitor dielectric may be replaced by a ferroelectric layer having a ferroelectric material (e.g., PZT or SBT). In some embodiments, the electrodes comprise conductive materials, including but not limited to: W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof.

[0063] like Figure 1 As shown, in some embodiments, the vertical transistor 126 is vertically disposed between the capacitor 128 and the bonding interface 106. That is, the vertical transistor 126 can be arranged closer to the peripheral circuitry 112 and the bonding interface 106 of the first semiconductor structure 102 than the capacitor 128. Since the bit line 123 and the capacitor 128 are coupled to opposite ends of the vertical transistor 126, the bit line 123 (as part of the interconnect layer 122) is vertically disposed between the vertical transistor 126 and the bonding interface 106. As a result, the interconnect layer 122, including the bit line 123, can be arranged close to the bonding interface 106, thereby reducing interconnect wiring distance and complexity.

[0064] In some embodiments, the second semiconductor structure 104 further includes a substrate 148 disposed above the DRAM cell 124. The substrate 148 may be part of a carrier wafer. It should be understood that in some examples, the substrate 148 may not be included in the second semiconductor structure 104.

[0065] like Figure 1As shown, the second semiconductor structure 104 may further include a pad output interconnect layer 150 located above the substrate 148 and the DRAM cell 124. The pad output interconnect layer 150 may include interconnects in one or more ILD layers, such as contact pads 154. The pad output interconnect layer 150 and interconnect layer 122 may be formed on opposite sides of the DRAM cell 124. A capacitor 128 may be vertically disposed between the vertical transistor 126 and the pad output interconnect layer 150. In some embodiments, the interconnects in the pad output interconnect layer 150 may transmit electrical signals between the 3D semiconductor device 100 and external circuitry, for example, for pad output purposes.

[0066] In some embodiments, the second semiconductor structure 104 further includes one or more contacts 152 extending through the substrate 148 and a portion of the pad output interconnect layer 150 to couple the pad output interconnect layer 150 to the DRAM cell 124 and the interconnect layer 122. As a result, peripheral circuitry 112 can be coupled to the DRAM cell 124 via interconnect layers 116 and 122 and bonding layers 120 and 118, and peripheral circuitry 112 and DRAM cell 124 can be coupled to external circuitry via the contacts 152 and the pad output interconnect layer 150. The contact pads 154 and contacts 152 may comprise conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In one example, the contact pads 154 may comprise Al, and the contacts 152 may comprise W. In some embodiments, the contacts 152 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the substrate 148. Depending on the thickness of the substrate 148, the contact 152 can be an ILV with a depth of submicron level (e.g., between 10 nm and 1 μm) or a TSV with a depth of micron level or tens of micron level (e.g., between 1 μm and 100 μm).

[0067] Although not shown, it should be understood that the pad outputs of the 3D memory device are not limited to those from sources such as... Figure 1 The second semiconductor structure 104 shown has DRAM cells 124 and may be derived from a first semiconductor structure 102 having peripheral circuitry 112. Although not shown, it should be understood that the air gaps between word lines and / or between semiconductor bodies 130 may be partially or completely filled with dielectric. Although not shown, it should also be understood that an array of more than one DRAM cell 124 may be stacked on top of each other to vertically increase the number of DRAM cells 124.

[0068] In some embodiments, the second semiconductor structure 104 includes a substrate disposed beneath the DRAM cell 124, rather than having a substrate as shown in the figure. Figure 1The substrate 148 is shown above the DRAM cell 124. The substrate may be part of a carrier wafer. The DRAM cell 124 may be formed on the front side of the substrate, and the bit line 123 may be formed on the back side of the substrate. The bit line 123 may be electrically coupled to the DRAM cell 124 (e.g., the terminal structure 158 of the vertical transistor 126) through the substrate.

[0069] Figure 2 A perspective view of an exemplary 3D semiconductor device 200 is shown. The 3D semiconductor device can be... Figure 1 3D semiconductor device 100 or Figure 1 The structure of the intermediate manufacturing process of the 3D semiconductor device 100.

[0070] like Figure 2 As shown, the 3D semiconductor device 200 may include one or more memory cells 202. In some embodiments, the memory cells 202 may be connected to... Figure 1 The memory cells 124 of the semiconductor device 100 shown are similar or identical. Each memory cell may include a vertical transistor 204 having a semiconductor body 206, a first terminal structure 208, a second terminal structure 210, and a gate structure 212, wherein the gate structure 212 extends in a vertical direction (e.g., the Z direction) within a first trench structure 213. In some embodiments, the vertical transistor 204 may include a conductive structure 214 located in a second trench structure 216 between the vertical transistors 204 of two adjacent memory cells 202. In some embodiments, such as Figure 2 As shown, conductive structure 214 is connected to the semiconductor body 206 of the vertical transistor 204 of two adjacent memory cells 202. In some embodiments, the transistors 204 of the two adjacent memory cells 202 have corresponding first terminal structures 208, identical semiconductor bodies 206, and identical second terminal structures 210, and conductive structure 214 contacts the semiconductor bodies 210 of the transistors 204 of the two adjacent memory cells 202. In some embodiments, the first trench structure 213 has a longer length along the Z direction than the second trench structure 216, and along a horizontal direction perpendicular to the Z direction (e.g., the X direction), the length of the first trench structure 213 is greater than the length of the second trench structure 216. In some embodiments, the bottom end of the first trench structure 213 is farther from the surface of the semiconductor device 200 near the first terminal structure 208 along the Z direction than the bottom end of the second trench structure 216. In some embodiments, the semiconductor bodies 206 of the vertical transistors 204 of the two adjacent memory cells 202 are connected together. In some embodiments, the vertical transistors 204 may be connected to... Figure 1 The vertical transistor 126 of the illustrated semiconductor device 100 is similar to or the same. In some embodiments, the semiconductor body 206 may be similar to... Figure 1 The semiconductor body 130 of the illustrated semiconductor device 100 is similar to or identical to that of the semiconductor device 100. In some embodiments, the first terminal structure 208 may be similar to... Figure 1 The first terminal structure 156 of the semiconductor device 100 shown is similar to or the same as that shown. In some embodiments, the second terminal structure 210 may be similar to... Figure 1 The second terminal structure 158 of the semiconductor device 100 shown is similar to or the same as that shown. In some embodiments, the gate structure 212 may be similar to... Figure 1 The gate structure 136 of the semiconductor device 100 shown is similar to or the same as that shown. In some embodiments, the first trench structure 213 may be similar to... Figure 1 The first trench structure 132 of the semiconductor device 100 shown is similar to or the same as that shown. In some embodiments, the conductive structure 214 may be similar to... Figure 1 The conductive structure 160 of the semiconductor device 100 shown is similar to or the same as that of the semiconductor device 100. In some embodiments, the second trench structure 216 may be similar to... Figure 1 The second trench structure 164 of the semiconductor device 100 shown is similar to or the same.

[0071] In some implementations, such as Figure 2 As shown, the semiconductor body 206 of the memory cell 202 includes opposing ends along the Z direction. A first terminal structure 208 and a second terminal structure 210 are located at the opposing ends of the semiconductor body 206 of the memory cell 202, and a second trench structure 216 is located along the X direction between two adjacent first trench structures 213. In some embodiments, a conductive structure 214 in the second trench structure 216 is coupled to an interconnect structure via a coupling output structure 218. The coupling output structure 218 extends along the second trench structure 216 and is connected to the conductive structure 214 along the Z direction. In some embodiments, the coupling output structure 218 may be a via structure. In some embodiments, the coupling output structure 218 includes a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicides, or any combination thereof. In some embodiments, the semiconductor bodies 206 of two adjacent memory cells 202 form a single semiconductor body 206. In some embodiments, the second trench structure 216 is surrounded by the single semiconductor body 206. In some embodiments, the second terminal structure 210 of the memory cell 202 forms a single second terminal structure 210. In some embodiments, the transistors of two adjacent memory cells 202 have corresponding first terminal structures 208 coupled to the respective memory nodes (or capacitors), the same semiconductor body 206, and the same second terminal structure 210.

[0072] In some implementations, such as Figure 2As shown, the first trench structure 213 and the second trench structure 216 may extend along a second horizontal direction (e.g., the Y direction) perpendicular to the X and Z directions. The semiconductor device 200 may include one or more third trench structures 220 extending through the semiconductor device 200 along the Z direction and spaced apart from each other along the Y direction. The one or more third trench structures 220 extend along the X direction and divide the semiconductor device 200 into multiple arrays. In some embodiments, the third trench structures 220 may be filled with a first dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some embodiments, the first trench structure 213 may be filled with a second dielectric material surrounding the gate structure 212, and the second trench structure 216 may be filled with a third dielectric material stacked on the conductive structure 214 along the Z direction. In some embodiments, the second and third dielectric materials may be the same material as the first dielectric material.

[0073] Figure 3A A cross-sectional view of an exemplary 3D semiconductor device 300-1 is shown. Figure 3B It shows along Figure 3A The cutting line AA' Figure 3A A top view of an exemplary 3D semiconductor device 300-1. The 3D semiconductor device 300-1 may be... Figure 2 3D semiconductor device 200 or Figure 1 3D semiconductor device 100 or Figure 1 The structure of the 3D semiconductor device 100 in the intermediate manufacturing process. The 3D semiconductor device 300-1 can be manufactured by... Figures 4A-4D and / or Figure 7 The methods and / or processes described in further detail herein are formed.

[0074] like Figure 3A As shown, the 3D semiconductor device 300-1 has a semiconductor substrate 301 comprising a semiconductor material (e.g., silicon). An array of memory cells 302 can be formed in the semiconductor substrate 301. The memory cells 302 can be connected to... Figure 1 The memory cell 124 of the semiconductor device 100 and Figure 2 The memory cells 202 of the semiconductor device 200 are similar to or identical. Each memory cell 302 may include a vertical transistor 304 (e.g., Figure 1 Vertical transistor 126 or Figure 2 The vertical transistor 204) and the capacitor 306 coupled to the vertical transistor 304 (e.g., Figure 1 The DRAM memory cell includes a capacitor 128. The vertical transistor 304 may include a semiconductor body 308 (e.g., capacitor 128). Figure 1 Semiconductor body 130 or Figure 2 The semiconductor body 206), the first terminal structure 310 (e.g., Figure 1 First terminal structure 156 or Figure 2 First terminal structure 208), second terminal structure 312 (e.g., Figure 1 The second terminal structure 158 or Figure 2 The second terminal structure 210) and the gate structure 314 (e.g., Figure 1 Gate structure 136 or Figure 2 The gate structure 314 extends in a vertical direction (e.g., the Z direction) within the first trench structure 316. In some embodiments, the first trench structure is filled with an insulating material (e.g., SiO2). In some embodiments, the first trench structure 316 may be connected to... Figure 1 The first trench structure 132 of the semiconductor device 100 and Figure 2 The first trench structure 213 of the semiconductor device 200 is similar to or the same as that of the first terminal structure 310 and the second terminal structure 312. One of the first terminal structure 310 and the second terminal structure 312 may be a source structure and coupled to a memory node, and the other of the first terminal structure 310 and the second terminal structure 312 may be coupled to a drain structure and coupled to a bit line.

[0075] Semiconductor body 308 may include semiconductor materials such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, Ge, any other semiconductor material, or any combination thereof. In one example, semiconductor body 308 may include monocrystalline silicon. As discussed in further detail below, each of the first terminal structure 310 and the second terminal structure 312 may be formed by implanting N+ type ions (e.g., P or As) or P type ions (e.g., B or Ga) into the ends of semiconductor body 308 at a desired doping level. In one example, the first terminal structure 310 represents a source structure, and the second terminal structure 312 represents a drain structure.

[0076] Semiconductor device 300-1 may include a conductive structure 318-1 located in a second trench structure 320 between vertical transistors 304 of two adjacent memory cells 302. The conductive structure 318-1 is connected to the semiconductor bodies 308 of the two adjacent memory cells 302. In some embodiments, the transistors 304 of the two adjacent memory cells 302 have corresponding first terminal structures 310, identical semiconductor bodies 308, and identical second terminal structures 312, and the conductive structure 318-1 contacts the semiconductor bodies 308 of the transistors 304 of the two adjacent memory cells 302. In some embodiments, the bottom end of the first trench structure 316 is farther along the Z-direction from the surface of semiconductor device 300-1 near the first terminal structure 310 than the bottom end of the second trench structure 320. Figure 3A As shown, the conductive structure 318-1 includes a semiconductor material (e.g., polycrystalline silicon). In some embodiments, the second trench structure 320 may include a dielectric body 322 stacked on top of the conductive structure 318-1 along the Z direction. In some embodiments, the thickness of the dielectric body 322 along the Z direction is greater than the thickness of the first terminal structure 310. In some embodiments, the conductive structure 318-1 is isolated from the first terminal structure 310 along the X direction by the dielectric body 322. In some embodiments, the conductive structure 318-1 is separated from each of the first terminal structure 310 and the second terminal structure 312 along the Z direction. In some embodiments, as... Figure 3A As shown, the semiconductor device 300-1 may include conductive contacts 317 between the conductive structure 318-1 and the semiconductor body 308. In some embodiments, the semiconductor bodies 308 of two adjacent memory cells 302 form a single semiconductor body 308. In some embodiments, the second trench structure 320 is surrounded by the single semiconductor body 308. In some embodiments, the second terminal structure 312 of the memory cell 302 forms a single second terminal structure 312. In some embodiments, the transistors of two adjacent memory cells 302 have corresponding first terminal structures 310 coupled to corresponding memory nodes (or capacitors), identical semiconductor bodies 308, and identical second terminal structures 312.

[0077] like Figure 3B As shown, semiconductor device 300-1 may include one or more oxide spacers 324 extending along the X direction and spaced apart from each other along the Y direction. The one or more oxide spacers 324 divide semiconductor device 300-1 into multiple arrays. In some embodiments ( Figures 3A-3B (Not shown in the image), the first trench structure 316 and the second trench structure 320 are partially surrounded by an oxide spacer 324. In some embodiments, the oxide spacer 324 may be... Figure 2The third trench structure 220 of the semiconductor device 200 is similar to or the same as that of the semiconductor device 200.

[0078] Figure 3C A cross-sectional view of an exemplary 3D semiconductor device 300-2 is shown. Figure 3D It shows along Figure 3C The cutting line BB' Figure 3C A top view of an exemplary 3D semiconductor device 300-2. The 3D semiconductor device 300-3 may be... Figure 2 3D semiconductor device 200 or Figure 1 3D semiconductor device 100 or in Figure 1 The structure of the intermediate manufacturing process of the 3D semiconductor device 100. In some embodiments, except that the conductive structure 318-2 of the semiconductor device 300-2 has a different conductive material compared to the conductive structure 318-1 of the semiconductor device 300-1, the semiconductor device 300-2 can be similar to... Figure 3A Semiconductor device 300-1. 3D semiconductor device 300-2 can be used in... Figures 5A-5D and / or Figure 7 The methods and / or processes described in further detail herein are formed.

[0079] In some implementations, such as Figure 3C As shown, semiconductor device 300-2 may include a conductive structure 318-2 in a second trench structure 320 located between vertical transistors 304 of two adjacent memory cells 302. The conductive structure is connected to the semiconductor bodies 308 of the two adjacent memory cells 302. In some embodiments, the transistors 304 of the two adjacent memory cells 302 have corresponding first terminal structures 310, identical semiconductor bodies 308, and identical second terminal structures 312, and the conductive structure 318-2 contacts the semiconductor bodies 308 of the transistors 304 of the two adjacent memory cells 302. In some embodiments, the bottom end of the first trench structure 316 is farther along the Z-direction from the surface of semiconductor device 300-2 near the first terminal structure 310 than the bottom end of the second trench structure 320. Figure 3CAs shown, conductive structure 318-2 includes a metallic material (e.g., W). In some embodiments, the second trench structure may include dielectric sidewalls 326 coated on the inner sidewalls of the second trench structure 320. In some embodiments, the second trench structure also includes a dielectric body 322 stacked on top of conductive structure 318-2 along the Z direction. In some embodiments, the thickness of dielectric body 322 along the Z direction is greater than the thickness of the first terminal structure 310. In some embodiments, conductive structure 318-1 is isolated from the first terminal structure 310 along the X direction by dielectric body 322. In some embodiments, conductive structure 318-2 is separated from each of the first terminal structure 310 and the second terminal structure 312 along the Z direction. In some embodiments, semiconductor device 300-2 may include an ohmic contact 319 between the metallic material and the semiconductor body. In some embodiments, the ohmic contact 319 includes a highly conductive semiconductor material diffused into the semiconductor body 308. In some embodiments, the dielectric sidewall 326 may include a first dielectric material, and the dielectric body 322 may include a second dielectric material. In some embodiments, the first dielectric material is different from the second dielectric material. In some embodiments, the semiconductor bodies 308 of two adjacent memory cells 302 form a single semiconductor body 308. In some embodiments, the second trench structure 320 is surrounded by the single semiconductor body 308. In some embodiments, the second terminal structure 312 of the memory cell 302 forms a single second terminal structure 312. In some embodiments, the transistors of two adjacent memory cells 302 have corresponding first terminal structures 310 coupled to corresponding memory nodes (or capacitors), the same semiconductor body 308, and the same second terminal structure 312.

[0080] like Figure 3D As shown, the semiconductor device 300-2 may include one or more oxide spacers 324 extending along the X direction and spaced apart from each other along the Y direction. The one or more oxide spacers 324 divide the semiconductor device 300-2 into multiple arrays. In some embodiments ( Figures 3C-3D (Not shown in the image), the first trench structure 316 and the second trench structure 320 are partially surrounded by an oxide spacer 324. In some embodiments, the oxide spacer 324 may be... Figure 2 The third trench structure 220 of the semiconductor device 200 is similar to or the same as that of the semiconductor device 200.

[0081] Figures 4A-4D This illustrates the manufacture of semiconductor devices (e.g., such as...). Figures 3A-3B An exemplary process of the semiconductor device 300-1 shown. Figures 4A-4D Cross-sectional views of exemplary semiconductor structures at various stages of the manufacturing process are shown.

[0082] like Figure 4A As shown, a semiconductor structure 400a is formed by etching one or more portions of a semiconductor substrate 402 along a vertical direction (e.g., the Z direction) to form one or more first holes 404. The semiconductor substrate 402 has two ends along the Z direction. In some embodiments, the two ends of the semiconductor substrate 402 may be doped with an N+ type dopant (e.g., phosphorus (P) or arsenic (As)) or a P-type dopant (e.g., boron (B) or gallium (Ga)) at a desired doping level to form a first terminal structure 406 and a second terminal structure 408. In some embodiments, the semiconductor substrate 402 may include a semiconductor body 410 located between the two terminal structures 406 and 408, wherein the semiconductor body 410 may be doped with a dopant. The dopant of the semiconductor body 410 is different from the dopant of the terminal structures 406 and 408. In some embodiments, the terminal structures 406 and 408 may be doped with N+ type dopant, and the semiconductor body may be doped with P-type dopant. In some embodiments, terminal structures 406 and 408 may be doped with P-type dopant, and the semiconductor body may be doped with N+ type dopant.

[0083] Figure 4B A semiconductor structure 400b is illustrated. The semiconductor structure 400b can be formed by depositing semiconductor material in one or more first vias 404 along the Z-direction to form a conductive structure 412, wherein the thickness of the semiconductor material along the Z-direction is no greater than the thickness of the semiconductor body 410. A portion of the semiconductor material diffuses into the semiconductor body 410 during the deposition process to form a conductive contact 414 between the conductive structure 412 and the semiconductor body 410 along the Z-direction. In some embodiments, the semiconductor structure 400b may include a dielectric body 416 stacked on top of the conductive structure 412 in a first trench. The dielectric body 416 is formed by filling the remaining portion of one or more first vias 404 with dielectric material to form one or more first filled vias 404. In some embodiments, the end 412-1 of the conductive structure 412 is farther from the surface of the semiconductor substrate 402 than the end 410-1 of the semiconductor body 410.

[0084] Figure 4C A semiconductor structure 400c is shown, which can be formed by etching one or more portions of a semiconductor substrate 402 along the Z-direction to form one or more second holes 418. The one or more second holes 418 and one or more first fill holes 404 are separated from each other along a horizontal direction perpendicular to the Z-direction (e.g., the X-direction). In some embodiments, the length of the one or more second holes 418 is greater than the length of the one or more first fill holes 404 along the Z-direction.

[0085] Figure 4D A semiconductor structure 400d is shown. The semiconductor structure 400d may include a gate structure 420. The gate structure can be formed by depositing a conductive material into one or more second vias 418 and filling the remainder of the second vias 418 with a dielectric material to form one or more second filled vias 418. In some embodiments, the end 420-1 of the gate structure 420 is further away from the first terminal structure 406 than the end 404-1 of the one or more first filled vias 404.

[0086] Figures 5A-5D This illustrates the manufacture of semiconductor devices (e.g., such as...). Figures 3C-3D An exemplary process of the semiconductor device 300-2 shown. Figures 5A-5D Cross-sectional views of exemplary semiconductor structures at various stages of the manufacturing process are shown.

[0087] like Figure 5A As shown, a semiconductor structure 500a is formed by etching one or more portions of a semiconductor substrate 502 along a vertical direction (e.g., the Z direction) to form one or more first holes 504. The semiconductor substrate 502 has two ends along the Z direction. In some embodiments, the two ends of the semiconductor substrate 502 may be doped with an N+ type dopant (e.g., phosphorus (P) or arsenic (As)) or a P type dopant (e.g., boron (B) or gallium (Ga)) at a desired doping level to form a first terminal structure 506 and a second terminal structure 508. In some embodiments, the semiconductor substrate 502 may include a semiconductor body 510 located between the two terminal structures 506 and 508, wherein the semiconductor body 510 may be doped with a dopant. The dopant of the semiconductor body 510 is different from the dopant of the terminal structures 506 and 508. In some embodiments, the terminal structures 506 and 508 may be doped with N+ type dopant, and the semiconductor body may be doped with P type dopant. In some embodiments, terminal structures 506 and 508 may be doped with P-type dopant, and the semiconductor body may be doped with N+ type dopant. Semiconductor structure 500a may include a dielectric sidewall 509, which is formed by coating a dielectric material on the sidewalls of one or more first holes 504 and etching through the bottom of the dielectric sidewall 509, wherein the bottom of the dielectric sidewall is connected to the semiconductor body 510 in the Z direction.

[0088] Figure 5B A semiconductor structure 500b is shown, which can be formed by implanting conductive ions into a semiconductor body at the bottom of one or more first holes 504 to form a conductive contact 514.

[0089] Figure 5CA semiconductor structure 500c is illustrated. The semiconductor structure 500c can be formed by depositing metal material in one or more first holes 504 on top of a conductive contact 514 along the Z-direction to form a conductive structure 512, wherein the thickness of the metal material along the Z-direction is no greater than the thickness of the semiconductor body 510. In some embodiments, the metal material and the conductive contact 514 form an ohmic contact. In some embodiments, the semiconductor structure 500c may include a dielectric body 516 stacked on top of the conductive structure 512 in a first trench. The dielectric body 516 is formed by filling the remaining portion of one or more first holes 504 with a dielectric material to form one or more first filled holes 504. In some embodiments, the end 512-1 of the conductive structure 512 is farther from the surface of the semiconductor substrate 502 than the end 510-1 of the semiconductor body 510.

[0090] Figure 5D A semiconductor structure 500d is illustrated. The semiconductor structure 500d can be formed by etching one or more portions of a semiconductor substrate 502 along the Z-direction to form one or more second holes 518. The one or more second holes 518 and one or more first fill holes 504 are separated from each other along a horizontal direction perpendicular to the Z-direction (e.g., the X-direction). In some embodiments, the length of the one or more second holes 518 along the Z-direction is greater than the length of the one or more first fill holes 504. The semiconductor structure 500d may include a gate structure 520. The gate structure can be formed by depositing a conductive material into the one or more second holes 518 and filling the remaining portions of the second holes 518 with a dielectric material to form one or more second fill holes 518. In some embodiments, the end 520-1 of the gate structure 520 is farther from the first terminal structure 506 than the end 504-1 of the one or more first fill holes 504.

[0091] Figures 6A-6B A perspective view of an exemplary 3D semiconductor device 600 is shown. The 3D semiconductor device 600 may be... Figure 2 3D semiconductor device 200 or Figure 1 3D semiconductor device 100 or in Figure 1 The structure of the intermediate manufacturing process of the 3D semiconductor device 100.

[0092] like Figures 6A-6B As shown, the semiconductor 600 may include a plurality of memory cells 602. The memory cells 602 may be connected to... Figure 1 The memory cell 124 of the semiconductor device 100 Figure 2 The memory cell 202 of the semiconductor device 200 and Figures 3A-3DThe memory cells 302 of the semiconductor device 300-1 are similar to or identical to those of the memory cell 302. Each memory cell 602 may include a vertical transistor 604 (e.g., Figure 1 Vertical transistor 126 Figure 2 Vertical transistor 204 or Figures 3A-3D A DRAM memory cell with a vertical transistor 604. The vertical transistor 604 may include a semiconductor body 608 (e.g., Figure 1 Semiconductor body 130, Figure 2 Semiconductor body 206 or Figures 3A-3D The semiconductor body 308), the first terminal structure 610 (e.g., Figure 1 First terminal structure 156 Figure 2 First terminal structure 208 or Figures 3A-3D First terminal structure 310), second terminal structure 612 (e.g., Figure 1 The second terminal structure 158 Figure 2 The second terminal structure 210 or Figures 3A-3D The second terminal structure 312) and the gate structure 614 (e.g., Figure 1 Gate structure 136 Figure 2 Gate structure 212 or Figures 3A-3D (Gate structure 314). In some embodiments, the semiconductor device 600 may include a conductive structure 616 located between vertical transistors 304 of two adjacent memory cells 602. In some embodiments, the conductive structure 316 is connected to the semiconductor body 608 of the vertical transistors 604 of the two adjacent memory cells 602. In some embodiments, the conductive structure 616 is connected to... Figure 1 The conductive structure 160 of the semiconductor 100 or Figure 2 The conductor structure 214 of semiconductor 200 is similar to or the same.

[0093] In some embodiments, when the storage cell 602 is configured to store a first programming level, the first leakage current from the first terminal structure 610 ranges from 1 × 10⁻⁶. -18 A and 1×10 -16 Between A, and the second leakage current from the second terminal structure 612 is less than 5 × 10 -15 A. In some embodiments, when the storage cell 602 is configured to store a second programming level, the range of the first leakage current from the first terminal structure 610 is less than 1 × 10⁻⁶. -14 A, and the second leakage current from the second terminal structure 612 is between 1×10 -18 A and 1×10 -16 Between A.

[0094] Figure 7A flowchart of an exemplary process 700 is shown. Process 700 can be performed to form a semiconductor device (e.g., Figures 3A-3B The semiconductor device 300-1 shown or Figures 3C-3D The semiconductor device shown is 300-2. (See reference 300-2). Figures 4A-4D or Figures 5A-5D To describe process 700. Process 700 may include forming Figures 4A-4D or Figures 5A-5D This refers to one or more steps in the manufacturing process of a semiconductor structure. It should be understood that the operations shown in process 700 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 7 The different sequences shown will be executed.

[0095] At operation 702, a semiconductor structure is formed (e.g., Figure 4D Semiconductor structure 400d or Figure 5D The semiconductor structure 500d). The semiconductor structure includes a semiconductor substrate (e.g., Figure 4A Semiconductor substrate 402 or Figure 5A Multiple memory cells (e.g., in the semiconductor substrate 502) in the semiconductor substrate 502 Figure 1 Storage unit 124 in Figure 2 storage units or Figures 3A-3D The storage cell 302 in the plurality of storage cells includes a transistor (e.g., Figure 1 Vertical transistor 126 in Figure 2 Vertical transistor 204 or Figures 3A-3D The vertical transistor 304 in the middle), the transistor has a first trench structure (e.g., Figure 4D One or more second filling holes 418 or Figure 5D A gate structure extending along a first direction (e.g., the Z direction) in one or more second filling holes 518. Figure 4D Gate structure 420 or Figure 5D (Gate structure 520 in the middle).

[0096] In operation 704, in the first memory cell ( Figure 1 The first storage cell 124a) and the second storage cell (e.g., Figure 1 The second trench structure between the transistors in the second memory cell 124b (e.g., Figure 4B One or more first filling holes 404 or Figure 5B Conductive structures are formed in one or more first filling holes 504 (e.g., Figure 4B Conductive structure 412 or Figure 5CThe conductive structure 512 in the first and second memory cells has corresponding first terminal structures (e.g., Figure 4A The first terminal structure 406 or Figure 5A The first terminal structure 506 in the same semiconductor body (e.g., Figure 4A Semiconductor body 410 or Figure 5A The semiconductor body 510 in the middle) and the same second terminal structure (e.g., Figure 4A The second terminal structure 408 or Figure 5A The second terminal structure 508 in the first memory cell and the semiconductor body of the transistor of the first memory cell and the second memory cell are in contact, and the first trench structure has a longer length than the second trench structure along the first direction.

[0097] In some embodiments, the semiconductor body of the memory cell includes opposite ends along a first direction and opposite sides along a second direction perpendicular to the first direction (e.g., the X direction), wherein a first terminal structure and a second terminal structure are located at opposite ends of the semiconductor body, and wherein a first trench structure and a second trench structure are located at opposite sides of the semiconductor body.

[0098] In some embodiments, forming the conductive structure includes etching the semiconductor substrate along a first direction to form trenches that contact the semiconductor body (e.g., Figure 4C One or more second holes 418 in the trench; and depositing semiconductor material in the trench along a first direction, wherein the thickness of the semiconductor material along the first direction is not greater than the thickness of the semiconductor body.

[0099] In some implementations, a portion of the semiconductor material diffuses into the semiconductor body to form a conductive contact between the semiconductor material and the semiconductor body (e.g., Figure 4B The conductive contact 414, wherein the conductive structure contacts the portion of the semiconductor body that is closer to the second terminal structure than the first terminal structure along the first direction.

[0100] In some embodiments, forming the conductive structure includes: etching a semiconductor substrate along a first direction to form a trench that contacts the semiconductor body (e.g., Figure 5D One or more second holes 518 in the trench); conductive ions are implanted into the semiconductor body at the bottom of the trench to form conductive contacts (e.g., Figure 5C The conductive contact 514); and depositing a metal material on the conductive contact in the trench to form a conductive structure, wherein the thickness of the metal material along the first direction is not greater than the thickness of the semiconductor body.

[0101] In some embodiments, process 700 further includes: forming a first trench structure including a gate structure, wherein the first trench structure and the second trench structure are located at different positions along a second direction perpendicular to the first direction, and wherein the gate structure extends in the first trench structure along the first direction, and wherein, along the first direction, the end of the gate structure of the vertical transistor of the memory cell is farther from the first terminal structure of the vertical transistor of the memory cell than the end of the second trench structure.

[0102] In some embodiments, the first trench structure and the second trench structure extend along a second direction perpendicular to the first direction (e.g., the Y direction), and the method further includes: forming one or more third trench structures that extend through the semiconductor substrate along the first direction and are spaced apart from each other along a third third direction perpendicular to the first and second directions (e.g., Figure 2 One or more third trench structures 220 in the process.

[0103] In some embodiments, one or more third trench structures are filled with an isolation material, wherein the first trench structure includes an isolation material filled around the gate structure, and the second trench structure includes an isolation material stacked on the conductive structure along a first direction.

[0104] In some embodiments, process 700 further includes: forming a coupled output structure (e.g., Figure 2 The coupling output structure 218 in the second trench structure is coupled to the interconnect structure through the coupling output structure.

[0105] Figure 8 This diagram illustrates a system 800 having one or more semiconductor devices (e.g., memory devices) according to one or more embodiments of the present disclosure. System 800 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 8 As shown, system 800 may include a host device 808 and a memory system 802 having one or more 3D memory devices 804 and a memory controller 806. The host device 808 may include a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host device 808 may be configured to send data to or receive data from one or more 3D memory devices 804.

[0106] 3D memory device 804 can be any 3D memory device disclosed herein, such as Figure 1 , Figure 2 , Figures 3A-3B , Figures 3C-3D , Figures 4A-4D , Figures 5A-5B or Figures 6A-6B The 3D memory device 804 is depicted in the present disclosure. In some embodiments, the 3D memory device 804 includes DRAM memory. A memory controller 806 (also referred to as controller circuitry) is coupled to the 3D memory device 804 and the host device 808. Consistent with embodiments of this disclosure, the 3D memory device 804 may include a plurality of conductive interconnects that pass through a cover layer and contact conductive pads in a conductive pad layer, and the memory controller 806 may be coupled to the 3D memory device 804 through at least one of the plurality of conductive interconnects. The memory controller 806 is configured to control the 3D memory device 804. For example, the memory controller 806 may be configured to operate a plurality of channel structures via word lines. The memory controller 806 may manage data stored in the 3D memory device 804 and communicate with the host device 808.

[0107] In some embodiments, the memory controller 806 is designed / configured to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 806 is designed / configured to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays. The memory controller 806 may be configured to control the operation of the 3D memory device 804, such as read, erase, and program (or write) operations. The memory controller 806 may also be configured to manage various functions regarding data stored or to be stored in the 3D memory device 804, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 806 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 804. The memory controller 806 can also perform any other appropriate functions, such as formatting the 3D memory device 804.

[0108] The memory controller 806 can communicate with external devices (e.g., host device 808) according to a specific communication protocol. For example, the memory controller 806 can communicate with external devices through at least one of a variety of interface protocols, such as: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, High Speed ​​PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0109] The memory controller 806 and one or more 3D memory devices 804 can be integrated into various types of memory devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 802 can be implemented and packaged into different types of end electronic products. Figure 8 In one example shown, the memory controller 806 and the single 3D memory device 804 can be integrated into the memory card 802. The memory card 802 may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, Memory Sticks, Multimedia Cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc.

[0110] The embodiments, actions, and operations of the subject matter described in this disclosure can be implemented in digital electronic circuits, tangibly embodied computer software or firmware, computer hardware (including the structures disclosed in this disclosure and their structural equivalents), or combinations thereof. Embodiments of the subject matter described in this disclosure can be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier for execution by or control of the operation of a data processing device. The carrier can be a tangible, non-transitory computer storage medium. Alternatively or additionally, the carrier can be an artificially generated propagation signal, such as a machine-generated electrical signal, optical signal, or electromagnetic signal, generated to encode information for transmission to a suitable receiving device for execution by the data processing device. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination thereof, or a portion thereof. The computer storage medium is not a propagation signal.

[0111] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some implementations," etc., in this disclosure indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment must include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other implementations is within the knowledge of those skilled in the art.

[0112] Generally, terms can be understood at least partly from their usage in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partly on the context, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage. Additionally, again depending at least partly on the context, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described.

[0113] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” not only means “directly on something,” but also includes the meaning of “on something” with an intermediate feature or layer between them. Furthermore, “above” or “on top of” not only means “above something” or “on top of something,” but can also include the meaning of “above something” or “on top of something” without an intermediate feature or layer between them (i.e., directly on something).

[0114] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature and another (or more) elements or features as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the apparatus during use or process steps. The apparatus may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0115] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore, unless otherwise stated, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite to the top surface, and therefore, the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

[0116] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper overlay structure, or may have a range smaller than that of the lower or upper overlay structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure having a thickness smaller than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnect lines, and / or vertical interconnect channels (VIAs) are formed) and one or more dielectric layers.

[0117] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter set for a component or process step during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. As used herein, the range of values ​​may be due to minor variations in manufacturing processes or tolerances. As used herein, the term "about" indicates the value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" may indicate the value of a given quantity that varies within, for example, 10-30% of that value (e.g., ±10%, ±20%, or ±30% of the value).

[0118] In this disclosure, the terms "horizontal / horizontally / laterally" mean nominally parallel to the lateral surface of the substrate, and the term "vertical / vertically" means nominally perpendicular to the lateral surface of the substrate.

[0119] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having strings of vertically oriented memory cell transistors (referred to herein as “memory strings”, such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in a vertical direction relative to the substrate.

[0120] This disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features can be in direct contact, and may also include embodiments where an additional feature can be formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or constructions discussed.

[0121] The descriptions of specific implementation methods described above can be easily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance provided herein, such adjustments and modifications are intended to fall within the meaning and scope of equivalents of the disclosed implementation methods.

[0122] While this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of the claims as defined by the claims themselves, but rather as descriptions of features that may be implemented for specific embodiments of a particular invention. In the context of individual embodiments, certain features described in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed in this way, one or more features from the claimed combination may be removed from the combination in some cases, and the claims may be for sub-combinations or variations thereof.

[0123] Similarly, although operations are depicted in the accompanying drawings in a specific order and referenced in the claims, this should not be construed as requiring the operations to be performed in the specific order or sequence shown, or requiring all shown operations to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0124] Specific embodiments of the subject matter have been described. Other embodiments are also within the scope of the following claims. For example, the actions cited in the claims can be performed in a different order and still achieve the desired result. As an example, the process depicted in the drawings does not necessarily require the specific order or sequence shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

[0125] The breadth and scope of this disclosure should not be limited to any of the embodiments described above, but should be defined solely by the following claims and their equivalents.

Claims

1. A semiconductor device, comprising: A plurality of memory cells, wherein a memory cell among the plurality of memory cells includes a transistor, the transistor having a gate structure extending along a first direction in a first trench structure; and A conductive structure is located in a second trench structure between transistors of a first memory cell and a second memory cell, wherein the transistors of the first memory cell and the second memory cell have corresponding first terminal structures, identical semiconductor bodies, and identical second terminal structures, and wherein the conductive structure is in contact with the semiconductor bodies of the transistors of the first memory cell and the second memory cell. Along the first direction, the first trench structure has a longer length than the second trench structure.

2. The semiconductor device according to claim 1, wherein, Along the first direction, the end of the gate structure of the transistor of the memory cell is farther from the first terminal structure of the transistor of the memory cell than the end of the second trench structure.

3. The semiconductor device according to claim 1 or 2, wherein, Along a second direction perpendicular to the first direction, the length of the first trench structure is greater than the length of the second trench structure.

4. The semiconductor device according to any one of claims 1 to 3, wherein, The semiconductor body of the memory cell includes opposing ends along the first direction. Wherein, the first terminal structure and the second terminal structure are respectively located at the opposite ends of the semiconductor body of the memory cell, and The second trench structure is located between two adjacent first trench structures along a second direction perpendicular to the first direction.

5. The semiconductor device according to any one of claims 1 to 4, wherein, The semiconductor device includes a third memory cell, wherein the first memory cell is located between the second memory cell and the third memory cell along a second direction perpendicular to the first direction, and The first trench structure includes two gate structures of two transistors in the first memory cell and the third memory cell, wherein the two gate structures are separated by an insulating material filled in the first trench structure.

6. The semiconductor device according to any one of claims 1 to 5, wherein, The conductive structure is isolated from the first terminal structure by a dielectric material along a second direction perpendicular to the first direction.

7. The semiconductor device according to any one of claims 1 to 6, wherein, The conductive structure includes a semiconductor material, and The second trench structure further includes a dielectric body stacked on the conductive structure along the first direction.

8. The semiconductor device according to any one of claims 1 to 6, wherein, The conductive structure includes a metallic material. The second trench structure further includes a dielectric body stacked on the conductive structure along the first direction, and The semiconductor device further includes an ohmic contact between the metal material and the semiconductor body.

9. The semiconductor device according to any one of claims 1 to 8, wherein, The conductive structure in the second trench structure is coupled to the interconnect structure through the coupling output structure.

10. The semiconductor device according to any one of claims 1 to 9, wherein, The first trench structure and the second trench structure extend along a second direction perpendicular to the first direction, and The semiconductor device further includes one or more third trench structures that extend through the semiconductor device along the first direction and are spaced apart from each other along a third direction perpendicular to the first direction and the second direction.

11. The semiconductor device according to any one of claims 1 to 10, wherein, The one or more third trench structures are filled with an isolation material, wherein the first trench structure includes the isolation material filled around the gate structure, and the second trench structure includes the isolation material stacked on the conductive structure along the first direction.

12. A method of forming a semiconductor device, the method comprising: A plurality of memory cells are formed in a semiconductor substrate, wherein a memory cell in the plurality of memory cells includes a transistor, the transistor having a gate structure extending along a first direction in a first trench structure; and A conductive structure is formed in a second trench structure between the transistors of the first and second memory cells, wherein the transistors of the first and second memory cells have corresponding first terminal structures, identical semiconductor bodies, and identical second terminal structures, and wherein the conductive structure is in contact with the semiconductor bodies of the transistors of the first and second memory cells. Along the first direction, the first trench structure has a longer length than the second trench structure.

13. The method according to claim 12, wherein, The semiconductor body of the memory cell includes opposing ends along the first direction. Wherein, the first terminal structure and the second terminal structure are respectively located at the opposite ends of the semiconductor body of the memory cell, and The second trench structure is located between two adjacent first trench structures along a second direction perpendicular to the first direction.

14. The method according to claim 12 or 13, wherein, Forming the conductive structure includes: Etching the semiconductor substrate along the first direction to form trenches; and Semiconductor material is deposited in the trench along the first direction, wherein the length of the semiconductor material along the first direction is not greater than the length of the semiconductor body.

15. The method according to any one of claims 12 to 14, wherein, A portion of the semiconductor material diffuses into the semiconductor body to form a conductive contact between the semiconductor material and the semiconductor body, wherein the conductive structure contacts a portion of the semiconductor body that is closer to the second terminal structure than the first terminal structure along the first direction.

16. The method according to claim 12 or 13, wherein, Forming the conductive structure includes: The semiconductor substrate is etched along the first direction to form a trench; Conductive ions are implanted into the semiconductor body at the bottom of the trench to form conductive contacts; and Metallic material is deposited on the conductive contacts in the trench to form the conductive structure. Wherein, along the first direction, the length of the metal material is not greater than the length of the semiconductor body.

17. The method according to any one of claims 12 to 16, further comprising: A first trench structure including the gate structure is formed, wherein the first trench structure and the second trench structure are located at different positions along a second direction perpendicular to the first direction; and The gate structure extends in the first trench structure along the first direction, and along the first direction, the end of the gate structure of the transistor of the memory cell is farther from the first terminal structure of the transistor of the memory cell than the end of the second trench structure.

18. The method according to any one of claims 12 to 17, wherein, The first trench structure and the second trench structure extend along a second direction perpendicular to the first direction; and The method further includes: One or more third trench structures are formed that extend through the semiconductor substrate along the first direction and are spaced apart from each other along a third direction perpendicular to the first and second directions.

19. The method according to any one of claims 12 to 18, further comprising: A coupling output structure is formed, wherein the conductive structure in the second trench structure is coupled to the interconnect structure through the coupling output structure.

20. A memory system, comprising: Memory devices; as well as A memory controller, coupled to and configured to control the memory device. The memory device includes: A plurality of memory cells, wherein a memory cell among the plurality of memory cells includes a transistor, the transistor having a gate structure extending along a first direction in a first trench structure; and A conductive structure is located in a second trench structure between transistors of a first memory cell and a second memory cell, wherein the transistors of the first memory cell and the second memory cell have corresponding first terminal structures, identical semiconductor bodies, and identical second terminal structures, and wherein the conductive structure is in contact with the semiconductor bodies of the transistors of the first memory cell and the second memory cell. Along the first direction, the first trench structure has a longer length than the second trench structure.

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