BFLOAT16 Scaling and / or Simplifying Instructions

Abstract

The present disclosure generally relates to BFLOAT16 scaling and / or simplifying instructions. Techniques for scaling and simplification of BF16 data elements are described. An exemplary instruction includes fields to: an opcode, an identification of a location of a first packed data source operand, an identification of a location of a second packed data source operand, and an identification of a packed data destination operand, the opcode is to instruct the execution circuitry to perform a floating-point scaling operation of a BF16 data element of a first packed data source by multiplying the BF16 data element of the first packed data source by a power of 2, where a value of an exponent of the power of 2 is a rounding-down value of a BF16 data element of a second packed data source and a value of an exponent of the power of 2 is a rounding-down value of the BF16 data element of the second packed data source. And storing a result of the floating point scaling operation into a corresponding data element position of the packed data destination operand.

Description

Technical Field

[0001] This disclosure generally relates to the BFLOAT16 scaling and / or simplification instructions. Background Technology

[0002] In recent years, fused-multiply-accumulate (FMA) units, which combine lower-precision multiplication with higher-precision accumulation, have proven useful in machine learning / artificial intelligence applications, particularly in training deep neural networks, due to their extremely high computational intensity. Compared to classic IEEE-754 32-bit (FP32) and 64-bit (FP64) arithmetic, this reduced-precision arithmetic can naturally be sped up disproportionately by its shortened width. Summary of the Invention

[0003] According to a first embodiment of this disclosure, an apparatus is provided, comprising: a decoding device for decoding an instance of a single instruction, the single instruction including fields for: an opcode, an identifier of the location of a first compressed data source operation object, an identifier of the location of a second compressed data source operation object, and an identifier of a compressed data destination operation object, wherein the opcode instructs an execution device to perform a floating-point scaling operation on each data element location of the compressed data source operation object by multiplying the BF16 data element of the first compressed data source operation object by a power of 2, wherein the exponent of the power of 2 is the floor value of the BF16 data element of the second compressed data source operation object, and the result of the floating-point scaling operation is stored in the corresponding data element location of the compressed data destination operation object; and the execution device for executing the decoded instruction according to the opcode.

[0004] According to a second embodiment of this disclosure, a system is provided, comprising: a memory for storing instances of a single instruction; a decoding device for decoding instances of the single instruction, the single instruction including fields for: an opcode, an identifier of the location of a first compressed data source operation object, an identifier of the location of a second compressed data source operation object, and an identifier of a compressed data destination operation object, wherein the opcode instructs an execution device to perform a floating-point scaling operation on each data element location of the compressed data source operation object by multiplying the BF16 data element of the first compressed data source operation object by a power of 2, wherein the exponent of the power of 2 is the floor value of the BF16 data element of the second compressed data source operation object, and the result of the floating-point scaling operation is stored in the corresponding data element location of the compressed data destination operation object; and the execution device for executing the decoded instruction according to the opcode.

[0005] According to a third embodiment of this disclosure, a non-transitory machine-readable medium is provided, which stores at least an instance of a specific single instruction, wherein the instance of the specific single instruction is processed by a processor by executing a method comprising: decoding the instance of the single instruction, the single instruction including fields for: an opcode, an identifier of the location of a first compressed data source operation object, an identifier of the location of a second compressed data source operation object, and an identifier of a compressed data destination operation object, wherein the opcode is used to instruct an execution module to perform a floating-point scaling operation on each data element location of the compressed data source operation object by multiplying the BF16 data element of the first compressed data source operation object by a power of 2, wherein the exponent of the power of 2 is the floor value of the BF16 data element of the second compressed data source operation object, and storing the result of the floating-point scaling operation in the corresponding data element location of the compressed data destination operation object; and executing the decoded instruction according to the opcode.

[0006] According to a fourth embodiment of this disclosure, a method is provided, comprising: converting a specific single instruction from a first instruction set architecture into one or more instructions of a different second instruction set architecture, the specific single instruction including fields for: an opcode, an identifier of the location of a first compressed data source operation object, an identifier of the location of a second compressed data source operation object, and an identifier of a compressed data destination operation object, wherein the opcode is used to instruct an execution module to perform a floating-point scaling operation on each data element location of the compressed data source operation object by multiplying the BF16 data element of the first compressed data source operation object by a power of 2, wherein the exponent of the power of 2 is the floor value of the BF16 data element of the second compressed data source operation object, and storing the result of the floating-point scaling operation in the corresponding data element location of the compressed data destination operation object; decoding the one or more instructions of the different second instruction set architecture; and executing the decoded one or more instructions of the different second instruction set architecture. Attached Figure Description

[0007] Various embodiments according to this disclosure will be described with reference to the accompanying drawings, in which:

[0008] Figure 1 Different floating-point representation formats are shown.

[0009] Figure 2 An exemplary execution of instructions for calculating the scaling of BF16 data elements is shown.

[0010] Figure 3An embodiment of a method is shown that is executed by a processor to process instructions for calculating the scaling of BF16 data elements.

[0011] Figure 4 An exemplary embodiment of pseudocode representing the execution and format of instructions for calculating the scaling of BF16 data elements is shown.

[0012] Figure 5 An example of the execution of instructions for extracting reduced arguments of BF16 data elements according to some embodiments is shown.

[0013] Figure 6 An embodiment of an exemplary method is shown, according to some embodiments, in which a processor executes instructions to process simplified parameters for extracting BF16 data elements.

[0014] Figure 7 An exemplary embodiment of pseudocode is shown, representing the execution and format of instructions for extracting simplified parameters of BF16 data elements.

[0015] Figure 8 An example of the execution of the rounding BF16 data element instruction according to some embodiments is shown.

[0016] Figure 9 An embodiment of an exemplary method is shown, according to some embodiments, of an instruction executed by a processor to process BF16 data elements for rounding.

[0017] Figure 10 An exemplary embodiment of pseudocode representing the execution and format of a BF16 data element rounding instruction is shown.

[0018] Figure 11 An embodiment of hardware that processes instructions such as VSCALEFNEPBF16, VREDUCENEPBF16 and / or VRNDSCALENEPBF16 is shown.

[0019] Figure 12 An embodiment of an exemplary system is shown.

[0020] Figure 13 A block diagram of an embodiment of a processor is shown, which may have more than one core, may have an integrated memory controller, and may have integrated graphics.

[0021] Figure 14(A) is a block diagram illustrating both an exemplary ordered pipeline and an exemplary register renaming, out-of-order issue / execution pipeline according to an embodiment of the present invention.

[0022] Figure 14(B) is a block diagram illustrating both an exemplary embodiment of an ordered architecture core to be included in a processor according to an embodiment of the present invention and an exemplary register renaming, out-of-order issue / execute architecture core.

[0023] Figure 15 Embodiments of one or more execution unit circuits are shown, such as the one or more execution unit circuits in FIG14(B).

[0024] Figure 16 This is a block diagram of a register architecture according to some embodiments.

[0025] Figure 17 An example of the instruction format is shown.

[0026] Figure 18 An example of an addressing field is shown.

[0027] Figure 19 An example of the first prefix is ​​shown.

[0028] Figures 20(A) to 20(D) An example of how to use the R, X, and B fields of the first prefix 1701(A) is shown.

[0029] Figures 21(A) to 21(B) An example of the second prefix is ​​shown.

[0030] Figure 22 An example of the third prefix is ​​shown.

[0031] Figure 23 A block diagram is shown that compares an embodiment of the present invention with the use of a software instruction converter to convert binary instructions in a source instruction set into binary instructions in a target instruction set. Detailed Implementation

[0032] This disclosure relates to methods, apparatus, systems, and nontransitory computer-readable storage media for calculating instructions for scaling, simplifying parameters, or rounding BF16 data elements.

[0033] BF16 is gaining increasing attention because it works well in machine learning algorithms, especially in deep learning training. Figure 1Different floating-point representation formats are shown. In this figure, these formats are little-endian; however, in some embodiments, big-endian formats are used. FP32 format 101 has a sign bit (S), an 8-bit exponent, and a 23-bit fraction (a 24-bit mantissa using implicit bits). FP16 format 103 has a sign bit (S), a 5-bit exponent, and a 10-bit fraction. BF16 format 105 has a sign bit (S), an 8-bit exponent, and a 7-bit fraction.

[0034] Compared to the 16-bit (FP16) variant standardized by IEEE 754, BF16 makes no compromise in range when compared to FP32. FP32 numbers have an 8-bit exponent and a 24-bit mantissa (including an implicit one). BF16 cuts 16 bits from the 24-bit FP32 mantissa to create a 16-bit floating-point data type. In contrast, FP16 roughly halves the FP32 mantissa to 10 dominant bits and simplifies the exponent to 5 bits to accommodate the 16-bit data type envelope.

[0035] While BF16 offers lower accuracy than FP16, it is generally better suited for supporting deep learning tasks. Due to its limited range, FP16 is insufficient for out-of-the-box deep learning training. BF16 does not have this problem, and its limited accuracy can actually help generalize learned weights in neural network training tasks. In other words, the lower accuracy can be seen as providing built-in regularization properties.

[0036] This document details instructions for operating on BF16 source data elements and their supported embodiments. In some embodiments, execution of a single instruction causes a floating-point scaling of a compressed BF16 floating-point value in a first source operand by multiplying the compressed BF16 floating-point value in the first source operand by a power of 2 (the exponent being the BF16 value in the second source operand), and the floating-point scaling is stored in a destination operand. In some embodiments, execution of a single instruction causes the extraction of a simplified parameter of the BF16 value in the first source operand according to the number of bits specified in the operand or immediate value, and the simplified parameter is placed in the destination operand. In some embodiments, execution of a single instruction causes the rounding of BF16 values ​​in the source operand according to the rounding mode specified in the operand or immediate value, and these values ​​are placed in the destination operand.

[0037] In some embodiments, the single instruction is translated from a first instruction set architecture (ISA) into one or more instructions of a second ISA, and the execution of one or more instructions of the second ISA performs those computations.

[0038] In some embodiments, one or more of the instructions are defined, for example, that their execution would treat irregular inputs or outputs as zero, support any rounding mode, and / or report or suppress floating-point numeric flags.

[0039] Figure 2 An exemplary execution of an instruction to calculate the scaling of a BF16 data element is shown. Although this diagram uses a least-bit-major format, the principles discussed herein are also applicable in a most-bit-major format. Specifically, the execution of this instruction causes the floating-point scaling of the compressed BF16 floating-point value in the first source operand to be calculated by multiplying the compressed BF16 floating-point value in the first source operand by a power of 2 of the BF16 in the second source operand, and then storing it in the destination operand.

[0040] The instruction for calculating the scaling of a BF16 data element (illustrated here using the exemplary opcode mnemonic of VSCALEFNEPBF) includes one or more fields to define the opcode of the instruction, one or more fields to reference or indicate the first and second compaction data sources (e.g., registers or memory locations), and / or one or more fields to reference or indicate the compaction data destination (e.g., registers or memory locations). In some embodiments, the instruction also includes one or more fields to reference or indicate a write mask or predicate register used to store write mask or predicate values, as described below.

[0041] One embodiment of the format of the instruction for scaling BF16 data elements is VSCALEFNEPBF DST{k}, SRC1, SRC2. In some embodiments, VSCALEFNEPBF is the opcode mnemonic for this instruction. DST is the field used for the compressed data destination register operand. SRC1 and SRC2 are one or more fields for the source, such as a compressed data register and / or memory. The source operand and destination operand can have one or more sizes, such as 128 bits, 256 bits, 512 bits, etc. {k} is used when a write mask or predicate is used.

[0042] In this example, the first compressed data source 201 comprises eight compressed data elements, each in BF16 format. The first compressed data source 201 can be a register or a memory location. The second compressed data source 203 comprises eight compressed data elements, each in BF16 format. The second compressed data source 203 can be a register or a memory location.

[0043] Compacted data sources 201 and 203 are fed into execution circuitry 209 for manipulation to calculate floating-point scaling. In some embodiments, execution circuitry 209 calculates scaling using scaling / simplification circuitry 211 according to the following formula: Destination = Source 1 * 2( floor( (Source 2). In some embodiments, this execution of the instruction uses rounding to the nearest (even) rounding mode. In some embodiments, the output non-normal number is always flushed to zero, and the input non-normal number is always treated as zero.

[0044] Compacted data destination 231 is written to store the resulting scaling value in the compacted data element corresponding to compacted data source 201. In some embodiments, when the instruction requires the use of a predicate or write mask, write mask (or predicate) register 223 specifies how to use write mask circuitry 221 to store and / or zero out the resulting scaling value.

[0045] Figure 3 An embodiment of a method is shown in which a processor executes instructions to process the scaling of BF16 data elements. This method is performed, for example, by a processor core as shown in Figure 14(B), pipelines as detailed below, etc.

[0046] At 301, an instruction is obtained, which has fields for the following: opcode, identifier of the location of the first compressed data source operation object, identifier of the location of the second compressed data source operation object, and identifier of the compressed data destination operation object, wherein the opcode is used to instruct the execution circuit to perform a floating-point scaling operation on each data element location of the compressed data source operation object by multiplying the data element of the first compressed data source by a power of 2, wherein the exponent of the power of 2 is the floor value of the data element of the second compressed data source, and the result of the floating-point scaling operation is stored in the corresponding data element location of the compressed data destination operation object.

[0047] In some embodiments, at 303, the instructions of the acquired first ISA are translated into one or more instructions of a different second ISA. When executed, the one or more instructions of the different second ISA provide the same result as if the acquired instructions had been executed. Note that this translation can be performed using hardware, software, or a combination thereof.

[0048] At 305, the instruction (or one or more translated instructions) is decoded. This decoding allows the generation of one or more micro-operations to be executed.

[0049] At 307, retrieve the data value associated with the source operand of the decoded instruction. For example, if the source operand is stored in memory, retrieve the data from the indicated memory location.

[0050] At 309, the decoded instruction(s) are executed by the execution circuit (hardware), such as the execution circuit detailed herein. For each data element position of the compressed data source operation object, the execution circuit performs a floating-point scaling operation on that data element by multiplying the data element of the first compressed data source by a power of 2, where the exponent of the power of 2 is the floor value of the data element of the second compressed data source, and stores the result of the floating-point scaling operation in the corresponding data element position of the compressed data destination operation object.

[0051] In some embodiments, at 311, the instruction is submitted or withdrawn.

[0052] Figure 4 An exemplary embodiment of pseudocode representing the execution and format of instructions for calculating the scaling of BF16 data elements is shown. Note that EVEX.b corresponds to b in prefix 1701(C). The comments DAZ, FTZ, RNE, and SAE refer to support for flush-to-zero (FTZ), denormals-are-zero (DAZ), suppress all exceptions (SAE), and round-to-even (RNE) rounding.

[0053] Figure 5An example of the execution of an instruction to extract simplification parameters of a BF16 data element is illustrated according to some embodiments. Although this figure adopts a least-bit-first format, the principles discussed herein are also applicable in a most-bit-first format. The instruction to extract simplification parameters of a BF16 data element (illustrated here with the exemplary opcode mnemonic of VREDUCENEPBF16) includes one or more fields to define the opcode of the instruction, one or more fields to reference or indicate a BF16 simplification data source (e.g., a register or memory location), one or more fields to indicate a scaling value (e.g., a portion of an immediate value or a scaling value stored in a register or memory location), and / or one or more fields to reference or indicate a simplification data destination (e.g., a register or memory location). In some embodiments, the instruction also includes one or more fields to reference or indicate a write mask or predicate register used to store write mask or predicate values, as described below.

[0054] One embodiment of the instruction format for extracting simplified parameters from BF16 data elements is VREDUCENEPBF16 DST{k},SRC1 IMM8. In some embodiments, VREDUCENEPBF16 is the opcode mnemonic for this instruction. DST is a field used to compress the data destination register operand. SRC1 is one or more fields for the source, such as a compressed data register and / or memory. IMM8 refers to an immediate value. The source and destination operands can have one or more sizes, such as 128 bits, 256 bits, 512 bits, etc. {k} is used when a write mask or predicate is used.

[0055] In this example, the compressed data source 501 comprises eight compressed data elements, each in BF16 format. The compressed data source 501 can be a register or a memory location.

[0056] Compact data source 501 and immediate value 505 are fed into execution circuitry 509 for operation. Specifically, execution circuitry 509 (e.g., scaling / simplification circuitry 511) extracts simplification parameters of the BF16 data elements of compact data source 501 based on the scaling ratio provided by immediate value 505. In some embodiments, execution circuitry 509 calculates using scaling / simplification circuitry 511 according to the following formula: Destination = Source 1 - (ROUND(2 M *Source 1))*2 -M The scaling value M comes from the immediate number 505.

[0057] In some embodiments, this execution of the instruction uses a rounding mode to the nearest (even) number. In some embodiments, the output non-normal number is always flushed to zero, and the input non-normal number is always treated as zero.

[0058] Compacted data destination 531 is written to store the resulting simplified value in the compacted data element corresponding to compacted data source 501. In some embodiments, when the instruction requires the use of a predicate or write mask, the write mask (or predicate) register 523 specifies how to use the write mask circuit 521 to store and / or zero out the resulting BF16 formatted simplified value.

[0059] Figure 6 An embodiment of an exemplary method, according to some embodiments, is shown in which a processor executes instructions to process simplified parameters for extracting BF16 data elements. This method is performed, for example, by a processor core as shown in FIG14(B), pipelines detailed below, etc.

[0060] At 601, an instruction is obtained, which has fields for the following: opcode, identifier of the location of the compressed data source operation object, and identifier of the compressed data destination operation object, wherein the opcode is used to instruct the execution circuit to extract the simplification parameters of the data elements of the compressed data source 501 for each data element location of the compressed data source operation object using the scaling / simplification circuit 511 according to the number of bits specified in the immediate value 505, and to store the extracted simplification parameters in the corresponding data element location of the compressed data destination operation object 531.

[0061] In some embodiments, the instructions of the acquired first ISA are translated at 603 into one or more instructions of a different second ISA. When executed, the one or more instructions of the different second ISA provide the same result as if the acquired instructions had been executed. Note that this translation can be performed using hardware, software, or a combination thereof.

[0062] In step 605, the instruction (or one or more translated instructions) is decoded. This decoding allows the generation of one or more micro-operations to be executed.

[0063] At 607, the data value associated with the source operand of the decoded instruction is retrieved. For example, if the source operand is stored in memory, the data is retrieved from the indicated memory location.

[0064] In 609, the decoded instruction(s) are executed by the execution circuit (hardware), such as the execution circuit detailed herein. For each data element location of the compressed data source operation object, the execution circuit extracts the simplified parameters of the data element of the compressed data source according to the number of bits specified in the immediate value, and stores the extracted simplified parameters in the corresponding data element location of the compressed data destination operation object.

[0065] In some embodiments, at 611, the instruction is submitted or withdrawn.

[0066] Figure 7 An exemplary embodiment of pseudocode representing the execution and format of instructions for extracting simplified parameters of BF16 data elements is shown. Note that EVEX.b corresponds to b in prefix 1701(C). The comments DAZ, FTZ, RNE, and SAE refer to support for flush to zero (FTZ), nonnormal zero (DAZ), suppress all anomalies (SAE), and round to even (RNE) rounding.

[0067] Figure 8 An embodiment of the execution of a round BF16 data element instruction according to some embodiments is shown. Although this figure adopts a least-bit-first format, the principles discussed herein are also applicable in a most-bit-first format. A round BF16 data element instruction (shown herein as an exemplary opcode mnemonic for VRNDSCALENEPBF16) includes one or more fields to define the opcode of the instruction, one or more fields to reference or indicate a BF16 compaction data source (e.g., a register or memory location), one or more fields to indicate a rounding mode (e.g., a portion of an immediate number or a rounding mode stored in a register or memory location), and / or one or more fields to reference or indicate a compaction data destination (e.g., a register or memory location). In some embodiments, the instruction also includes one or more fields to reference or indicate a write mask or predicate register used to store write mask or predicate values, as described below.

[0068] One embodiment of the format for the BF16 data element rounding instruction is VRNDSCALENEPBF16DST{k},SRC1IMM. In some embodiments, VRNDSCALENEPBF16 is the opcode mnemonic for this instruction. DST is a field used to compress the data destination register operand. SRC1 is one or more fields for the source, such as a compressed data register, memory location, and / or a vector broadcast from a memory location. IMM refers to the immediate value encoding the rounding mode. The source operand and destination operand can have one or more sizes, such as 128 bits, 256 bits, 512 bits, etc. {k} is used when a write mask or predicate is used.

[0069] In this example, the compressed data source 801 comprises eight compressed data elements, each in BF16 format. The compressed data source 801 can be a register or a memory location.

[0070] The compressed data source 801 and the immediate value 805 are fed into the execution circuit 809 for operation. Specifically, the execution circuit 809 (e.g., scaling / simplification circuit 811) performs rounding on the BF16 data elements in the source operation object 801 according to the rounding mode specified by the immediate value 805. This rounding rounds the input to an integer value, adds the number of bits of the fraction specified by the immediate value (to be included in the result), to produce a result for each data element, and stores the result as a BF16 value in the destination 831. In some embodiments, this rounding is defined as destination = 2. -M Round to the nearest even integer (2) M *Source). M is set by an immediate value, such as bits 7:4 of an 8-bit immediate value. In some embodiments, the scaling / simplification circuit 811 of the execution circuit 809 performs this operation.

[0071] In some embodiments, if any data element is a signaling non-a-number (SNAN), it will be converted to a quiet not-a-number (QNaN). In some embodiments, this execution of the instruction uses rounding to the nearest (even) rounding mode. In some embodiments, the output non-normal number is always flushed to zero, and the input non-normal number is always treated as zero. The sign of the result of this instruction is preserved, including the sign of zero.

[0072] Compacted data destination 831 is written to store the resulting value in the compacted data element corresponding to compacted data source 801. In some embodiments, when an instruction requires the use of a predicate or write mask, write mask (or predicate) register 823 specifies how to use write mask circuitry 821 to store and / or zero out the resulting value.

[0073] Figure 9 An embodiment of an exemplary method is shown, according to some embodiments, in which a processor executes instructions to process BF16 data elements. This method is performed, for example, by a processor core as shown in FIG14(B), pipelines as detailed below, and the like.

[0074] At 901, an instruction is obtained, which has fields for the following: opcode, identifier of the location of the compressed data source operation object, indication of the rounding mode, and identifier of the compressed data destination operation object, wherein the opcode is used to instruct the execution circuit to round the compressed data element at each compressed data element location of the compressed data source operation object according to the indicated rounding mode, and to store the rounding result in the corresponding compressed data element location of the compressed data destination operation object.

[0075] In some embodiments, at 903, the instructions of the acquired first ISA are translated into one or more instructions of a different second ISA. When executed, the one or more instructions of the different second ISA provide the same result as if the acquired instructions had been executed. This translation can be performed using hardware, software, or a combination thereof.

[0076] In step 905, the instruction (or one or more translated instructions) is decoded. This decoding enables the generation of one or more micro-operations to be executed.

[0077] At 907, retrieve the data value associated with the source operand of the decoded instruction. For example, if the source operand is stored in memory, retrieve the data from the indicated memory location.

[0078] At 909, the decoded instruction(s) are executed by the execution circuitry (hardware), such as the execution circuitry detailed herein. For each compressed data element position of the compressed data source operation object, the execution circuitry rounds the compressed data element at that position according to the indicated rounding mode and stores the rounding result in the corresponding compressed data element position of the compressed data destination operation object.

[0079] In some embodiments, at 911, the instruction is submitted or withdrawn.

[0080] Figure 10An exemplary embodiment of pseudocode representing the execution and format of the BF16 data element rounding instruction is shown. Note that EVEX.b corresponds to b in prefix 1701(C). The comments DAZ, FTZ, RNE, and SAE refer to support for flush to zero (FTZ), nonnormal zero (DAZ), suppress all exceptions (SAE), and round to even (RNE) rounding.

[0081] Figure 11 An embodiment of hardware for processing instructions such as VSCALEFNEPBF16, VREDUCENEPBF16, and / or VRNDSCALENEPBF16 instructions is shown. As shown, storage device 1103 stores VSCALEFNEPBF16, VREDUCENEPBF16, and / or VRNDSCALENEPBF16 instructions 1101 to be executed.

[0082] Instruction 1101 is received by decoding circuitry 1105. For example, decoding circuitry 1105 receives this instruction from an acquisition logic / circuit. The instruction includes fields for the opcode, first and second sources, and destination. In some embodiments, the source and destination are registers, while in other embodiments, one or more are memory locations. In some embodiments, the opcode specifies which arithmetic operation to perform.

[0083] A more detailed embodiment of at least one instruction format will be described later. Decoding circuit 1105 decodes the instruction into one or more operations. In some embodiments, this decoding includes generating multiple micro-operations to be executed by execution circuitry (e.g., execution circuitry 1109). Decoding circuit 1105 also decodes instruction prefixes.

[0084] In some embodiments, register renaming, register allocation, and / or scheduling circuitry 1107 provides functionality for one or more of the following: 1) renaming logical operand values ​​to physical operand values ​​(e.g., register alias tables in some embodiments), 2) assigning status bits and flags to decoded instructions, and 3) scheduling decoded instructions from an instruction pool (e.g., reserved stations in some embodiments) for execution on execution circuitry.

[0085] Registers (register files) and / or memory 1108 store data as the objects of operations for instructions to be performed by execution circuitry 1109. Exemplary register types include compact data registers, general-purpose registers, and floating-point registers.

[0086] Execution circuit 1109 executes the decoded instructions. Figure 2 Exemplary detailed execution circuitry is shown in Figure 14, etc. The execution of the decoded instructions causes the execution circuitry to perform the operations detailed above.

[0087] In some embodiments, the write-back / write-back circuit 1111 submits the result 1108 and writes back the instruction at the architecture level.

[0088] Exemplary Computer Architecture

[0089] The exemplary computer architectures, instruction formats, and so on that support the instructions discussed are described in detail below. Other system designs and configurations known in the art for laptops, desktop computers, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. In short, a wide variety of systems or electronic devices capable of incorporating processors and / or other execution logic as disclosed herein are generally suitable.

[0090] Figure 12 An embodiment of an exemplary system is illustrated. The multiprocessor system 1200 is a point-to-point interconnect system and includes a plurality of processors, including a first processor 1270 and a second processor 1280 coupled via a point-to-point interconnect 1250. In some embodiments, the first processor 1270 and the second processor 1280 are homogeneous. In some embodiments, the first processor 1270 and the second processor 1280 are heterogeneous.

[0091] Processors 1270 and 1280 are shown to include integrated memory controller (IMC) unit circuitry 1272 and 1282, respectively. Processor 1270 also includes point-to-point (PP) interfaces 1276 and 1278 as part of its interconnect controller unit; similarly, the second processor 1280 includes PP interfaces 1286 and 1288. Processors 1270 and 1280 can exchange information via point-to-point (PP) interface 1250 using PP interface circuitry 1278 and 1288. IMCs 1272 and 1282 couple processors 1270 and 1280 to their respective memories, namely memories 1232 and 1234, which may be portions of the main memory locally attached to the respective processors.

[0092] Processors 1270 and 1280 can each exchange information with chipset 1290 via individual PP interconnects 1252 and 1254 using point-to-point interface circuits 1276, 1294, 1286, and 1298, respectively. Chipset 1290 can optionally exchange information with coprocessor 1238 via high-performance interface 1292. In some embodiments, coprocessor 1238 is a dedicated processor, such as a high-throughput MIC processor, network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, etc.

[0093] A shared cache (not shown) may be included in either of the processors 1270 or 1280, or may be located outside of the two processors but connected to the processors via a PP interconnect, such that local cache information of either or both processors may be stored in the shared cache when the processors are in a low-power mode.

[0094] Chipset 1290 may be coupled to a first interconnect 1216 via interface 1296. In some embodiments, the first interconnect 1216 may be a Peripheral Component Interconnect (PCI) interconnect, or an interconnect such as a PCI Fast Interconnect or another I / O interconnect. In some embodiments, one of the interconnects is coupled to a power control unit (PCU) 1217, which may include circuitry, software, and / or firmware to perform power management operations in relation to processors 1270, 1280, and / or coprocessor 1238. PCU 1217 provides control information to a voltage regulator to cause the voltage regulator to generate an appropriate regulated voltage. PCU 1217 also provides control information to control the generated operating voltage. In various embodiments, PCU 1217 may include various power management logic units (circuitry) to perform hardware-based power management. Such power management can be entirely processor-controlled (e.g., controlled by various processor hardware and can be triggered by workload and / or power constraints, thermal constraints or other processor constraints), and / or power management can be performed in response to external sources (e.g., platform or power management sources or system software).

[0095] PCU 1217 is illustrated as logic separate from processor 1270 and / or processor 1280. In other cases, PCU 1217 may execute on one or more given cores (not shown) of processor 1270 or 1280. In some cases, PCU 1217 may be implemented as a microcontroller (dedicated or general purpose) or other control logic configured to execute its own dedicated power management code (sometimes called P-code). In still other embodiments, the power management operations to be performed by PCU 1217 may be implemented outside the processor, for example, via a separate power management integrated circuit (PMIC) or another component located outside the processor. In still other embodiments, the power management operations to be performed by PCU 1217 may be implemented within the BIOS or other system software.

[0096] Various I / O devices 1214 can be coupled to a first interconnect 1216, and an interconnect (bus) bridge 1218 couples the first interconnect 1216 to a second interconnect 1220. In some embodiments, one or more additional processors 1215, such as a coprocessor, a high-throughput MIC processor, a GPGPU, an accelerator (e.g., a graphics accelerator or digital signal processing (DSP) unit), a field-programmable gate array (FPGA), or any other processor, are coupled to the first interconnect 1216. In some embodiments, the second interconnect 1220 can be a low pin count (LPC) interconnect. Various devices can be coupled to the second interconnect 1220, including, for example, a keyboard and / or mouse 1222, a communication device 1227, and a memory cell circuit 1228. The memory cell circuit 1228 can be a disk drive or other mass storage device, and in some embodiments, it can include instruction / code and data 1230. Additionally, audio I / O 1224 can be coupled to the second interconnect 1220. Note that other architectures besides the point-to-point architecture described above are also possible. For example, instead of a point-to-point architecture, systems such as the Multiprocessor System 1200 can implement multi-branch interconnects or other such architectures.

[0097] Exemplary core architecture, processor, and computer architecture

[0098] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, such core implementations can include: 1) general-purpose ordered cores designed for general-purpose computing; 2) high-performance general-purpose unordered cores designed for general-purpose computing; and 3) dedicated cores primarily designed for graphics and / or scientific (throughput) computing. Different processor implementations can include: 1) CPUs comprising one or more general-purpose ordered cores and / or one or more general-purpose unordered cores designed for general-purpose computing; and 2) coprocessors comprising one or more dedicated cores primarily designed for graphics and / or scientific (throughput) computing. Such different processors lead to different computer system architectures, which may include: 1) a coprocessor located on a separate chip from the CPU; 2) a coprocessor located on a separate die within the same package as the CPU; 3) a coprocessor located on the same die as the CPU (in this case, such a coprocessor is sometimes referred to as dedicated logic, such as integrated graphics and / or scientific (throughput) logic, or a dedicated core); and 4) a system-on-a-chip that may include the aforementioned coprocessors and additional functionality on the same die as the described CPU (sometimes referred to as one or more application cores or one or more application processors). An exemplary core architecture is described next, followed by a description of exemplary processors and computer architectures.

[0099] Figure 13 A block diagram of an embodiment of processor 1300 is shown. This processor may have more than one core, may have an integrated memory controller, and may have integrated graphics. Solid-line boxes illustrate processor 1300 having a single core 1302A, a system agent 1310, and a set of one or more interconnect controller unit circuits 1316, while dashed-line boxes optionally show alternative processor 1300 having multiple cores 1302A-N, a set of one or more integrated memory controller unit circuits 1314 from the system agent unit circuits 1310, dedicated logic 1308, and a set of one or more interconnect controller unit circuits 1316. Note that processor 1300 may be… Figure 12 One of the processors 1270 or 1280 or the coprocessor 1238 or 1215.

[0100] Therefore, different implementations of processor 1300 may include: 1) a CPU, where dedicated logic 1308 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores, not shown), and cores 1302A-N are one or more general-purpose cores (e.g., general-purpose ordered cores, general-purpose unordered cores, or a combination of both); 2) a coprocessor, where cores 1302A-N are a large number of dedicated cores primarily intended for graphics and / or scientific (throughput); and 3) a coprocessor, where cores 1302A-N are a large number of general-purpose ordered cores. Thus, processor 1300 can be a general-purpose processor, a coprocessor, or a dedicated processor, such as a network or communication processor, a compression engine, a graphics processor, a GPGPU (General-Purpose Graphics Processing Unit circuit), a high-throughput many-integrated-core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor can be implemented on one or more chips. Processor 1300 may be part of one or more substrates and / or may be implemented on one or more substrates using any of several process technologies, such as BiCMOS, CMOS, or NMOS.

[0101] The memory hierarchy includes one or more levels of cache unit circuitry 1304A-N within the cores 1302A-N, a group of one or more shared cache unit circuitry 1306, and external memory (not shown) coupled to the group of integrated memory controller unit circuitry 1314. The group of one or more shared cache unit circuitry 1306 may include one or more intermediate level caches (e.g., level 2 (L2), level 3 (L3), level 4 (4), or other levels of cache), such as the last-level cache (LLC), and / or combinations thereof. While in some embodiments a ring-based interconnect network circuitry 1312 interconnects dedicated logic 1308 (e.g., integrated graphics logic), the group of shared cache unit circuitry 1306, and system proxy unit circuitry 1310, alternative embodiments use any number of known techniques to interconnect such units. In some embodiments, consistency is maintained between one or more of the shared cache unit circuitry 1306 and the cores 1302A-N.

[0102] In some embodiments, one or more of the cores 1302A-N are capable of multi-threaded processing. The system proxy unit circuitry 1310 includes those components that coordinate and operate the cores 1302A-N. The system proxy unit circuitry 1310 may include, for example, power control unit (PCU) circuitry and / or display unit circuitry (not shown). The PCU may be, or may include, the logic and components required to regulate the power state of the cores 1302A-N and / or dedicated logic 1308 (e.g., integrated graphics logic). The display unit circuitry is used to drive one or more externally connected displays.

[0103] Core 1302A-N can be homogeneous or heterogeneous in terms of its architecture instruction set; that is, two or more cores in 1302A-N may be able to execute the same instruction set, while other cores may be able to execute only a subset of that instruction set or a different instruction set.

[0104] Exemplary Core Architecture

[0105] Ordered and disordered core diagrams

[0106] Figure 14(A) is a block diagram illustrating both an exemplary ordered pipeline and an exemplary register renaming, out-of-order issue / execution pipeline according to an embodiment of the present invention. Figure 14(B) is a block diagram illustrating both an exemplary embodiment of an ordered architecture core to be included in a processor according to an embodiment of the present invention and an exemplary register renaming, out-of-order issue / execution architecture core. Figures 14(A) to 14(B) The solid boxes in the diagram illustrate ordered pipelines and ordered cores, while the optional addition of dashed boxes illustrates register renaming, out-of-order issue / execute pipelines, and cores. Given that ordered aspects are a subset of out-of-order aspects, the out-of-order aspects will be described.

[0107] In Figure 14(A), the processor pipeline 1400 includes a fetch phase 1402, an optional length-decode phase 1404, a decode phase 1406, an optional allocation phase 1408, an optional rename phase 1410, a scheduling (also known as dispatch or issue) phase 1412, an optional register read / memory read phase 1414, an execution phase 1416, a write-back / memory write phase 1418, an optional exception handling phase 1422, and an optional commit phase 1424. One or more operations can be performed in each of these processor pipeline phases. For example, during the fetch phase 1402, one or more instructions are fetched from instruction memory; during the decode phase 1406, one or more fetched instructions can be decoded; an address using a forward register port (e.g., a load store unit (LSU) address) can be generated; and branch forwarding (e.g., immediate offset or link register (LR)) can be performed. In one embodiment, the decoding phase 1406 and the register read / memory read phase 1414 can be combined into a single pipeline phase. In one embodiment, during the execution phase 1416, decoded instructions can be executed, LSU address / data pipelined to the Advanced Microcontroller Bus (AHB) interface can be executed, multiplication and addition operations can be performed, arithmetic operations with branch results can be performed, and so on.

[0108] As an example, the exemplary register renaming, out-of-order issue / execution core architecture can implement pipeline 1400 as follows: 1) Instruction fetch 1438 executes fetch and length decoding stages 1402 and 1404; 2) Decoding unit circuit 1440 executes decoding stage 1406; 3) Rename / allocator unit circuit 1452 executes allocation stage 1408 and rename stage 1410; 4) (one or more) Scheduler unit circuit 1456 executes scheduling stage 1412; 5) (one or more) Physical register file unit circuits 1458 and memory unit circuit 1470 execute register read / memory read phase 1414; execution cluster 1460 executes execution phase 1416; 6) memory unit circuit 1470 and (one or more) physical register file unit circuits 1458 execute write-back / memory write phase 1418; 7) various units (unit circuits) may be involved in exception handling phase 1422; and 8) retirement unit circuit 1454 and (one or more) physical register file unit circuits 1458 execute commit phase 1424.

[0109] Figure 14(B) illustrates processor core 1490, which includes front-end unit circuitry 1430 coupled to execution engine unit circuitry 1450, and both are coupled to memory unit circuitry 1470. Core 1490 can be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. Alternatively, core 1490 can be a dedicated core, such as a network or communication core, a compression engine, a coprocessor core, a general purpose computing graphics processing unit (GPGPU) core, a graphics core, etc.

[0110] The front-end unit circuit 1430 may include a branch prediction unit circuit 1432 coupled to an instruction cache unit circuit 1434, which is coupled to a translation lookaside buffer (TLB) 1436. The instruction TLB 1436 is coupled to an instruction fetch unit circuit 1438, which is coupled to a decode unit circuit 1440. In one embodiment, the instruction cache unit circuit 1434 is included in a memory unit circuit 1470 instead of the front-end unit circuit 1430. The decode unit circuit 1440 (or decoder) can decode instructions and generate one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals as outputs. These micro-operations, microcode entry points, microinstructions, other instructions, or other control signals are decoded from, or otherwise reflect, or derived from the original instructions. The decode unit circuit 1440 may also include an address generation unit circuit (AGU, not shown). In one embodiment, the AGU uses the forwarded register port to generate the LSU address and can further perform branch forwarding (e.g., immediate offset branch forwarding, LR register branch forwarding, etc.). Various different mechanisms can be used to implement the decoding unit circuitry 1440. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memory (ROMs), etc. In one embodiment, core 1490 includes a microcode ROM (not shown) or other medium that stores microcode for certain macro instructions (e.g., in the decoding unit circuitry 1440 or otherwise within the front-end unit circuitry 1430). In one embodiment, the decoding unit circuitry 1440 includes micro-ops or operation caches (not shown) to hold / cachive decoded operations, micro-tags, or micro-operations generated during decoding or other stages of the processor pipeline 1400. The decoding unit circuitry 1440 may be coupled to the rename / allocator unit circuitry 1452 in the execution engine unit circuitry 1450.

[0111] The execution engine circuitry 1450 includes a renaming / allocator unit circuitry 1452, which is coupled to a retirement unit circuitry 1454 and a set of one or more scheduler circuits 1456. The scheduler circuits 1456 represent any number of different schedulers, including reservation stations, central instruction windows, etc. In some embodiments, the scheduler circuits 1456 may include an arithmetic logic unit (ALU) scheduler / scheduling circuit, an ALU queue, an arithmetic generation unit (AGU) scheduler / scheduling circuit, an AGU queue, etc. The scheduler circuits 1456 are coupled to one or more physical register file circuits 1458. Each of the physical register file circuits 1458 represents one or more physical register files, which store one or more different data types, such as scalar integers, scalar floating-point numbers, compressed integers, compressed floating-point numbers, vector integers, vector floating-point numbers, status (e.g., an instruction pointer as the address of the next instruction to be executed), etc. In one embodiment, one or more physical register file unit circuits 1458 include vector register unit circuits, write mask register unit circuits, and scalar register unit circuits. These register units can provide architectural vector registers, vector mask registers, general-purpose registers, etc. One or more physical register file unit circuits 1458 overlap with retirement unit circuits 1454 (also referred to as a retirement queue or decommissioning queue) to illustrate various ways that can be used to implement register renaming and out-of-order execution (e.g., utilizing one or more reorder buffers (ROBs) and one or more retirement register files; utilizing one or more future files, one or more history buffers, and one or more retirement register files; utilizing register maps and register pools; etc.). Retirement unit circuits 1454 and one or more physical register file circuits 1458 are coupled to one or more execution clusters 1460. One or more execution clusters 1460 include a set of one or more execution unit circuits 1462 and a set of one or more memory access circuits 1464. Execution unit circuit 1462 can perform various arithmetic, logical, floating-point, or other types of operations (e.g., shift, addition, subtraction, multiplication) on various types of data (e.g., scalar floating-point, compressed integer, compressed floating-point, vector integer, vector floating-point). While some embodiments may include several execution units or execution unit circuits dedicated to a particular function or set of functions, other embodiments may include only one execution unit circuit or multiple execution units / execution unit circuits that perform all functions.One or more scheduler circuits 1456, one or more physical register file unit circuits 1458, and one or more execution clusters 1460 are shown as possibly multiple, because some embodiments create separate pipelines for certain types of data / operations (e.g., scalar integer pipelines, scalar floating-point / compact integer / compact floating-point / vector integer / vector floating-point pipelines, and / or memory access pipelines, each having its own scheduler circuitry, one or more physical register file unit circuits, and / or execution clusters—and in the case of separate memory access pipelines, some embodiments are implemented where only the execution cluster of this pipeline has one or more memory access unit circuits 1464). It should also be understood that, in the case of using separate pipelines, one or more of these pipelines may be issued / executed out of order, while the remainder are ordered.

[0112] In some embodiments, the execution engine unit circuit 1450 can perform load memory unit (LSU) address / data pipelined to the Advanced Microcontroller Bus (AHB) interface (not shown), as well as address phase and write-back, data phase load, store, and branch.

[0113] The memory access circuitry 1464 is coupled to memory cell circuitry 1470, which includes data TLB circuitry 1472. Data TLB circuitry 1472 is coupled to data cache circuitry 1474, which is coupled to Level 2 (L2) cache circuitry 1476. In one exemplary embodiment, memory access circuitry 1464 may include load circuitry, memory address circuitry, and memory data circuitry, each of which is coupled to data TLB circuitry 1472 in memory cell circuitry 1470. Instruction cache circuitry 1434 is further coupled to Level 2 (L2) cache circuitry 1476 in memory cell circuitry 1470. In one embodiment, instruction cache 1434 and data cache 1474 are combined into a single instruction and data cache (not shown) in L2 cache circuitry 1476, Level 3 (L3) cache circuitry (not shown), and / or main memory. L2 cache circuitry 1476 is coupled to one or more other levels of cache and ultimately to main memory.

[0114] Core 1490 may support one or more instruction sets (e.g., x86 instruction set (with some extensions added with newer versions); MIPS instruction set; ARM instruction set (with optional additional extensions, such as NEON)), including one or more instructions described herein. In one embodiment, core 1490 includes logic to support compressed data instruction set extensions (e.g., AVX1, AVX2), thereby allowing operations used by many multimedia applications to be performed using compressed data.

[0115] (one or more) exemplary execution unit circuits

[0116] Figure 15 An embodiment of one or more execution unit circuits is illustrated, such as execution unit circuit 1462 of FIG. 14(B). As shown, execution unit circuit 1462 may include one or more ALU circuits 1501, vector / SIMD unit circuits 1503, load / store unit circuits 1505, and / or branch / jump unit circuits 1507. ALU circuit 1501 performs integer arithmetic and / or Boolean operations. Vector / SIMD unit circuit 1503 performs vector / SIMD operations on compressed data (e.g., SIMD / vector registers). Load / store unit circuit 1505 executes load and store instructions to load data from memory into registers or store data from registers into memory. Load / store unit circuit 1505 may also generate addresses. Branch / jump unit circuit 1507 causes a branch or jump to a memory address based on an instruction. Floating-point unit (FPU) circuit 1509 performs floating-point arithmetic. The width of the execution unit circuit 1462 varies depending on the embodiment and can range from 16 bits to 1024 bits. In some embodiments, two or more smaller execution units are logically combined to form a larger execution unit (e.g., two 128-bit execution units are logically combined to form a 256-bit execution unit).

[0117] Exemplary Register Architecture

[0118] Figure 16This is a block diagram of a register architecture 1600 according to some embodiments. As shown, there is a vector / SIMD register 1610 with a width ranging from 128 bits to 1024 bits. In some embodiments, the vector / SIMD register 1610 is physically 512 bits, and depending on the mapping, only some low-order bits are used. For example, in some embodiments, the vector / SIMD register 1610 is a 512-bit ZMM register: the lower 256 bits are used for the YMM register, and the lower 128 bits are used for the XMM register. Therefore, register overriding exists. In some embodiments, the vector length field is selected between a maximum length and one or more other shorter lengths, where each such shorter length is half the length of the previous length. Scalar operations are performed at the lowest-order data element position in the ZMM / YMM / XMM registers; higher-order data element positions are either kept at the same position as before the instruction or are zeroed, depending on the embodiment.

[0119] In some embodiments, register architecture 1600 includes write mask / predicate register 1615. For example, in some embodiments, there are eight write mask / predicate registers (sometimes referred to as k0 to k7), each of which is 16-bit, 32-bit, 64-bit, or 128-bit in size. Write mask / predicate register 1615 may allow merging (e.g., allowing any set of elements in the destination to be unupdated during the execution of any operation) and / or zeroing (e.g., a zeroing vector mask allows any set of elements in the destination to be zeroed during the execution of any operation). In some embodiments, each data element position in a given write mask / predicate register 1615 corresponds to a data element position in the destination. In other embodiments, write mask / predicate register 1615 is scalable and consists of a set number of enable bits for a given vector element (e.g., eight enable bits for each 64-bit vector element).

[0120] The register architecture 1600 includes multiple general-purpose registers 1625. These registers can be 16-bit, 32-bit, 64-bit, etc., and can be used for scalar operations. In some embodiments, these registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0121] In some embodiments, register architecture 1600 includes a scalar floating-point register 1645, which is used to perform scalar floating-point operations on 32 / 64 / 80-bit floating-point data using x87 instruction set extensions, or as an MMX register to perform operations on 64-bit compressed integer data, and to hold operation objects for some operations performed between the MMX and XMM registers.

[0122] One or more flag registers 1640 (e.g., EFLAGS, RFLAGS, etc.) store status and control information for arithmetic, comparison, and system operation. For example, one or more flag registers 1640 may store condition code information such as carry, parity, auxiliary carry, zero, sign, and overflow. In some embodiments, one or more flag registers 1640 are referred to as program status and control registers.

[0123] Segmentation register 1620 contains segmentation points for accessing memory. In some embodiments, these registers are referenced by the names CS, DS, SS, ES, FS, and GS.

[0124] The machine-specific register (MSR) 1635 controls and reports processor performance. Most MSR 1635s handle system-related functions and are not accessible to applications. The machine check register 1660 consists of control, status, and error reporting MSRs used to detect and report hardware errors.

[0125] One or more instruction pointer registers 1630 store instruction pointer values. One or more control registers 1655 (e.g., CR0-CR4) determine the operating mode and characteristics of the currently executing task of the processor (e.g., processors 1270, 1280, 1238, 1215, and / or 1300). Debug register 1650 controls and allows monitoring of debug operations on the processor or core.

[0126] Memory management register 1665 specifies the location of data structures used in protected-mode memory management. These registers may include the GDTR, IDRT, task register, and LDTR register.

[0127] Alternative embodiments of the present invention may use wider or narrower registers. Furthermore, alternative embodiments of the present invention may use more, fewer, or different register files and registers.

[0128] Instruction set

[0129] An instruction set architecture (ISA) may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, bit positions) to specify the operation to be performed (e.g., opcode) and the operand(s) on which the operation is performed, and / or other data fields (e.g., mask), etc. Some instruction formats are further decomposed through the definition of instruction templates (or subformats). For example, an instruction template for a given instruction format may be defined as having different subsets of the fields of that instruction format (the included fields are usually in the same order, but at least some have different bit positions because fewer fields are included) and / or may be defined as having given fields interpreted in different ways. Thus, each instruction in an ISA is expressed using a given instruction format (and, if defined, as a given instruction template in the instruction template of that instruction format) and includes fields for specifying the operation and operand. For example, an exemplary ADD instruction has a specific opcode and instruction format, which includes an opcode field to specify the opcode and an operand field to select the operand (source 1 / destination and source 2); and the appearance of this ADD instruction in the instruction stream will have specific content in the operand field for selecting the specific operand.

[0130] Exemplary instruction format

[0131] Embodiments of the instructions(s) described herein may be implemented in different formats. Furthermore, exemplary systems, architectures, and pipelines are detailed below. Embodiments of the instructions(s) may be executed on such systems, architectures, and pipelines, but are not limited to those detailed herein.

[0132] Figure 17 An embodiment of the instruction format is illustrated. As shown, an instruction may include multiple components, including but not limited to one or more fields for: one or more prefixes 1701, opcode 1703, addressing information 1705 (e.g., register identifier, memory addressing information, etc.), offset value 1707, and / or immediate value 1709. Note that some instructions utilize some or all of the fields of this format, while other instructions may only use the fields of opcode 1703. In some embodiments, the illustrated order is the order in which these fields are to be encoded; however, it should be understood that in other embodiments, these fields may be encoded in different orders, combined, etc.

[0133] One or more prefix fields 1701 modify instructions when used. In some embodiments, one or more prefixes are used to repeat string instructions (e.g., 0xF0, 0xF2, 0xF3, etc.) to provide fragment overlay (e.g., 0x2E, 0x36, 0x3E, 0x26, 0x64, 0x65, 0x2E, 0x3E, etc.) to perform bus locking operations, and / or change the operand (e.g., 0x66) and address size (e.g., 0x67). Some instructions require mandatory prefixes (e.g., 0x66, 0xF2, 0xF3, etc.). Some of these prefixes may be considered "traditional" prefixes. Other prefixes—one or more examples of which are detailed here—indicate and / or provide further capabilities, such as specifying a particular register, etc. Other prefixes typically follow "traditional" prefixes.

[0134] Opcode field 1703 is used to at least partially define the operation to be performed during instruction decoding. In some embodiments, the length of the primary opcode encoded in opcode field 1703 is 1, 2, or 3 bytes. In other embodiments, the primary opcode can be of different lengths. An additional 3-bit opcode field is sometimes encoded in another field.

[0135] Address field 1705 is used to address one or more operands of an instruction, such as a location in memory or one or more registers. Figure 18 An embodiment of addressing field 1705 is shown. This illustration shows an optional ModR / M byte 1802 and optional Scale, Index, Base (SIB) bytes 1804. ModR / M bytes 1802 and SIB bytes 1804 are used to encode up to two operands of an instruction, each operand being a direct register or an effective memory address. Note that each of these fields is optional; that is, not all instructions include one or more of these fields. The MOD R / M byte 1802 includes the MOD field 1842, the register field 1844, and the R / M field 1846.

[0136] The content of the MOD field 1842 distinguishes between memory access and non-memory access modes. In some embodiments, when the value of the MOD field 1842 is b11, register direct addressing mode is used; otherwise, register indirect addressing is used.

[0137] Register field 1844 may encode a destination register operand or a source register operand, or it may encode an opcode extension, and may not be used to encode any instruction operand. The contents of register index field 1844 directly specify or are generated from an address to specify the location of the source or destination operand (in a register or in memory). In some embodiments, register field 1844 is supplemented with extra bits from a prefix (e.g., prefix 1701) to allow for larger addressing.

[0138] The R / M field 1846 can be used to encode instruction operands that reference memory addresses, or it can be used to encode destination register operands or source register operands. Note that in some embodiments, the R / M field 1846 can be combined with the MOD field 1842 to specify the addressing mode.

[0139] SIB byte 1804 includes a scaling field 1852, an index field 1854, and a base field 1856 for generating addresses. The scaling field 1852 indicates a scaling factor. The index field 1854 specifies the index register to be used. In some embodiments, the index field 1854 is supplemented with extra bits from a prefix (e.g., prefix 1701) to allow for larger addressing. The base field 1856 specifies the base address register to be used. In some embodiments, the base field 1856 is supplemented with extra bits from a prefix (e.g., prefix 1701) to allow for larger addressing. In practice, the contents of the scaling field 1852 allow scaling of the contents of the index field 1854 for memory address generation (e.g., for address generation using 2 scaling factor * index + base address).

[0140] Some addressing schemes use bitwise shift values ​​to generate memory addresses. For example, they can be based on 2 缩放 Memory addresses are generated using methods such as scaling factor * index + base address + displacement, index * scaling factor + displacement, r / m + displacement, instruction pointer (RIP / EIP) + displacement, register + displacement, etc. This displacement can be a value of 1 byte, 2 bytes, 4 bytes, etc. In some embodiments, the displacement field 1707 provides this value. Furthermore, in some embodiments, the displacement factor usage is encoded in the MOD field of the addressing field 1705, indicating a compressed displacement scheme for which the displacement value is calculated by multiplying disp8 by a scaling factor N, which is determined based on the vector length, the value of b bits, and the size of the instruction input elements. This displacement value is stored in the displacement field 1707.

[0141] In some embodiments, the immediate number field 1709 specifies an immediate value for the instruction. The immediate value can be encoded as a 1-byte value, a 2-byte value, a 4-byte value, and so on.

[0142] Figure 19 An embodiment of the first prefix 1701(A) is shown. In some embodiments, the first prefix 1701(A) is an embodiment of the REX prefix. Instructions using this prefix can specify general-purpose registers, 64-bit compact data registers (e.g., single-instruction multiple-data (SIMD) registers or vector registers), and / or control registers and debug registers (e.g., CR8-CR15 and DR8-DR15).

[0143] Instructions using the first prefix 1701(A) can specify up to three registers using 3-bit fields, depending on the format: 1) using the reg field 1844 and the R / M field 1846 of Mod R / M byte 1802; 2) using Mod R / M byte 1802 with SIB byte 1804, including using the reg field 1844, the base address field 1856, and the index field 1854; or 3) using the register field of the opcode.

[0144] In the first prefix 1701(A), bits 7:4 are set to 0100. Bit 3(W) can be used to determine the operand size, but may not determine the operand width independently. Therefore, when W=0, the operand size is determined by the code segment descriptor (CS.D), while when W=1, the operand size is 64 bits.

[0145] Note that adding another bit allows addressing 16(2) 4 The MOD R / M reg field 1844 and MOD R / MR / M field 1846 can each address 8 registers, while the individual MOD R / M reg field 1844 and MOD R / MR / M field 1846 can each address 8 registers.

[0146] In the first prefix 1701(A), bit position 2(R) can be an extension of the MOD R / M reg field 1844, and bit position 2(R) can be used to modify the Mod R / M reg field 1844 when this field encodes a general-purpose register, a 64-bit compressed data register (e.g., the SSE register), or a control or debug register. R is ignored when the Mod R / M byte 1802 specifies other registers or defines extended opcodes.

[0147] Bit position 1(X)X bits can modify SIB byte index field 1854.

[0148] Bit position B(B)B can modify the base address in Mod R / MR / M field 1846 or SIB byte base address field 1856; or it can modify the opcode register field used to access general-purpose registers (e.g., general-purpose register 1625).

[0149] Figures 20(A) to 20(D) An example of how the R, X, and B fields of the first prefix 1701(A) are used is illustrated. Figure 20(A) shows that when SIB byte 1804 is not used for memory addressing, the R and B from the first prefix 1701(A) are used to extend the reg field 1844 and R / M field 1846 of MOD R / M byte 1802. Figure 20(B) shows that when SIB byte 1804 is not used (register-to-register addressing), the R and B from the first prefix 1701(A) are used to extend the reg field 1844 and R / M field 1846 of MOD R / M byte 1802. Figure 20(C) shows that when SIB byte 1804 is used for memory addressing, the R, X, and B from the first prefix 1701(A) are used to extend the reg field 1844, as well as the index field 1854 and the base address field 1856 of MOD R / M byte 1802. Figure 20(D) shows that when the register is encoded in opcode 1703, the B from the first prefix 1701(A) is used to extend the reg field 1844 of MOD R / M byte 1802.

[0150] Figures 21(A) to 20(B) An embodiment of the second prefix 1701(B) is shown. In some embodiments, the second prefix 1701(B) is an embodiment of the VEX prefix. The second prefix 1701(B) encoding allows instructions to have more than two operands and allows SIMD vector registers (e.g., vector / SIMD register 1610) to be longer than 64 bits (e.g., 128 bits and 256 bits). The use of the second prefix 1701(B) provides a syntax for three operands (or more). For example, a previous two-operand instruction performs an operation such as A = A + B, which overwrites the source operand. The use of the second prefix 1701(B) enables operands to perform non-destructive operations, such as A = B + C.

[0151] In some embodiments, the second prefix 1701(B) has two forms—a two-byte form and a three-byte form. The two-byte second prefix 1701(B) is primarily used for 128-bit, scalar, and some 256-bit instructions; while the three-byte second prefix 1701(B) provides a compact replacement for the first prefix 1701(A) and 3-byte opcode instructions.

[0152] Figure 21(A) shows an embodiment of the two-byte form of the second prefix 1701(B). In one example, format field 2101 (byte 0 2103) contains the value C5H. In one example, byte 12105 includes the value “R” in bit [7]. This value is the complement of the same value of the first prefix 1701(A). Bit [2] is used to specify the length (L) of the vector (where value 0 is a scalar or a 128-bit vector, and value 1 is a 256-bit vector). Bits [1:0] provide opcode extrapolation equivalent to some conventional prefixes (e.g., 00 = no prefix, 01 = 66H, 10 = F3H, and 11 = F2H). The bits [6:3] shown as vvvv can be used to: 1) encode a first source register operand specified in inverted (1s complement) form and valid for instructions with two or more source operands; 2) encode a destination register operand specified in 1s complement form for some vector shift; or 3) not encode any operand, the field is reserved and should contain a value such as 1111b.

[0153] Instructions using this prefix can use the Mod R / MR / M field 1846 to encode instruction operands that reference memory addresses, or to encode destination register operands or source register operands.

[0154] Instructions using this prefix can use the Mod R / M reg field 1844 to encode either the destination register operand or the source register operand, and are treated as an opcode extension, rather than being used to encode any instruction operand.

[0155] For the instruction syntax that supports four operands, vvvv, Mod R / MR / M field 1846, and Mod R / M reg field 1844 encode three of the four operands. Then bits [7:4] of the immediate value 1709 are used to encode the third source register operand.

[0156] Figure 21(B) illustrates an embodiment of the three-byte form of the second prefix 1701(B). In one example, format field 2111 (byte 0 2113) contains the value C4H. Byte 1 2115 includes “R”, “X”, and “B” in bits [7:5], which are complements of the same values ​​of the first prefix 1701(A). Bits [4:0] of byte 1 2115 (shown as mmmmm) contain content to encode one or more implicit preamble opcode bytes as needed. For example, 00001 means 0FH preamble opcode, 00010 means 0F38H preamble opcode, 00011 means 0F3AH preamble opcode, and so on.

[0157] Bits [7] of byte 2 2117 are used similarly to W of the first prefix 1701(A), including to help determine the size of the operand that can be promoted. Bit [2] is used to specify the length (L) of the vector (where a value of 0 is a scalar or a 128-bit vector, and a value of 1 is a 256-bit vector). Bits [1:0] provide opcode extrapolation equivalent to some conventional prefixes (e.g., 00 = no prefix, 01 = 66H, 10 = F3H, and 11 = F2H). Bits [6:3] shown as vvvv can be used to: 1) encode the first source register operand, which is specified in inverted (1s complement) form and is valid for instructions with two or more source operands; 2) encode the destination register operand specified in 1s complement form for some vector shift; or 3) not encode any operand, the field is reserved and should contain a value, such as 1111b.

[0158] Instructions using this prefix can use the Mod R / MR / M field 1846 to encode instruction operands that reference memory addresses, or to encode destination register operands or source register operands.

[0159] Instructions using this prefix can use the Mod R / M reg field 1844 to encode either the destination register operand or the source register operand, and are treated as an opcode extension, rather than being used to encode any instruction operand.

[0160] For the instruction syntax that supports four operands, vvvv, Mod R / MR / M field 1846, and Mod R / M reg field 1844 encode three of the four operands. Then bits [7:4] of the immediate value 1709 are used to encode the third source register operand.

[0161] Figure 22 An embodiment of the third prefix 1701(C) is shown. In some embodiments, the first prefix 1701(A) is an embodiment of the EVEX prefix. The third prefix 1701(C) is a four-byte prefix.

[0162] The third prefix 1701(C) can encode 32 vector registers (e.g., 128-bit, 256-bit, and 512-bit registers) in 64-bit mode. In some embodiments, write masks / operation masks are used (see the discussion of registers in the previous figures, e.g.) Figure 16Instructions that use predicates or operators utilize this prefix. Operation mask registers allow for conditional processing or selection control. Operation mask instructions—whose source / destination operands are operation mask registers and whose contents are treated as a single value—are encoded using the second prefix 1701(B).

[0163] The third prefix 1701(C) can encode instruction class-specific features (e.g., a compact instruction with "load + operation" semantics can support embedded broadcast functionality, a floating-point instruction with rounding semantics can support static rounding functionality, a floating-point instruction with non-rounding arithmetic semantics can support "suppress all exceptions" functionality, etc.).

[0164] The first byte of the third prefix 1701(C) is the format field 2211, which has a value of 62H in one example. The subsequent bytes are called payload bytes 2215-2219, and together they form the 24-bit value of P[23:0], which provides specific capabilities in the form of one or more fields (detailed here).

[0165] In some embodiments, P[1:0] of payload byte 2219 is identical to the two lower mm bits. In some embodiments, P[3:2] is reserved. Bit P[4] (R') allows access to the upper 16 vector register sets when combined with P[7] and Mod R / M reg field 1844. P[6] can also provide access to the upper 16 vector registers when SIB type addressing is not required. P[7:5] consists of R, X, and B, which are operand specifier modifier bits for vector registers, general-purpose registers, and memory addressing, and when combined with Mod R / M register field 1844 and Mod R / MR / M field 1846, allows access to the next set of 8 registers beyond the lower 8 registers. P[9:8] provides opcode extrapolation equivalent to some conventional prefixes (e.g., 00 = no prefix, 01 = 66H, 10 = F3H, and 11 = F2H). P

[10] is a fixed value of 1 in some embodiments. P[14:11], shown as vvvv, can be used to: 1) encode a first source register operand specified in inverted (1s complement) form and valid for instructions with two or more source operands; 2) encode a destination register operand specified in 1s complement form for some vector shift; or 3) not encode any operand, the field is reserved and should contain a value such as 1111b.

[0166] P

[15] is similar to W of the first prefix 1701(A) and the second prefix 1701(B), and can be used as an opcode extension bit or an op object size boost.

[0167] P[18:16] specifies the index of a register in the operation mask (write mask) register (e.g., write mask / predicate register 1615). In one embodiment of the invention, the specific value aaa = 000 has special behavior, implying that no operation mask is used for a particular instruction (this can be implemented in various ways, including using a hard-wired operation mask to all one or hardware that bypasses the masking hardware). When merged, the vector mask allows any set of elements in the destination to be protected from updates during the execution of any operation (specified by the basic and enhanced operations); in another embodiment, the old value of each element in the destination with the corresponding mask bit being 0 is preserved. In contrast, when the zero-reset vector mask allows any set of elements in the destination to be zeroed during the execution of any operation (specified by the basic and enhanced operations); in one embodiment, the elements in the destination are set to 0 when the corresponding mask bit has a value of 0. A subset of this functionality is the ability to control the vector length of the operations performed (i.e., the span of the modified elements, from the first to the last); however, the modified elements need not be contiguous. Therefore, the operation mask field allows for some vector operations, including load, store, arithmetic, logic, etc. While an embodiment of the invention has been described in which the contents of the operation mask field selects the operation mask to be used from among several operation mask registers (thus the contents of the operation mask field indirectly identify the mask to be performed), alternative embodiments may, or additionally, allow the contents of the mask write field to directly specify the mask to be performed.

[0168] P

[19] can be combined with P[14:11] to encode the second source vector register in a non-destructive source syntax that allows access to the high 16 vector registers using P

[19] . P

[20] encodes various functions that differ across different classes of instructions and can affect the meaning of the vector length / rounding control specifier field (P[22:21]). P

[23] indicates support for merge-write masking (e.g., when set to 0) or support for zeroing and merge-write masking (e.g., when set to 1).

[0169] The table below details exemplary embodiments of register encoding in instructions using the third prefix 1701(C).

[0170]

[0171] Table 1: 32 Registers Supported in 64-bit Mode

[0172] [2:0] Register type Common uses register Mod R / M reg GPR, vector Destination or source VVVV vvvv GPR, vector Second source or destination RM Mod R / MR / M GPR, vector Source or destination base address Mod R / MR / M GPR Memory addressing index SIB. Index GPR Memory addressing VIDX SIB. Index vector VSIB memory addressing

[0173] Table 2: Encoding Register Specifiers in 32-bit Mode

[0174]

[0175]

[0176] Table 3: Operation Mask Register Specifier Encoding

[0177] Program code can be applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system with a processor, such as a digital signal processor (DSP), microcontroller, application-specific integrated circuit (ASIC), or microprocessor.

[0178] The program code can be implemented in a high-level procedural or object-oriented programming language to communicate with the processing system. Assembly or machine language can also be used if desired. In fact, the mechanisms described in this article are not limited to any particular programming language. In any case, the language can be compiled or interpreted.

[0179] Embodiments of the mechanisms disclosed herein can be implemented using hardware, software, firmware, or a combination of such implementations. Embodiments of the invention can be implemented as computer programs or program code executable on a programmable system comprising: at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0180] One or more aspects of at least one embodiment can be implemented by representative instructions representing various logics within a processor, stored on a machine-readable medium, which, when read by a machine, cause the machine-made logic to perform the techniques described herein. This representation, referred to as an "IP core," can be stored on a tangible machine-readable medium and provided to various customer or manufacturing facilities for loading into the manufacturing machine that actually manufactures the logic or processor.

[0181] Such machine-readable storage media may include—but are not limited to—a non-transitory tangible arrangement of articles made or formed by a machine or device, including storage media such as: hard disks, any other type of disk (including floppy disks, optical disks, compact disk read-only memory (CD-ROM), compact disk rewritable (CD-RW), and magneto-optical disks), semiconductor devices (e.g., read-only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase change memory (PCM)), magnetic cards or optical cards, or any other type of medium suitable for storing electronic instructions.

[0182] Therefore, embodiments of the present invention also include a non-transitory tangible machine-readable medium containing instructions or design data, such as a Hardware Description Language (HDL), that defines the features of the structures, circuits, devices, processors, and / or systems described herein. Such embodiments may also be referred to as program products.

[0183] Simulation (including binary conversion, code transformation, etc.)

[0184] In some cases, an instruction translator can be used to translate instructions from a source instruction set to a target instruction set. For example, an instruction translator can transform (e.g., using static binary translation, including dynamic binary translation with dynamic compilation), morph, emulate, or otherwise convert instructions into one or more other instructions to be processed by the kernel. Instruction translators can be implemented in software, hardware, firmware, or a combination thereof. Instruction translators can be on the processor, off the processor, or partially on the processor and partially off the processor.

[0185] Figure 23A block diagram is shown that contrasts the use of a software instruction converter to convert binary instructions in a source instruction set into binary instructions in a target instruction set, according to an embodiment of the invention. In the illustrated embodiment, the instruction converter is a software instruction converter; however, alternatively, the instruction converter can be implemented using software, firmware, hardware, or various combinations thereof. Figure 23 The program of high-level language 2302 is shown to be compiled using a first ISA compiler 2304 to generate first ISA binary code 2306, which can be natively executed by a processor 2316 having at least one first instruction set core. A processor 2316 having at least one first ISA instruction set core represents any processor that can execute, or otherwise process, the following: The processor has substantially the same functionality to achieve substantially the same results as a processor having at least one first ISA instruction set core: (1) a substantial portion of the instruction set of the first ISA instruction set core or (2) a version of object code for an application or other software intended to run on an Intel processor having at least one first ISA instruction set core. The first ISA compiler 2304 represents a compiler operable to generate first ISA binary code 2306 (e.g., object code), which can be executed on a processor 2316 having at least one first ISA instruction set core, with or without additional linking processing. Similarly, Figure 23 A program in high-level language 2302 is shown to be compiled using a replacement instruction set compiler 2308 to generate replacement instruction set binary code 2310, which can be natively executed by a processor 2314 without a first ISA instruction set core. An instruction converter 2312 is used to convert the first ISA binary code 2306 into code that can be natively executed by a processor 2314 without a first ISA instruction set core. This converted code is unlikely to be identical to the replacement instruction set binary code 2310, as an instruction converter capable of doing so would be difficult to manufacture; however, the converted code will implement general operations and consist of instructions from the replacement instruction set. Therefore, the instruction converter 2312 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device without a first ISA instruction set processor or core to execute the first ISA binary code 2306 through emulation, simulation, or any other process.

[0186] The use of phrases such as "an embodiment," "an example embodiment," or "an exemplary embodiment" indicates that the described embodiment may include a specific feature, structure, or characteristic, but not every embodiment may necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, it is considered that implementing that feature, structure, or characteristic in conjunction with other embodiments (whether explicitly described or not) is within the knowledge of those skilled in the art.

[0187] Furthermore, in the various embodiments described above, unless otherwise specifically stated, connective language such as the phrase "at least one of A, B, or C" is intended to be understood as referring to A, B, or C, or any combination thereof (e.g., A, B, and / or C). Therefore, connective language is not intended and should not be construed as implying that a given embodiment requires at least one A, at least one B, or at least one C to be present.

[0188] Exemplary support for operations involving compressed BF16 data elements includes, but is not limited to:

[0189] 1. An apparatus comprising:

[0190] A decoding circuit is used to decode an instance of a single instruction, the single instruction including fields for: an opcode, an identifier of the location of a first compressed data source operation object, an identifier of the location of a second compressed data source operation object, and an identifier of a compressed data destination operation object, wherein the opcode instructs the execution circuit to perform a floating-point scaling operation on each data element location of the compressed data source operation object by multiplying the data element of the first compressed data source by a power of 2, wherein the exponent of the power of 2 is the floor value of the data element of the second compressed data source, and to store the result of the floating-point scaling operation in the corresponding data element location of the compressed data destination operation object; and

[0191] The execution circuit is used to execute the decoded instructions according to the opcode.

[0192] 2. The apparatus as described in Example 1, wherein the field for identifying the first source operation object is used to identify the vector register.

[0193] 3. The apparatus as described in Example 1, wherein the field for identifying the first source operation object is used to identify the memory location.

[0194] 4. The apparatus as described in Example 1, wherein the execution circuitry is configured to use a rounding mode to the nearest even number during the execution of the decoded instruction.

[0195] 5. The apparatus as described in Example 1, wherein the floor value is zero when the data element of the second compressed data source is a non-normal number.

[0196] 6. The apparatus as described in Example 1, wherein the data element of the first compressed data source is zero when the data element of the first compressed data source is a nonnormal number.

[0197] 7. The apparatus as described in Example 1, wherein the instructions further include one or more fields for writing to the mask register.

[0198] 8. A system comprising:

[0199] Memory is used to store instances of a single instruction;

[0200] A decoding circuit is used to decode an instance of the single instruction, the single instruction including fields for: an opcode, an identifier of the location of a first compressed data source operation object, an identifier of the location of a second compressed data source operation object, and an identifier of a compressed data destination operation object, wherein the opcode instructs the execution circuit to perform a floating-point scaling operation on each data element location of the compressed data source operation object by multiplying the data element of the first compressed data source by a power of 2, wherein the exponent of the power of 2 is the floor value of the data element of the second compressed data source, and to store the result of the floating-point scaling operation in the corresponding data element location of the compressed data destination operation object; and

[0201] The execution circuit is used to execute the decoded instructions according to the opcode.

[0202] 9. The system as described in Example 8, wherein the field for identifying the first source operation object is used to identify the vector register.

[0203] 10. The system as described in Example 8, wherein the field for identifying the first source operation object is used to identify the storage location.

[0204] 11. The system as described in Example 8, wherein the execution circuitry is configured to use a rounding mode to the nearest even number during the execution of the decoded instruction.

[0205] 12. The system as described in Example 8, wherein the floor value is zero when the data element of the second compacted data source is a non-normal number.

[0206] 13. The system as described in Example 8, wherein the instructions further include one or more fields for writing to the mask register.

[0207] 14. The system as described in Example 8, wherein the data element of the first compacted data source is zero when the data element of the first compacted data source is a nonnormal number.

[0208] 15. A non-transitory machine-readable medium storing at least an instance of a particular single instruction, wherein the instance of the particular single instruction will be processed by a processor by executing a method comprising:

[0209] Decoding an instance of the single instruction, which includes fields for the following: an opcode, an identifier of the location of the first compressed data source operation object, an identifier of the location of the second compressed data source operation object, and an identifier of the compressed data destination operation object, wherein the opcode instructs the execution circuit to perform a floating-point scaling operation on each data element location of the compressed data source operation object by multiplying the data element of the first compressed data source by a power of 2, wherein the exponent of the power of 2 is the floor value of the data element of the second compressed data source, and the result of the floating-point scaling operation is stored in the corresponding data element location of the compressed data destination operation object; and

[0210] The decoded instructions are executed according to the opcode.

[0211] 16. The non-transitory machine-readable medium as described in Example 15, wherein the field for identifying the first source operation object is used to identify the vector register.

[0212] 17. The non-transitory machine-readable medium as described in Example 15, wherein a field for identifying a first source operation object is used to identify a memory location.

[0213] 18. The non-transitory machine-readable medium as described in Example 15, wherein the execution is configured to use rounding to the nearest even number during the execution of the decoded instructions.

[0214] 19. The non-transitory machine-readable medium as described in Example 15, wherein the round-down value is zero when the data element of the second compressed data source is a non-normal number.

[0215] 20. The non-transitory machine-readable medium as described in Example 15, wherein the instructions further include one or more fields for writing to a mask register.

[0216] 21. The non-transitory machine-readable medium as described in Example 15, wherein the data element of the first compacted data source is zero when the data element of the first compacted data source is a nonnormal number.

[0217] 22. A non-transitory machine-readable medium storing at least an instance of a particular single instruction, wherein the instance of the particular single instruction will be processed by a processor by executing a method comprising:

[0218] One or more instructions that convert a specific single instruction from a first instruction set architecture to a different second instruction set architecture, the specific single instruction including fields for the following: opcode, identifier of the location of a first compressed data source operation object, identifier of the location of a second compressed data source operation object, and identifier of a compressed data destination operation object, wherein the opcode is used to instruct the execution circuit to perform a floating-point scaling operation on each data element location of the compressed data source operation object by multiplying the data element of the first compressed data source by a power of 2, wherein the exponent of the power of 2 is the floor value of the data element of the second compressed data source, and the result of the floating-point scaling operation is stored in the corresponding data element location of the compressed data destination operation object;

[0219] Decode one or more instructions of the different second instruction set architectures;

[0220] Execute one or more instructions of a different second instruction set architecture that have been decoded.

[0221] 23. The non-transitory machine-readable medium as described in Example 22, wherein the field for identifying the first source operation object is used to identify the vector register.

[0222] 24. The non-transitory machine-readable medium as described in Example 22, wherein a field for identifying a first source operation object is used to identify a memory location.

[0223] 25. The non-transitory machine-readable medium as described in Example 22, wherein the execution is configured to use rounding to the nearest even number during the execution of the decoded instructions.

[0224] 26. The non-transient machine-readable medium as described in Example 22, wherein the floor value is zero when the data element of the second compressed data source is a non-normal number.

[0225] 27. The non-transitory machine-readable medium as described in Example 22, wherein the data element of the first compacted data source is zero when the data element of the first compacted data source is a nonnormal number.

[0226] 28. The non-transitory machine-readable medium as described in Example 22, wherein the instructions further include one or more fields for writing to a mask register.

[0227] 29. A method comprising:

[0228] One or more instructions that transform a specific single instruction from a first instruction set architecture into a different second instruction set architecture, the specific single instruction including fields for: opcode, identifier of the location of a first compressed data source operation object, identifier of the location of a second compressed data source operation object, and identifier of a compressed data destination operation object, wherein the opcode is used to instruct the execution circuit to perform a floating-point scaling operation on each data element location of the compressed data source operation object by multiplying the data element of the first compressed data source by a power of 2, wherein the exponent of the power of 2 is the floor value of the data element of the second compressed data source, and the result of the floating-point scaling operation is stored in the corresponding data element location of the compressed data destination operation object;

[0229] Decode one or more instructions of the different second instruction set architectures;

[0230] Execute one or more instructions of a different second instruction set architecture that have been decoded.

[0231] 30. The non-transitory machine-readable medium as described in Example 29, wherein the field for identifying the first source operation object is used to identify the vector register.

[0232] 31. The non-transitory machine-readable medium as described in Example 29, wherein a field for identifying a first source operation object is used to identify a memory location.

[0233] 32. The non-transitory machine-readable medium as described in Example 29, wherein the execution is configured to use rounding to the nearest even number during the execution of the decoded instructions.

[0234] 33. The non-transient machine-readable medium as described in Example 29, wherein the floor value is zero when the data element of the second compressed data source is a non-normal number.

[0235] 34. The non-transitory machine-readable medium as described in Example 29, wherein the instructions further include one or more fields for writing to a mask register.

[0236] 35. The non-transitory machine-readable medium as described in Example 29, wherein the data element of the first compacted data source is zero when the data element of the first compacted data source is a nonnormal number.

[0237] 36. A method comprising:

[0238] An instance of a single instruction is decoded, the single instruction including fields for: an opcode, an identifier of the location of the compressed data source operation object, an immediate value, and an identifier of the compressed data destination operation object, wherein the opcode instructs the execution circuit to extract the simplification parameters of the data elements of the compressed data source for each data element location of the compressed data source operation object, according to the number of bits specified in the immediate value, and to store the extracted simplification parameters in the corresponding data element location of the compressed data destination operation object; and

[0239] The decoded instructions are executed according to the opcode.

[0240] 37. The method described in Example 36 further includes:

[0241] The single instruction is converted into one or more instructions of a different second instruction set architecture, wherein the execution includes executing one or more instructions of the different second instruction set architecture.

[0242] 38. An apparatus for performing one or more of the methods described in Examples 3 to 37.

[0243] 39. A method comprising:

[0244] An instance of a single instruction is decoded, the single instruction including fields for: an opcode, an identifier of the location of the compressed data source operation object, an indication of the rounding mode, and an identifier of the compressed data destination operation object, wherein the opcode instructs the execution circuit to round the compressed data element at each location of the compressed data source operation object according to the indicated rounding mode, and to store the rounding result in the corresponding compressed data element location of the compressed data destination operation object; and

[0245] The decoded instructions are executed according to the opcode.

[0246] 40. The method described in Example 39 further includes:

[0247] The single instruction is converted into one or more instructions of a different second instruction set architecture, wherein the execution includes executing one or more instructions of the different second instruction set architecture.

[0248] 41. An apparatus for performing one or more of the methods described in Examples 40 to 41.

[0249] The description and drawings should therefore be considered illustrative rather than restrictive. However, it will be apparent that various modifications and changes may be made thereto without departing from the broader spirit and scope of this disclosure as set forth in the claims.

Claims

1. A processor comprising: A decoding circuit is used to decode instructions, the instructions including one or more fields for opcodes, a field for identifying a first vector register, a field for identifying a second vector register, and a field for identifying a predicate register. The first vector register is used to store a first compressed data operation object including multiple BF16 data elements, the second vector register is used to store a second compressed data operation object including multiple data elements, and the predicate register is used to store multiple predicate values. as well as Execution circuitry, configured to perform operations corresponding to the instructions, including, for each BF16 data element in the first compressed data operation object whose predicate value among the plurality of predicate values ​​is a first value: Performing a floating-point scaling operation on the BF16 data element includes multiplying the BF16 data element by a power of 2, wherein the power of 2 has an exponent based on the corresponding data element of the second compact data operation object; as well as The result of the floating-point scaling operation is stored in the corresponding data element position of the destination operation object.

2. The processor according to claim 1, wherein, The execution circuit, for each BF16 data element in the first compressed data operation object whose predicate value is the second value among the plurality of predicate values, does not store the result of the floating-point scaling operation in the corresponding data element position of the destination operation object.

3. The processor according to claim 1, wherein, The execution circuit protects the data element at the corresponding data element position in the destination operation object from being altered for each BF16 data element in the first compressed data operation object whose predicate value is the second value among the plurality of predicate values.

4. The processor according to claim 3, wherein, The second value is a bit value of zero.

5. The processor according to claim 1, wherein, The execution circuit performs the floating-point scaling operation using a rounding mode that rounds to the nearest even number.

6. The processor according to claim 1, wherein, The execution circuit performs the floating-point scaling operation using any of a variety of rounding modes.

7. The processor according to claim 1, wherein, The execution circuit treats irregular inputs as zero and performs the floating-point scaling operation.

8. The processor according to claim 1, wherein, The execution circuit reports the floating-point value flag to perform the floating-point scaling operation.

9. The processor according to claim 1, wherein, The first compressed data manipulation object has any of a plurality of sizes including 128 bits, 256 bits and 512 bits.

10. The processor according to claim 1, wherein, The execution circuit protects the data element at the corresponding data element position in the destination operation object from being changed for each BF16 data element in the first compressed data object whose predicate value is a second value among a plurality of predicate values, wherein the second value is a bit value of zero, and wherein the execution circuit performs the floating-point scaling operation using any of a plurality of rounding modes.

11. The processor of claim 10, wherein the first compressed data operation object has any one of a plurality of sizes including 128 bits, 256 bits and 512 bits, wherein the execution circuit treats irregular inputs as zero when performing the floating-point scaling operation, and wherein the execution circuit reports floating-point value flags when performing the floating-point scaling operation.

12. A calculation method, comprising: The instruction is decoded, the instruction including one or more fields for the opcode, a field identifying a first vector register, a field identifying a second vector register, and a field identifying a predicate register, the first vector register storing a first compressed data operation object including multiple BF16 data elements, the second vector register storing a second compressed data operation object including multiple data elements, and the predicate register storing multiple predicate values; as well as Executing the operation corresponding to the instruction includes, for each BF16 data element in the first compressed data operation object whose predicate value among a plurality of predicate values ​​is a first value: Performing a floating-point scaling operation on the BF16 data element includes multiplying the BF16 data element by a power of 2, wherein the power of 2 has an exponent based on the corresponding data element of the second compact data operation object; as well as The result of the floating-point scaling operation is stored in the corresponding data element position of the destination operation object.

13. The method of claim 12, further comprising, for each BF16 data element in the first compressed data operation object whose corresponding predicate value among a plurality of predicate values ​​is a second value, protecting the data element at the corresponding data element position in the destination operation object from being altered, and wherein the second value is a bit value zero.

14. The method according to claim 12, wherein, Performing the operation also includes: When performing floating-point scaling operations, rounding is performed based on the rounding pattern to the nearest even number; and When performing a floating-point scaling operation, irregular inputs are treated as zeros during the floating-point scaling operation.

15. The method according to claim 12, wherein, Performing the floating-point scaling operation includes performing rounding according to any of a variety of rounding modes, wherein performing the operation further includes reporting a floating-point value flag, and wherein the first compressed data operation object has any of a variety of sizes including 128 bits, 256 bits, and 512 bits.

16. A computing system comprising: The processor according to any one of claims 1 to 11; and Dynamic random access memory (DRAM) coupled to the processor.

17. One or more computer-readable media, the computer-readable medium comprising instructions that, in response to being executed by one or more processors, cause the one or more processors to perform the method of any one of claims 12 to 15.

18. A computing device comprising means for performing the method of any one of claims 12 to 15.

19. A computer program product comprising instructions that, in response to being executed on a computing device, cause the computing device to perform the method of any one of claims 12 to 15.

20. A memory system comprising: One or more cache units within the core; One or more shared cache units coupled to one or more cache units within the core; An integrated memory controller unit coupled to at least one external memory; as well as Interconnect units configured to interconnect the following: one or more cache units within the core, one or more shared cache units, and the integrated memory controller unit; One or more shared cache units include one or more intermediate-level caches and the last-level cache; Among these, consistency is maintained between the one or more shared cache units and the core.

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