Method and apparatus for implementing non-temporal storage in a risc-v processor

Abstract

The present disclosure relates to a method and apparatus for implementing non-temporal storage in a RISC-V processor. The method comprises: obtaining a non-temporal storage hint table associated with a process, the non-temporal storage hint table being used to record respective instruction addresses of one or more non-temporal storage instructions in the process; when the process is running on the RISC-V processor, performing a lookup in the non-temporal storage hint table for an instruction address of a to-be-executed storage instruction in the process; in response to a hit of the to-be-executed storage instruction in the non-temporal storage hint table, executing the to-be-executed storage instruction in a non-temporal storage mode, wherein in the non-temporal storage mode, to-be-stored data of the to-be-executed storage instruction is directly written into a main memory by bypassing a multi-level cache of the processor.

Description

Technical Field

[0001] This disclosure relates to the field of computers, and more specifically, to methods and apparatus for implementing non-temporary storage in RISC-V processors. Background Technology

[0002] Modern processors commonly employ multi-level caching mechanisms. By capturing the temporal and spatial locality of data and instruction accesses, they place frequently accessed data in high-speed caches closest to the computing core. This design is extremely efficient for the vast majority of applications and has therefore become an indispensable standard component of contemporary processor microarchitectures.

[0003] In existing technologies, mainstream processor architectures have introduced dedicated hardware support to improve the storage efficiency of non-temporary data (e.g., streaming data). For example, the Intel x86 architecture defines non-temporary storage instructions in its SSE and AVX instruction sets to allow data to bypass the cache hierarchy and be written directly to memory, thereby increasing bandwidth and reducing cache pollution. Similarly, the ARM architecture also provides hint instructions for non-temporary storage. Summary of the Invention

[0004] According to embodiments of this disclosure, a method for implementing non-temporary storage in a RISC-V processor is provided, comprising: obtaining a non-temporary storage hint table associated with a process, the non-temporary storage hint table being used to record the corresponding instruction addresses of one or more non-temporary storage instructions in the process; when the process is running on the RISC-V processor, performing a lookup in the non-temporary storage hint table for the instruction address of a storage instruction to be executed in the process; and, in response to a match in the non-temporary storage hint table, executing the storage instruction to be executed in a non-temporary storage mode, wherein, in the non-temporary storage mode, the data to be stored of the storage instruction to be executed is directly written to main memory by bypassing the processor's multi-level cache.

[0005] According to embodiments of this disclosure, an apparatus for implementing non-temporary storage in a RISC-V processor is provided, wherein the apparatus includes processor circuitry configured to perform the methods described above.

[0006] According to embodiments of the present disclosure, a computer-readable storage medium is provided having instructions stored thereon, wherein the instructions, when executed by a processor, cause the processor to perform the methods described above.

[0007] According to embodiments of this disclosure, a computer program product is provided, including instructions, wherein the instructions, when executed by a processor, cause the processor to perform the methods described above. Attached Figure Description

[0008] Embodiments of this disclosure will be described by way of example, not limitation, in conjunction with the accompanying drawings, wherein similar reference numerals denote similar elements, and wherein:

[0009] Figure 1 The diagram illustrates a block diagram of an example processor and / or SoC 100, which may have one or more cores and an integrated memory controller.

[0010] Figure 2 A flowchart illustrating a method for implementing non-temporary storage in a RISC-V processor according to an embodiment of the present disclosure is shown.

[0011] Figure 3 A flowchart illustrating a method for configuring a non-temporary storage prompt table according to an embodiment of the present disclosure is shown.

[0012] Figure 4 An exemplary schematic diagram is shown illustrating the configuration of a non-temporary storage prompt table using CSR1 and CSR2 according to an embodiment of the present disclosure.

[0013] Figure 5 The diagram illustrates the encoding format of CSR read / write instructions with the SYSTEM opcode.

[0014] Figure 6 This is an exemplary schematic diagram of inserting CSR operation instructions into the instruction stream of an application according to an embodiment of the present disclosure.

[0015] Figure 7 This is a block diagram illustrating components capable of reading instructions from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium) and performing any one or more of the methods discussed herein, according to some example embodiments. Detailed Implementation

[0016] The features and exemplary embodiments of various aspects of this application will now be described in detail. Numerous specific details are set forth in the following detailed description to provide a comprehensive understanding of this application. However, it will be apparent to those skilled in the art that this application can be implemented without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of this application by illustrating examples. This application is by no means limited to any specific configuration presented below, but covers any modifications, substitutions, and improvements to elements, components, and algorithms without departing from the spirit of this application. Well-known structures and techniques are not shown in the accompanying drawings and the following description in order to avoid unnecessary obfuscation of this application.

[0017] Furthermore, the various operations will be described as multiple discrete operations in a manner most conducive to understanding the illustrative embodiments; however, the order of description should not be construed as implying that these operations must depend on the order. In particular, these operations do not need to be performed in the order presented.

[0018] The phrases “in an embodiment,” “in one embodiment,” and “in some embodiments” are used repeatedly throughout this document. These phrases do not typically refer to the same embodiment; however, they may refer to the same embodiment. Unless the context otherwise specifies, the terms “comprising,” “having,” and “including” are synonyms. The phrases “A or B” and “A / B” mean “(A), (B) or (A and B).”

[0019] Figure 1 A block diagram of an example processor and / or SoC 100 is illustrated, which may have one or more cores and an integrated memory controller. The processor 100 illustrated by solid-line boxes has a single core 102(A), system proxy unit circuitry 110, and a set of one or more interface controller unit circuitry 116, while alternative processors 100 can be illustrated by dashed-line boxes having multiple cores 102(A)-(N), a set of one or more integrated memory control unit circuitry 114 in the system proxy unit circuitry 110, dedicated logic 108, and a set of one or more interface controller unit circuitry 116.

[0020] Different implementations of processor 100 may include: 1) a CPU, where dedicated logic 108 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores, not shown), and cores 102(A)-(N) are one or more general-purpose cores (e.g., general-purpose ordered cores, general-purpose out-of-order cores, or a combination of both); 2) a coprocessor, where cores 102(A)-(N) are a large number of dedicated cores primarily for graphics and / or scientific (throughput) purposes; and 3) a coprocessor, where cores 102(A)-(N) are a large number of general-purpose ordered cores. Thus, processor 100 may be a general-purpose processor, a coprocessor, or a dedicated processor, such as a network or communication processor, a compression engine, a graphics processor, a GPGPU (General-Purpose Graphics Processing Unit), a high-throughput integrated many-core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor may be implemented on one or more chips. The processor 100 may be part of one or more substrates and / or may be implemented on one or more substrates using any of a variety of process technologies, such as complementary metal oxide semiconductor (CMOS), bipolar CMOS (BiCMOS), P-type metal oxide semiconductor (PMOS), or N-type metal oxide semiconductor (NMOS).

[0021] The memory hierarchy includes one or more levels of cache cell circuitry 104(A)-(N) within cores 102(A)-(N), a group of one or more shared cache cell circuitry 106, and external memory (not shown) coupled to the group of integrated memory controller cell circuitry 114. The group of one or more shared cache cell circuitry 106 may include one or more intermediate level caches, such as level 2 (L2), level 3 (L3), level 4 (4), or other levels of cache, such as the last-level cache (LLC), and / or combinations thereof. While in some examples interface network circuitry 112 (e.g., a ring interconnect) provides an interface to dedicated logic 108 (e.g., integrated graphics logic), the group of shared cache cell circuitry 106, and system agent cell circuitry 110, alternative examples use any number of known techniques to interface to these units. In some examples, one or more circuits in the shared cache cell circuitry 106 maintain consistency with cores 102(A)-(N). In some examples, the interface controller unit circuit 116 couples these cores to one or more other devices 118, such as one or more I / O devices, storage devices, one or more communication devices (e.g., wireless networks, wired networks, etc.).

[0022] In some examples, one or more of cores 102(A)-(N) have multi-threading capabilities. System agent unit circuitry 110 includes those components that coordinate and operate cores 102(A)-(N). System agent unit circuitry 110 may include, for example, power control unit (PCU) circuitry and / or display unit circuitry (not shown). The PCU may be (or may include) the logic and components required to regulate the power state of cores 102(A)-(N) and / or dedicated logic 108 (e.g., integrated graphics logic). Display unit circuitry is used to drive one or more externally connected displays.

[0023] Core 102(A)-(N) can be homogeneous in terms of instruction set architecture (ISA). Alternatively, core 102(A)-(N) can also be heterogeneous in terms of ISA; that is, a subset of core 102(A)-(N) may be able to execute one ISA, while other cores may be able to execute only a subset of that ISA or be able to execute another ISA. In one embodiment, processor core 102(A)-(N) may employ all or part of the Reduced Instruction Set Computer (RISC-V) instruction set architecture. In another embodiment, processor core 102(A)-(N) may employ various other instruction set architectures, such as x86, ARM, MIPS, etc.

[0024] Modern CPUs use multi-level caching to optimize temporal and spatial locality of data access, which benefits most applications. However, as applications evolve and large-scale deployments of data processing requiring non-temporary storage (e.g., streaming storage) pose significant challenges to the memory organization of traditional processor microarchitectures. Applications employing data access patterns lacking strong locality perform poorly under traditional multi-level caching mechanisms due to the complex control cycles across multiple cache levels. While loading non-temporary data, such as streaming data, can be managed by streaming prefetchers, the lack of temporal and spatial locality in non-temporary storage leads to wasted cache capacity. Currently, the RISC-V architecture does not offer a solution to this problem.

[0025] Streaming storage is one of the most typical and common scenarios in non-temporary storage. A typical characteristic of applications supporting streaming storage is that data access is streamed; that is, data to be processed enters the processor's computation pipeline sequentially and is then written back to memory sequentially. For example, AI models (especially deep learning models) process massive amounts of data sequentially. This involves data flowing through the layers of a neural network, each layer performing computations on the input data and passing the results to the next layer. This sequential processing is analogous to data flowing through a pipeline.

[0026] When processor microarchitecture processes this type of data, cache misses occur at each level, and data is moved sequentially from the outermost cache to the innermost cache. Load instructions then load the data into registers for computation, and the results are written back to the innermost cache. Once the cache is full, this data lacking locality is replaced level by level in the outer cache, just like useful data, and eventually reaches main memory. Most processor microarchitectures have used stream prefetchers to accelerate the process of loading data, such as streaming data, from main memory to the inner cache. However, there is currently no mature solution for writing data lacking locality to main memory (i.e., non-temporary storage). This process involves a large amount of redundant control and data movement operations between cache levels, leading not only to data access latency but also to significant power wastage.

[0027] Unlike Intel x86 or ARM solutions that support non-temporary memory (e.g., streaming memory) by introducing new instructions, embodiments of this disclosure rely on basic Control Status Register (CSR) extensions and microarchitectural design to address this issue in the RISC-V architecture. To this end, this disclosure proposes a radically different implementation path: instead of introducing any new non-temporary memory instructions, it achieves equivalent or even more flexible non-temporary memory optimizations by reusing existing control read / write instructions from the RISC-V standard, combined with an innovative microarchitectural component—the non-temporary memory hint table. This design maintains the purity of the RISC-V instruction set while achieving hardware acceleration transparent to upper-level software, significantly reducing the complexity and cost of processor design, compiler support, and system software adaptation.

[0028] In the embodiments of this disclosure, two key microarchitectural structures are introduced:

[0029] (1) Non-Temporal Store Hint Table (NTSHT): NTSHT is a fully associative table in which entries indicate the address of a stored instruction, i.e., the program counter (PC) value, or a compressed form of the PC value. The size of the NTSHT can be determined by available resources or timing constraints. The NTSHT can support read and write operations by user-level applications. The NTSHT can be part of the process context, so if the process supports multithreading, the NTSHT can be shared among multiple threads;

[0030] (2) CSR: Two user-mode CSRs are available for applications to program NTSHT. CSR1 is used to program the entry index of NTSHT; CSR2 is used to store the PC value or compressed PC value corresponding to the NTSHT entry pointed to by CSR1.

[0031] This disclosure introduces a novel microarchitectural feature called the "Non-Temporary Storage Hint Table" (NTSHT) to optimize non-temporary storage (especially streaming storage) in RISC-V architectures. Programming the NTSHT can be achieved, for example, through two user-mode CSRs. Applications can program the NTSHT to inform the microarchitecture which memory operations are non-temporary. Through, for example, developer identification, performance profiling, or the use of inline functions, applications can identify the PC addresses corresponding to non-temporary storage instructions and load these addresses into the NTSHT before program execution. During runtime, storage instructions with PC matches are executed as non-temporary instructions, and their data is written directly to main memory, bypassing all cache levels. This disclosure enables RISC-V processors to enhance support for non-temporary storage access without introducing new instructions.

[0032] Figure 2A flowchart illustrating a method 200 for implementing non-temporary storage in a RISC-V processor according to an embodiment of the present disclosure is shown. Method 200 may include steps S202, S204, and S206. However, in some embodiments, method 200 may include more or fewer different steps, which is not limited by the present disclosure.

[0033] In step S202, the non-temporary storage hint table NTSHT associated with the process is obtained. NTSHT is used to record the corresponding instruction address of one or more non-temporary storage instructions in the process.

[0034] In one embodiment, NTSHT may include a streaming storage hint table (SSHT), which may be used to record the instruction addresses of one or more streaming storage instructions in a process.

[0035] In embodiments of this disclosure, the instruction address recorded in NTSHT may include: the program counter address of a non-temporary storage instruction (e.g., a streaming storage instruction), the hash value of the program counter address, or the compressed value of the program counter address.

[0036] In embodiments of this disclosure, the NTSHT can be part of the process context. In embodiments of this disclosure, the NTSHT can be bound to the hardware context of a thread, and its contents can be saved and restored along with the thread context when the RISC-V processor switches contexts between different threads.

[0037] In step S204, when a process is running on a RISC-V processor, a lookup is performed in NTSHT for the address of the instruction to be executed stored instruction in the process.

[0038] In embodiments of this disclosure, the NTSHT is preferably implemented as a fully associative structure. In this configuration, the lookup operation is performed by comparing the instruction address of the store instruction to be executed with all entries in the NTSHT in parallel. Specifically, the memory cell compares the program counter value of the store instruction to be executed with each entry in the NTSHT simultaneously. When a match occurs, the store instruction is identified as a non-temporary store instruction and the corresponding optimized execution mode is triggered.

[0039] It is understood that, in scenarios with a limited number of entries (typically 16 to 32), a fully associative design maximizes hardware resource utilization and completely avoids mapping conflicts, making it the optimal choice for achieving a high hit rate. Furthermore, this disclosure does not limit the specific hardware implementation structure of NTSHT. Based on different design goals (such as area, power consumption, or timing), those skilled in the art can also use other equivalent variant structures to implement NTSHT, and these implementations all fall within the protection scope of this disclosure.

[0040] In step S206, in response to a hit in NTSHT, the store instruction to be executed is executed in non-temporary storage mode, wherein, in non-temporary storage mode, the data to be stored for the store instruction is directly written to main memory by bypassing the processor's multi-level cache.

[0041] Specifically, when a hit occurs, the store instruction is identified as a non-temporary store instruction. For example, in response to a store instruction hit in SSHT, the store instruction can be determined to be a streaming store instruction. At this point, the data to be stored is directly transferred from the processor's execution unit into the memory subsystem, ultimately bypassing all levels of cache (such as L1, L2, and L3 caches) and reaching main memory directly. This process eliminates the latency and power overhead caused by data movement, replacement, and consistency maintenance between cache levels. It is particularly suitable for large-scale sequential data (e.g., streaming data) that is written once and not accessed again in a short period, thereby significantly improving memory bandwidth utilization and reducing pollution of shared cache resources.

[0042] Figure 3 A flowchart illustrating a method 300 for configuring a non-temporary storage prompt table according to an embodiment of the present disclosure is shown. Figure 3 As shown, method 300 may include steps S302, S304, and S306. However, in some embodiments, method 300 may include more or fewer different steps, which is not limited in this disclosure.

[0043] In step S302, the instruction addresses of non-temporary storage instructions in the process are identified by analyzing the instruction stream of the application corresponding to the process.

[0044] In embodiments of this disclosure, the analysis of the application's instruction flow includes static analysis performed by compiler tools. In embodiments of this disclosure, the analysis of the application's instruction flow includes runtime-based performance profiling performed by a program profiling tool. In one embodiment, the program profiling tool is a profiling-guided optimization (PGO) tool.

[0045] In embodiments of this disclosure, non-temporary storage instructions in an application or process can be identified by the developer during the development phase.

[0046] In step S304, a CSR operation instruction is generated to write the instruction address of the identified non-temporary storage instruction to NTSHT.

[0047] In step S306, the NTSHT is configured by executing the generated CSR operation instructions and utilizing multiple preset CSRs in the RISC-V processor.

[0048] In embodiments of this disclosure, the multiple CSRs that the CSR operation instructions can operate on may include: a first CSR and a second CSR, and wherein configuring NTSHT using multiple preset CSRs in the RISC-V processor may include: loading the entry index of NTSHT by writing to the first CSR (CSR1); and loading the non-temporary storage instruction address (e.g., streaming storage instruction address) corresponding to the entry index by writing to the second CSR (CSR2).

[0049] Figure 4 An exemplary schematic diagram illustrating the configuration of NTSHT using CSR1 and CSR2 according to embodiments of the present disclosure is shown. Specifically, NTSHT can be configured by performing the following operations on CSR1 and CSR2:

[0050] (1) First step: Write the first entry ID to CSR1, for example, write 0 to CSR1;

[0051] (2) Second step: Write the PC value of the first non-temporary storage instruction (e.g., the first streaming storage instruction) to CSR2, for example, write 0x003 to CSR2;

[0052] (3) Third step: Repeat the first step (write 1 to CSR1), and then repeat the second step (write 0x008 to CSR2).

[0053] (4) Fourth step: Repeat the first step (write 2 to CSR1), and then repeat the second step (write 0x100 to CSR2).

[0054] (5) ... Subsequent entries are similar to steps three and four.

[0055] RISC-V defines a separate address space containing 4096 control status registers for each hardware process. While CSRs are primarily used by the privileged architecture, they are also used in non-privileged (user-level) code, including for counters and timers, and for managing floating-point operation states. Therefore, in embodiments of this disclosure, the CSRs used to configure NTSHT (e.g., CSR1 and CSR2) can be user-mode accessible CSRs.

[0056] In embodiments of this disclosure, the addresses of the CSRs (e.g., CSR1 and CSR2) used to configure NTSHT can be located within the custom read / write CSR address space reserved in the RISC-V privileged architecture standard. Table 1 shows the available address space for non-privileged user-level CSRs in the RISC-V architecture, defining the encoding of different CSR addresses, their corresponding hexadecimal address ranges, and access permissions / purposes. As shown in Table 1, the address range 0x800-0x8FF is explicitly reserved for custom, read / write-enabled CSRs. In one embodiment, the CSRs (e.g., CSR1 and CSR2) used to configure NTSHT can be located within the address range of 0x800-0x8FF.

[0057] Table 1

[0058]

[0059] In embodiments of this disclosure, the CSR operation instruction for writing the instruction address of the identified non-temporary storage instruction (e.g., streaming storage instruction) to the NTSHT (e.g., SSHT) may include: CSR read / write instructions with SYSTEM opcodes defined in the RISC-V instruction set standard. In the RISC-V architecture, CSR instructions use the "SYSTEM" opcode, which predefines six instructions for CSR read / write: CSR Read After Write (CSRRW), CSR Immediate Read After Write (CSRRWI), CSR Read After Set (CSRRS), CSR Immediate Read After Set (CSRRSI), CSR Read After Clear (CSRRC), and CSR Immediate Read After Clear (CSRRCI).

[0060] Figure 5 The diagram illustrates the encoding format of CSR read / write instructions with the SYSTEM opcode. These CSR read / write instructions can be reused to operate on CSR1 (e.g., address 0x800) and CSR2 (e.g., 0x804), thereby enabling flexible configuration of NTSHT (e.g., SSHT) without introducing non-standard instructions.

[0061] Preferably, the write operation to the CSR can be implemented by executing the CSRRW and / or CSRRWI instructions defined in the RISC-V instruction set architecture. Since the programming of NTSHT in this embodiment only involves writing the complete preset value to the CSR, without performing bit-by-bit or clear-bit operations, the CSRRW / CSRRWI instructions can meet all programming requirements.

[0062] Table 2 shows an example encoding scheme for CSR instructions used to program NTSHT. As shown in Table 2, this embodiment reuses the CSRRW and CSRRWI instruction formats under the SYSTEM main opcode (1110011) in the RISC-V instruction set standard. The target register is distinguished by different values ​​of the csr field: when the csr field is 0x800, the operand is CSR1 (used to specify the NTSHT entry index); when the csr field is 0x804, the operand is CSR2 (used to write the address of a non-temporary storage instruction). The data source is distinguished by different encodings of the func3 field: 001 indicates that the source operand comes from the general-purpose register rs1 (corresponding to the CSRRW instruction), and 101 indicates that the source operand is a 5-bit zero-extension immediate value uimm (corresponding to the CSRRWI instruction). This encoding scheme strictly follows the RISC-V architecture specification, implementing a complete programming interface for NTSHT without the need for new instruction extensions. It can be understood that the encoding shown in Table 2 is an exemplary implementation method conforming to the RISC-V standard. Without departing from the core idea of ​​this invention, those skilled in the art can also use other equivalent coding methods under this architecture specification to implement the CSR operation instructions.

[0063] Table 2

[0064]

[0065] In embodiments of this disclosure, method 300 may further include: inserting the generated CSR operation instruction at the beginning of the instruction stream of the application corresponding to the process, such that the CSR operation instruction is automatically executed when the process is running to complete the writing of NTSHT without interrupting the process.

[0066] In practice, to enable a program (especially a pre-compiled binary program) to utilize non-temporary memory storage characteristics, instructions for programming two specific CSRs need to be inserted into the program. To minimize the impact on the original program execution flow, in one embodiment, the aforementioned CSR operation instructions can be inserted at the very beginning of the program instruction stream.

[0067] Figure 6 This is an exemplary schematic diagram illustrating the insertion of CSR operation instructions into the instruction stream of an application according to embodiments of this disclosure. Figure 6As shown, if the application analyzes and identifies the third instruction, Store 003 (i.e., the store instruction with program counter 0x003), as a non-temporary store instruction, then two CSR write instructions are inserted at the beginning of the application's instruction stream: the first instruction writes 1 to CSR1, indicating the operation of the first entry of NTSHT; the second instruction writes 003 to CSR2, writing the value 003 into entry 1 of NTSHT, thus marking the third instruction as a non-temporary store instruction (e.g., a streaming store instruction). In this way, the programming configuration of NTSHT is completed without affecting the original instruction stream.

[0068] This approach is well-suited for Profiling Guided Optimization (PGO), especially when non-temporary storage is used for streaming storage, as PGO typically targets binary programs and avoids recompiling the source code. This is particularly beneficial in data center scenarios: NTSHT can be programmed and configured online without interrupting program execution, enabling streaming operation optimizations for the corresponding storage instructions.

[0069] This disclosure enables RISC-V processors to enhance support for non-temporary memory access without introducing new instructions. Users can utilize non-temporary memory capabilities without recompiling their applications; they only need to insert a few instructions at the beginning of the program to configure the prompt table.

[0070] The RISC-V non-temporary storage technology disclosed herein is suitable for various computing scenarios involving large-scale, sequential data write operations, effectively improving memory subsystem efficiency and reducing cache pollution. Typical applications include: large-scale sequential write scenarios (data volume exceeding the capacity of the last-level (L3) cache), such as frame data writing for video encoding / decoding, large array initialization filling, and memory region copying operations; and streaming computing task scenarios, such as scientific simulations, image / signal processing, and database batch operations. In these scenarios, this disclosure significantly improves execution efficiency and overall system performance by identifying and optimizing such storage instructions.

[0071] This disclosure boasts extremely low hardware implementation costs, offering high design feasibility and cost-effectiveness. The non-temporary memory hint table only needs to store the virtual addresses of frequently used non-temporary memory instructions (typically 39-bit or 48-bit in RISC-V architecture). With 16 to 32 entries, it can cover most application requirements, with static storage overhead ranging from 624 bits (39 bits × 16) to 1536 bits (48 bits × 48), resulting in negligible impact on chip area. The core hardware implementation involves comparing the address of a running memory instruction with the hint table entry, requiring only a one-bit hit / miss signal. This comparison logic is simple and easily integrated into the processor pipeline. To further reduce resource consumption, a hash function can be introduced to compress and store addresses during comparison. This optimization, even if a hash collision leads to a mismatch, only incurs a slight performance penalty without affecting functional correctness, thus ensuring the overall robustness of the system.

[0072] Compared to traditional storage methods that rely on explicit software management (such as by referencing new non-temporary storage instructions) or lack hardware optimization, this disclosure delivers significant performance improvements through transparent optimization at the microarchitecture level.

[0073] This disclosure defines a streamlined NTSHT hardware architecture and a corresponding software-transparent configuration and management mechanism, enabling RISC-V processors to achieve significant performance gains without modifying application source code or binary code. This not only enhances the competitiveness of RISC-V processors in high-performance computing and data center scenarios, but also provides efficient streaming data processing capabilities for a wide range of applications due to its low-cost hardware implementation and flexible software interfaces.

[0074] Figure 7 This is a block diagram illustrating components capable of reading instructions from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium) and performing any one or more of the methods discussed herein, according to some example embodiments. Specifically, Figure 7 A schematic diagram of hardware resource 700 is shown, which includes one or more processors (or processor cores) 710, one or more memory / storage devices 720, and one or more communication resources 730, wherein each of these processors, memory / storage devices, and communication resources can be communicatively coupled via bus 740 or other interface circuitry. For embodiments utilizing node virtualization (e.g., Network Functions Virtualization (NFV)), a hypervisor 702 can be executed to provide an execution environment for one or more network slices / subslices, thereby utilizing hardware resource 700.

[0075] Processor 710 may include, for example, processor 712 and processor 714. Processor 710 may be, for example, a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP) such as a baseband processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a radio frequency integrated circuit (RFIC), another processor (including those discussed herein), or any suitable combination thereof.

[0076] The memory / storage device 720 may include main memory, disk storage devices, or any suitable combination thereof. The memory / storage device 720 may include, but is not limited to, any type of volatile, non-volatile, or semi-volatile memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, solid-state memory, etc.

[0077] Communication resource 730 may include interconnect or network interface controllers, components, or other suitable devices for communicating with one or more peripheral devices 704 or one or more databases 706 or other network elements via network 708. For example, communication resource 730 may include wired communication components (e.g., for coupling via USB, Ethernet, etc.), cellular communication components, near field communication (NFC) components, Bluetooth® (or Bluetooth® Low Energy) components, Wi-Fi® components, and other communication components.

[0078] Instruction 750 may include software, a program, application program, applet, or other executable code for causing at least any one of the processors 710 to perform any one or more of the methods discussed herein. Instruction 750 may reside wholly or partially within processor 710 (e.g., in the processor's cache), memory / storage device 720, or any suitable combination thereof. Furthermore, any portion of instruction 750 may be transferred from any combination of peripheral device 704 or database 706 to hardware resource 700. Therefore, the memory of processor 710, memory / storage device 720, peripheral device 704, and database 706 are examples of computer-readable and machine-readable media.

[0079] Some examples may be implemented or be implemented as an article of art or at least a computer-readable medium. The computer-readable medium may include a non-transitory storage medium for storing logic. In some examples, the non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, and so on. In some examples, the logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computational code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.

[0080] According to some examples, computer-readable media may include non-transitory storage media to store or maintain instructions that, when executed by a machine, computing device, or system, cause that machine, computing device, or system to perform methods and / or operations according to the described examples. Instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, etc. Instructions may be implemented according to a predetermined computer language, manner, or syntax to instruct a machine, computing device, or system to perform specific functions. Instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled, and / or interpreted programming language.

[0081] One or more aspects of at least one example can be implemented by representative instructions representing various logic within a processor, stored on at least one machine-readable medium, which, when read by a machine, computing device, or system, cause the machine, computing device, or system to manufacture logic to perform the techniques described herein. This representation, referred to as an "IP core," can be stored on a tangible machine-readable medium and provided to various customer or manufacturing facilities for loading into the manufacturing machine that actually manufactures the logic or processor.

[0082] The phrase "an example" or "an example" does not necessarily refer to the same example or embodiment. Any aspect described herein may be combined with any other aspect or similar aspect described herein, whether or not these aspects are described with reference to the same drawings or elements. The division, omission, or inclusion of block functions depicted in the drawings does not imply that hardware components, circuits, software, and / or elements used to implement these functions will necessarily be divided, omitted, or included in the embodiments.

[0083] Examples can be described using the terms “coupling” and “connection” and their derivatives. These terms are not necessarily intended to be synonyms. For example, a description using the terms “connection” and / or “coupling” may indicate that two or more elements are in direct physical or electrical contact with each other. However, the term “coupling” may also refer to two or more elements that are not in direct contact with each other but still cooperate or interact with each other.

[0084] The terms “first,” “second,” and the like are not used herein to indicate any order, quantity, or importance, but rather to distinguish one element from another. The term “a” herein does not imply a limitation on quantity, but rather indicates the presence of at least one mentioned item. The term “assertion” as used herein when referring to a signal refers to a state in which the signal is valid and can be achieved by applying any logic level (whether logic 0 or logic 1) to the signal. The terms “subsequently” or “afterward” can mean immediately following or following one or more other events. According to alternative embodiments, other sequences of steps may also be performed. Furthermore, depending on the specific application, additional steps may be added or removed. Any combination of variations can be used, and many variations, modifications, and alternative embodiments will be understood by those skilled in the art who benefit from this disclosure.

[0085] Unless otherwise specifically stated, disjunctive language such as the phrase "at least one of X, Y, or Z" is understood in context to generally state that an item, term, etc., can be X, Y, or Z, or any combination thereof (e.g., X, Y, and / or Z). Thus, such disjunctive language is generally not intended, nor should it imply, that certain embodiments require the presence of each of at least one X, at least one Y, or at least one Z. Furthermore, unless otherwise specifically stated, connective language such as the phrase "at least one of X, Y, and Z" should also be understood to refer to X, Y, Z, or any combination thereof, including "X, Y, and / or Z".

Claims

1. A method for implementing non-temporary storage in a RISC-V processor, comprising: Obtain a non-temporary storage hint table associated with the process, wherein the non-temporary storage hint table is used to record the corresponding instruction address of one or more non-temporary storage instructions in the process; When the process is running on the RISC-V processor, a lookup is performed in the non-temporary memory hint table for the address of the instruction to be executed in the process. In response to a hit in the non-temporary storage hint table, the pending storage instruction is executed in non-temporary storage mode, wherein, in non-temporary storage mode, the data to be stored in the pending storage instruction is directly written to main memory by bypassing the processor's multi-level cache. The prompt table for retrieving non-temporary storage associated with a process includes: By analyzing the instruction stream of the application corresponding to the process, the instruction addresses of non-temporary storage instructions in the process can be identified; Generate a control status register operation instruction for writing the instruction address of the identified non-temporary storage instruction into the non-temporary storage prompt table; and By executing the generated control status register operation instructions, the non-temporary storage hint table can be configured using multiple preset control status registers in the RISC-V processor.

2. The method according to claim 1, wherein, The plurality of control status registers includes a first control status register and a second control status register, and wherein configuring the non-temporary storage hint table using the plurality of preset control status registers in the RISC-V processor includes: The entry index of the non-temporary storage prompt table is loaded by writing to the first control status register; and The non-temporary storage instruction address corresponding to the entry index is loaded by writing to the second control status register.

3. The method according to claim 2, wherein, The control status register operation instructions include: control status register read and write instructions with SYSTEM opcodes as defined in the RISC-V instruction set standard.

4. The method according to claim 3, wherein, The control status register operation instructions include: control status register read-after-write CSRRW and / or control status register immediate value read-after-write CSRRWI.

5. The method according to claim 1, wherein, The plurality of control status registers are user-mode accessible control status registers.

6. The method according to claim 5, wherein, The addresses of the multiple control status registers are located within the custom read / write control status register address space reserved in the RISC-V privileged architecture standard.

7. The method according to claim 6, wherein, The addresses of the multiple control status registers are in the address range of 0x800-0x8FF.

8. The method according to claim 1, further comprising: The generated control status register operation instructions are inserted at the beginning of the application's instruction stream, so that the control status register operation instructions are automatically executed when the process is running to complete the writing to the non-temporary storage hint table without interrupting the process's execution.

9. The method according to claim 8, wherein, The analysis of the instruction flow of the application includes static analysis performed by compiler tools.

10. The method according to claim 8, wherein, The analysis of the instruction flow of the application includes runtime-based performance profiling performed by a program profiling tool.

11. The method according to claim 10, wherein, The program profiling tool is a Profiling Guided Optimization (PGO) tool.

12. The method according to claim 1, wherein, The instruction addresses recorded in the non-temporary storage prompt table include: the program counter address of the non-temporary storage instruction, the hash value of the program counter address, or the compressed value of the program counter address.

13. The method according to claim 1, wherein, The non-temporary storage hint table is part of the process context of the process, and when the process supports multithreading, the non-temporary storage hint table is shared by the multiple threads.

14. The method according to claim 1, wherein, The non-temporary storage hint table is implemented as a fully associative structure, and the lookup operation is performed by comparing the instruction address of the storage instruction to be executed with all entries in the non-temporary storage hint table in parallel.

15. The method according to any one of claims 1-14, wherein, The non-temporary storage instructions include streaming storage instructions, and the non-temporary storage prompt table includes a streaming storage prompt table.

16. An apparatus for implementing non-temporary storage in a RISC-V processor, wherein, The apparatus includes a processor circuit configured to perform the method of any one of claims 1-15.

17. A computer-readable storage medium having instructions stored thereon, wherein the instructions, when executed by a processor, cause the processor to perform the method according to any one of claims 1-15.

18. A computer program product comprising instructions, wherein the instructions, when executed by a processor, cause the processor to perform the method according to any one of claims 1-15.

Images