Cache manager and control component

Abstract

The invention provides a cache manager and a control component. Wherein the cache manager comprises an interface, a distribution module and a memory, and the interface receives a cache distribution request and sends the cache distribution request to the distribution module; the interface receives the first cache index information returned by the distribution module and outputs the first cache index information; in response to the cache allocation request, the allocation module reads data in the memory to obtain indexes of N idle storage blocks and generate first cache index information, the storage blocks are located in the cache, N is a positive integer, and the first cache index information comprises the indexes of the N storage blocks; the memory stores an index of a plurality of memory blocks. According to the technical scheme, the cache manager realized by hardware is used for replacing software management cache in the prior art, so that the number of times of interaction between the software and the hardware during cache allocation in the control component is reduced, the information interaction speed in the control component is improved, and the technical effect of reducing the time of data transmission from a host to a flash memory chip is achieved.

Description

Technical Field

[0001] This application relates to storage technology, and in particular to cache managers and control components. Background Technology

[0002] Figure 1 A block diagram of a solid-state storage device (SSD) is shown. The SSD 102 is coupled to a host computer to provide storage capabilities. The host computer and the SSD 102 can be coupled in various ways, including but not limited to connections via SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIe (Peripheral Component Interconnect Express), NVMe (NVM Express), Ethernet, Fibre Channel, and wireless communication networks. The host computer can be an information processing device capable of communicating with the storage device via the above methods, such as a personal computer, tablet computer, server, laptop computer, network switch, router, cellular phone, or personal digital assistant. Storage device 102 includes interface 103, control unit 104, one or more NVM chips 105, and DRAM (Dynamic Random Access Memory) 110.

[0003] Common types of NVMs include NAND flash memory, phase-change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), and XPoint memory.

[0004] Interface 103 is compatible with exchanging data with the host via methods such as SATA, IDE, USB, PCIe, NVMe, SAS, Ethernet, and Fibre Channel.

[0005] The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the DRAM 110. It is also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, etc. The control unit 104 can be implemented in various ways, including software, hardware, firmware, or a combination thereof. For example, the control unit 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control unit 104 may also include a processor or controller, in which software executes to manipulate the hardware of the control unit 104 to process I / O (Input / Output) commands. The control unit 104 can also be coupled to the DRAM 110 and access the data in the DRAM 110. FTL tables and / or cached I / O command data can be stored in the DRAM.

[0006] The control unit 104 includes a flash interface controller (or media interface controller, flash channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in accordance with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives the command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

[0007] With the rapid growth of information volume, each data transfer between storage devices and the host carries a large amount of data. Furthermore, due to the limitations of flash memory storage characteristics, direct data transfer between the host and flash memory is not possible. Therefore, current control components typically incorporate a buffer to temporarily store data to be transferred. With this buffer, the data transfer process is divided into two stages: one between the host and the buffer, and the other between the buffer and the storage device. Thus, while existing technology enables data transfer from the host to the flash memory chip, dividing the data transfer into two stages inevitably increases the number of internal information exchanges within the control component, resulting in a long data transfer time between the host and the flash memory chip. Summary of the Invention

[0008] To address the technical problem of long data transfer time between the host and the flash memory chip in the prior art, this application provides a cache manager and control components.

[0009] According to a first aspect of this application, a first cache manager according to the first aspect of this application is provided, including an interface, an allocation module, and a memory, wherein the interface receives a cache allocation request and sends the cache allocation request to the allocation module; and the interface receives first cache index information returned by the allocation module and outputs the first cache index information; in response to the cache allocation request, the allocation module allocates N free storage blocks and generates the first cache index information, wherein the storage blocks are located in the cache, N is a positive integer, and the first cache index information includes the indices of the N storage blocks; the memory stores the indices of at least N storage blocks.

[0010] In this embodiment, a hardware-implemented cache manager is used instead of the software-managed cache in the prior art, thereby reducing the number of interactions between software and hardware when allocating cache in the control unit, improving the information interaction speed within the control unit, and achieving the technical effect of reducing the data transmission time between the host and the flash memory chip.

[0011] According to the first cache manager of the first aspect of this application, a second cache manager according to the first aspect of this application is provided, the cache manager further comprising a release module, wherein the interface receives a cache release request and sends the cache release request to the release module, the cache release request carrying second cache index information, the second cache index information including indices of M storage blocks to be released, the storage blocks to be released being located in the cache, and M being a positive integer; in response to the cache release request, the release module writes the indices of the M storage blocks into the memory, so that the storage blocks to be released become free storage blocks.

[0012] According to the first or second cache manager of the first aspect of this application, a third cache manager according to the first aspect of this application is provided, wherein the memory includes at least one storage space, each storage space having an equal length, and each storage space storing an index of a storage block.

[0013] According to one of the first to third cache managers of the first aspect of this application, a fourth cache manager according to the first aspect of this application is provided. The allocation module manages a first pointer, which points to a first storage space. The first storage space stores the indexes of free storage blocks, and two adjacent storage spaces on both sides of the first storage space respectively store the indexes of free storage blocks and the indexes of allocated storage blocks. When allocating the N storage blocks, the allocation module reads the indexes of N storage blocks from the N consecutive storage spaces starting from the first storage space. The first pointer is modified so that it points to a second storage space, which is the (N+1)th storage space starting from the first storage space, and the second storage space stores the indexes of free storage blocks.

[0014] According to one of the first to fourth cache managers of the first aspect of this application, a fifth cache manager according to the first aspect of this application is provided. The release module manages a second pointer, which points to a third storage space. The third storage space stores the indexes of allocated storage blocks, and two adjacent storage spaces on both sides of the third storage space respectively store the indexes of free storage blocks and the indexes of allocated storage blocks. When writing the indexes of the M storage blocks to the memory, the release module obtains the indexes of the M storage blocks from the cache release request. The indexes of the M storage blocks are sequentially written to the M consecutive storage spaces starting from the third storage space. The second pointer is modified so that it points to a fourth storage space, which is the (M+1)th storage space starting from the third storage space, and the fourth storage space stores the indexes of allocated storage blocks.

[0015] According to the third cache manager of the first aspect of this application, a sixth cache manager according to the first aspect of this application is provided, wherein the indexes of the storage blocks are stored in the memory in the form of an array or a linked list, the array or linked list corresponding to the at least N storage spaces.

[0016] According to a second aspect of this application, a first control component according to the second aspect of this application is provided, comprising a command manager, a first direct memory access (DMA) unit, a second DMA unit, a cache, and a cache manager as described in any one of the first aspects above, wherein the command manager sends a first data transfer request to the first DMA unit, the first data transfer request including a source address and an operating mode; when the operating mode is a first mode, in response to the first data transfer request, the first DMA unit accesses the source address, obtains first data in the source address, and sends a cache allocation request to the cache manager; in response to the cache allocation request, the cache manager allocates N storage blocks and returns cache index information to the first DMA unit; after receiving the cache index information, the first DMA unit transfers the first data to the N storage blocks according to the indices of the N storage blocks.

[0017] According to the first control component of the second aspect of this application, a second control component according to the second aspect of this application is provided, wherein when the working mode in the first data transfer request is the second mode, the first data transfer request further includes a target address; before sending the first data transfer request to the first DMA unit, the command manager sends the cache allocation request to the cache manager; in response to the cache allocation request, the cache manager allocates the N storage blocks for the first data and returns cache index information to the command manager; the command manager obtains the target address according to the index of the N storage blocks.

[0018] According to the second control component of the second aspect of this application, a third control component according to the second aspect of this application is provided, wherein, in the second operating mode, in response to the first data transfer request, the first DMA unit transfers the first data from the storage space corresponding to the source address to the N storage blocks.

[0019] According to one of the first to third control components of the second aspect of this application, a fourth control component according to the second aspect of this application is provided. Before sending a first data transfer request to the first DMA unit, the command manager obtains a first command and generates the first data transfer request according to the first command. The first command is a read command or a write command. When the first command is a write command, the source address in the first data transfer request is a host address. When the first command is a read command, the source address in the first data transfer request points to flash memory.

[0020] According to one of the first to fourth control components of the second aspect of this application, a fifth control component according to the second aspect of this application is provided. After the first data is moved to the N storage blocks, the first DMA unit returns completion information to the command manager to indicate that the first data has been moved to the cache. After receiving the completion information, the command manager sends a second data move request to the second DMA unit, the second data move request including a source address and a target address. In response to the second data move request, the second DMA unit accesses the source address, obtains the second data in the source address, and moves the second data to the storage space corresponding to the target address.

[0021] According to the fifth control component of the second aspect of this application, a sixth control component according to the second aspect of this application is provided, wherein when the first command is a write command, the source address in the second data transfer request is the physical address of the N storage blocks, and the target address points to the flash memory; when the first command is a read command, the source address in the second data transfer request is the physical address of the N storage blocks, and the target address points to the host.

[0022] According to one of the first to fourth control components of the second aspect of this application, a seventh control component according to the second aspect of this application is provided. When the first data is moved to the N storage blocks, the first DMA unit divides the first data into N first messages and moves the N first messages to the N storage blocks in sequence. Each storage block stores a different first message, and each first message has the same length.

[0023] According to the seventh control component of the second aspect of this application, an eighth control component according to the second aspect of this application is provided, wherein the first data transfer request further includes a feedback mode, the feedback mode indicating that for every X first messages transferred, the first DMA unit returns a completion message to the command manager, wherein X is a positive integer less than or equal to N.

[0024] According to the first or sixth control component of the second aspect of this application, a ninth control component according to the second aspect of this application is provided. After the second data is moved to the storage space corresponding to the target address, the second DMA unit sends a cache release request to the cache manager. The cache release request carries the index of the storage block where the second data is located. In response to the cache release request, the cache manager saves the index of the storage block where the second data is located to complete the resource release of the storage block where the second data is located.

[0025] This application provides a cache manager to manage cache allocation and release, replacing the cache management function of the firmware in the control unit, thereby reducing the number of software and hardware interactions in the control unit. This application employs a faster hardware-to-hardware interaction method to solve the problem of long data transmission time between the host and flash memory chip in the prior art, thereby improving the interaction speed of the control unit during data transmission, and ultimately increasing the data transmission speed of the control unit and reducing data transmission time. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0027] Figure 1 A block diagram of a storage device in the prior art; Figure 2A This is a schematic diagram of the structure of the cache manager provided in an embodiment of this application; Figure 2B This is a schematic diagram illustrating the state of data storage in a memory provided in an embodiment of this application; Figure 2C A schematic diagram illustrating the relationship between storage space and pointers provided in the embodiments of this application; Figure 3A This is a schematic diagram of the structure of the control component provided in an embodiment of this application; Figure 3B A schematic diagram illustrating the process of a control component executing a read command, as provided in an embodiment of this application; Figure 4A This is a schematic diagram of the structure of the DMA unit provided in the embodiments of this application; Figure 4B This is a schematic diagram illustrating the data storage and transmission of the trigger provided in an embodiment of this application. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0029] The terms "first," "second," and "third," etc., in this application description, claims, and drawings are used to distinguish different objects, not to define a specific order. Furthermore, the terms "comprising" and "having," and their various variations, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or modules is not limited to the listed steps or units, but may optionally include steps or modules not listed, or may optionally include other steps or modules inherent to these processes, methods, products, or apparatuses.

[0030] The term "embodiment" as used in this application means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It will be explicitly or implicitly understood by those skilled in the art that the embodiments described in this application can be combined with other embodiments.

[0031] In this application, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B represents three possibilities: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0032] Figure 2A The diagram below illustrates the structure of a cache manager. Figure 2AAs shown, the cache manager 200 includes an interface 201, an allocation module 202, a memory 203, and a release module 204. The interface 201 is coupled to the allocation module 202 and also to the release module 204. Both the allocation module 202 and the release module 204 are coupled to the memory 203.

[0033] Interface 201 receives a cache allocation request and sends it to allocation module 202. In response to the cache allocation request, allocation module 202 allocates N free storage blocks and generates first cache index information. The storage blocks are located within the cache, N is a positive integer, and the first cache index information includes the indices of the N storage blocks. Allocation module 202 feeds back the first cache index information to interface 201. Interface 201 receives the first cache index information returned by allocation module 202 and outputs the first cache index information. Memory 203 stores the indices of at least N storage blocks. N is a positive integer, for example, N equals 64.

[0034] Specifically, the allocation module 202 manages the data stored in the memory 203. After receiving a cache allocation request, the allocation module 202 reads the data in the memory 203 and obtains the indices of N free storage blocks.

[0035] Interface 201 also receives cache release requests and sends them to release module 204. The cache release request carries second cache index information, which includes the indices of M storage blocks to be released, where M is a positive integer. In response to the cache release request, release module 204 writes the indices of the M storage blocks to memory 203, thus making the storage blocks to be released free.

[0036] In this application, all storage blocks are located within the cache, and there is a mapping relationship between the cache and the cache manager 200, but the cache and the cache manager 200 do not necessarily need to be coupled. Except for storage blocks that are used for the first time or whose data has been erased, which are usually empty, the free storage blocks and storage blocks awaiting release within the cache typically contain data. The difference between free and storage blocks awaiting release is that the data in free storage blocks has already completed the data transfer between the host and the flash memory chip, meaning the data in free storage blocks does not need to be used further. The data in storage blocks awaiting release has not yet completed the data transfer between the host and the flash memory chip, meaning the data in storage blocks awaiting release is still in use.

[0037] Optionally, for ease of management, the memory 203 includes at least one storage space. When the memory 203 includes multiple storage spaces, each storage space has an equal length, and each storage space stores an index of a storage block. For example, Figure 2B A schematic diagram is provided showing that the memory 203 includes 50 memory spaces. Figure 2BEach storage space in the system is 4 bytes long, and the index of the storage block within each storage space is also 4 bytes. In this embodiment, the length of the storage space can be adjusted according to the length of the storage block index, and is not limited here.

[0038] Further optionally, the indices of the storage blocks in memory 203 are stored in the form of an array or linked list, which corresponds to at least N storage spaces. For example, Figure 2B The 50 storage spaces in the array correspond to the form of an array.

[0039] Optionally, in this embodiment, the allocation module 202 and the release module 204 utilize pointers to manage the data in the memory 203.

[0040] Specifically, Figure 2C A schematic diagram showing the relationship between storage space, the first pointer, and the second pointer is provided. Figure 2C There are a total of 40 storage spaces. For example... Figure 2C As shown, the allocation module 202 manages the first pointer 205, which points to the first storage space C31. The first storage space C31 stores the indexes of free storage blocks. The two adjacent storage spaces on either side of the first storage space C31 (C30 and C32) respectively store the indexes of free storage blocks and the indexes of allocated storage blocks. Specifically, storage space C32 stores the indexes of free storage blocks, and storage space C30 stores the indexes of allocated storage blocks. When allocating N storage blocks, the allocation module 202 reads the indices of N storage blocks from the N consecutive storage spaces starting from the first storage space C31; it then modifies the first pointer 205 to point to the second storage space, which is the (N+1)th storage space starting from the first storage space C31, and stores the indexes of free storage blocks. For example, if N=5, then the second storage space is storage space C36.

[0041] See also Figure 2CThe release module 204 manages the second pointer 207, which points to the third storage space C15. The third storage space C15 stores the indexes of allocated storage blocks. The two adjacent storage spaces on either side of the third storage space C15 (C14 and C16) store the indexes of free storage blocks and the indexes of allocated storage blocks, respectively. Storage space C14 stores the index of free storage blocks, and storage space C16 stores the index of allocated storage blocks. When writing the indexes of M storage blocks to memory 203, the release module 204 obtains the indexes of M storage blocks from the cache release request; it then writes the indexes of the M storage blocks sequentially to the M consecutive storage spaces starting from the third storage space C15; it modifies the second pointer 207 to point to the fourth storage space, which is the (M+1)th storage space starting from the third storage space C15, and stores the indexes of allocated storage blocks. For example, if M=10, then the fourth storage space is storage space C25.

[0042] See Figure 3A The control unit 300 includes a command manager 301, a direct memory access (DMA) unit 302, a DMA unit 303, a cache 304, and a cache manager 200 as described in the above embodiments. The command manager 301 generates a first data transfer request or a second data transfer request in response to a received read / write command. The control unit 300 is coupled to the host 310 and the flash memory chip 320.

[0043] Both read and write commands instruct data to be transferred between the host and the flash memory chip. However, since data cannot be directly transferred between the host and the flash memory chip, existing technologies typically use a cache (e.g., Dynamic Random Access Memory, DRAM) as a data transfer intermediary. Therefore, when executing a read or write command, data transfer is divided into two stages: one stage involves data transfer between the host and the cache, and the other stage involves data transfer between the cache and the flash memory chip. In this embodiment, the first data transfer request and the second data transfer request correspond to these two stages. For example, when command manager 301 receives a read command, the first data transfer request generated by command manager 301 instructs the first data to be transferred from flash memory chip 320 to cache 304, and the second data transfer request generated by command manager 301 instructs the second data to be transferred from cache 304 to host 310. For example, when command manager 301 receives a write command, it generates a first data transfer request based on the write command to transfer the first data from host 310 to cache 304. Then, it generates a second data transfer request to transfer the second data from cache 304 to flash memory chip 320. In this embodiment, the first data is data whose source address points to host 310 or flash memory chip 320, and the second data is data whose source address points to cache 304. It should be noted that in this application, the first DMA unit is the DMA unit that executes the first data transfer request, and the second DMA unit is the DMA unit that executes the second data transfer request. Figure 3A The DMA units 302 and DMA units 303 in this application can execute both the first data transfer request and the second data transfer request. That is, the first DMA unit and the second DMA unit in this application are not limited to a fixed DMA unit.

[0044] Specifically, in response to a read or write command, the command manager 301 sends a first data transfer request to the first DMA unit. The first data transfer request includes a source address and an operating mode. In this embodiment, the operating modes include a first mode and a second mode. The first mode refers to the mode where the DMA unit requests cache allocation, and the second mode refers to the mode where the CPU will allocate cache. Optionally, the command manager 301 determines the first DMA unit based on the type of the read / write command or the source address. For example, if the command manager 301 receives a read command whose source address is a logical page address of the flash memory, then the first DMA unit is DMA unit 303, and the command manager 301 sends the first data transfer request to DMA unit 303.

[0045] The following description uses the example of command processor 301 receiving a write command to illustrate this embodiment.

[0046] When the operating mode is the first mode, in response to the first data transfer request, the DMA unit 302 accesses the source address, obtains the first data from the source address, and sends a cache allocation request to the cache manager 200. Specifically, the DMA unit 302 learns that the operating mode in the first data transfer request is the first mode, generates a cache allocation request, and sends the cache allocation request to the cache manager 200.

[0047] In response to the cache allocation request, the cache manager 200 allocates N storage blocks and returns cache index information to the DMA unit 302. In this embodiment, the storage blocks are located within the cache 304, and N is a positive integer. The cache index information includes the indices of the N storage blocks; for example, the cache index information is the physical addresses of the N storage blocks. After receiving the cache index information, the DMA unit 302 moves the first data to the N storage blocks according to their indices.

[0048] When the operating mode is the second mode, the first data transfer request also includes the target address. Specifically, in the second mode, cache allocation is performed by the command manager 301. The command manager 301 sends the index of the allocated N storage blocks along with the first data transfer request, thereby allowing the command manager 301 to directly obtain the target address.

[0049] For example, before sending the first data transfer request to DMA unit 302, command manager 301 sends a cache allocation request to cache manager 200. In response to the cache allocation request, cache manager 200 allocates N storage blocks for the first data and returns cache index information to command manager 301. Command manager 301 obtains the target address based on the indices of the N storage blocks.

[0050] Optionally, when the operating mode is the second mode, in response to the first data transfer request, the DMA unit 302 transfers the first data from the storage space corresponding to the source address to N storage blocks. The DMA unit 302 directly obtains the source address and the destination address from the first data transfer request, thereby the DMA unit 302 directly accesses the source address to obtain the first data and sends the first data to the N storage blocks.

[0051] Optionally, before sending the first data transfer request to the DMA unit 302, the command manager 301 obtains the first command and generates the first data transfer request based on the first command. The first command is either a read command or a write command. When the first command is a write command, the source address in the first data transfer request is the host address. When the first command is a read command, the source address in the first data transfer request points to the flash memory.

[0052] Optionally, after moving the first data to N storage blocks, the DMA unit 302 returns completion information to the command manager 301 to indicate that the first data has been moved to the cache 304. In this embodiment, another stage of data moving can only begin after one stage of data moving is completed. In this application, the DMA unit 302 sends completion information to the command manager 301 after moving the data to inform the command manager 301 that the next stage of data moving can continue.

[0053] Upon receiving the completion message, the command manager 301 sends a second data transfer request to the DMA unit 303. This second data transfer request includes a source address and a destination address. In response to the second data transfer request, the DMA unit 303 accesses the source address, retrieves the second data from the source address, and transfers the second data to the storage space corresponding to the destination address. In this embodiment, the source address points to the cache 304, and the destination address points to the flash memory chip 320. The DMA unit 303 accesses the source address, retrieves the second data from N storage blocks, and stores the second data in the flash memory chip 320. It should be noted that, to easily distinguish the two stages of data transfer, the first data transfer request corresponds to the first data, and the second data transfer request corresponds to the second data. For a write command, the second data is actually the first data stored in the N storage blocks.

[0054] In some embodiments, when the first command is a write command, the source address in the second data transfer request is the physical address of N storage blocks, and the destination address is the logical page address of the flash memory chip 320. When the first command is a read command, the source address in the second data transfer request is the physical address of N storage blocks, and the destination address is the host address.

[0055] In some embodiments, when moving the first data to N storage blocks, the first DMA unit divides the first data into N first messages and moves the N first messages sequentially to the N storage blocks. Each storage block stores a different first message, and each first message has the same length. For example, if N=24 and the first command is a read command, then the DMA unit 303 divides the first data into 24 first messages of equal length and moves the 24 first messages sequentially to 24 storage blocks.

[0056] Optionally, when moving the second data to the storage space corresponding to the target address, the second DMA unit divides the second data into multiple second messages and moves the multiple second messages to the storage space corresponding to the target address in sequence.

[0057] In some embodiments, the first data transfer request further includes a feedback mode, which indicates that for every X first messages transferred, the first DMA unit returns a completion message to the command manager, where X is a positive integer less than or equal to N. For example, if the first command is a read command, X=6, N=24, then the DMA unit 303 will send a completion message to the command manager 301 every 6 first messages transferred, for a total of 4 completion messages. This completion message represents the current status of the transferred data. For example, upon the first completion message, the command manager 301 knows that 6 first messages have been transferred to the cache 304; upon the second completion message, the command manager 301 knows that another 6 first messages have been transferred to the cache 304. Optionally, the second data transfer request includes a feedback mode, which can be found in the description of the feedback mode of the first data transfer request, and will not be repeated here.

[0058] Optionally, after moving the second data to the storage space corresponding to the target address, the second DMA unit sends a cache release request to the cache manager, the cache release request carrying the index of the storage block where the second data is located. In response to the cache release request, the cache manager saves the index of the storage block where the second data is located to complete the resource release of the storage block where the second data is located. For example, the second data moving request instructs the DMA unit 303 to move the second data from the cache 304 to the flash memory chip 320. After moving the second data to the flash memory chip 320, the DMA unit 303 sends a cache release request to the cache manager 200, the cache release request carrying the index of the storage block where the second data has been moved. The cache manager 200 saves these storage block indices, completing the resource release of the storage blocks, so that the storage blocks pointed to by these indices become free storage blocks and can be used to store data again.

[0059] Alternatively, the command manager 301 in this application can be replaced by a CPU.

[0060] Figure 3B A flowchart illustrating the execution of a read command by the control unit 300 is provided. The following description uses a read command as an example to illustrate the process of the control unit 300 processing the read command.

[0061] In step S310, the control unit 300 sends a read command to the command manager 301. In step S320, the command manager 301 generates a first data transfer request based on the read command and sends the first data transfer request to the DMA unit 303. The source address carried by the first data transfer request is the logical page address of the flash memory chip 320, and the operating mode is the first mode. Continuing to execute step S330, the DMA unit 303, in response to the first data transfer request, sends a cache allocation request to the cache manager 200 and accesses the logical page address of the flash memory chip 320 to obtain the first data.

[0062] In step S340, the DMA unit 303 receives the target address from the cache manager 200, moves the first data to the storage space corresponding to the target address, and sends a completion message to the command manager 301. The target address is the physical address in the cache 304. In step S350, the command manager 301 sends a second data move request to the DMA unit 302. The source address in this second data move request is the physical address in the cache 304, and the target address is the host address. In step S360, the DMA unit 302 moves the second data from the cache 304 to the host and sends a cache release request to the cache manager 200. This cache release request carries the physical address in the cache 304. In step S370, after moving the second data, the DMA unit 302 sends a completion message to the command manager 301 to indicate that the read command has been executed successfully.

[0063] See Figure 4A , Figure 4A A schematic diagram of a Direct Memory Access (DMA) unit is given, wherein the DMA unit 400 includes a control logic module 401, a timing module 402, a buffer register 403, and a flip-flop 404.

[0064] The DMA unit 400 receives a data transfer request, which carries a source address and an operating mode. In this embodiment, the data transfer request is generated by the command manager or the CPU in response to a read / write command. For example, the command manager generates a data transfer request after receiving a read command, and the source address carried in this request points to the flash memory chip or cache. Alternatively, if the data transfer request is generated by the CPU based on a write command, then the source address carried in this request points to the host or cache. Besides the host and command manager, the data transfer request can also be generated by other devices with command processing capabilities, which is not limited here. In this embodiment, the data transfer request carries a source address and an operating mode, and optionally a target address depending on the operating mode. The operating modes described here are the same as those in the previous embodiments and will not be repeated here. In the first mode, the data transfer request does not carry a target address; in the second mode, the data transfer request carries a target address.

[0065] When the source address points to a host computer or a flash memory chip, in response to a data transfer request, the DMA unit 400 accesses the source address to obtain the first data. For example, if the source address is a host address, the DMA unit 400 controls the bus to access the host address, thereby obtaining the first data from the host. Alternatively, if the source address is a logical page address of a flash memory chip, the DMA unit 400 controls the bus to access the flash memory chip through the media interface controller to obtain the first data from the flash memory chip.

[0066] After a preset duration following the DMA unit 400 accesses the source address, a cache allocation request is output to obtain the target address. The preset duration is greater than or equal to 0. In this embodiment, the cache allocation request is output to the device managing the cache. For example, if the cache is managed by a cache manager (hardware), the cache allocation request is sent to the cache manager. Alternatively, if the cache is managed by firmware, the DMA unit 400 sends the cache allocation request to the CPU (the firmware runs on the CPU). Upon receiving the cache allocation request, the corresponding device (e.g., the cache manager and the CPU) allocates several memory blocks (located in the cache) and returns the index of the memory blocks to the DMA unit 400. The target address can be obtained based on the index of the memory blocks, or the index of the memory blocks itself may be the target address. After obtaining the target address, the DMA unit 400 moves the first data to the memory space where the target address is located. The preset duration in this embodiment is related to the device managing the cache. For example, when using a cache manager, the preset duration is 3µs. When using firmware to manage the cache, the preset duration is 10µs. The preset duration can also be 0. The preset duration is configured during the initialization process of DMA unit 400, or it can be carried in the data transfer request.

[0067] Specifically, after the DMA unit 400 receives a data transfer request, the control logic module 401 parses the data transfer request and obtains the parsing result. In this embodiment, the data transfer request has a fixed format. The control logic module 401 extracts the information required for data transfer from the data transfer request according to preset rules and stores it in the corresponding registers. The preset rules are related to the communication protocol and are not limited here. For example, the source address in the data transfer request will be stored in the address register (not shown in the figure).

[0068] Based on the analysis results, the control logic module 401 controls the bus and accesses the source address. In this embodiment, when sending a data transfer request to the DMA unit 400, the CPU relinquishes bus control to the DMA unit 400, eliminating the need for the DMA unit 400 to request bus control, thus reducing interaction and improving data transfer efficiency. It should be noted that the CPU is not necessarily the one sending the data transfer request to the DMA unit 400. The control logic module 401 sends a timing start signal to the timing module 402. In this embodiment, the timing module 402 receives an externally input clock signal to achieve timing and maintain the same time state as external devices. This timing start signal instructs the timing module 402 to start the timing function. In response to the timing start signal, the timing module 402 starts timing. After the timing time reaches a preset duration, the timing module 402 sends a timing completion signal back to the control logic module 401. In response to the timing completion signal, the control logic module 401 outputs a buffer allocation request. Specifically, when the preset duration is 0, no timing is performed, and the control logic module 401 directly outputs a buffer allocation request.

[0069] In some embodiments, based on the parsing result, the control logic module 401 controls the bus to access the source address and outputs a cache allocation request. Before receiving the target address, if the first data has already been acquired, a portion of the data already transferred to the DMA unit is temporarily stored using a trigger 404 until the target address is received. After receiving the target address, the control logic module 401 controls the bus to move the data in the trigger 404 and a portion of the first data on the bus to the storage space where the target address is located.

[0070] In this embodiment, the first data is not transferred from the source address to the DMA unit 400 all at once, but is divided into multiple transfers, such as transferring one byte at a time. For example, if the total length of the first data is 20 bytes, and one byte is transferred each time, before the target address is obtained, 5 bytes of the first data will be transferred to the DMA unit 400. These 5 bytes are temporarily stored using a trigger 404 until the target address is obtained, at which point the trigger stops storing the remaining 15 bytes. After receiving the target address, the control logic module 401, according to the time sequence, first moves the 5 bytes of data in the trigger 404 to the storage space where the target address is located, and then moves the remaining 15 bytes of data still being transmitted on the bus to that storage space.

[0071] Optionally, after obtaining the target address, trigger 404 is used to save and transmit the remaining 15 bytes of the first data. See also Figure 4B , Figure 4B A schematic diagram is given on how to save and transmit the first data using trigger 404. Figure 4BThere are five triggers: triggers 404-1, 404-2, 404-3, 404-4, and 404-5. Before receiving the target address at time T0, triggers 404 store the state of 5 bytes of data, with each trigger storing one byte. Triggers 404-1, 404-2, 404-3, 404-4, and 404-5 store data D1, D2, D3, D4, and D5, respectively. After receiving the target address at time T1 and having transmitted one byte of data, triggers 404-1, 404-2, 404-3, 404-4, and 404-5 store data D2, D3, D4, D5, and D6, respectively. At time T2, only 3 bytes remain to be transmitted; triggers 404-1, 404-2, 404-3, 404-4, and 404-5 store data D18, D19, D20, 0, and 0, respectively.

[0072] In another embodiment, based on the parsing result, the control logic module 401 controls the bus to access the source address. After receiving the first data, the control logic module 401 outputs a cache allocation request and uses a buffer register 403 to temporarily store a portion of the first data that has been transferred to the DMA unit 400 until the target address is received. After receiving the target address, the control logic module 401 controls the bus to move the data in the buffer register 403 and a portion of the first data on the bus to the storage space where the target address is located. In this embodiment, waiting to receive the first data before issuing the cache allocation request would mean that the trigger's capacity could not meet the amount of data that needed to be temporarily stored. Therefore, a buffer register is used to temporarily store the data, saving hardware resources.

[0073] In one embodiment, a trigger 404 is used to temporarily store a portion of the first data that has been transferred to the DMA unit until the target address is received. This includes: the control logic module 401 sending a start signal to the trigger 404 each cycle until the target address is received, at which point the start signal is stopped; after receiving the start signal, the trigger 404 saves the timing state of a portion of the first data received in the current cycle. Optionally, the trigger 404 is a D-type trigger. The trigger 404 saves data once upon receiving the start signal. One byte of data is transferred into the DMA unit 400 each cycle, thus sending a start signal once per cycle, causing the trigger 404 to save the data entering the DMA unit 400 in the current cycle.

[0074] In some embodiments, when the source address points to the cache, the DMA unit accesses the source address to obtain the second data. When the source address points to the cache, the data transfer request also carries the target address. The control logic module 401 controls the bus to transfer the second data to the storage space corresponding to the target address. For example, if the target address is a host address, the second data is transferred from the cache to the host. The control logic module 401 outputs a cache release request, which carries the cache index of the source address to complete the resource release.

[0075] In one embodiment, outputting a cache release request, the cache release request carrying the cache index of the source address includes: after each fixed length of data is transported, the control logic module 401 outputs a cache release request, the cache release request carrying the cache index corresponding to the fixed length of data; or, after the second data is transported, the control logic module 401 outputs a cache release request, the cache release request carrying the cache index corresponding to the second data.

[0076] In this embodiment, the control logic module 401 outputs cache release requests in multiple ways. For example, a cache release request is output after every 4 bytes of data are moved, and this cache release request carries the cache index corresponding to these 4 bytes of data. As another example, after all the second data has been moved, the control logic module 401 sends a cache release request, which includes the cache index corresponding to the entire second data set. The method of outputting cache release requests in this embodiment can be configured during the initialization of the DMA unit 400 and is not limited here.

[0077] In some embodiments, if the data transfer request also includes a target address, the DMA unit 400, after obtaining the first data from the source address, transfers the first data to the storage space corresponding to the target address. In this embodiment, after accessing the source address, the control logic module 401 directly transfers the first data to the storage space corresponding to the target address, without needing to use the trigger 404 or the buffer memory 403 to temporarily store the data.

[0078] Optionally, the DMA unit 400 in this application can be used in conjunction with the cache manager 200 and control unit 300 in the above embodiments. The usage is described above and will not be elaborated here. When used in conjunction, since both the DMA unit 400 and the cache manager 200 are hardware, the interaction between them is a very fast hardware interaction method. This further reduces the interaction speed within the control unit 300, achieving the technical effect of further improving the data transfer speed between the host and the flash memory chip.

[0079] Although the examples referenced in this application are described for illustrative purposes only and not for limiting the scope of this application, changes, additions and / or deletions to the implementation may be made without departing from the scope of this application.

[0080] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A cache manager, characterized in that, Includes interfaces, allocation modules, and memory, among which, The interface receives a cache allocation request and sends the cache allocation request to the allocation module; and the interface receives the first cache index information returned by the allocation module and outputs the first cache index information. In response to the cache allocation request, the allocation module reads the data in the memory, obtains the indices of N free storage blocks, and generates the first cache index information. The storage blocks are located in the cache, N is a positive integer, and the first cache index information includes the indices of the N free storage blocks. The memory stores indexes of multiple memory blocks; the memory blocks are located within the cache; The memory includes multiple storage spaces, each of which stores an index of a storage block; The allocation module manages a first pointer, which points to a first storage space of the memory. The first storage space stores the index of free storage blocks, and two adjacent storage spaces on both sides of the first storage space store the index of free storage blocks and the index of allocated storage blocks, respectively. When allocating N free storage blocks, the allocation module reads the indices of N free storage blocks from N consecutive storage spaces starting from the first storage space; and Modify the first pointer so that it points to the second storage space, which is the (N+1)th storage space starting from the first storage space.

2. The cache manager as described in claim 1, characterized in that, The cache manager also includes a release module, wherein, The interface receives a cache release request and sends the cache release request to the release module. The cache release request carries second cache index information, which includes the indices of M storage blocks to be released. The storage blocks to be released are located in the cache, and M is a positive integer. In response to the cache release request, the release module writes the indexes of the M storage blocks into the memory, so that the storage blocks to be released become free storage blocks.

3. The cache manager as described in claim 2, characterized in that, The release module manages the second pointer, which points to the third storage space. The third storage space stores the indexes of allocated storage blocks, and the two adjacent storage spaces on both sides of the third storage space store the indexes of free storage blocks and the indexes of allocated storage blocks, respectively. When writing the indices of the M storage blocks into the memory, the release module obtains the indices of the M storage blocks from the cache release request; Write the indices of the M storage blocks sequentially into the M consecutive storage spaces starting from the third storage space; Modify the second pointer so that it points to the fourth storage space, which is the (M+1)th storage space starting from the third storage space, and the fourth storage space stores the index of the allocated storage blocks.

4. The cache manager as described in any one of claims 1-3, characterized in that, The memory includes at least one storage space, each storage space having an equal length, and each storage space stores an index of a storage block.

5. The cache manager as described in any one of claims 1-4, characterized in that, The allocated N free storage blocks are used to cache data moved from the flash memory chip or the host based on data move requests; the data move requests are generated based on read commands or write commands, both of which indicate that data is transferred between the host and the flash memory chip.

6. A control component, characterized in that, include: Command manager, first DMA unit, second DMA unit, cache, and cache manager as described in any one of claims 1-5, wherein, The command manager sends a first data transfer request to the first DMA unit, the first data transfer request including the source address and the working mode; When the working mode is the first mode, in response to the first data transfer request, the first DMA unit accesses the source address, obtains the first data in the source address, and sends a cache allocation request to the cache manager; In response to the cache allocation request, the cache manager allocates N storage blocks and returns cache index information to the first DMA unit; After receiving the cache index information, the first DMA unit moves the first data to the N storage blocks according to the indexes of the N storage blocks.

7. The control component as claimed in claim 6, characterized in that, When the working mode in the first data transfer request is the second mode, the first data transfer request also includes the target address; Before sending the first data transfer request to the first DMA unit, the command manager sends the cache allocation request to the cache manager; In response to the cache allocation request, the cache manager allocates the N storage blocks for the first data and returns cache index information to the command manager; The command manager obtains the target address based on the indexes of the N storage blocks.

8. The control component as claimed in claim 7, characterized in that, When the operating mode is the second mode, in response to the first data transfer request, the first DMA unit transfers the first data from the storage space corresponding to the source address to the N storage blocks.

9. The control component as described in any one of claims 6-8, characterized in that, After moving the first data to the N storage blocks, the first DMA unit returns completion information to the command manager to indicate that the first data has been moved to the cache; After receiving the completion information, the command manager sends a second data transfer request to the second DMA unit, the second data transfer request including a source address and a destination address; In response to the second data transfer request, the second DMA unit accesses the source address, obtains the second data in the source address, and transfers the second data to the storage space corresponding to the target address.

10. The control component as described in any one of claims 6-9, characterized in that, Before sending the first data transfer request to the first DMA unit, the management command obtains a first command and generates the first data transfer request based on the first command. The first command is either a read command or a write command, both of which indicate that data is transferred between the host and the flash memory chip. When the first command is a write command, the source address in the first data transfer request is the host address. When the first command is a read command, the source address in the first data transfer request points to the flash memory chip.

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