Method and device for determining grade of nonvolatile memory chip

Abstract

The invention discloses a method and a device for determining the grade of a nonvolatile memory chip. The method comprises the following steps: acquiring current frequency, capacity and time sequence test data and failure evaluation test data of the nonvolatile memory chip; determining a dynamic weighting matrix according to the use scene information of the nonvolatile memory chip, mapping the current test data to a pre-constructed first chip feature space according to the dynamic weighting matrix, calculating a corresponding likelihood probability, and determining a current data scoring level according to the likelihood probability; calculating a personalized degradation rate parameter according to the failure evaluation test data and a pre-constructed chip degradation track curve, and determining failure evaluation data according to the personalized degradation rate parameter; and determining the current data scoring grade and the comprehensive grade corresponding to the binary grading interval to which the failure evaluation data belongs as the target comprehensive grade of the nonvolatile memory chip. According to the technical scheme, automatic, multi-dimensional and high-precision grade division of the nonvolatile memory chips is realized.

Description

Technical Field

[0001] This application belongs to the field of electronic digital data processing technology, specifically relating to a method and apparatus for determining the grade of a non-volatile memory chip. Background Technology

[0002] Non-volatile memory chips are storage devices that retain data even after power loss. They are widely used in electronic devices such as solid-state drives, automotive electronic systems, and industrial control equipment as core components for data storage. Classifying non-volatile memory chips during mass production allows for precise matching of chip performance with application scenarios, ensuring the reliability and security of high-end devices while also rationally allocating chip resources and reducing overall application costs.

[0003] Currently, the main method for classifying non-volatile memory chips involves workers manually placing the chips from the supply area into a test fixture for electrical testing, and then determining the chip's grade based on the test results and their historical experience. However, this method is inefficient, inconsistent, and prone to errors due to reliance on subjective human judgment. It fails to meet the demands for large-scale, high-precision, and scenario-based automated classification, thus limiting mass production efficiency and classification accuracy. Summary of the Invention

[0004] This application provides a method and apparatus for determining the grade of non-volatile memory chips, with the aim of achieving automated, multi-dimensional, and high-precision grade classification of non-volatile memory chips.

[0005] In a first aspect, embodiments of this application provide a method for determining the grade of a non-volatile memory chip, the method comprising:

[0006] The non-volatile memory chips in the feeding area are moved to the target placement position in the test fixture by a robotic arm; The non-volatile memory chip is subjected to multi-dimensional memory chip testing to obtain current test data and failure assessment test data of the non-volatile memory chip; wherein, the current test data includes current frequency test data, current capacity test data and current timing test data; The usage scenario information of the non-volatile memory chip is obtained and a dynamic weighting matrix is ​​determined based on the usage scenario information. The current test data is mapped to a pre-constructed first chip feature space based on the dynamic weighting matrix and the corresponding likelihood probability is calculated. The current data scoring level is determined based on the likelihood probability. The individual degradation rate parameters are calculated based on the failure assessment test data and the pre-constructed chip degradation trajectory curve, and the failure assessment data is determined based on the individual degradation rate parameters. Obtain the binary grading interval and the comprehensive grade corresponding to the binary grading interval, and determine the current data scoring grade and the comprehensive grade corresponding to the binary grading interval to which the failure assessment data belongs as the target comprehensive grade of the non-volatile memory chip.

[0007] Furthermore, determining the current data rating level based on the likelihood probability includes: If the likelihood probability is lower than a first preset probability threshold or higher than a second preset probability threshold, the current data rating level is determined based on the likelihood probability and the correspondence between the pre-constructed likelihood probability threshold range and the current data rating level, wherein the first preset probability threshold is less than the second preset probability threshold. If the likelihood probability is not lower than the first preset probability threshold and not higher than the second preset probability threshold, calculate the deviation vector of the current test data relative to the first chip feature space, and determine the current data rating level based on the deviation vector and the likelihood probability.

[0008] Furthermore, determining the current data rating level based on the deviation vector and the likelihood probability includes: The deviation score is determined based on the deviation vector, and the likelihood probability and the weight coefficient corresponding to the deviation score are determined based on the usage scenario information. The current data rating level is obtained by weighting and summing the likelihood probability and the deviation score according to the weight coefficient.

[0009] Furthermore, the step of calculating the individual degradation rate parameter based on the failure assessment test data and the pre-constructed chip degradation trajectory curve includes: The prior probability distribution information of the degradation rate parameter is determined based on the pre-constructed chip degradation trajectory curve; Construct the likelihood function corresponding to the failure assessment test data, and determine the posterior probability distribution information of the degradation rate parameter based on the prior probability distribution information and the likelihood function; The expected value of the posterior probability distribution information is determined as the individual degradation rate parameter.

[0010] Furthermore, determining the failure assessment data based on the individual degradation rate parameter includes: Based on the individual degradation rate parameter and the preset failure threshold, the remaining lifetime probability distribution information of the non-volatile memory chip is calculated; Calculate the expected value of the remaining lifetime probability distribution information and normalize the expected value to obtain failure assessment data.

[0011] Furthermore, obtaining the binary hierarchical interval and the corresponding comprehensive level of the binary hierarchical interval includes: Historical chip sample data is acquired and cluster analysis is performed on the historical chip sample data to obtain multiple sample clusters; Calculate the centroid coordinates of each sample cluster, and calculate the high-quality reference distance of each sample cluster based on the centroid coordinates; The sample clusters are sorted according to the superior reference distance, and a corresponding comprehensive level is assigned to each sample cluster based on the sorting results. The corresponding binary classification intervals are determined based on each sample cluster, and the binary classification intervals and comprehensive levels corresponding to each sample cluster are integrated.

[0012] Furthermore, determining the corresponding binary hierarchical interval based on each of the sample clusters includes: Calculate the covariance matrix of each sample cluster, and determine the optimal classification hyperplane based on the centroid coordinates and covariance matrix of each sample cluster; Calculate the binary intercept of the optimal classification hyperplane, and use the binary intercept as the interval boundary to determine the binary classification interval corresponding to each sample cluster.

[0013] Secondly, embodiments of this application provide a grade determination device for a non-volatile memory chip, the device comprising: The chip placement module is used to move non-volatile memory chips from the feeding area to the target placement position in the test fixture via a robotic arm; The chip testing module is used to perform multi-dimensional memory chip testing on the non-volatile memory chip to obtain the current test data and failure assessment test data of the non-volatile memory chip; wherein, the current test data includes current frequency test data, current capacity test data and current timing test data; The current evaluation module is used to obtain the usage scenario information of the non-volatile memory chip and determine a dynamic weighting matrix based on the usage scenario information. Based on the dynamic weighting matrix, the current test data is mapped to a pre-constructed first chip feature space and the corresponding likelihood probability is calculated. Based on the likelihood probability, the current data score level is determined. The failure assessment module is used to calculate individual degradation rate parameters based on the failure assessment test data and the pre-constructed chip degradation trajectory curve, and to determine the failure assessment data based on the individual degradation rate parameters. The rating determination module is used to obtain the binary rating interval and the comprehensive rating corresponding to the binary rating interval, and to determine the current data rating level and the comprehensive rating corresponding to the binary rating interval to which the failure assessment data belongs as the target comprehensive rating of the non-volatile memory chip.

[0014] Furthermore, the current evaluation module is specifically used for: If the likelihood probability is lower than a first preset probability threshold or higher than a second preset probability threshold, the current data rating level is determined based on the likelihood probability and the correspondence between the pre-constructed likelihood probability threshold range and the current data rating level, wherein the first preset probability threshold is less than the second preset probability threshold. If the likelihood probability is not lower than the first preset probability threshold and not higher than the second preset probability threshold, calculate the deviation vector of the current test data relative to the first chip feature space, and determine the current data rating level based on the deviation vector and the likelihood probability.

[0015] Furthermore, the current evaluation module is specifically used for: The deviation score is determined based on the deviation vector, and the likelihood probability and the weight coefficient corresponding to the deviation score are determined based on the usage scenario information. The current data rating level is obtained by weighting and summing the likelihood probability and the deviation score according to the weight coefficient.

[0016] Furthermore, the failure assessment module is specifically used for: The prior probability distribution information of the degradation rate parameter is determined based on the pre-constructed chip degradation trajectory curve; Construct the likelihood function corresponding to the failure assessment test data, and determine the posterior probability distribution information of the degradation rate parameter based on the prior probability distribution information and the likelihood function; The expected value of the posterior probability distribution information is determined as the individual degradation rate parameter.

[0017] Furthermore, the failure assessment module is specifically used for: Based on the individual degradation rate parameter and the preset failure threshold, the remaining lifetime probability distribution information of the non-volatile memory chip is calculated; Calculate the expected value of the remaining lifetime probability distribution information and normalize the expected value to obtain failure assessment data.

[0018] Furthermore, the level determination module is specifically used for: Historical chip sample data is acquired and cluster analysis is performed on the historical chip sample data to obtain multiple sample clusters; Calculate the centroid coordinates of each sample cluster, and calculate the high-quality reference distance of each sample cluster based on the centroid coordinates; The sample clusters are sorted according to the superior reference distance, and a corresponding comprehensive level is assigned to each sample cluster based on the sorting results. The corresponding binary classification intervals are determined based on each sample cluster, and the binary classification intervals and comprehensive levels corresponding to each sample cluster are integrated.

[0019] Furthermore, the level determination module is specifically used for: Calculate the covariance matrix of each sample cluster, and determine the optimal classification hyperplane based on the centroid coordinates and covariance matrix of each sample cluster; Calculate the binary intercept of the optimal classification hyperplane, and use the binary intercept as the interval boundary to determine the binary classification interval corresponding to each sample cluster.

[0020] Thirdly, embodiments of this application provide an electronic device including a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the method described in the first aspect.

[0021] Fourthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the method described in the first aspect.

[0022] In this embodiment, a robotic arm moves a non-volatile memory chip from the feeding area to a target placement position in the test fixture; multi-dimensional memory chip testing is performed on the non-volatile memory chip to obtain current test data and failure assessment test data; wherein, the current test data includes current frequency test data, current capacity test data, and current timing test data; usage scenario information of the non-volatile memory chip is obtained, and a dynamic weighting matrix is ​​determined based on the usage scenario information; the current test data is mapped to a pre-constructed first chip feature space based on the dynamic weighting matrix, and the corresponding likelihood probability is calculated; the current data rating level is determined based on the likelihood probability; a personalized degradation rate parameter is calculated based on the failure assessment test data and a pre-constructed chip degradation trajectory curve, and failure assessment data is determined based on the personalized degradation rate parameter; a binary grading interval and the comprehensive level corresponding to the binary grading interval are obtained, and the current data rating level and the comprehensive level corresponding to the binary grading interval to which the failure assessment data belongs are determined as the target comprehensive level of the non-volatile memory chip. The above-mentioned method for determining the grade of non-volatile memory chips enables automated, multi-dimensional, and high-precision grade classification of non-volatile memory chips. Attached Figure Description

[0023] Figure 1This is a flowchart illustrating a method for determining the grade of a non-volatile memory chip according to an embodiment of this application; Figure 2 This is a flowchart illustrating another method for determining the grade of a non-volatile memory chip provided in an embodiment of this application; Figure 3 This is a flowchart illustrating another method for determining the grade of a non-volatile memory chip provided in this application embodiment; Figure 4 This is a flowchart illustrating another method for determining the grade of a non-volatile memory chip provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of a non-volatile memory chip level determination device provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, specific embodiments of this application will be described in further detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining this application and not for limiting it. It should also be noted that, for ease of description, only the parts relevant to this application are shown in the drawings, not all of them. Before discussing exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe operations (or steps) as sequential processes, many of these operations can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the operations can be rearranged. The process can be terminated when its operation is completed, but may also have additional steps not included in the drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0025] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0026] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0027] The method and apparatus for determining the grade of non-volatile memory chips provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0028] First, this application is applicable to the scenario of automated testing and grading of non-volatile memory chips. Based on the above application scenario, it can be understood that the executing entity of this application can be an intelligent terminal device with computing capabilities, such as an industrial control computer or an embedded control system. In this solution, the intelligent terminal device can perform motion control of the robotic arm and test process control of the test fixture.

[0029] Non-volatile memory chips can be chips that can retain stored data even after power is lost, such as NAND Flash.

[0030] Figure 1 This is a flowchart illustrating a method for determining the grade of a non-volatile memory chip according to an embodiment of this application. Figure 1 As shown, the specific steps include the following: S101 uses a robotic arm to move a non-volatile memory chip from the feeding area to the target placement position in the test fixture.

[0031] Among them, the robotic arm can be an automated execution device with high-precision positioning and grasping functions, such as a three-axis / four-axis / six-axis industrial robotic arm, a Cartesian coordinate robotic arm, or a pneumatic pick-and-place robotic arm.

[0032] The feeding area can be a material carrying area for storing non-volatile memory chips to be tested, such as a chip tray, tape, hopper, or the discharge position of an automatic feeding mechanism.

[0033] The test fixture can be a special tooling for electrical connection and multi-dimensional testing of non-volatile memory chips. The test fixture may include structures such as pogo pins, programming sockets and conductive springs.

[0034] The target placement location can be a test station on the test fixture used for precise placement and electrical contact of the non-volatile memory chip.

[0035] In one embodiment, the process of moving a non-volatile memory chip from a feeding area to a target placement position in a test fixture using a robotic arm may include: acquiring chip images using a top-view camera fixed above the feeding area; identifying feature points of the non-volatile memory chip in the chip image using edge detection algorithms, contour extraction algorithms, and feature matching algorithms; calculating the center coordinates and rotation angle of the non-volatile memory chip based on the feature points and transforming them into the robotic arm coordinate system to obtain the robotic arm's grasping pose; and controlling the robotic arm to move to the feeding area based on the robotic arm's grasping pose. The robot arm is positioned directly above a non-volatile memory chip and is stably gripped using vacuum adsorption. After the non-volatile memory chip is transferred to the target placement position in the test fixture, a downward-looking camera mounted on top of the test fixture performs a second high-precision imaging of the feature points of the non-volatile memory chip and the reference marks of the test fixture slot to calculate the pose deviation between the non-volatile memory chip and the test fixture slot. The robot arm performs real-time closed-loop fine-tuning compensation based on the pose deviation. Finally, the robot arm places the non-volatile memory chip into the slot of the test fixture.

[0036] S102, perform multi-dimensional memory chip testing on the non-volatile memory chip to obtain current test data and failure assessment test data of the non-volatile memory chip; wherein, the current test data includes current frequency test data, current capacity test data and current timing test data.

[0037] Multi-dimensional memory chip testing can be a comprehensive test of various aspects of non-volatile memory chips, including electrical performance, reliability, read and write characteristics, and may include basic electrical testing, capacity testing, bad block detection, timing testing, and frequency testing.

[0038] The current test data can be quantitative indicators reflecting the real-time working capability of the non-volatile memory chip at the current moment, including current frequency test data, current capacity test data, and current timing test data. Specifically, the current frequency test data can be the highest usable frequency value at which the non-volatile memory chip can stably perform read and write operations at different clock frequencies such as 3600, 2400, 2200, 1600, 800, 600, and 400. The current capacity test data can be the effective usable storage capacity confirmed after reading the chip ID (an identification code used to uniquely identify the chip), the total number of blocks, and detecting bad block markers of the non-volatile memory chip. The current timing test data can be the deviation range between the actual timing parameters and standard values ​​of key operations such as page programming timing (tPROG), random read timing, and continuous write timing of the non-volatile memory chip in a specified operating mode.

[0039] Among them, failure assessment test data can be test data used to evaluate the potential failure risk and long-term reliability of non-volatile memory chips, which may include the number of initial bad blocks, the number of stable bad blocks, the number of bad blocks after write / erase, the number of bad blocks in read / write cycles, the deviation of page programming timing / random read timing / continuous write timing, the number of failed bits after high temperature baking, and the error probability under voltage disturbance, etc.

[0040] In one embodiment, the method of performing multi-dimensional memory chip testing on a non-volatile memory chip to obtain the current test data and failure assessment test data of the non-volatile memory chip can be achieved by sequentially or as needed performing basic electrical tests, capacity tests, bad block tests, timing tests, and frequency tests according to a preset automated process.

[0041] S103, obtain the usage scenario information of the non-volatile memory chip and determine the dynamic weighting matrix based on the usage scenario information, map the current test data to the pre-constructed first chip feature space based on the dynamic weighting matrix and calculate the corresponding likelihood probability, and determine the current data rating level based on the likelihood probability.

[0042] The usage scenario information can be the terminal scenarios and operating conditions in which the non-volatile memory chip is expected to be applied, such as consumer electronics, industrial control, automotive electronics, server storage, and IoT terminals.

[0043] In one embodiment, the method for obtaining the usage scenario information of the non-volatile memory chip can be through preset configuration, user input, or retrieval from a database based on the read ID.

[0044] The dynamic weighting matrix can be a matrix determined based on usage scenario information to weight the current test data, adjusting the weights of different parameter indicators in the current test data within the current data rating level. The current data rating level can be a quantitative grading result characterizing the current real-time operating level of the non-volatile memory chip.

[0045] In one embodiment, determining the dynamic weighting matrix based on usage scenario information can be achieved by pre-establishing a correlation between usage scenario information and the dynamic weighting matrix. The current usage scenario information is then mapped based on this correlation to obtain the target dynamic weighting matrix. The correlation between usage scenario information and the dynamic weighting matrix can be constructed based on scenario requirement priorities, industry standards, historical test data statistical analysis, or expert experience knowledge bases.

[0046] The first chip feature space can be a high-dimensional feature space that characterizes a high-quality non-volatile memory chip, consisting of multiple key parameter indicators (i.e., the current frequency test data, current capacity test data, and current timing test data included in the current test data).

[0047] In one embodiment, the method of pre-constructing the first chip feature space can be achieved by having professionals select a predetermined number of high-quality non-volatile memory chips and conduct multi-dimensional memory chip tests on them to obtain current test data of these high-quality non-volatile memory chips. Based on a benchmark weighting matrix, the current test data of these high-quality non-volatile memory chips is weighted to obtain high-quality test vectors. A multi-dimensional space is established based on multiple key indicators in the current test data, and these high-quality test vectors are embedded as sample points into the multi-dimensional space to obtain the first chip feature space.

[0048] The likelihood probability can be the probability density value of the current test data in the feature space of the first chip, used to characterize the degree of matching between the key parameter indicators of the current non-volatile memory chip and the feature distribution of the key parameter indicators of the high-quality non-volatile memory chip.

[0049] In one embodiment, the method of mapping the current test data to the first chip feature space according to the dynamic weighting matrix and calculating the corresponding likelihood probability can be achieved by weighting the current test data according to the dynamic weighting matrix to obtain the current test vector, using the current test vector as the query point to calculate its probability density value in the first chip feature space, and using the probability density value as the likelihood probability.

[0050] In one embodiment, the current data rating level can be determined based on the likelihood probability by using the correspondence between the likelihood probability and a pre-built likelihood probability threshold range and the current data rating level.

[0051] S104, calculate the individual degradation rate parameter based on the failure assessment test data and the pre-constructed chip degradation trajectory curve, and determine the failure assessment data based on the individual degradation rate parameter.

[0052] Among them, the chip degradation trajectory curve can be a curve constructed based on the failure assessment test data of historical batches of non-volatile memory chips under accelerated life testing, used to describe the gradual degradation of key reliability indicators of these historical batches of non-volatile memory chips as the usage time increases.

[0053] In one embodiment, the method of pre-constructing the chip degradation trajectory curve can be achieved by selecting a preset number of historical batches of non-volatile memory chips and conducting accelerated life tests on them. During the test, the failure assessment test data of the non-volatile memory chips (i.e., the number of initial bad blocks, the number of stable bad blocks, the number of bad blocks after write / erase, the number of bad blocks in read / write cycles, the deviation of page programming timing / random read timing / continuous write timing, the number of failed bits after high-temperature baking, and the error probability under voltage disturbance, etc.) are recorded at fixed intervals. The failure assessment test data of the non-volatile memory chips recorded at the same time are normalized and weighted to obtain the comprehensive key reliability index corresponding to that time. The comprehensive key reliability index of each historical batch of non-volatile memory chips at each time is fitted to obtain the change curve of the comprehensive key reliability index of each historical batch of non-volatile memory chips over time, i.e., the chip degradation trajectory curve.

[0054] Among them, the individual degradation rate parameter can be a quantitative indicator used to characterize the degree of individual degradation of the current non-volatile memory chip compared to the average level of non-volatile memory chips.

[0055] In one embodiment, the method of calculating the individual degradation rate parameter based on failure assessment test data and chip degradation trajectory curve can be achieved by constructing a likelihood function corresponding to the failure assessment test data based on the prior probability distribution information of the degradation rate parameter determined according to the chip degradation trajectory curve, and determining the posterior probability distribution information of the degradation rate parameter based on the prior probability distribution information and the likelihood function, and determining the expected value of the posterior probability distribution information as the individual degradation rate parameter.

[0056] Among them, failure assessment data can be a quantitative score used to characterize the long-term reliability of non-volatile memory chips, reflecting the remaining lifespan or failure risk of non-volatile memory chips under expected usage conditions.

[0057] In one embodiment, the method of determining failure assessment data based on the individual degradation rate parameter can be to calculate the remaining lifetime probability distribution information of the non-volatile memory chip based on the individual degradation rate parameter and a preset failure threshold, calculate the expected value of the remaining lifetime probability distribution information, and normalize the expected value to obtain the failure assessment data.

[0058] S105, obtain the binary classification interval and the comprehensive level corresponding to the binary classification interval, and determine the current data scoring level and the comprehensive level corresponding to the binary classification interval to which the failure assessment data belongs as the target comprehensive level of the non-volatile memory chip.

[0059] The binary grading interval can be a partition on a two-dimensional plane consisting of the current data rating level and the failure assessment data. Each binary grading interval corresponds to a comprehensive level, which can be a predefined level label.

[0060] The binary classification interval and the corresponding comprehensive level can be preset based on historical test data.

[0061] The target overall rating can be the final overall rating determined for the current non-volatile memory chip.

[0062] In one embodiment, the method of determining the comprehensive level of the non-volatile memory chip as the target comprehensive level of the binary classification interval to which the current data rating level and failure assessment data belong can be achieved by using the current data rating level and failure assessment data of the non-volatile memory chip as coordinate points, identifying the binary classification interval to which the coordinate points fall, and then reading the comprehensive level corresponding to the binary classification interval as the target comprehensive level.

[0063] In this embodiment, a robotic arm moves a non-volatile memory chip from the feeding area to a target placement position in the test fixture; multi-dimensional memory chip testing is performed on the non-volatile memory chip to obtain current test data and failure assessment test data; wherein, the current test data includes current frequency test data, current capacity test data, and current timing test data; usage scenario information of the non-volatile memory chip is obtained, and a dynamic weighting matrix is ​​determined based on the usage scenario information; the current test data is mapped to a pre-constructed first chip feature space based on the dynamic weighting matrix, and the corresponding likelihood probability is calculated; the current data rating level is determined based on the likelihood probability; a personalized degradation rate parameter is calculated based on the failure assessment test data and a pre-constructed chip degradation trajectory curve, and failure assessment data is determined based on the personalized degradation rate parameter; a binary grading interval and the comprehensive level corresponding to the binary grading interval are obtained, and the current data rating level and the comprehensive level corresponding to the binary grading interval to which the failure assessment data belongs are determined as the target comprehensive level of the non-volatile memory chip. The above-mentioned method for determining the grade of non-volatile memory chips enables automated, multi-dimensional, and high-precision grade classification of non-volatile memory chips.

[0064] Figure 2 This is a flowchart illustrating another method for determining the grade of a non-volatile memory chip provided in an embodiment of this application. Figure 2 As shown, the specific steps include the following: S201, using a robotic arm to move the non-volatile memory chip in the feeding area to the target placement position in the test fixture.

[0065] S202, perform multi-dimensional memory chip testing on the non-volatile memory chip to obtain current test data and failure assessment test data of the non-volatile memory chip; wherein, the current test data includes current frequency test data, current capacity test data and current timing test data.

[0066] S203, obtain the usage scenario information of the non-volatile memory chip and determine the dynamic weighting matrix based on the usage scenario information, map the current test data to the pre-constructed first chip feature space based on the dynamic weighting matrix and calculate the corresponding likelihood probability.

[0067] S204, if the likelihood probability is lower than a first preset probability threshold or the likelihood probability is higher than a second preset probability threshold, determine the current data rating level according to the likelihood probability and the correspondence between the pre-constructed likelihood probability threshold range and the current data rating level, wherein the first preset probability threshold is less than the second preset probability threshold.

[0068] The first preset probability threshold can be a critical likelihood value used to determine whether the current real-time operating level of the non-volatile memory chip is significantly lower than the excellent real-time operating level, for example, 5%; the second preset probability threshold can be a critical likelihood value used to determine whether the current real-time operating level of the non-volatile memory chip is significantly higher than the excellent level, for example, 95%. It is understood that the first preset probability threshold should be less than the second preset probability threshold.

[0069] In one embodiment, the current data rating level can be determined based on the likelihood probability and the correspondence between the pre-constructed likelihood probability threshold interval and the current data rating level by querying the mapping table between the likelihood probability threshold interval and the current data rating level, classifying the currently calculated likelihood probability into the matching likelihood probability threshold interval, and thus determining the current data rating level corresponding to the likelihood probability threshold interval.

[0070] The advantage of this scheme is that when the likelihood probability is lower than the first preset probability threshold or higher than the second preset probability threshold, the current data rating level can be determined by a simple threshold judgment. This allows for a quick and clear determination of the current data rating level of non-volatile memory chips with extremely excellent or extremely poor real-time performance, avoiding unnecessary complex calculations and improving the efficiency of the rating process.

[0071] S205, if the likelihood probability is not lower than the first preset probability threshold and not higher than the second preset probability threshold, calculate the deviation vector of the current test data relative to the first chip feature space, and determine the current data rating level based on the deviation vector and the likelihood probability.

[0072] The deviation vector is the multidimensional deviation vector between the current test vector and the distribution center of each high-quality test vector in the feature space of the first chip.

[0073] In one embodiment, the deviation vector of the current test data relative to the feature space of the first chip can be calculated by calculating the mean vector of each high-quality test vector in the feature space of the first chip, and subtracting the mean vector from the current test vector to obtain the deviation vector.

[0074] In one embodiment, the method for determining the current data rating level based on the deviation vector and the likelihood probability can be as follows: calculate the magnitude of the deviation vector and normalize the magnitude to obtain the deviation score, and then weight and fuse the deviation score with the likelihood probability to obtain the final current data rating level.

[0075] In one embodiment, determining the current data rating level based on the deviation vector and the likelihood probability includes: determining a deviation score based on the deviation vector, and determining the weight coefficients corresponding to the likelihood probability and the deviation score based on the usage scenario information; and performing a weighted summation calculation on the likelihood probability and the deviation score based on the weight coefficients to obtain the current data rating level.

[0076] The deviation score can be a value obtained by quantifying the deviation vector, used to characterize the degree of deviation between the current chip's real-time operating level and the benchmark of the real-time operating level of a high-quality chip.

[0077] In one embodiment, the deviation score can be determined based on the deviation vector by calculating the magnitude of the deviation vector and normalizing the magnitude to obtain the deviation score.

[0078] The weighting coefficient can be used to adjust the contribution of likelihood probability and deviation score to the current data rating level.

[0079] In one embodiment, determining the likelihood probability and the weighting coefficients corresponding to the deviation score based on usage scenario information can be achieved by pre-constructing a correlation between usage scenario information and weighting coefficients. The current usage scenario information is then mapped based on this correlation to obtain the target weighting coefficients. This correlation between usage scenario information and weighting coefficients can be constructed based on the priority of chip real-time operational similarity and stability requirements for different usage scenarios, industry application standards, and historical test verification data. As an example, the correlation between usage scenario information and weighting coefficients can be as follows: when the usage scenario information is automotive electronics, the corresponding likelihood probability and the weighting coefficients corresponding to the deviation score are 0.4 and 0.6, respectively; when the usage scenario information is consumer electronics, the corresponding likelihood probability and the weighting coefficients corresponding to the deviation score are 0.7 and 0.3, respectively.

[0080] In one embodiment, the current data rating level is obtained by weighted summation of the likelihood probability and the deviation score based on the weight coefficient. This can be achieved by multiplying the likelihood probability by its corresponding weight coefficient to obtain a first intermediate result, subtracting the deviation score from 1 and multiplying the result by the weight coefficient corresponding to the deviation score to obtain a second intermediate result, and then summing the first and second intermediate results to obtain the current data rating level.

[0081] The advantage of this approach is that by dynamically allocating the weights of likelihood probability and deviation score based on the usage scenario, the current data rating level can accurately match the core needs of different scenarios, ensuring the scenario adaptability of the real-time work performance rating.

[0082] S206, calculate the individual degradation rate parameter based on the failure assessment test data and the pre-constructed chip degradation trajectory curve, and determine the failure assessment data based on the individual degradation rate parameter.

[0083] S207, obtain the binary classification interval and the comprehensive level corresponding to the binary classification interval, and determine the current data scoring level and the comprehensive level corresponding to the binary classification interval to which the failure assessment data belongs as the target comprehensive level of the non-volatile memory chip.

[0084] The advantage of this scheme is that, when the likelihood probability is not lower than the first preset probability threshold and not higher than the second preset probability threshold, the current data rating level is determined based on the deviation vector of the current test data relative to the first chip feature space and the likelihood probability. This allows for a more refined and comprehensive evaluation of the overall performance of non-volatile memory chips in the intermediate real-time operating level range. It considers both the similarity of their features to those of high-quality chips and the degree of deviation of their real-time operating level, thereby improving the accuracy and discriminativeness of the rating.

[0085] Figure 3 This is a flowchart illustrating another method for determining the grade of a non-volatile memory chip provided in this application embodiment. For example... Figure 3 As shown, the specific steps include the following: S301 uses a robotic arm to move non-volatile memory chips from the feeding area to the target placement position in the test fixture.

[0086] S302, perform multi-dimensional memory chip testing on the non-volatile memory chip to obtain current test data and failure assessment test data of the non-volatile memory chip; wherein, the current test data includes current frequency test data, current capacity test data and current timing test data.

[0087] S303, obtain the usage scenario information of the non-volatile memory chip and determine the dynamic weighting matrix based on the usage scenario information, map the current test data to the pre-constructed first chip feature space based on the dynamic weighting matrix and calculate the corresponding likelihood probability, and determine the current data rating level based on the likelihood probability.

[0088] S304 determines the prior probability distribution information of the degradation rate parameter based on the pre-constructed chip degradation trajectory curve.

[0089] Among them, the degradation rate parameter can be a quantitative parameter that characterizes how fast the key reliability indicators of non-volatile memory chips decay over time, reflecting the evolution rate of failure risk during long-term use of the chip.

[0090] The prior probability distribution information can be the probability density function of the degradation rate parameter obtained statistically from a pre-constructed chip degradation trajectory curve. Specifically, the probability density function can be a function that describes the relative probability density of the degradation rate parameter (a continuous random variable) at different value points, and its integral over a certain interval is the probability that the degradation rate parameter falls within that interval.

[0091] In one embodiment, the method for determining the prior probability distribution information of degradation rate parameters based on chip degradation trajectory curves can be as follows: for each chip degradation trajectory curve, the corresponding degradation rate parameter is calculated using the linear regression slope method; the degradation rate parameters corresponding to all chip degradation trajectory curves are summarized to form a degradation rate parameter sample set; statistical analysis is performed on the degradation rate parameter sample set to calculate the probability density function of the degradation rate parameter sample set, i.e., the prior probability distribution information of the degradation rate parameters.

[0092] S305, construct the likelihood function corresponding to the failure assessment test data, and determine the posterior probability distribution information of the degradation rate parameter based on the prior probability distribution information and the likelihood function.

[0093] The likelihood function can be a function that takes the degradation rate parameter as the independent variable and the comprehensive key reliability index corresponding to the current failure assessment test data as the observed value, and is used to characterize the probability density of observing the comprehensive key reliability index under the premise of a certain degradation rate parameter.

[0094] In one embodiment, the likelihood function corresponding to the failure assessment test data can be constructed by normalizing and weighting the failure assessment test data of non-volatile memory chips recorded at the same time to obtain the comprehensive key reliability index corresponding to that time. The comprehensive key reliability index corresponding to the current non-volatile memory chip at each time is fitted to obtain the current chip degradation trajectory curve. For the chip degradation trajectory curves corresponding to each batch of historical non-volatile memory chips, the starting segment corresponding to the current chip degradation trajectory curve is extracted. The current chip degradation trajectory curve is compared with each starting segment to calculate the similarity between the two. According to the degradation rate parameter corresponding to the starting segment, the similarity of multiple starting segments with similar values ​​of a degradation rate parameter is weighted and averaged to obtain the relative probability of observing the current chip degradation trajectory curve near the value of the degradation rate parameter. Finally, with the degradation rate parameter as the independent variable and the relative probability of observing the current chip degradation trajectory curve as the dependent variable, the above statistical results are curve fitted or interpolated and smoothed to obtain the likelihood function corresponding to the current chip failure assessment test data.

[0095] The posterior probability distribution information can be an updated probability density function for the degradation rate parameter obtained by fusing the prior probability distribution information with the likelihood function corresponding to the current failure assessment test data.

[0096] In one embodiment, the method of determining the posterior probability distribution information of the degradation rate parameter based on the prior probability distribution information and the likelihood function can be achieved by fusing the prior probability distribution information and the likelihood function based on Bayes' theorem, and normalizing the product of the prior probability distribution information and the likelihood function to obtain the posterior probability distribution information corresponding to the degradation rate parameter.

[0097] S306, the expected value of the posterior probability distribution information is determined as the individual degradation rate parameter.

[0098] The expected value can be the first moment of the posterior probability distribution information, that is, the average value obtained by weighted integration of the posterior probability density function.

[0099] S307, determine failure assessment data based on the individual degradation rate parameter.

[0100] In one embodiment, determining the failure assessment data based on the individual degradation rate parameter includes: calculating the remaining lifetime probability distribution information of the non-volatile memory chip based on the individual degradation rate parameter and a preset failure threshold; calculating the expected value of the remaining lifetime probability distribution information and normalizing the expected value to obtain the failure assessment data.

[0101] The preset failure threshold can be the critical value corresponding to the decline of the comprehensive key reliability index of the non-volatile memory chip to the point that it can no longer meet the normal read / write, erase, or data retention functions.

[0102] Among them, the remaining lifetime probability distribution information can be the probability density function of the remaining effective working time of the non-volatile memory chip from the current moment to the preset failure threshold under the current individual degradation rate parameter.

[0103] In one embodiment, the method for calculating the remaining lifetime probability distribution information of a non-volatile memory chip based on individual degradation rate parameters and a preset failure threshold can be achieved by fitting the degradation trajectory curves of each chip to obtain an average chip degradation trajectory curve, calculating the average value of the degradation rate parameters corresponding to each chip degradation trajectory curve, calculating the ratio of the individual degradation rate parameter to the average value as a correction coefficient, using this correction coefficient to scale and correct the average chip degradation trajectory curve on the time axis to obtain the individual chip degradation trajectory curve of the current non-volatile memory chip, determining the theoretical remaining time required for key reliability indicators to decline to the preset failure threshold based on the individual chip degradation trajectory curve, and constructing the probability density function corresponding to the theoretical remaining time by combining the standard deviation of the degradation rate parameters corresponding to each chip degradation trajectory curve, thus obtaining the remaining lifetime probability distribution information.

[0104] In one embodiment, the method of calculating the expected value of the remaining lifetime probability distribution information and normalizing the expected value to obtain failure assessment data can be achieved by integrating the remaining lifetime probability distribution information to obtain the expected value, and then calculating the ratio of the expected value to the preset remaining lifetime as the failure assessment data.

[0105] The advantage of this approach is that it ensures the personalized accuracy of the evaluation results while reducing computational complexity through the reuse of historical data, enabling rapid quantitative assessment of the failure risk of non-volatile memory chips.

[0106] S308, obtain the binary classification interval and the comprehensive level corresponding to the binary classification interval, and determine the current data scoring level and the comprehensive level corresponding to the binary classification interval to which the failure assessment data belongs as the target comprehensive level of the non-volatile memory chip.

[0107] The advantage of this approach is that by modeling the degradation patterns of historical batches of chips as a prior probability distribution, and then combining it with current short-term failure assessment test data to construct a likelihood function, we can infer the posterior distribution of personalized degradation rate parameters, thus achieving an organic integration of historical statistical patterns and individual experimental evidence.

[0108] Figure 4 This is a flowchart illustrating another method for determining the grade of a non-volatile memory chip provided in an embodiment of this application. For example... Figure 4 As shown, the specific steps include the following: S401 uses a robotic arm to move non-volatile memory chips from the feeding area to the target placement position in the test fixture.

[0109] S402, perform multi-dimensional memory chip testing on the non-volatile memory chip to obtain current test data and failure assessment test data of the non-volatile memory chip; wherein, the current test data includes current frequency test data, current capacity test data and current timing test data.

[0110] S403, obtain the usage scenario information of the non-volatile memory chip and determine the dynamic weighting matrix based on the usage scenario information, map the current test data to the pre-constructed first chip feature space based on the dynamic weighting matrix and calculate the corresponding likelihood probability, and determine the current data rating level based on the likelihood probability.

[0111] S404, calculate the individual degradation rate parameter based on the failure assessment test data and the pre-constructed chip degradation trajectory curve, and determine the failure assessment data based on the individual degradation rate parameter.

[0112] S405, acquire historical chip sample data and perform cluster analysis on the historical chip sample data to obtain multiple sample clusters.

[0113] Among them, historical chip sample data can be the current data rating level and failure assessment data corresponding to non-volatile memory chips that have completed testing and grading in the past.

[0114] In one embodiment, historical chip sample data can be obtained by reading and summarizing it from a local database, a cloud database, or the historical records of a test system.

[0115] Among them, a sample cluster can be a data set formed by aggregating historical chip sample data with similar index characteristics through a clustering algorithm.

[0116] In one embodiment, the method of performing cluster analysis on historical chip sample data to obtain multiple sample clusters can be achieved by using machine learning clustering algorithms such as K-means clustering, DBSCAN clustering, or hierarchical clustering to classify and aggregate the historical chip sample data to obtain multiple sample clusters.

[0117] S406, calculate the centroid coordinates of each sample cluster, and calculate the high-quality reference distance of each sample cluster based on the centroid coordinates.

[0118] The centroid coordinates can be two-dimensional center coordinates formed by the current data rating level and failure assessment data of all sample points in a sample cluster.

[0119] In one embodiment, the centroid coordinates of each sample cluster can be calculated by averaging the current data rating and failure assessment data of all sample points within the sample cluster, and then combining the two average values ​​to form two-dimensional centroid coordinates, i.e., centroid coordinates.

[0120] The optimal reference distance can be the Euclidean distance or Manhattan distance between the centroid coordinates of the sample cluster and a preset optimal chip benchmark. The preset optimal chip benchmark can be the upper limit of the current data rating level and the failure assessment data.

[0121] In one embodiment, the method for calculating the optimal reference distance for each sample cluster based on the centroid coordinates can be to use the Euclidean distance or Manhattan distance between the centroid coordinates and a preset optimal chip reference point as the optimal reference distance.

[0122] S407, sort each of the sample clusters according to the superior reference distance, and assign a corresponding comprehensive level to each of the sample clusters according to the sorting results.

[0123] In one embodiment, the sample clusters are sorted according to the quality reference distance, and a corresponding comprehensive level is assigned to each sample cluster based on the sorting result. This can be done by sorting the sample clusters from smallest to largest quality reference distance, with a higher comprehensive level assigned to a smaller quality reference distance and a lower comprehensive level assigned to a larger quality reference distance.

[0124] S408, determine the corresponding binary classification interval based on each sample cluster, and integrate the binary classification interval and comprehensive level corresponding to each sample cluster.

[0125] In one embodiment, the method of determining the corresponding binary classification interval based on each sample cluster can be to use the minimum and maximum values ​​of the current data rating levels of all sample points in the sample cluster and the minimum and maximum values ​​of the failure assessment data to form the corresponding two-dimensional interval as the binary classification interval of the sample cluster.

[0126] In one embodiment, determining the corresponding binary classification interval based on each sample cluster includes: calculating the covariance matrix of each sample cluster, and determining the optimal classification hyperplane based on the centroid coordinates and covariance matrix of each sample cluster; calculating the binary intercept of the optimal classification hyperplane, and determining the binary classification interval corresponding to each sample cluster using the binary intercept as the interval boundary.

[0127] The covariance matrix can be a second-order square matrix used to characterize the dispersion of the current data rating level and failure assessment data in the sample cluster and the correlation between the dimensions, reflecting the distribution pattern and directional characteristics of the sample cluster in the two-dimensional feature space.

[0128] In one embodiment, the covariance matrix of each sample cluster can be calculated by decentralizing the two-dimensional feature data (current data rating level, failure assessment data) of all sample points within the sample cluster, and then constructing a 2×2 covariance matrix by calculating the covariance values ​​of the two dimensions.

[0129] The optimal classification hyperplane can be a linear boundary line in the two-dimensional feature space formed by the current data rating level and the failure assessment data, which can achieve the optimal classification division between adjacent sample clusters, satisfying the minimum classification error and the maximum classification interval for adjacent sample clusters.

[0130] In one embodiment, the optimal classification hyperplane can be determined based on the centroid coordinates and covariance matrix of each sample cluster by using linear discriminant analysis or support vector machine algorithms. The centroid coordinates of adjacent sample clusters are used as the classification center. Combined with the sample distribution divergence represented by the covariance matrix, the linear classification boundary that maximizes the inter-class distance and minimizes the intra-class distance is solved to obtain the optimal classification hyperplane.

[0131] Here, the binary intercept can be the intercept parameter of the optimal classification hyperplane in the two-dimensional feature space.

[0132] In one embodiment, the binary intercept of the optimal classification hyperplane can be calculated by solving the intercept parameter based on the linear equation of the optimal classification hyperplane, combined with the centroid coordinates and covariance matrix of the adjacent sample clusters, and then deriving the boundary intercepts corresponding to the two feature dimensions, i.e., the binary intercept, based on the intercept parameter.

[0133] In one embodiment, the method of determining the binary classification interval corresponding to each sample cluster by using the binary intercept as the interval boundary can be achieved by using the binary intercept corresponding to the optimal classification hyperplane as the boundary threshold of the adjacent sample clusters, and combining it with the centroid coordinate distribution direction of each sample cluster to define the upper and lower limit intervals of each sample cluster in the current data scoring level dimension and the upper and lower limit intervals of the failure assessment data dimension, thus forming the exclusive binary classification interval for each sample cluster.

[0134] The advantage of this scheme is that it accurately captures the distribution characteristics of sample clusters through the covariance matrix, and determines the classification interval by combining the optimal classification hyperplane and the binary intercept. This breaks through the limitations of traditional fixed threshold division, can adapt to the actual distribution of sample data, effectively solve the problem of overlapping division of adjacent sample clusters, and significantly improve the accuracy of binary classification intervals and the reliability of chip classification results.

[0135] In one embodiment, the method of integrating the binary hierarchical intervals and comprehensive levels corresponding to each sample cluster can be achieved by associating and storing the binary hierarchical intervals of each sample cluster with the comprehensive level corresponding to that sample cluster, thus forming a hierarchical mapping table.

[0136] S409, the comprehensive level corresponding to the current data rating level and the binary classification interval to which the failure assessment data belongs is determined as the target comprehensive level of the non-volatile memory chip.

[0137] The advantage of this scheme is that it automatically generates grading intervals and comprehensive grades by clustering historical chip sample data, eliminating the need for manual threshold division. It can adapt to changes in the distribution of chip indicator characteristics, improving the objectivity, accuracy, and universality of the grading results, while making the grading standards more closely match the distribution patterns of actual production test data.

[0138] Figure 5 This is a schematic diagram of a non-volatile memory chip level determination device provided in an embodiment of this application. Figure 5 As shown, the device includes: The chip placement module 510 is used to move non-volatile memory chips in the feeding area to the target placement position in the test fixture by means of a robotic arm; The chip testing module 520 is used to perform multi-dimensional memory chip testing on the non-volatile memory chip to obtain current test data and failure assessment test data of the non-volatile memory chip; wherein, the current test data includes current frequency test data, current capacity test data and current timing test data; The current evaluation module 530 is used to obtain the usage scenario information of the non-volatile memory chip and determine a dynamic weighting matrix based on the usage scenario information, map the current test data to a pre-constructed first chip feature space based on the dynamic weighting matrix and calculate the corresponding likelihood probability, and determine the current data rating level based on the likelihood probability. The failure assessment module 540 is used to calculate individual degradation rate parameters based on the failure assessment test data and the pre-constructed chip degradation trajectory curve, and to determine failure assessment data based on the individual degradation rate parameters. The rating determination module 550 is used to obtain the binary rating interval and the comprehensive rating corresponding to the binary rating interval, and to determine the current data rating level and the comprehensive rating corresponding to the binary rating interval to which the failure assessment data belongs as the target comprehensive rating of the non-volatile memory chip.

[0139] Furthermore, the current evaluation module 530 is specifically used for: If the likelihood probability is lower than a first preset probability threshold or higher than a second preset probability threshold, the current data rating level is determined based on the likelihood probability and the correspondence between the pre-constructed likelihood probability threshold range and the current data rating level, wherein the first preset probability threshold is less than the second preset probability threshold. If the likelihood probability is not lower than the first preset probability threshold and not higher than the second preset probability threshold, calculate the deviation vector of the current test data relative to the first chip feature space, and determine the current data rating level based on the deviation vector and the likelihood probability.

[0140] Furthermore, the current evaluation module 530 is specifically used for: The deviation score is determined based on the deviation vector, and the likelihood probability and the weight coefficient corresponding to the deviation score are determined based on the usage scenario information. The current data rating level is obtained by weighting and summing the likelihood probability and the deviation score according to the weight coefficient.

[0141] Furthermore, the failure assessment module 540 is specifically used for: The prior probability distribution information of the degradation rate parameter is determined based on the pre-constructed chip degradation trajectory curve; Construct the likelihood function corresponding to the failure assessment test data, and determine the posterior probability distribution information of the degradation rate parameter based on the prior probability distribution information and the likelihood function; The expected value of the posterior probability distribution information is determined as the individual degradation rate parameter.

[0142] Furthermore, the failure assessment module 540 is specifically used for: Based on the individual degradation rate parameter and the preset failure threshold, the remaining lifetime probability distribution information of the non-volatile memory chip is calculated; Calculate the expected value of the remaining lifetime probability distribution information and normalize the expected value to obtain failure assessment data.

[0143] Furthermore, the level determination module 550 is specifically used for: Historical chip sample data is acquired and cluster analysis is performed on the historical chip sample data to obtain multiple sample clusters; Calculate the centroid coordinates of each sample cluster, and calculate the high-quality reference distance of each sample cluster based on the centroid coordinates; The sample clusters are sorted according to the superior reference distance, and a corresponding comprehensive level is assigned to each sample cluster based on the sorting results. The corresponding binary classification intervals are determined based on each sample cluster, and the binary classification intervals and comprehensive levels corresponding to each sample cluster are integrated.

[0144] Furthermore, the level determination module 550 is specifically used for: Calculate the covariance matrix of each sample cluster, and determine the optimal classification hyperplane based on the centroid coordinates and covariance matrix of each sample cluster; Calculate the binary intercept of the optimal classification hyperplane, and use the binary intercept as the interval boundary to determine the binary classification interval corresponding to each sample cluster.

[0145] In this embodiment, a chip placement module is used to move a non-volatile memory chip from the feeding area to a target placement position in the test fixture using a robotic arm; a chip testing module is used to perform multi-dimensional memory chip testing on the non-volatile memory chip to obtain current test data and failure assessment test data of the non-volatile memory chip; a current assessment module is used to acquire usage scenario information of the non-volatile memory chip and determine a dynamic weighting matrix based on the usage scenario information, map the current test data to a pre-constructed first chip feature space based on the dynamic weighting matrix and calculate the corresponding likelihood probability, and determine the current data rating level based on the likelihood probability; a failure assessment module is used to calculate a personalized degradation rate parameter based on the failure assessment test data and a pre-constructed chip degradation trajectory curve, and determine the failure assessment data based on the personalized degradation rate parameter; and a rating determination module is used to acquire a binary rating interval and the comprehensive rating corresponding to the binary rating interval to which the failure assessment data belongs as the target comprehensive rating of the non-volatile memory chip. The aforementioned non-volatile memory chip classification device enables automated, multi-dimensional, and high-precision classification of non-volatile memory chips.

[0146] The non-volatile memory chip level determination device in this application embodiment can be a device, or it can be a component, integrated circuit, or chip in a terminal. The device can be a mobile electronic device or a non-mobile electronic device. For example, mobile electronic devices can be mobile phones, tablets, laptops, PDAs, in-vehicle electronic devices, wearable devices, ultra-mobile personal computers (UMPCs), netbooks, or personal digital assistants (PDAs), etc., while non-mobile electronic devices can be servers, network attached storage (NAS), personal computers (PCs), televisions (TVs), ATMs, or self-service machines, etc. This application embodiment does not impose specific limitations.

[0147] The non-volatile memory chip level determination device in this application embodiment can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this application embodiment does not specifically limit it.

[0148] The non-volatile memory chip level determination device provided in this application embodiment can implement the various processes implemented in the above embodiments. To avoid repetition, it will not be described again here.

[0149] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. For example... Figure 6 As shown, this application embodiment also provides an electronic device 600, including a processor 601, a memory 602, and a program or instructions stored in the memory 602 and executable on the processor 601. When the program or instructions are executed by the processor 601, they implement the various processes of the above-described non-volatile memory chip level determination method embodiment and can achieve the same technical effect. To avoid repetition, they will not be described again here.

[0150] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0151] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above-described method embodiment for determining the level of a non-volatile memory chip and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0152] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0153] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0154] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0155] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

[0156] The above description is merely a preferred embodiment and the technical principles employed in this application. This application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions that can be made by those skilled in the art will not depart from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the claims.

Claims

1. A method for determining the grade of a non-volatile memory chip, characterized in that, The method includes: The non-volatile memory chips in the feeding area are moved to the target placement position in the test fixture by a robotic arm; The non-volatile memory chip is subjected to multi-dimensional memory chip testing to obtain current test data and failure assessment test data of the non-volatile memory chip; wherein, the current test data includes current frequency test data, current capacity test data and current timing test data; The usage scenario information of the non-volatile memory chip is obtained and a dynamic weighting matrix is ​​determined based on the usage scenario information. The current test data is mapped to a pre-constructed first chip feature space based on the dynamic weighting matrix and the corresponding likelihood probability is calculated. The current data scoring level is determined based on the likelihood probability. The individual degradation rate parameters are calculated based on the failure assessment test data and the pre-constructed chip degradation trajectory curve, and the failure assessment data is determined based on the individual degradation rate parameters. Obtain the binary grading interval and the comprehensive grade corresponding to the binary grading interval, and determine the current data scoring grade and the comprehensive grade corresponding to the binary grading interval to which the failure assessment data belongs as the target comprehensive grade of the non-volatile memory chip.

2. The method for determining the grade of a non-volatile memory chip according to claim 1, characterized in that, Determining the current data rating level based on the likelihood probability includes: If the likelihood probability is lower than a first preset probability threshold or higher than a second preset probability threshold, the current data rating level is determined based on the likelihood probability and the correspondence between the pre-constructed likelihood probability threshold range and the current data rating level, wherein the first preset probability threshold is less than the second preset probability threshold. If the likelihood probability is not lower than the first preset probability threshold and not higher than the second preset probability threshold, calculate the deviation vector of the current test data relative to the first chip feature space, and determine the current data rating level based on the deviation vector and the likelihood probability.

3. The method for determining the grade of a non-volatile memory chip according to claim 2, characterized in that, The step of determining the current data rating level based on the deviation vector and the likelihood probability includes: The deviation score is determined based on the deviation vector, and the likelihood probability and the weight coefficient corresponding to the deviation score are determined based on the usage scenario information. The current data rating level is obtained by weighting and summing the likelihood probability and the deviation score according to the weight coefficient.

4. The method for determining the grade of a non-volatile memory chip according to claim 1, characterized in that, The calculation of individual degradation rate parameters based on the failure assessment test data and the pre-constructed chip degradation trajectory curve includes: The prior probability distribution information of the degradation rate parameter is determined based on the pre-constructed chip degradation trajectory curve; Construct the likelihood function corresponding to the failure assessment test data, and determine the posterior probability distribution information of the degradation rate parameter based on the prior probability distribution information and the likelihood function; The expected value of the posterior probability distribution information is determined as the individual degradation rate parameter.

5. The method for determining the grade of a non-volatile memory chip according to claim 1, characterized in that, The process of determining failure assessment data based on the individual degradation rate parameter includes: Based on the individual degradation rate parameter and the preset failure threshold, the remaining lifetime probability distribution information of the non-volatile memory chip is calculated; Calculate the expected value of the remaining lifetime probability distribution information and normalize the expected value to obtain failure assessment data.

6. The method for determining the grade of a non-volatile memory chip according to any one of claims 1-5, characterized in that, The acquisition of the binary hierarchical interval and the corresponding comprehensive level of the binary hierarchical interval includes: Historical chip sample data is acquired and cluster analysis is performed on the historical chip sample data to obtain multiple sample clusters; Calculate the centroid coordinates of each sample cluster, and calculate the high-quality reference distance of each sample cluster based on the centroid coordinates; The sample clusters are sorted according to the superior reference distance, and a corresponding comprehensive level is assigned to each sample cluster based on the sorting results. The corresponding binary classification intervals are determined based on each sample cluster, and the binary classification intervals and comprehensive levels corresponding to each sample cluster are integrated.

7. The method for determining the grade of a non-volatile memory chip according to claim 6, characterized in that, The step of determining the corresponding binary hierarchical interval based on each of the sample clusters includes: Calculate the covariance matrix of each sample cluster, and determine the optimal classification hyperplane based on the centroid coordinates and covariance matrix of each sample cluster; Calculate the binary intercept of the optimal classification hyperplane, and use the binary intercept as the interval boundary to determine the binary classification interval corresponding to each sample cluster.

8. A grade determination device for a non-volatile memory chip, characterized in that, The device includes: The chip placement module is used to move non-volatile memory chips from the feeding area to the target placement position in the test fixture via a robotic arm; The chip testing module is used to perform multi-dimensional memory chip testing on the non-volatile memory chip to obtain the current test data and failure assessment test data of the non-volatile memory chip; wherein, the current test data includes current frequency test data, current capacity test data and current timing test data; The current evaluation module is used to obtain the usage scenario information of the non-volatile memory chip and determine a dynamic weighting matrix based on the usage scenario information. Based on the dynamic weighting matrix, the current test data is mapped to a pre-constructed first chip feature space and the corresponding likelihood probability is calculated. Based on the likelihood probability, the current data score level is determined. The failure assessment module is used to calculate individual degradation rate parameters based on the failure assessment test data and the pre-constructed chip degradation trajectory curve, and to determine the failure assessment data based on the individual degradation rate parameters. The rating determination module is used to obtain the binary rating interval and the comprehensive rating corresponding to the binary rating interval, and to determine the current data rating level and the comprehensive rating corresponding to the binary rating interval to which the failure assessment data belongs as the target comprehensive rating of the non-volatile memory chip.

9. An electronic device, characterized in that, It includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the method for determining the grade of a non-volatile memory chip as described in any one of claims 1-7.

10. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions, which, when executed by a processor, implement the method for determining the level of a non-volatile memory chip as described in any one of claims 1-7.

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