Low-computational complexity neural network accelerator based on superposed pilot frequency

Abstract

The invention relates to the technical field of wireless communication, in particular to a hardware accelerator of a channel estimation model based on a neural network in the field of wireless communication, the accelerator adopts a software and hardware collaborative design, and the core architecture comprises a control processing unit, a computing unit, an on-chip memory, an off-chip memory and an AXI interface, the control processing unit is integrated with a least square method module, a control module and a hardware interface module, the control module adopts a ping-pong buffer mechanism to schedule tasks, the computing unit comprises an OFDM decoder, a fixed-point quantization module, a superposition pilot frequency module, a channel judgment module, a neural network module and an output module, and by utilizing a superposition pilot frequency technology, the channel judgment module and the neural network module are integrated into the control processing unit. Through low-bit wide fixed-point quantization, sparse weight decoding and a special pipeline computing architecture, a computing link is constructed in a neural network module, and the scheme is used for solving the problem of high computing complexity when a deep learning channel estimation method is deployed in a resource-limited edge scene in the prior art.

Description

Technical Field

[0001] This invention relates to the field of wireless communication, and more specifically, to a hardware accelerator for a neural network-based channel estimation model in the field of wireless communication. Background Technology

[0002] The performance of wireless communication systems is largely constrained by the wireless channel. During propagation, signals undergo complex phenomena such as multipath effects and Doppler shift, leading to distortion in the received signal. To accurately recover the transmitted signal at the receiver, the characteristics of the channel must be estimated; this process is called channel estimation. Accurate channel estimation is a crucial step in ensuring communication quality.

[0003] Traditional channel estimation methods are mainly divided into non-blind estimation, blind estimation, and semi-blind estimation. Among them, non-blind estimation based on pilots or training sequences is widely used due to its simple principle and stable performance. These methods (such as Least Squares (LS) and Minimum Mean Square Error (MMSE) algorithms) estimate the channel response by comparing the transmitted and received pilots, based on reference signals known to both the transmitter and receiver. However, the performance of traditional methods degrades rapidly when faced with complex, fast-time-varying channels and high-order MIMO systems. Furthermore, high-performance algorithms such as MMSE require knowledge of channel statistical characteristics, resulting in high computational complexity and making them difficult to implement in practical systems.

[0004] In recent years, deep learning technology has provided new approaches to channel estimation. Channel estimation algorithms based on neural networks (such as CNNs and DNNs) have demonstrated great potential. These data-driven methods do not rely on precise mathematical models; they can directly establish an end-to-end mapping from received signals to channel state information or even the original transmitted signals by learning from large amounts of channel data, thereby significantly improving estimation accuracy and robustness. In particular, neural networks can effectively mine the correlation of channel responses in the time and frequency domains, and for channels with sparse characteristics, they can further reduce pilot overhead by combining compressed sensing theory.

[0005] However, while deep learning offers many high-performance solutions for channel estimation, they generally suffer from complex network structures, large parameter counts, and high computational complexity. Complex models require enormous computational and storage bandwidth, leading to high power consumption and latency, severely limiting their deployment and application on resource-constrained edge devices (such as those using SoC or FPGA platforms). Therefore, significantly reducing computational complexity while maintaining channel estimation performance has become a key challenge in making deep learning channel estimation practical, especially for edge computing scenarios. Summary of the Invention

[0006] (a) Technical problems to be solved

[0007] To address the shortcomings of existing technologies, this invention provides a low-computational-complexity neural network accelerator based on superimposed pilots, which solves the problems mentioned in the background section.

[0008] (II) Technical Solution

[0009] To achieve the above objectives, the present invention specifically adopts the following technical solution:

[0010] According to a first aspect of the present invention, a low computational complexity neural network accelerator based on superimposed pilots is provided, comprising: a control processing unit (1), a computing unit (2), on-chip storage (3), off-chip storage (4), and an AXI interface (5); the control processing unit (1) includes a least squares module (6), a control module (7), and a hardware interface module (8), the control module (7) including a performance analysis module (15), an interrupt controller (16), a DMA controller (17), and a task controller (18), the hardware interface module (8) including a memory controller (19), an SD card controller (20), a UART (21), and an Ethernet controller (22); the computing unit (2) includes an OFDM decoder (9), a fixed-point quantization module (9), and a fixed-point quantization module (10), which are connected in sequence. 10) A superimposed pilot module (11), a channel judgment module (12), a neural network module (13), and an output module (14). The neural network module (13) includes a weight decoder (23), a processing unit array (24), an addition tree (25), an activation function (26), and a matrix splicing module (27). The weight decoder (23) includes a weight and index module (30) and a multiplier module (31). The output module (14) includes a channel estimation matrix (28) and an output buffer (29). The AXI interface (5) connects the on-chip storage (3) to the off-chip storage (4) and the control processing unit (1) to the computing unit (2). The off-chip storage (4) is used to store weight data (32) and OFDM frame data (33).

[0011] Further defined, the control module (7) coordinates the operation of the computing unit (2), the on-chip storage (3) and the hardware interface module (8) through the internal bus, wherein the task controller (18) uses a ping-pong buffer mechanism to schedule the least squares module (6) and the computing unit (2); the DMA controller (17) accesses the off-chip storage (4) through the AXI interface (5) and completes the transmission of the weight data (32) and the OFDM frame data (33) between the off-chip storage (4), the on-chip storage (3) or the computing unit (2) under the control of the task controller (18); the interrupt controller (16) is used to summarize the status signals of the DMA controller (17), the performance analysis module (15) and the computing unit (2) and generate an interrupt request; the performance analysis module (15) is used to monitor the computing unit utilization, data throughput and task latency of the accelerator in real time.

[0012] Furthermore, the least squares module (6) is integrated inside the control processing unit (1), unlike the architecture where it is deployed in the computing unit (2); the module (6) is used to perform initial channel estimation, and its calculation result is directly scheduled to the channel judgment module (12) of the computing unit (2) through the control module (7), thereby reducing the fixed function calculation burden of the computing unit (2) and improving its parallel efficiency of neural network processing.

[0013] Further defined, the hardware interface module (8) is interconnected with the control module (7) via an internal bus to provide the accelerator with a connection to external devices and to operate under the scheduling of the task controller (18). The memory controller (19) is used to access the off-chip storage (4) to transfer the OFDM frame data (33) to the least squares module (6). The SD card controller (20) is used to load firmware and parameters during system initialization. The UART (21) is used to output debugging information and perform low-speed command interaction. The Ethernet controller (22) works in conjunction with the AXI interface (5) through the DMA controller (17) to receive network data and transmit processing results back.

[0014] Further defining the data flow of the computing unit (2), the core of which is processing superimposed pilot signals, specifically includes: the OFDM decoder (9) performs Fourier transform, demodulation and deinterleaving operations on the OFDM frame data to recover the symbol data stream in the frequency domain; outputs it to the fixed-point quantization module (10) to quantize the decoded floating-point symbol data into fixed-point data; the superimposed pilot module (11) extracts the known superimposed pilot signal from the quantized data stream to provide a reference for subsequent channel state estimation; then combines it with the initial channel estimation from the least squares module (6) in the channel judgment module (12) to select a neural network algorithm; the neural network module (13) performs calculations based on the selected algorithm and the weight data from the on-chip storage (3), and outputs the result to the channel estimation matrix (28) and output buffer (29) in the output module (14).

[0015] Further, the superimposed pilot module (11) is configured to: extract pilot signals from the data stream output by the fixed-point quantization module (10) while allowing user data to continuously flow to the channel judgment module (12), thereby realizing parallel processing of pilot extraction and user data transmission.

[0016] Furthermore, the neural network module (13) is configured to process low bit-width fixed-point data, and its computational precision is compatible with the output precision of the fixed-point quantization module (10) in the computing unit (2), so that the low bit-width fixed-point data output by the fixed-point quantization module (10) can be directly processed by the neural network module (13), forming a coherent low-precision computing link within the accelerator, thereby reducing data storage bandwidth and computing resource consumption.

[0017] Further specified, the low bit width fixed-point data adopts the (W, I) fixed-point number format, where W is the total bit width, I is the integer part bit width, and the value of I is increased with a safety margin on the basis of ensuring that the data representation does not overflow. The value of W makes the operation accuracy of the neural network module (13) meet the predetermined performance requirements.

[0018] Further specified, the weight decoder (23) in the neural network module (13) is configured to: parse the sparse compressed weight data from the on-chip storage (3) through the weight and index module (30) to generate non-zero weights and their corresponding indices; the multiplier module (31) performs multiplication and addition operations on the non-zero weights only with the corresponding input data in the processing unit array (24) according to the index, skipping the calculation of zero weights or zero activation values, thereby further reducing the computational complexity of the neural network module (13).

[0019] Furthermore, the neural network module (13) employs a pipelined design, wherein the processing unit array (24) performs multiplication and addition operations to generate a partial sum; the result is then fed into the addition tree (25) for accumulation; the activation function (26) applies a nonlinear transformation to the accumulation result; the matrix splicing module (27) reassembles the transformed output features and sends the reassembled result into the output module (14). Through the pipelined design, when the neural network module (13) is engaged in continuous computation, each operation is performed simultaneously on its own dedicated functional segment, thereby improving hardware utilization and computational throughput.

[0020] (III) Beneficial Effects

[0021] Compared with existing technologies, the advantages of this invention are: it innovatively proposes a hardware accelerator architecture that combines traditional signal processing and neural networks. This approach does not simply deploy complex network models onto hardware, but rather optimizes the channel estimation task at both the algorithm and hardware levels. By utilizing a series of designs including superimposed pilot technology, fixed-point quantization, sparsity compression, and pipelined computing architecture, the computational complexity and resource consumption of the neural network model are reduced, providing a valuable implementation scheme for deploying channel estimation technology on edge platforms. Attached Figure Description

[0022] Figure 1 This is an overview diagram of the functional modules of the accelerator hardware architecture of the present invention.

[0023] Figure 2 This is a hardware architecture diagram of the accelerator of the present invention.

[0024] In the diagram: 1. Control and processing unit; 2. Computation unit; 3. On-chip storage; 4. Off-chip storage; 5. AXI interface; 6. Least squares module; 7. Control module; 8. Hardware interface module; 9. OFDM decoder; 10. Fixed-point quantization module; 11. Superimposed pilot module; 12. Channel judgment module; 13. Neural network module; 14. Output module; 15. Performance analysis module; 16. Interrupt controller; 17. DMA controller; 18. Task controller; 19. Memory controller; 20. SD card controller; 21. UART controller; 22. Ethernet controller; 23. Weight decoder; 24. Processing unit array; 25. Addition tree; 26. Activation function; 27. Matrix splicing module; 28. Channel estimation matrix; 29. ​​Output buffer; 30. Weight and index module; 31. Multiplier module; 32. Weight data; 33. OFDM frame data. Detailed Implementation

[0025] Before describing the embodiments of the present invention in detail, some of the terms used therein are explained as follows:

[0026] Pilot overlay is a method of superimposing a known pilot signal onto the signal carrying user data in the frequency or time domain, rather than occupying a separate subcarrier or time slot. Consider a superimposed signal where a low-power pilot (training) signal is superimposed onto the data signal at the transmitter. Then, this superimposed signal is used for channel estimation at the receiver without sacrificing information rate.

[0027] A superimposed signal, which includes a power of Pilot signal and a power of The data signal, assuming the total power of the signal is equal to .

[0028] For in the first The first subcarrier transmission Each OFDM symbol, when superimposed, can be represented as... ,in and These represent data and pilot signals, respectively. The corresponding received signal can be represented as:

[0029]

[0030] in, and They represent the first time. The received signal and noise of the k-th subcarrier in a symbol period This indicates the corresponding channel frequency response.

[0031] Here, we assume the channel's coherence time or bandwidth is M, where the channel response is almost constant along the time or frequency axis. Furthermore, for a time or frequency interval of length M, if the pilot signal is kept constant, then:

[0032]

[0033] Assuming the data signal and noise are independent and identically distributed processes with zero mean, then the average received signal over a time or frequency interval of length M can be expressed as:

[0034]

[0035] Assuming M in the equation is large enough, the average value of the data signal is approximately zero:

[0036]

[0037] The channel estimate can be obtained using the formula:

[0038]

[0039] The method of superimposing pilot signals, because each pilot is superimposed on the data, not only reflects changes at each location, but also results in a denser received pilot matrix. It is transmitted along with the data at the transmitting end and extracted from the received mixed signal by the receiving end through a dedicated module (such as the superimposed pilot module 11). This technique can significantly improve spectral efficiency.

[0040] Fixed-point quantization is a method of converting floating-point numbers into a data representation with a lower bit width and a specific number of bits. It maps the decoded floating-point sign data to a total bit width. The integer part has a bit width of Fixed-point numbers. Floating-point numbers. Quantized into fixed-point numbers The formula can be expressed as:

[0041]

[0042] in, The bit width of the decimal part , This represents rounding or truncation. This operation greatly reduces data storage bandwidth and computing resource consumption. It significantly reduces the bandwidth required for data storage and the hardware resources (such as DSP units) needed for subsequent computations. Through careful selection... Parameters can significantly reduce computational complexity and power consumption while ensuring algorithm performance (such as channel estimation accuracy), and are a key technology for enabling complex neural network models to run efficiently on resource-constrained edge devices.

[0043] Heterogeneous computing architecture refers to a computing platform that integrates different types of processing units, such as the PS (processing system) and PL (programmable logic) components of the ZYNQ series. In this invention, it specifically refers to a hardware system consisting of a control processing unit 1 (as the management core) and a computing unit 2 (as a dedicated computing engine). The control unit is responsible for task scheduling and system management, while the computing unit focuses on performing highly parallel signal processing and neural network inference tasks. This architecture achieves efficient interconnection and collaborative operation through the AXI interface 5, making it particularly suitable for handling computationally intensive tasks such as wireless channel estimation, achieving an excellent balance between performance, power consumption, and flexibility.

[0044] The ping-pong buffer mechanism is a highly efficient data flow control technique that enables continuous data processing by configuring two or more buffers and having them work alternately. Under the scheduling of the task controller 18, while one buffer (such as the "ping" buffer) is being processed by the computing unit 2, the other buffer (the "pong" buffer) can be simultaneously filled with the next batch of data by the DMA controller 17. This mechanism effectively hides the access latency of moving data from off-chip storage 4 to on-chip storage 3 or the computing unit, ensuring that the computing unit can work almost continuously and avoiding idle time due to waiting for data, thereby maximizing data transfer bandwidth and the utilization of the hardware computing unit.

[0045] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0046] Please see Figure 1 and Figure 2 This invention relates to a low-computational-complexity neural network accelerator based on superimposed pilots. This system can efficiently coordinate traditional signal processing and neural network computation to achieve a complete hardware acceleration process from physical layer signal decoding to high-precision channel estimation. The heterogeneous computing architecture and optimized accelerator structure significantly reduce model computational complexity and data transfer overhead, providing a solution for achieving high-performance, low-power channel estimation on resource-constrained edge platforms, and has important application value and practical significance.

[0047] The core architecture of the accelerator includes: a control processing unit 1, a computing unit 2, on-chip storage 3, off-chip storage 4, and an AXI interface 5 connecting the above components.

[0048] The control processing unit 1, serving as the system's command center, integrates the least squares method module 6, the control module 7, and the hardware interface module 8. Its innovation lies in integrating the least squares method module 6, traditionally deployed in the computing unit 2, into the control unit. This module utilizes the least squares estimation algorithm to perform initial channel estimation. Its function is to directly schedule the calculation results to the computing unit 2 via the control module 7, thereby reducing the fixed function calculation burden on the computing unit 2 without compromising algorithm accuracy.

[0049] The computing unit 2 serves as the core of heterogeneous computing, with its internal modules connected sequentially to form an efficient data processing pipeline: OFDM decoder 9 → fixed-point quantization module 10 → superimposed pilot module 11 → channel judgment module 12 → neural network module 13 → output module 14.

[0050] AXI interface 5 serves as a high-performance system bus, responsible for interconnecting all critical data paths. Off-chip memory 4 (such as DDR memory) is used to store large amounts of weight data 32 and OFDM frame data 33, while on-chip memory 3 provides a high-speed cache for the computation process.

[0051] The control module 7 is the system's scheduling hub, with its internal sub-modules working collaboratively. The task controller 18 employs a ping-pong buffer mechanism for task scheduling. This works by setting up two buffers; while one set of data is being processed by the least squares module 6 or the computing unit 2, the other buffer can be simultaneously filled with the next batch of data. This parallelizes computation and data transfer, effectively hiding access latency and ensuring continuous operation of the computing unit. The DMA controller 17 directly accesses the off-chip storage 4 via the AXI interface 5, efficiently completing the transfer of weight data 32 and OFDM frame data 33 between storage levels under the command of the task controller 18. The interrupt controller 16 aggregates the status signals from the DMA controller 17, performance analysis module 15, and computing unit 2 and generates interrupt requests. The performance analysis module 15 has a built-in counter for real-time monitoring of key performance indicators such as computing unit utilization, data throughput, and task latency, providing data support for system optimization.

[0052] The data flow of computing unit 2 focuses on processing superimposed pilot signals. Its specific process is as follows: OFDM decoder 9 performs Fourier transform, demodulation, and deinterleaving operations on the OFDM frame data to recover the frequency domain symbol data stream. Fixed-point quantization module 10 quantizes the floating-point symbol data into low-bit-width fixed-point numbers. The principle is to convert floating-point numbers... Mapped to Its function is to significantly reduce data storage bandwidth and computing resource consumption. The superimposed pilot module 11 is configured to extract known superimposed pilot signals from the quantized data stream. Its key innovation in deployment on the device lies in realizing parallel processing of pilot extraction and user data transmission, that is, while extracting pilot signals, user data can be continuously fed to subsequent modules, thereby reducing overall processing latency. The channel determination module 12 combines the extracted pilot information with the initial channel estimation results from the least squares module 6 to select the optimal neural network algorithm.

[0053] The neural network module 13 is the core computing engine of this invention. It is configured to process low-bit-width fixed-point data, and its computational precision is compatible with the output of the fixed-point quantization module 10, thereby forming a coherent low-precision computing chain within the accelerator.

[0054] The neural network module 13 achieves low-complexity computation through multiple optimization techniques: the weight decoder 23 processes sparse compressed weight data. The principle is that the weight and index module 30 parses the sparse data from on-chip storage 3, generating non-zero weights and their corresponding indices; the multiplier module 31 then performs multiplication and addition operations only on the valid input data in the processing unit array 24 based on the indices. This skips invalid calculations for zero weights or zero activation values, significantly reducing computational complexity. Pipeline design: The module internally forms a highly efficient pipeline. The processing unit array 24 performs multiplication and addition operations to generate partial sums; the results are fed into the addition tree 25 for accumulation; the activation function 26 applies a nonlinear transformation (such as the ReLU function) to the accumulated result; the matrix concatenation module 27 reassembles the features and sends them to the output module 14. The principle is time overlap technology; when the module is engaged in continuous computation, multiplication, accumulation, nonlinear transformation, and other operations are performed simultaneously on their respective dedicated functional segments. This greatly improves hardware utilization and computational throughput.

[0055] The accelerator described in this specific embodiment reduces the computational complexity, data storage bandwidth, and resource consumption of channel estimation tasks through a series of collaborative optimization techniques, including heterogeneous computing architecture, parallel processing of superimposed pilots, low-bit-width fixed-point quantization, sparsity-based weight decoding, and deep pipeline design. This enables high-performance neural network channel estimation models to be efficiently deployed on resource-constrained edge computing platforms, solving problems encountered in practical applications.

[0056] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, and are not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A low-computational-complexity neural network accelerator based on superimposed pilots, comprising: The system comprises a control processing unit (1), a computing unit (2), on-chip storage (3), off-chip storage (4), and an AXI interface (5); the control processing unit (1) includes a least squares module (6), a control module (7), and a hardware interface module (8); the control module (7) includes a performance analysis module (15), an interrupt controller (16), a DMA controller (17), and a task controller (18); the hardware interface module (8) includes a memory controller (19), an SD card controller (20), a UART (21), and an Ethernet controller (22); the computing unit (2) includes an OFDM decoder (9), a fixed-point quantization module (10), a superimposed pilot module (11), and a channel determination module connected in sequence. The system comprises a module (12), a neural network module (13), and an output module (14). The neural network module (13) includes a weight decoder (23), a processing unit array (24), an addition tree (25), an activation function (26), and a matrix concatenation module (27). The weight decoder (23) includes a weight and index module (30) and a multiplier module (31). The output module (14) includes a channel estimation matrix (28) and an output buffer (29). The AXI interface (5) connects the on-chip storage (3) to the off-chip storage (4) and the control processing unit (1) to the computing unit (2). The off-chip storage (4) is used to store weight data (32) and OFDM frame data (33).

2. The accelerator according to claim 1, characterized in that, The least squares module (6) is integrated inside the control processing unit (1), unlike the architecture where it is deployed in the computing unit (2). The module (6) is used to perform initial channel estimation, and its calculation result is directly scheduled to the channel judgment module (12) of the computing unit (2) through the control module (7), thereby reducing the fixed function calculation burden of the computing unit (2) and improving its parallel efficiency of neural network processing.

3. The accelerator according to claim 1, characterized in that, The control module (7) coordinates the operation of the computing unit (2), the on-chip storage (3), and the hardware interface module (8) through the internal bus. The task controller (18) uses a ping-pong buffer mechanism to schedule the least squares module (6) and the computing unit (2). The DMA controller (17) accesses the off-chip storage (4) through the AXI interface (5) and completes the transmission of the weight data (32) and the OFDM frame data (33) between the off-chip storage (4), the on-chip storage (3), or the computing unit (2) under the control of the task controller (18). The interrupt controller (16) is used to summarize the status signals of the DMA controller (17), the performance analysis module (15), and the computing unit (2) and generate an interrupt request. The performance analysis module (15) is used to monitor the computing unit utilization, data throughput, and task latency of the accelerator in real time.

4. The accelerator according to claim 1, characterized in that, The hardware interface module (8) is interconnected with the control module (7) via an internal bus to provide the accelerator with a connection to external devices and to work under the scheduling of the task controller (18). The memory controller (19) is used to access the off-chip storage (4) to transfer the OFDM frame data (33) to the least squares module (6). The SD card controller (20) is used to load firmware and parameters during system initialization. The UART (21) is used to output debugging information and perform low-speed command interaction. The Ethernet controller (22) works in conjunction with the AXI interface (5) through the DMA controller (17) to receive network data and transmit processing results back.

5. The accelerator according to claim 1, characterized in that, The data flow of the computing unit (2) is centered on processing superimposed pilot signals, specifically including: the OFDM decoder (9) performs Fourier transform, demodulation and deinterleaving operations on the OFDM frame data to recover the symbol data stream in the frequency domain; outputs it to the fixed-point quantization module (10) to quantize the decoded floating-point symbol data into fixed-point data; the superimposed pilot module (11) extracts the known superimposed pilot signal from the quantized data stream to provide a reference for subsequent channel state estimation; then it combines the initial channel estimation from the least squares module (6) in the channel judgment module (12) to select a neural network algorithm; the neural network module (13) performs calculations based on the selected algorithm and the weight data from the on-chip storage (3), and outputs the results to the channel estimation matrix (28) and output buffer (29) in the output module (14).

6. The accelerator according to claim 5, characterized in that, The superimposed pilot module (11) is configured to extract pilot signals from the data stream output by the fixed-point quantization module (10) while allowing user data to continuously flow to the channel judgment module (12), thereby realizing parallel processing of pilot extraction and user data transmission.

7. The accelerator according to claim 5, characterized in that, The neural network module (13) is configured to process low bit-width fixed-point data, and its computational precision is compatible with the output precision of the fixed-point quantization module (10) in the computing unit (2), so that the low bit-width fixed-point data output by the fixed-point quantization module (10) can be directly processed by the neural network module (13), forming a coherent low-precision computing link within the accelerator, thereby reducing data storage bandwidth and computing resource consumption.

8. The accelerator according to claim 7, characterized in that, The low bit-width fixed-point data adopts the (W, I) fixed-point number format, where W is the total bit width and I is the integer part bit width. The value of I is increased with a safety margin on the basis of ensuring that the data representation does not overflow. The value of W makes the operation accuracy of the neural network module (13) meet the predetermined performance requirements.

9. The accelerator according to claim 7, characterized in that, The weight decoder (23) in the neural network module (13) is configured to: parse the sparse compressed weight data from the on-chip storage (3) through the weight and index module (30) to generate non-zero weights and their corresponding indices; the multiplier module (31) performs multiplication and addition operations on the non-zero weights only with the corresponding input data in the processing unit array (24) according to the index, skipping the calculation of zero weights or zero activation values, thereby further reducing the computational complexity of the neural network module (13).

10. The accelerator according to claim 9, characterized in that, The neural network module (13) employs a pipelined design, wherein the processing unit array (24) performs multiplication and addition operations to generate a partial sum; the result is then fed into the addition tree (25) for accumulation; the activation function (26) applies a nonlinear transformation to the accumulation result; the matrix splicing module (27) reassembles the transformed output features and sends the reassembled result into the output module (14). Through the pipelined design, when the neural network module (13) is engaged in continuous computation, each operation is performed simultaneously on its own dedicated functional segment, thereby improving hardware utilization and computational throughput.

Images