Semiconductor device and data storage system including the same

Abstract

The invention discloses a semiconductor device and a data storage system. A semiconductor device according to an example embodiment of the present disclosure includes gate electrodes spaced apart from each other in a first direction and stacked; a channel structure extending through the gate electrode and extending in a first direction; and contact plugs extending in a first direction and electrically connected to the gate electrodes, respectively, at least a portion of the contact plugs extending through at least one of the gate electrodes and contacting the gate electrodes, the contact plugs including first contact plugs and second contact plugs alternately arranged in a second direction, the first contact plugs have respective depths that increase as distance from the memory cell region increases in the second direction, and the second contact plugs have respective depths that decrease as distance from the memory cell region increases in the second direction.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and data storage systems including such semiconductor devices. Background Technology

[0002] In data storage systems that utilize data storage, semiconductor devices capable of storing large amounts of data may be required. Therefore, methods to increase the data storage capacity of semiconductor devices have been investigated. For example, as one method to increase the data storage capacity of semiconductor devices, semiconductor devices comprising memory cells arranged in a three-dimensional rather than a two-dimensional arrangement have been proposed. Summary of the Invention

[0003] One aspect of this disclosure is to provide a semiconductor device with improved reliability.

[0004] One aspect of this disclosure is to provide a data storage system that includes semiconductor devices with improved reliability.

[0005] A semiconductor device according to an example embodiment may include: a plate including a memory cell region and a contact region on at least one side of the memory cell region; gate electrodes spaced apart from each other and stacked in a first direction perpendicular to the upper surface of the plate; a channel structure extending through the gate electrodes in the memory cell region and extending in the first direction; and contact plugs extending in the contact region in the first direction and electrically connected to the gate electrodes respectively, at least a portion of the contact plugs extending through at least one of the gate electrodes and contacting the gate electrode, the contact plugs including a first contact plug and a second contact plug alternately arranged in a second direction perpendicular to the first direction, the first contact plug having a corresponding depth that increases with increasing distance from the memory cell region in the second direction, and the second contact plug having a corresponding depth that decreases with increasing distance from the memory cell region in the second direction.

[0006] A semiconductor device according to an example embodiment may include: a substrate including a memory cell region and a contact region on at least one side of the memory cell region; gate electrodes spaced apart from each other and stacked in a first direction perpendicular to the upper surface of the substrate; a channel structure extending through the gate electrodes in the memory cell region and extending in the first direction; and contact plugs arranged upward in the contact region in a second direction perpendicular to the first direction and a third direction perpendicular to the first and second directions, extending in the first direction and electrically connected to the gate electrodes respectively, the contact region including a first region and a second region, two or more contact plugs in the first region and the second region respectively, the first region and the second region being adjacent to each other in a plan view and having the same area, the sum of the layer numbers of the gate electrodes electrically connected to the contact plugs arranged in the first region and the sum of the layer numbers of the gate electrodes electrically connected to the contact plugs arranged in the second region may be the same as each other.

[0007] A data storage system according to an example embodiment may include: a semiconductor memory device including a first semiconductor structure containing circuit elements, a second semiconductor structure on the first semiconductor structure, and input / output pads electrically connected to the circuit elements; and a controller electrically connected to the semiconductor memory device via the input / output pads and configured to control the semiconductor memory device. The second semiconductor structure may include: a plate including a memory cell region and a contact region on at least one side of the memory cell region; N gate electrodes spaced apart from each other and stacked in a first direction perpendicular to the upper surface of the plate; a channel structure extending through the gate electrodes in the memory cell region and extending in the first direction; and contact plugs arranged upward in a second direction perpendicular to the first direction and a third direction perpendicular to the first and second directions in the contact region and extending in the first direction and electrically connected to the gate electrodes respectively. The contact region may include a first region and a second region. Two or more contact plugs are respectively located in the first region and the second region. The first region and the second region are adjacent to each other in a plan view and have the same area. The difference between the sum of the layer numbers of the gate electrodes electrically connected to the contact plugs arranged in the first region and the sum of the layer numbers of the gate electrodes electrically connected to the contact plugs arranged in the second region may be 0.2N or less, where N is a natural number.

[0008] Contact plugs can be configured such that the sum of the depths of contact plugs in adjacent regions differs within a certain range, thereby providing semiconductor devices and data storage systems including such semiconductor devices with improved reliability.

[0009] The advantages and effects of this application are not limited to the foregoing, and can be more easily understood in the process of describing specific exemplary embodiments of this disclosure. Attached Figure Description

[0010] The above and other aspects, features and advantages of this disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a schematic plan view of a semiconductor device according to an example embodiment;

[0012] Figure 2A and Figure 2B This is a schematic cross-sectional view of a semiconductor device according to an example embodiment;

[0013] Figure 3 This is a schematic diagram illustrating the arrangement of the lower contact plug of a semiconductor device according to an exemplary embodiment;

[0014] Figures 4A to 4C These are a plan view and a cross-sectional view of a semiconductor device according to an example embodiment, and a schematic diagram showing the arrangement of the lower contact plug;

[0015] Figures 5A to 5C These are a plan view and a cross-sectional view of a semiconductor device according to an example embodiment, and a schematic diagram showing the arrangement of the lower contact plug;

[0016] Figure 6A and Figure 6B These are a plan view of a semiconductor device according to an example embodiment and a schematic diagram showing the arrangement of the lower contact plugs, respectively.

[0017] Figure 7A and Figure 7B This is a plan view of a semiconductor device according to an example embodiment;

[0018] Figure 8 This is a cross-sectional view of a semiconductor device according to an example embodiment;

[0019] Figure 9 This is a cross-sectional view of a semiconductor device according to an example embodiment;

[0020] Figure 10A and Figure 10B This is a cross-sectional view of a semiconductor device according to an example embodiment;

[0021] Figures 11A to 11L This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment;

[0022] Figure 12 This is a schematic diagram of a data storage system including semiconductor devices according to an example embodiment; and

[0023] Figure 13 This is a perspective view schematically illustrating a data storage system including semiconductor devices according to an example embodiment. Detailed Implementation

[0024] In the following description, exemplary embodiments of the present disclosure will be illustrated with reference to the accompanying drawings. In the drawings, the same reference numerals denote the same elements, and redundant descriptions thereof will be omitted. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items. It should be noted that aspects described with respect to one embodiment may be incorporated into different embodiments, although not specifically described therewith. That is, features of all and / or any embodiment may be combined in any manner and / or combination.

[0025] Figure 1 This is a schematic plan view of a semiconductor device according to an example embodiment.

[0026] Figure 2A and Figure 2B This is a schematic cross-sectional view of a semiconductor device according to an example embodiment. Figure 2A and Figure 2B They are along Figure 1 The cross sections cut by cutting lines I-I' and II-II'.

[0027] Figure 3 This is a schematic diagram illustrating the arrangement of the lower contact plug of a semiconductor device according to an example embodiment.

[0028] Reference Figure 1 , Figure 2A , Figure 2B and Figure 3The semiconductor device 100 may include a memory cell region MCA and a first contact region CT1 and a second contact region CT2. The semiconductor device 100 includes a plate layer 101, a gate electrode 130 stacked on the plate layer 101 and included in a gate structure GS, an interlayer insulating layer 120 alternately stacked with the gate electrode 130 and included in the gate structure GS, a channel structure CH configured to penetrate or extend through the gate structure GS in the memory cell region MCA, a gate separation region MS penetrating or extending through the gate structure GS, a first upper separation region SS1 and a second upper separation region SS2 penetrating or extending through the upper gate electrode 130U disposed in the upper part of the gate electrode 130, an upper contact plug MC_U electrically connected to the upper gate electrode 130U in the first contact region CT1 and extending vertically (in the Z direction), a lower contact plug MC_L electrically connected to the memory gate electrode 130M and the lower gate electrode 130L in the second contact region CT2 and extending vertically (in the Z direction), and a dummy vertical structure DH disposed around the contact plugs MC_U and MC_L. Semiconductor device 100 may further include contact spacers 160, studs 180, cell interconnects 185, and a first cell region insulating layer 192 and a second cell region insulating layer 194, at least partially surrounding contact plugs MC_U and MC_L. As may be used herein, the term "surround" (or "surrounds" or similar terms) is intended to broadly refer to an element, structure, or layer that extends around, encloses, surrounds, or surrounds another element, structure, or layer on all sides, although breaks or gaps may also be present. Thus, for example, a layer of material having voids or gaps therein may still "surround" another layer it surrounds.

[0029] In the semiconductor device 100, the memory cell region MCA can be a region in which a channel structure CH is disposed, and it can also be a region in which memory cells are disposed. The first contact region CT1 and the second contact region CT2 can correspond to regions used for electrically connecting the gate electrode 130 to a circuit element (not shown). The first contact region CT1 and the second contact region CT2 can be sequentially disposed from at least one end of the memory cell region MCA in at least one direction (e.g., in the X direction). Depending on the description, the memory cell region MCA and the first contact region CT1 and the second contact region CT2 can be referred to as regions of the plate 101 rather than regions of the semiconductor device 100.

[0030] The plate layer 101 may have a plate shape and may serve as at least a portion of the common source line of the semiconductor device 100. The plate layer 101 may include a conductive material. For example, the plate layer 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon, germanium, or silicon-germanium. The plate layer 101 may further include impurities. The plate layer 101 may be provided as a polycrystalline semiconductor layer (such as a polycrystalline silicon layer) or an epitaxial layer.

[0031] Gate electrodes 130 may be vertically spaced and stacked on the plate layer 101 (in the Z direction) and may be included in the gate structure GS together with the interlayer insulating layer 120. The gate structure GS may include first to fourth stacked structures GS1, GS2, GS3, and GS4 stacked vertically (in the Z direction). However, according to exemplary embodiments, the number of stacked structures included in the gate structure GS may vary in various ways. For example, in some exemplary embodiments, the gate structure GS may be formed by fewer than four stacked structures or five or more stacked structures, or it may be formed as a single stacked structure. The number of gate electrodes 130 included in each of the first to fourth stacked structures GS1, GS2, GS3, and GS4 may be the same or different from each other.

[0032] The gate electrode 130 may include an upper gate electrode 130U comprising gate electrodes included in a string select transistor and an erase transistor, a memory gate electrode 130M comprising gate electrodes included in a plurality of memory cells, and a lower gate electrode 130L comprising a gate electrode included in a ground select transistor. The number of memory gate electrodes 130M may be determined according to the capacity of the semiconductor device 100. In some example embodiments, the upper gate electrode 130U may not include the gate electrode included in the erase transistor. In some example embodiments, the lower gate electrode 130L may further include the gate electrode included in the erase transistor. According to example embodiments, the number of gate electrodes 130 included in the upper gate electrode 130U and the lower gate electrode 130L may vary in various ways. Some of the gate electrodes 130 (e.g., memory gate electrodes 130M adjacent to the upper gate electrode 130U and / or the lower gate electrode 130L) may be dummy gate electrodes.

[0033] like Figure 1 As shown, the gate electrode 130 can be configured to be separated from each other in the Y direction by gate separation regions MS that extend continuously in the memory cell region MCA and the first contact region CT1 and the second contact region CT2. The gate electrode 130 between a pair of gate separation regions MS can form a memory block, but the scope of the memory block is not limited thereto.

[0034] The gate electrodes 130 can be vertically spaced apart and stacked in the memory cell region MCA and the first contact region CT1 and the second contact region CT2. The gate electrodes 130 do not form a stepped shape throughout the memory cell region MCA and the first contact region CT1 and the second contact region CT2, and all gate electrodes 130 can be stacked vertically. The gate electrodes 130 can extend the same length in the horizontal direction (X or Y direction) in the memory cell region MCA and the first contact region CT1 and the second contact region CT2. Therefore, portions of the upper contact plug MC_U and the lower contact plug MC_L can penetrate or extend through at least one gate electrode 130 from above and can be electrically connected to the gate electrode 130. The end of the gate electrode 130 in the X direction can be located outside the second contact region CT2.

[0035] The gate electrode 130 may include a conductive material, such as a metallic or semiconductor material. The gate electrode 130 may include, for example, tungsten (W) and / or doped polycrystalline silicon. Each gate electrode 130 may further include a barrier layer included in portions of its upper, lower, and side surfaces. For example, the barrier layer may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or combinations thereof.

[0036] Interlayer insulating layers 120 may be disposed between gate electrodes 130. Interlayer insulating layers 120 may also be similar to gate electrodes 130, spaced apart from each other in a direction perpendicular to the upper surface of plate 101, and may be configured to extend in the X direction. Interlayer insulating layers 120 may comprise insulating materials such as silicon oxide or silicon nitride. In example embodiments, the thickness of each interlayer insulating layer 120 may vary considerably.

[0037] The channel structure CH extends through the gate electrode 130 in the Z direction and can be connected to the plate layer 101. Each channel structure CH can be included in a memory cell string, and the channel structures CH can be spaced apart from each other in rows and columns on the plate layer 101 in the memory cell region MCA. The channel structures CH can be configured to form a grid pattern in the XY plane, or can be configured in a zigzag shape in one direction. The channel structure CH can have a column shape and can have sloping side surfaces such that the width of the channel structure CH narrows as the channel structure CH approaches the plate layer 101. In the example embodiment, the number of channel structures CH forming a row in the Y direction and their arrangement shape can be varied.

[0038] Each channel structure CH may include first to fourth channel portions CH1, CH2, CH3, and CH4 stacked vertically (in the Z direction). The first to fourth channel portions CH1, CH2, CH3, and CH4 may penetrate or extend through the first to fourth stacked structures GS1, GS2, GS3, and GS4 in the gate structure GS, respectively. The first to fourth channel portions CH1, CH2, CH3, and CH4 may be interconnected, and may have a width where the upper surface of the channel portion in the lower portion at the interface between the first to fourth channel portions CH1, CH2, CH3, and CH4 is wider than the lower surface of the channel portion in the upper portion. Due to the width difference at the interface between the first to fourth channel portions CH1, CH2, CH3, and CH4, the channel structure CH may have a curved portion. The lower end of the first channel portion CH1 may be disposed in the plate layer 101.

[0039] Each channel structure CH may include a channel layer 140, a channel dielectric layer 145, a channel buried insulation layer 147, and a channel pad 149 disposed in a channel hole. The channel layer 140, the channel dielectric layer 145, and the channel buried insulation layer 147 may be connected to each other between the first to fourth channel portions CH1, CH2, CH3, and CH4.

[0040] The channel layer 140 may be formed in an annular shape that at least partially surrounds the internal channel-buried insulating layer 147. In the board layer 101, the channel layer 140 may be at least partially exposed from the channel dielectric layer 145 and may contact and be electrically connected to the board layer 101. The term "exposed" (or "exposes" or similar terms) may be used herein to describe relationships between components and / or with reference to intermediate manufacturing processes, but may not require exposure of the entire specific component in the completed device.

[0041] The channel layer 140 may include a semiconductor material, such as polycrystalline silicon or monocrystalline silicon.

[0042] A channel dielectric layer 145 may be disposed between the gate electrode 130 and the channel layer 140. Although not specifically shown, the channel dielectric layer 145 may include a tunneling layer, a charge storage layer, and a barrier layer stacked sequentially from the channel layer 140. The tunneling layer can tunnel charge into the charge storage layer and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxide nitride (SiON), or combinations thereof. The charge storage layer may be a charge trapping layer or a floating gate conductive layer. The barrier layer may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxide nitride (SiON), a high-k dielectric material, or combinations thereof. In an example embodiment, at least a portion of the channel dielectric layer 145 may extend along the gate electrode 130 in a horizontal direction (e.g., the Y direction). The channel pad 149 may be disposed only at the upper end of the fourth channel portion CH4 in the upper part. The channel pad 149 may include, for example, doped polysilicon.

[0043] The gate separation region MS can be configured to extend in the X direction and penetrate or extend through the gate electrode 130. For example... Figure 1 As shown, the gate separation regions MS can be arranged parallel to each other. However, the arrangement shape and number of the gate separation regions MS are not limited to... Figure 1 The arrangement shape and quantity are shown. For example, in some example embodiments, the gate separation region MS may be further arranged in a discontinuous form, at least in the first contact region CT1 and the second contact region CT2.

[0044] like Figure 2B As shown, the gate separation region MS can penetrate or extend through the gate electrode 130 stacked on the plate 101 and can be connected to the plate 101. The gate separation region MS can have a shape in which its width decreases toward the plate 101 due to a high aspect ratio. The gate separation region MS can have curved portions corresponding to the first to fourth channel portions CH1, CH2, CH3, and CH4. The gate separation region MS can further include protrusions on its side surfaces toward the gate electrode 130, but in some example embodiments, the protrusions can be omitted. Although in Figure 1 The gate separation region MS is not specifically shown, but in the plan view, the gate separation region MS may have a curved portion on its Y-direction-facing side surface. The gate separation region MS may include an insulating material, such as silicon oxide, silicon nitride, and / or silicon nitride.

[0045] The first upper separation region SS1 can extend in the X direction between a pair of gate separation regions MS, such as Figure 1As shown. The first upper separation region SS1 can be disposed in the memory cell region MCA and the first contact region CT1. The first upper separation region SS1 can penetrate or extend through the upper gate electrode 130U in the gate electrode 130. The first upper separation region SS1 can divide each upper gate electrode 130U into four segments in the Y direction between a pair of gate separation regions MS, as shown. Figure 1 As shown. However, in the example implementation, the number of the first upper separation region SS1 disposed between a pair of gate separation regions MS can be varied.

[0046] The first upper separation region SS1 can be set as the part that cuts the channel structure CH, such as Figure 1 As shown. The first upper separation region SS1 can extend to penetrate a portion of the channel structure CH, and thus can also contact the channel layer 140. In the example embodiment, Figure 1 The relative arrangement of the first upper separation region SS1 and the channel structure CH partially penetrated by the first upper separation region SS1 in the plan view can be changed in various ways.

[0047] like Figure 1 As shown, the second upper separation region SS2 can be connected to the end of the first upper separation region SS1 at the boundary between the first contact region CT1 and the second contact region CT2, and can extend in the Y direction. The second upper separation region SS2 can be set at the same level as the first upper separation region SS1 (in the Z direction), and can have the same depth as the first upper separation region SS1 (in the Z direction). The width of the second upper separation region SS2 can be the same as or different from the width of the first upper separation region SS1. Through the first upper separation region SS1 and the second upper separation region SS2, each upper gate electrode 130U can be divided into multiple electrodes and can receive individual electrical signals. In some example embodiments, the arrangement shape of the first upper separation region SS1 and the second upper separation region SS2 can be varied, and in some example embodiments, the second upper separation region SS2 can be omitted.

[0048] The first upper separation region SS1 and the second upper separation region SS2 may include insulating materials, such as silicon oxide, silicon nitride and / or silicon nitride.

[0049] Contact plugs MC_U and MC_L can be physically connected and electrically connected to gate electrode 130. Upper contact plug MC_U can be connected to upper gate electrode 130U in a first contact area CT1 adjacent to memory cell region MCA. Lower contact plug MC_L can be connected to memory gate electrode 130M and lower gate electrode 130L in a second contact area CT2 outside the first contact area CT1.

[0050] In the plan view, the upper contact plug MC_U can be disposed between first upper separation regions SS1 adjacent to each other along the Y direction and between the first upper separation regions SS1 and the gate separation region MS adjacent to each other along the Y direction. The lower contact plug MC_L can be disposed between gate separation regions MS adjacent to each other along the Y direction. The lower contact plug MC_L can be disposed between a pair of gate separation regions MS to form three rows, each of which can extend in the X direction. However, in the example embodiment, the number of rows formed by the lower contact plug MC_L can vary in various ways. The upper contact plug MC_U and the lower contact plug MC_L can be arranged in a zigzag shape in the plan view, but are not limited thereto. The lower contact plug MC_L can be arranged with a different pattern and / or a different spacing than the upper contact plug MC_U. The lower contact plug MC_L can have the same or different diameter as the upper contact plug MC_U. For example, based on the upper end, the diameters of the contact plugs MC_U and MC_L can be in the range of about 350 nm to 550 nm.

[0051] The number of upper contact plugs MC_U disposed between adjacent first upper separation regions SS1 along the Y direction and between adjacent first upper separation regions SS1 and gate separation regions MS along the Y direction can be equal to or greater than the number of upper gate electrodes 130U stacked in the Z direction. The number of lower contact plugs MC_L disposed between adjacent gate separation regions MS along the Y direction can be equal to or greater than the number of memory gate electrodes 130M and lower gate electrodes 130L stacked in the Z direction.

[0052] Contact plugs MC_U and MC_L may extend in the Z direction only to the gate electrode 130 electrically connected from the top. The upper contact plug MC_U may penetrate or extend through at least one of the upper gate electrodes 130U and may be electrically connected to the upper gate electrode 130U, except for the upper contact plug MC_U electrically connected to the uppermost upper gate electrode 130U. The lower contact plug MC_L may penetrate or extend through all of the upper gate electrodes 130U and may be electrically connected to the memory gate electrode 130M and the lower gate electrode 130L. Contact plugs MC_U and MC_L may be electrically disengaged from the penetrated gate electrode 130 at least by contact spacers 160. Contact plugs MC_U and MC_L may be electrically connected to the gate electrode 130 by partially recessing the gate electrode 130 from its upper surface. However, in the example embodiment, the depth to which the contact plugs MC_U and MC_L recess the gate electrode 130 may vary considerably.

[0053] The second contact area CT2 may include first to sixth areas R1, R2, R3, R4, R5, and R6 that are adjacent to each other and have the same area in the plan view. In each of the first to sixth areas R1, R2, R3, R4, R5, and R6, two lower contact plugs MC_L may be arranged along a row (e.g., the second row). The lower contact plugs MC_L arranged in each of the first to sixth areas R1, R2, R3, R4, R5, and R6 may be referred to as the first contact plug MC1 and the second contact plug MC2. In the second row, the first contact plug MC1 and the second contact plug MC2 may be arranged alternately in the X direction.

[0054] The lower contact plug MC_L can be connected to the S-th gate electrode 130 from the top (where S is a natural number greater than or equal to 4), where S can refer to the layer number (serial number) from the top of the gate electrode 130 electrically connected to each lower contact plug MC_L. The layer number of the gate electrode 130 electrically connected to the lower contact plug MC_L can be a concept proportional to the depth or height of the lower contact plug MC_L. When the layer number of the gate electrode 130 electrically connected to the lower contact plug MC_L is relatively large, the depth of the lower contact plug MC_L can be relatively large. The sum or average of the layer numbers of the gate electrodes 130 electrically connected to the lower contact plug MC_L can be the same or similar to each other in the first to sixth regions R1, R2, R3, R4, R5, and R6.

[0055] like Figure 3 As shown, specifically, the lower contact plugs MC_L located in the first region R1 are electrically connected to the fifth and nineteenth gate electrodes 130, respectively, and the sum of the layer numbers of the gate electrodes 130 is 24. The lower contact plugs MC_L located in the second region R2 are electrically connected to the eighth and sixteenth gate electrodes 130, respectively, and the sum of the layer numbers of the gate electrodes 130 is 24. The lower contact plugs MC_L located in the third region R3 are electrically connected to the eleventh and thirteenth gate electrodes 130, respectively, and the sum of the layer numbers of the gate electrodes 130 is 24. The lower contact plugs MC_L located in the fourth region R4 are electrically connected to the fourteenth and tenth gate electrodes 130, respectively, and the sum of the layer numbers of the gate electrodes 130 is 24. The lower contact plugs MC_L located in the fifth region R5 are electrically connected to the seventeenth and seventh gate electrodes 130, respectively, and the sum of the layer numbers of the gate electrodes 130 is 24. The lower contact plug MC_L, located in the sixth region R6, is electrically connected to the twentieth and fourth gate electrodes 130, respectively, and the sum of the layer numbers of the gate electrodes 130 is 24.

[0056] Here, the sum of layer numbers 24 can correspond to the total number of gate electrodes 130 stacked in the Z direction. For example, when a total of N gate electrodes 130 are stacked and the first contact plug MC1 in each of the first to sixth regions R1, R2, R3, R4, R5, and R6 is electrically connected to the Mth gate electrode 130, the second contact plug MC2 can be electrically connected to the NM (N minus M)th gate electrode 130. However, the sum of layer numbers is not limited to this. For example, when a total of N gate electrodes 130 are stacked and each of the first to sixth regions R1, R2, R3, R4, R5, and R6 includes A lower contact plugs MC_L, the sum of layer numbers can be in the range of (NA / 2) ± 0.2N, where the value NA / 2 is the product of the median value (N / 2) of the number of stacked gate electrode layers × the number of lower contact plugs (A). For example, when each of the first to sixth regions R1, R2, R3, R4, R5 and R6 includes two lower contact plugs MC_L, the sum of the layer numbers can be at least one value greater than 0.8N and less than 1.2N.

[0057] In some example implementations, the sum of layer numbers in at least one of the first to sixth regions R1, R2, R3, R4, R5, and R6 may differ from, but be similar to, the sum of layer numbers in the other regions. "Similar" can mean that the difference is within a predetermined range. For example, when a total of N gate electrodes 130 are stacked, the difference in the sum of layer numbers between any two adjacent regions of the first to sixth regions R1, R2, R3, R4, R5, and R6 can be 0.2N or less. For example, even if the sums of layer numbers are not identical, the difference in the sums of layer numbers can be within a predetermined range relative to the total number of gate electrodes 130, and can be 0.2N or less, for example, 0.1N or less.

[0058] In each of at least a plurality of regions among the first to sixth regions R1, R2, R3, R4, R5, and R6, the difference between the layer number of the gate electrode 130 electrically connected to the first contact plug MC1 and the layer number of the gate electrode 130 electrically connected to the second contact plug MC2 can be 2 or more. For example, the difference in layer numbers can be greater than the number of rows of the lower contact plug MC_L, and in this example embodiment, it can be, for example, greater than 3.

[0059] In the second row, as the first contact plug MC1 moves away from the memory cell region MCA in the X direction, the layer number of the gate electrode 130 connected to the first contact plug MC1 can be increased, that is, the depth of the first contact plug MC1 can be increased. In this example embodiment, the depth of the first contact plug MC1 can be increased by a certain (e.g., constant) layer number in the Z direction, that is, a certain (e.g., constant) length, but this disclosure is not limited thereto. In the second row, as the second contact plug MC2 moves away from the memory cell region MCA in the X direction, the layer number of the gate electrode 130 connected to the second contact plug MC2 can be decreased, that is, the depth of the second contact plug MC2 can be decreased. In this example embodiment, the depth of the second contact plug MC2 can be decreased by a certain (e.g., constant) layer number in the Z direction, that is, a certain (e.g., constant) length, but this disclosure is not limited thereto.

[0060] The second contact plug MC2 in the first region R1 may have a greater depth in the Z-direction than the first contact plug MC1 in the first region R1 and the first contact plug MC1 in the second region R2, where the first contact plug MC1 in the first region R1 and the first contact plug MC1 in the second region R2 are adjacent first contact plugs MC1. The second contact plug MC2 in the second region R2 may also have a greater depth in the Z-direction than the adjacent first contact plug MC1. In contrast, the second contact plug MC2 in the third region R3 may have a greater depth in the Z-direction than the first contact plug MC1 in the third region R3, but may have a smaller depth in the Z-direction than the first contact plug MC1 in the fourth region R4. The second contact plug MC2 in the fourth region R4 may have a smaller depth in the Z-direction than the first contact plug MC1 in the fourth region R4 and the first contact plug MC1 in the fifth region R5. The second contact plug MC2 in the fifth region R5 may also have a smaller depth in the Z-direction than the first contact plug MC1 in the fifth region R5 and the first contact plug MC1 in the sixth region R6.

[0061] In the first and third rows, similar to the second row, the sum of the layer numbers of the gate electrodes 130 electrically connected to the lower contact plug MC_L can be the same in certain unit regions along the X direction (e.g., the first to sixth regions R1, R2, R3, R4, R5, and R6), or their differences can be within a predetermined range. For example, compared to the lower contact plug MC_L in the second row adjacent to the first and third rows, the sum of the layer numbers of the gate electrodes 130 electrically connected to the lower contact plug MC_L in the first and third rows can differ by one layer in certain unit regions along the X direction, but embodiments of this disclosure are not limited to this. According to an example embodiment, the sum of the layer numbers of the gate electrodes 130 electrically connected to adjacent lower contact plugs MC_L can be the same or similar in certain unit regions along the first to third rows.

[0062] During the manufacturing process of semiconductor device 100, the sacrificial insulating layer 118, which is first formed in the region of gate electrode 130 (see [link to manufacturing process]), can be repeatedly performed. Figure 11A Etching 2 n (Where n = 0, 1, 2, ...) processes are used to form contact holes in which the lower contact plug MC_L is disposed. As described above, the sum of the layer numbers of the gate electrode 130 electrically connected to the lower contact plug MC_L can be the same or similar to each other in the first to sixth regions R1, R2, R3, R4, R5, and R6, such that the photoresist layer formed during this manufacturing process can be formed to have a relatively uniform thickness. This will be referred to below. Figures 11B to 11G To describe in more detail. Therefore, depth of focus (DOF) can be ensured during the photolithography process, thereby improving process reliability.

[0063] In this example embodiment, the lower contact plug MC_L is arranged as described above, but the ranges of the first to sixth regions R1, R2, R3, R4, R5, and R6 are not limited to the second contact region CT2. In some example embodiments, not only the lower contact plug MC_L can be arranged in this manner, but all contact plugs MC_U and MC_L, including the upper contact plug MC_U, can be arranged in this manner.

[0064] The contact plugs MC_U and MC_L may include a conductive material, such as at least one of tungsten (W), copper (Cu), aluminum (Al), and alloys thereof. In some example embodiments, each of the contact plugs MC_U and MC_L may include a barrier layer in its lower and side surfaces, the barrier layer comprising a conductive material, such as tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0065] Contact spacers 160 may be disposed on the side surfaces of contact plugs MC_U and MC_L, respectively. Contact spacers 160 electrically isolate contact plugs MC_U and MC_L from the gate electrode 130 through which contact plugs MC_U and MC_L penetrate. Contact spacers 160 may at least partially expose the lower surfaces of contact plugs MC_U and MC_L. The lower end of contact spacer 160 may be disposed on the upper surface of the gate electrode 130 electrically connected to contact plugs MC_U and MC_L. The lower end of contact spacer 160 may be disposed at a level higher than the lower ends of contact plugs MC_U and MC_L (in the Z direction), but embodiments of this disclosure are not limited thereto.

[0066] The contact spacer 160 may include an insulating material, such as silicon oxide, silicon nitride, or silicon nitride. In some example embodiments, the contact spacer 160 may include multiple layers. For example, the contact spacer 160 may include an outer silicon oxide layer and an inner silicon nitride layer.

[0067] The virtual vertical structure DH can be spaced apart from each other by forming rows and columns on the plate 101 in the first contact area CT1 and the second contact area CT2. For example... Figure 1 As shown, the dummy vertical structure DH can be arranged in a zigzag shape with the contact plugs MC_U and MC_L in a plan view. The dummy vertical structure DH can be arranged in different patterns in the first contact area CT1 and the second contact area CT2, but the embodiments of this disclosure are not limited thereto. In some example embodiments, some of the dummy vertical structures DH can contact the contact plugs MC_U and MC_L.

[0068] The dummy vertical structure DH can have a circular, elliptical, or similar shape in plan view. The dummy vertical structure DH can have a columnar shape that penetrates or extends through the gate electrode 130, and can have sloping side surfaces such that the width of the dummy vertical structure DH depends on its aspect ratio and narrows as it approaches the plate layer 101. The diameter of the dummy vertical structure DH can be larger than the diameter of the channel structure CH, but embodiments of this disclosure are not limited thereto. The dummy vertical structure DH may include protrusions extending from its side surfaces toward the gate electrode 130. The dummy vertical structure DH may have curved portions corresponding to the first to fourth channel portions CH1, CH2, CH3, and CH4. The dummy vertical structure DH may not include conductive material and may include insulating material. The dummy vertical structure DH may include, for example, silicon oxide, silicon nitride, and / or silicon nitride.

[0069] The first cell region insulating layer 192 may be configured to cover the gate structure GS. As may be used herein, the term "covers" (or "covering" or similar terms) is intended to broadly refer to an element, structure, or layer that is directly on or over another element, structure, or layer, or in the presence of one or more other intervening elements, structures, or layers. A second cell region insulating layer 194 may be disposed on the first cell region insulating layer 192. According to an example embodiment, each of the first cell region insulating layer 192 and the second cell region insulating layer 194 may include multiple insulating layers. The first cell region insulating layer 192 and the second cell region insulating layer 194 may be formed of an insulating material, such as at least one of silicon oxide, silicon nitride, and silicon nitride.

[0070] Stub 180 and cell interconnect 185 may be included in a cell interconnect structure electrically connected to a memory cell. Stub 180 penetrates or extends through a portion of the second cell region insulating layer 194 and may connect to the channel structure CH and contact plugs MC_U and MC_L, and may be electrically connected to the channel layer 140 and the gate electrode 130. Stub 180 may have a plug shape, and cell interconnect 185 may have a line shape, but embodiments of this disclosure are not limited thereto. Stub 180 and cell interconnect 185 may include metals, such as tungsten (W), copper (Cu), and / or aluminum (Al).

[0071] Figures 4A to 4C These are a plan view and a cross-sectional view of a semiconductor device according to an example embodiment, and a schematic diagram showing the arrangement of the lower contact plugs.

[0072] Reference Figures 4A to 4C In semiconductor device 100a, the arrangement of the lower contact plug MC_L in the second contact region CT2 can be different from that in semiconductor device 100a. Figure 1 , Figure 2A , Figure 2B and Figure 3 An example implementation is provided. The lower contact plugs MC_L can be arranged in two rows extending in the X direction within the second contact area CT2. According to the example implementation, a dummy vertical structure DH can be additionally provided in the second contact area CT2.

[0073] The second contact region CT2 may include first to fourth regions R1, R2, R3, and R4, each having the same area. In the first to fourth regions R1, R2, R3, and R4, three lower contact plugs MC_L may be arranged in a row (e.g., along the first row). The lower contact plug MC_L arranged in each of the first to fourth regions R1, R2, R3, and R4 may be referred to as the first to third contact plugs MC1, MC2, and MC3, respectively. In the first row, the first to third contact plugs MC1, MC2, and MC3 may be arranged alternately in the X direction. The sum of the layer numbers of the gate electrodes 130 connected to the lower contact plugs MC_L may be the same or similar to each other in the first to fourth regions R1, R2, R3, and R4.

[0074] like Figure 4CAs shown, specifically, the lower contact plugs MC_L disposed in the first region R1 are electrically connected to the fifth, twenty-third, and tenth gate electrodes 130, respectively, and the sum of the layer numbers of the gate electrodes 130 is 38. The lower contact plugs MC_L disposed in the second region R2 are electrically connected to the seventh, twentieth, and eleventh gate electrodes 130, respectively, and the sum of the layer numbers of the gate electrodes 130 is 38. The lower contact plugs MC_L disposed in the third region R3 are electrically connected to the ninth, seventeenth, and twelfth gate electrodes 130, respectively, and the sum of the layer numbers of the gate electrodes 130 is 38. The lower contact plugs MC_L disposed in the fourth region R4 are connected to the eleventh, fourteenth, and thirteenth gate electrodes 130, respectively, and the sum of the layer numbers of the gate electrodes 130 is 38. In this example embodiment, two lower contact plugs MC_L connected to the eleventh gate electrode 130 are respectively arranged in the second region R2 and the fourth region R4. One of these two lower contact plugs MC_L may be a dummy contact plug that does not function electrically, but the embodiments of this disclosure are not limited thereto.

[0075] In some example implementations, the sum of the layer numbers in at least one of the first to fourth regions R1, R2, R3, and R4 may differ from the sum of the layer numbers in the other regions, but the difference may not be significant. In each of at least a plurality of regions among the first to fourth regions R1, R2, R3, and R4, for example, in each of the first to third regions R1, R2, and R3, the difference in the layer numbers of the gate electrodes 130 connected to the first to third contact plugs MC1, MC2, and MC3 may be greater than 2.

[0076] In the first row, as the first contact plug MC1 moves away from the memory cell region MCA in the X direction, the layer number of the gate electrode 130 connected to the first contact plug MC1 can be increased, that is, the depth of the first contact plug MC1 can be increased. In this example embodiment, the depth of the first contact plug MC1 can be increased by a certain (e.g., constant) layer number in the Z direction, that is, a certain (e.g., constant) length, but this disclosure is not limited thereto. In the first row, as the second contact plug MC2 moves away from the memory cell region MCA in the X direction, the layer number of the gate electrode 130 electrically connected to the second contact plug MC2 can be decreased, that is, the depth of the second contact plug MC2 can be decreased. In this example embodiment, the depth of the second contact plug MC2 can be decreased by a certain (e.g., constant) layer number in the Z direction, that is, a certain (e.g., constant) length, but this disclosure is not limited thereto. In the first row, as the third contact plug MC3 moves away from the memory cell region MCA in the X direction, the layer number of the gate electrode 130 connected to the third contact plug MC3 can be increased, that is, the depth of the third contact plug MC3 can be increased. In this example embodiment, the depth of the third contact plug MC3 can be increased by a certain (e.g., constant) layer number in the Z direction, that is, a certain (e.g., constant) length, but the embodiments of this disclosure are not limited thereto.

[0077] In the second row, similar to the first row, the sum of the layer numbers of the gate electrodes 130 electrically connected to the lower contact plugs MC_L can be the same or similar to each other between regions that are adjacent to each other and include two or more lower contact plugs MC_L.

[0078] Figures 5A to 5C These are a plan view and a cross-sectional view of a semiconductor device according to an example embodiment, and a schematic diagram showing the arrangement of the lower contact plugs.

[0079] Reference Figures 5A to 5C In semiconductor device 100b, the distance between the gate separation regions MS and the arrangement of the lower contact plug MC_L in the second contact region CT2 can differ from... Figure 1 , Figure 2A , Figure 2B and Figure 3 The distance and arrangement in the example implementation. In semiconductor device 100b, only one first upper separation region SS1 may be provided between a pair of gate separation regions MS. The lower contact plugs MC_L may be arranged in a row extending in the X direction in the second contact region CT2. According to the example implementation, a dummy vertical (in the Z direction) structure DH may be additionally provided in the second contact region CT2.

[0080] The second contact area CT2 may include first to eleventh areas R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, and R11, each having the same area. In each of the first to eleventh areas R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, and R11, two lower contact plugs MC_L arranged in a single row may be provided. The lower contact plugs MC_L provided in each of the first to eleventh areas R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, and R11 may be referred to as the first contact plug MC1 and the second contact plug MC2, respectively. The first contact plug MC1 and the second contact plug MC2 may be arranged alternately in the X direction. The sum of the layer numbers of the gate electrode 130 connected to the lower contact plug MC_L can be the same or similar to each other in the first to eleventh regions R1, R2, R3, R4, R5, R6, R7, R8, R9, R10 and R11.

[0081] like Figure 5CAs shown, specifically, the lower contact plugs MC_L disposed in the first region R1 are electrically connected to the fourth and twenty-fourth gate electrodes 130, respectively, and the sum of the layer numbers of the gate electrodes 130 is 28. The lower contact plugs MC_L disposed in the second region R2 are electrically connected to the sixth and twenty-second gate electrodes 130, respectively, and the sum of the layer numbers of the gate electrodes 130 is 28. The lower contact plugs MC_L disposed in the third region R3 are electrically connected to the eighth and twentyth gate electrodes 130, respectively, and the sum of the layer numbers of the gate electrodes 130 is 28. The lower contact plugs MC_L disposed in the fourth region R4 are electrically connected to the tenth and eighteenth gate electrodes 130, respectively, and the sum of the layer numbers of the gate electrodes 130 is 28. The lower contact plugs MC_L disposed in the fifth region R5 are electrically connected to the twelfth and sixteenth gate electrodes 130, respectively, and the sum of the layer numbers of the gate electrodes 130 is 28. The lower contact plugs MC_L located in the sixth region R6 are electrically connected to the fifth and twenty-third gate electrodes 130, respectively, and the sum of the layer numbers of the gate electrodes 130 is 28. The lower contact plugs MC_L located in the seventh region R7 are electrically connected to the seventh and twenty-first gate electrodes 130, respectively, and the sum of the layer numbers of the gate electrodes 130 is 28. The lower contact plugs MC_L located in the eighth region R8 are electrically connected to the ninth and nineteenth gate electrodes 130, respectively, and the sum of the layer numbers of the gate electrodes 130 is 28. The lower contact plugs MC_L located in the ninth region R9 are electrically connected to the eleventh and seventeenth gate electrodes 130, respectively, and the sum of the layer numbers of the gate electrodes 130 is 28. The lower contact plugs MC_L located in the tenth region R10 are electrically connected to the thirteenth and fifteenth gate electrodes 130, respectively, and the sum of the layer numbers of the gate electrodes 130 is 28. The lower contact plugs MC_L disposed in the eleventh region R11 are all electrically connected to the fourteenth gate electrode 130, the sum of the layer numbers of the gate electrodes 130 being 28. In this example embodiment, the two lower contact plugs MC_L electrically connected to the fourteenth gate electrode 130 are arranged in the eleventh region R11. One of these two lower contact plugs MC_L may be a dummy contact plug that does not function electrically, but embodiments of this disclosure are not limited thereto.

[0082] In some example implementations, the sum of the layer numbers in at least one of the first to eleventh regions R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, and R11 may differ from the sum of the layer numbers in the other regions, but the difference may not be significant. In each of the first to ninth regions R1, R2, R3, R4, R5, R6, R7, R8, and R9, the difference in layer numbers between the gate electrodes 130 electrically connected to the first contact plug MC1 and the second contact plug MC2 may be greater than 2.

[0083] The second contact area CT2 may include a front contact area CT2_A, a rear contact area CT2_B, and an additional contact area CT2_C. The front contact area CT2_A may include the first to fifth areas R1, R2, R3, R4, and R5; the rear contact area CT2_B may include the sixth to tenth areas R6, R7, R8, R9, and R10; and the additional contact area CT2_C may include the eleventh area R11.

[0084] In each of the front contact region CT2_A and the rear contact region CT2_B, as the first contact plug MC1 moves away from the memory cell region MCA in the X direction, the layer number of the gate electrode 130 connected thereto can be increased; that is, the depth of the first contact plug MC1 (in the Z direction) can be increased. In this example embodiment, the depth of the first contact plug MC1 can be increased by a certain (e.g., constant) layer number in the Z direction, i.e., a certain (e.g., constant) length, but the embodiment is not limited to this. In the additional contact region CT2_C, compared with the rear contact region CT2_B, the layer number of the gate electrode 130 connected to the first contact plug MC1 can be increased, but its spacing can be different from the spacing in the rear contact region CT2_B.

[0085] In each of the front contact region CT2_A and the rear contact region CT2_B, as the second contact plug MC2 moves away from the memory cell region MCA in the X direction, the layer number of the gate electrode 130 connected thereto can be reduced; that is, the depth of the second contact plug MC2 (in the Z direction) can be reduced. In this example embodiment, the second contact plug MC2 may have a depth in the Z direction that is reduced by a certain (e.g., constant) layer number, i.e., a certain (e.g., constant) length, but embodiments of this disclosure are not limited thereto. In the additional contact region CT2_C, compared to the rear contact region CT2_B, the layer number of the gate electrode 130 electrically connected to the second contact plug MC2 can be reduced, but its spacing may differ from the spacing in the rear contact region CT2_B.

[0086] In some example implementations, not only the lower contact plug MC_L can be arranged in this way, but all contact plugs MC_U and MC_L, including the upper contact plug MC_U, can be arranged in this way.

[0087] Figure 6A and Figure 6B These are a plan view of a semiconductor device according to an example embodiment and a schematic diagram showing the arrangement of the lower contact plugs, respectively.

[0088] Reference Figure 6A and Figure 6B In semiconductor device 100c, the number and arrangement of gate electrode 130 and lower contact plug MC_L can differ from those of other devices. Figure 1, Figure 2A , Figure 2B and Figure 3 The number and arrangement of the example implementation. The lower contact plugs MC_L can be arranged in the second contact area CT2 as first to third rows ROW1, ROW2 and ROW3 extending in the X direction.

[0089] The second contact area CT2 may include multiple areas R1, R2, R3, ..., Rn-2, Rn-1, and Rn with the same area. These multiple areas R1, R2, R3, ..., Rn-2, Rn-1, and Rn may be rectangular areas extending in the Y direction. In each of the multiple areas R1, R2, R3, ..., Rn-2, Rn-1, and Rn, one lower contact plug MC_L may be provided from each of the first to third rows ROW1, ROW2, and ROW3, ​​i.e., a total of three lower contact plugs MC_L. These three lower contact plugs MC_L may be adjacent to each other in the Y direction.

[0090] For example, in an example implementation, approximately 308 gate electrodes 130 can be stacked, and a total of 306 lower contact plugs MC_L can be provided, where n can be 102. The sum of the layer numbers of the gate electrodes 130 electrically connected to the lower contact plugs MC_L can be the same as each other in multiple regions R1, R2, R3, ..., Rn-2, Rn-1, and Rn, or they can differ by one layer. In this case, in the X direction, the lower contact plugs MC_L can be arranged in the first to third rows ROW1, ROW2, and ROW3 as follows: Figure 6B The depth setting shown.

[0091] like Figure 6B As shown, the second contact area CT2 may include a front contact area CT2_A and a rear contact area CT2_B. The front contact area CT2_A is the area adjacent to the memory cell area MCA based on the center of the second contact area CT2 in the X direction, that is, the left side area. The rear contact area CT2_B may be the area corresponding to the right side based on the center of the second contact area CT2 in the X direction.

[0092] In the front contact region CT2_A, the lower contact plug MC_L of the first row ROW1 may include a first contact plug and a second contact plug. The gate electrode 130 electrically connected to the first contact plug has a layer number that decreases as the lower contact plug MC_L moves away from the memory cell region MCA in the X direction, and the gate electrode 130 electrically connected to the second contact plug has an increasing layer number. In the rear contact region CT2_B, the lower contact plug MC_L of the first row ROW1 may include a first contact plug and a second contact plug. The gate electrode 130 electrically connected to the first contact plug has a layer number that increases as the lower contact plug MC_L moves away from the memory cell region MCA in the X direction, and the gate electrode 130 electrically connected to the second contact plug has a decreasing layer number. The first contact plug and the second contact plug may be arranged alternately. The deepest second contact plug in the front contact region CT2_A may have a depth equal to or similar to the depth of the adjacent and deepest second contact plug in the rear contact region CT2_B (in the Z direction).

[0093] The gate electrode 130 electrically connected to the lower contact plug MC_L of the second row ROW2 can have a layer number in the front contact region CT2_A that decreases as the lower contact plug MC_L moves away from the memory cell region MCA in the X direction, and can have a layer number in the rear contact region CT2_B that increases as the lower contact plug MC_L moves away from the memory cell region MCA in the X direction. The depth difference (in the Z direction) between adjacent lower contact plugs MC_L in each of the front contact region CT2_A and the rear contact region CT2_B can be smaller than the depth difference (in the Z direction) between adjacent lower contact plugs MC_L in the front contact region CT2_A and the rear contact region CT2_B, respectively.

[0094] In the front contact region CT2_A, the lower contact plug MC_L of the third row ROW3 may include a first contact plug and a second contact plug. The gate electrode 130 electrically connected to the first contact plug has a layer number that increases as the lower contact plug MC_L moves away from the memory cell region MCA in the X direction, and the gate electrode 130 electrically connected to the second contact plug has a decreasing layer number. In the rear contact region CT2_B, the lower contact plug MC_L of the third row ROW3 may include a first contact plug and a second contact plug. The gate electrode 130 electrically connected to the first contact plug has a layer number that decreases as the lower contact plug MC_L moves away from the memory cell region MCA in the X direction, and the gate electrode 130 electrically connected to the second contact plug has an increasing layer number. The first contact plug and the second contact plug may be arranged alternately. The deepest first contact plug in the front contact region CT2_A may have a depth equal to or similar to the depth of the adjacent and deepest first contact plug in the rear contact region CT2_B (in the Z direction).

[0095] Considering the 128 sacrificial insulating layers 118 first formed in the region of the gate electrode 130 during the manufacturing process of semiconductor device 100c (see... Figure 11A During the etching process, the depth (in the Z direction) difference of the contact holes formed during the etching process can be up to 73 layers in the first row ROW1, up to 101 layers in the second row ROW2, and up to 77 layers in the third row ROW3. In this way, in a 128-layer etching process, the depth (in the Z direction) difference in each row can be less than 128; specifically, in the first row ROW1 and the third row ROW3, ​​the depth (in the Z direction) difference can be less than 80. In a process of etching 256 sacrificial insulating layers 118, the depth (in the Z direction) difference of the contact holes in the second row ROW2 can be up to 50 layers.

[0096] In this way, in the Y direction, the sum of the layer numbers of the gate electrodes 130 connected to the lower contact plugs MC_L in multiple regions R1, R2, R3, ..., Rn-2, Rn-1 and Rn can be the same or differ by 1, while in the X direction, as described above, the layer number difference is reduced or minimized to less than 128, thereby improving the accuracy in the manufacturing process of the semiconductor device 100c.

[0097] Figure 7A and Figure 7B This is a plan view of a semiconductor device according to an example implementation.

[0098] Reference Figure 7A In the semiconductor device 100d, the shapes and arrangements of the first to sixth regions R1, R2, R3, R4, R5, and R6 can differ from those of other regions. Figure 1 The shape and arrangement are shown in the example implementation. The first to sixth regions R1, R2, R3, R4, R5, and R6 may each have six lower contact plugs MC_L disposed therein, and may have the same area. Specifically, each of the first to sixth regions R1, R2, R3, R4, R5, and R6 may include two lower contact plugs MC_L disposed adjacently in the X direction in each of the three rows. The sum of the layer numbers of the gate electrodes 130 electrically connected to the lower contact plugs MC_L may be the same or similar to each other in the first to sixth regions R1, R2, R3, R4, R5, and R6.

[0099] Reference Figure 7B In semiconductor device 100e, the shape and arrangement of the first to sixth regions R1, R2, R3, R4, R5 and R6 may differ from those of other regions. Figure 1The shapes and arrangements in the example embodiments are shown below. The first to sixth regions R1, R2, R3, R4, R5, and R6 may each have six lower contact plugs MC_L disposed therein, and may have the same area. However, the shapes of the first to third regions R1, R2, and R3 may differ from the shapes of the fourth to sixth regions R4, R5, and R6.

[0100] Each of the first to sixth regions R1, R2, R3, R4, R5, and R6 may include four lower contact plugs MC_L arranged adjacently in the X direction in a row and two lower contact plugs MC_L arranged adjacently in a row adjacent to said row. The sum of the layer numbers of the gate electrodes 130 electrically connected to the lower contact plugs MC_L may be the same or similar to each other in the first to sixth regions R1, R2, R3, R4, R5, and R6.

[0101] In such an example implementation, the multiple regions R1, R2, R3, ..., Rn-2, Rn-1, and Rn where multiple lower contact plugs MC_L are respectively provided can have various sizes and shapes, and the number of regions can also vary in a variety of ranges. The number of lower contact plugs MC_L provided in each of the regions R1, R2, R3, ..., Rn-2, Rn-1, and Rn can range, for example, from 2 to 64, and the same number of lower contact plugs MC_L can be provided in each of the multiple regions R1, R2, R3, ..., Rn-2, Rn-1, and Rn.

[0102] Figure 8 This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0103] Reference Figure 8 In semiconductor device 100f, the upper contact plug MC_Uf can be configured to either not penetrate or extend through the gate electrode 130. Semiconductor device 100f may not include... Figure 1 and Figure 2A The second upper separation region SS2.

[0104] In an example embodiment, the upper gate electrode 130U may have a stepped structure GP in a stepped shape within the first contact region CT1. Therefore, in the upper gate electrode 130U, the lower portion of the upper gate electrode 130U may extend wider in the X direction than the upper portion, such that its upper surface may be exposed to the first cell region insulating layer 192. The upper gate electrode 130U may be connected to the upper contact plug MC_Uf in the region exposed in this manner.

[0105] The upper contact plug MC_Uf can be connected to the upper gate electrode 130U by penetrating or extending through the insulating layer 192 of the first cell region. The contact spacer 160 may not be provided on the side surface of the upper contact plug MC_Uf. However, in some example embodiments, the contact spacer 160 may be further provided on the side surface of the upper contact plug MC_Uf.

[0106] Figure 9 This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0107] Reference Figure 9 In the contact plugs MC_U and MC_L of the semiconductor device 100g, the diameter of the contact plug with a relatively large depth can be larger than the diameter of the contact plug with a small depth. For example, in the sixth region R6, the first contact plug on the left, which is relatively deep (in the Z direction), can have a first diameter D1, which can be larger than the second diameter D2 of the second contact plug on the right. The first diameter D1 and the second diameter D2 can be, for example, based on the upper end. This form of the diameters of the contact plugs MC_U and MC_L can be applied to other exemplary embodiments.

[0108] Figure 10A and Figure 10B This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0109] Reference Figure 10A The semiconductor device 100h may include a first semiconductor structure S1 and a second semiconductor structure S2 located below (in the Z direction) the first semiconductor structure S1. The first semiconductor structure S1 may include a memory cell region, and the second semiconductor structure S2 may include a peripheral circuit region. In some example embodiments, the second semiconductor structure S2 may be disposed on the first semiconductor structure S1.

[0110] Reference Figure 1 , Figure 2A , Figure 2B and Figure 3 The description can be applied in the same way to the first semiconductor structure S1. However, the second semiconductor structure S2 further includes a through interconnect region THV, and may further include a first horizontal conductive layer 102 and a second horizontal conductive layer 104, a horizontal insulating layer 110, a substrate insulating layer 121, and a through path TH disposed in the through interconnect region THV.

[0111] The through-interconnect region THV can be a region in which the gate electrode 130 does not extend. In the through-interconnect region THV, the sacrificial insulating layer 118 can be alternately stacked with the interlayer insulating layer 120 on the plate layer 101. The through-path TH can penetrate or extend through the stacked structure of the sacrificial insulating layer 118 and the interlayer insulating layer 120, and can extend into the second semiconductor structure S2. However, in some example embodiments, the through-path TH can be configured to penetrate or extend through an insulating region formed after the sacrificial insulating layer 118 is removed.

[0112] The through-path TH can electrically connect unit interconnect 185 and circuit interconnect 280. The through-path TH can be electrically isolated from board layer 101 through substrate insulating layer 121. The through-path TH can have first to fourth channel portions CH1, CH2, CH3, and CH4 (see...) of the channel structure CH. Figure 2A The corresponding curved portion. However, in some example implementations, the through passage TH may not have a curved portion and may extend from the upper end to the lower end at a constant slope.

[0113] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 can be stacked sequentially in the memory cell region MCA and disposed on the upper surface of the plate layer 101. The first horizontal conductive layer 102 and the second horizontal conductive layer 104 can be included together with the plate layer 101 in the source structure SS and can be used as a common source line of the semiconductor device 100h. The first horizontal conductive layer 102 can be directly connected to the channel layer 140 at the bottom of the channel structure CH. The first horizontal conductive layer 102 and the second horizontal conductive layer 104 can include semiconductor materials, such as polysilicon. In this case, at least the first horizontal conductive layer 102 can be a layer doped with impurities of the same conductivity type as the plate layer 101.

[0114] A horizontal insulating layer 110 may be disposed on the plate layer 101 at the same level (in the Z direction) as the first horizontal conductive layer 102 in at least a portion of the first contact region CT1, the second contact region CT2, and the through interconnect region THV. The horizontal insulating layer 110 may comprise a first horizontal insulating layer and a second horizontal insulating layer alternately stacked on the plate layer 101. The horizontal insulating layer 110 may be a layer remaining after a portion of the initially formed horizontal insulating layer has been replaced with the first horizontal conductive layer 102 during the manufacturing process of the semiconductor device 100h. The horizontal insulating layer 110 may comprise silicon oxide, silicon nitride, silicon carbide, and / or silicon oxide nitride. The first horizontal insulating layer and the second horizontal insulating layer may comprise different insulating materials.

[0115] The substrate insulating layer 121 may be configured to penetrate or extend through the plate layer 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104 in the through interconnect region THV. The substrate insulating layer 121 may include an insulating material, such as silicon oxide, silicon nitride, silicon carbide, and / or silicon nitride.

[0116] The second semiconductor structure S2 may include a substrate 201, a source / drain region 205 and a device isolation layer 210 in the substrate 201, a circuit element 220 disposed on the substrate 201, a peripheral region insulating layer 290, a circuit contact plug 270 and a circuit interconnect 280.

[0117] The substrate 201 may have an upper surface extending in both the X and Y directions. An active region may be defined within the substrate 201 by a device isolation layer 210. Source / drain regions 205, including impurities, may be disposed within a portion of the active region. The substrate 201 may comprise a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The substrate 201 may be provided as a bulk wafer or an epitaxial layer.

[0118] Circuit element 220 may include a planar transistor. Each circuit element 220 may include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. Source / drain regions 205 may be disposed on both sides of the circuit gate electrode 225 in the substrate 201 as source / drain regions.

[0119] The peripheral region insulating layer 290 may be configured to at least partially cover the circuit element 220 on the upper surface of the substrate 201. The peripheral region insulating layer 290 may include multiple insulating layers formed in different process operations. The peripheral region insulating layer 290 may be formed of an insulating material.

[0120] Circuit contact plugs 270 and interconnects 280 may be included in a circuit interconnect structure electrically connected to circuit element 220 and source / drain region 205. Circuit contact plugs 270 may have a cylindrical shape, and interconnects 280 may have a line shape. Electrical signals can be applied to circuit element 220 through circuit contact plugs 270 and interconnects 280. In areas not shown, circuit contact plugs 270 may also be connected to circuit gate electrode 225. Interconnects 280 may be connected to circuit contact plugs 270 and may be arranged in multiple layers. Circuit contact plugs 270 and interconnects 280 may include conductive materials, such as tungsten (W), copper (Cu), and / or aluminum (Al), and each of circuit contact plugs 270 and interconnects 280 may further include a diffusion barrier. In example embodiments, the number of layers of circuit contact plugs 270 and interconnects 280 may vary considerably.

[0121] Reference Figure 10B ,and Figure 10A Unlike the example implementation, the semiconductor device 100i may have a structure in which a first semiconductor structure S1 and a second semiconductor structure S2 are joined. Therefore, the first semiconductor structure S1 may further include a first bonding path 195, a first bonding metal layer 198 and a first bonding insulating layer 199, and the second semiconductor structure S2 may further include a second bonding path 295, a second bonding metal layer 298 and a second bonding insulating layer 299.

[0122] The first bonding path 195, the first bonding metal layer 198, and the first bonding insulating layer 199 may be included in the first bonding structure of the first semiconductor structure S1. The first bonding path 195 may be disposed below the cell interconnect 185, and the first bonding metal layer 198 may be connected to the first bonding path 195. The lower surface of the first bonding metal layer 198 may form the lower surface of the first semiconductor structure S1. The first bonding metal layer 198 may be bonded to and connected to the second bonding metal layer 298 of the second semiconductor structure S2. The first bonding path 195 and the first bonding metal layer 198 may include a conductive material, such as copper (Cu). The first bonding insulating layer 199 may form a dielectric-dielectric bond with the second bonding insulating layer 299 of the second semiconductor structure S2. The first bonding insulating layer 199 may include at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0123] The second bonding path 295, the second bonding metal layer 298, and the second bonding insulating layer 299 may be included in the second bonding structure and may be disposed on at least a portion of the uppermost circuit interconnect 280. The second bonding path 295 may have a cylindrical shape, and the second bonding metal layer 298 may have a pad shape or a relatively short line shape with a circular shape in a plane. The upper surface of the second bonding metal layer 298 may form the upper surface of the second semiconductor structure S2. The second bonding path 295 and the second bonding metal layer 298 may provide an electrical connection path with the first semiconductor structure S1. In an example embodiment, a portion of the second bonding metal layer 298 may not be connected to the circuit interconnect 280 and may be disposed solely for bonding. The second bonding path 295 and the second bonding metal layer 298 may include a conductive material, such as copper (Cu). The second bonding insulating layer 299 may be configured to have a predetermined thickness from the upper surface of the peripheral region insulating layer 290. The second bonding insulating layer 299 may be a layer for dielectric-dielectric bonding with the first bonding insulating layer 199 of the first semiconductor structure S1. The second bonding insulating layer 299 can also be used as a diffusion barrier layer for the second bonding metal layer 298, and may include at least one of, for example, SiO, SiN, SiCN, SiOC, SiON and SiOCN.

[0124] The first semiconductor structure S1 and the second semiconductor structure S2 can be joined by joining the first bonding metal layer 198 and the second bonding metal layer 298, and by joining the first bonding insulating layer 199 and the second bonding insulating layer 299. The joining of the first bonding metal layer 198 and the second bonding metal layer 298 can be, for example, a copper (Cu) to copper (Cu) bonding, and the joining of the first bonding insulating layer 199 and the second bonding insulating layer 299 can be, for example, a dielectric to dielectric bonding, such as a SiCN to SiCN bonding. The first semiconductor structure S1 and the second semiconductor structure S2 can be joined by a hybrid bonding including copper (Cu) to copper (Cu) bonding and dielectric to dielectric bonding.

[0125] The first semiconductor structure S1 and the second semiconductor structure S2 can be packaged such that the second semiconductor structure S2 is disposed in the lower part, as shown below. Figure 10A and Figure 10B As shown. Optionally, the first semiconductor structure S1 and the second semiconductor structure S2 can be packaged by reversing the upper and lower parts so that the second semiconductor structure S2 is disposed in the upper part.

[0126] Figures 11A to 11L This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. Figures 11A to 11L It shows the relationship with Figure 2A and Figure 10B The corresponding cross section.

[0127] Reference Figure 11A The manufacturing process of the first semiconductor structure S1 can be started first. On the substrate SUB, sacrificial insulating layer 118 and interlayer insulating layer 120 can be stacked alternately to form a module structure PS and a vertical sacrificial structure VS that penetrates or extends through the module structure PS, and a first cell region insulating layer 192 can be formed.

[0128] The substrate SUB is a layer removed by subsequent processes and can be a semiconductor substrate, such as a silicon (Si) wafer. A first-mode stack structure PS1 can be formed first, and a portion of the vertical sacrificial structure VS can be formed penetrating or extending through the first-mode stack structure PS1. Then, a second-mode stack structure PS2 can be formed, and a portion of the vertical sacrificial structure VS can be formed penetrating or extending through the second-mode stack structure PS2. Similarly, a third-mode stack structure PS3 and a fourth-mode stack structure PS4, along with the remaining portion of the vertical sacrificial structure VS, can be formed.

[0129] The sacrificial insulating layer 118 can be replaced by the gate electrode 130 through a subsequent process (see...). Figure 2A The interlayer insulating layer 118 can be formed of a different material than the interlayer insulating layer 120, and can be formed of a material that can be etched selectively relative to the interlayer insulating layer 120 under specific etch conditions. For example, the interlayer insulating layer 120 can be formed of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layer 118 can be formed of a different material selected from silicon, silicon oxide, silicon carbide, and / or silicon nitride. In example embodiments, the thickness of the interlayer insulating layer 120 may not all be the same. The thickness and number of films constituting the interlayer insulating layer 120 and the sacrificial insulating layer 118 can vary from the thicknesses and numbers shown in different embodiments.

[0130] Vertical sacrificial structures (VS) can be formed in relation to Figure 2A The channel structure CH, the virtual vertical structure DH and Figure 2B The location corresponding to the gate separation region MS. The vertical sacrificial structure VS can be formed, for example, having the same dimensions as the channel structure CH. The vertical sacrificial structure VS can include, for example, carbon (C), but embodiments of this disclosure are not limited thereto.

[0131] Reference Figure 11B A first mask layer ML1 and a second mask layer ML2 can be formed on the insulating layer 192 of the first unit region, and an opening OP can be formed in the first mask layer ML1 and the second mask layer ML2.

[0132] The first mask layer ML1 and the second mask layer ML2 may be stacked sequentially on the insulating layer 192 of the first cell region. The first mask layer ML1 may be a hard mask layer, and in some example embodiments, the first mask layer ML1 may include multiple layers comprising different materials. For example, the first mask layer ML1 may include polysilicon and / or silicon oxide. The second mask layer ML2 may be a photoresist layer, and may be, for example, a positive photoresist layer in which the exposed area is dissolved by the developer.

[0133] First, the second mask layer ML2 can be patterned using photolithography. Then, the patterned second mask layer ML2 can be used to etch the first mask layer ML1, thereby forming the opening OP. The opening OP can be formed corresponding to... Figure 2A The contact plugs MC_U and MC_L are provided. The lower end of the opening OP can be disposed in the insulating layer 192 of the first cell region. However, in the example embodiment, the horizontal position (in the Z direction) of the lower end of the opening OP in the insulating layer 192 of the first cell region can be varied. After the opening OP is formed, the second mask layer ML2 can be removed.

[0134] Reference Figure 11C A patterned third mask layer ML3 can be formed on the first mask layer ML1, and a first etching process can be performed to form a contact hole CTH.

[0135] The third mask layer ML3 can be a photoresist layer, and for example, it can be a negative photoresist layer where the unexposed areas are dissolved by the developer. The third mask layer ML3 can be exposed in some areas corresponding to the openings OP, where the exposed areas can be preserved, and some openings OP in the unexposed areas can be exposed. In this operation, for example, in... Figure 2A In this configuration, the corresponding contact plugs MC_U and MC_L can be electrically connected to the Nth gate electrode 130 from the top. When N is converted to binary form, the opening OP corresponding to the case where the last bit is 1 can be at least partially exposed.

[0136] The first cell region insulating layer 192, at least partially exposed through the bottom surface of the exposed opening OP, can be etched to form the contact hole CTH. The first etching process can be, for example, a dry etching process. For example, the first cell region insulating layer 192 below the opening OP can be completely etched, exposing the uppermost sacrificial insulating layer 118 through the bottom surface of the contact hole CTH.

[0137] Reference Figure 11D It can form a patterned fourth mask layer ML4, and can perform a second etching process to form or expand contact holes CTH.

[0138] First, the third mask layer ML3 can be removed, as can be referred to... Figure 11C The above process is performed similarly. The fourth mask layer ML4 can be a photoresist layer, for example, a negative photoresist layer. This is achieved through a photolithography process, for example, in... Figure 2A In this process, the corresponding contact plugs MC_U and MC_L can be electrically connected to the Nth gate electrode 130 from the top. When N is converted to binary form, the opening OP corresponding to the penultimate bit being 1 can be at least partially exposed. Next, a second etching process can remove the two sacrificial insulating layers 118 and two interlayer insulating layers 120 from the top to form a contact hole CTH or to extend an existing contact hole CTH in the Z direction. The sacrificial insulating layer 118 can be at least partially exposed through the bottom surface of the contact hole CTH. In some example embodiments, the diameters of some openings OP and contact holes CTH can be increased with repeated etching processes.

[0139] Reference Figure 11E It can form a patterned fifth mask layer ML5, and can perform a third etching process to form or expand contact holes CTH.

[0140] First, the fourth mask layer ML4 can be removed to form the fifth mask layer ML5. The fifth mask layer ML5 can be a photoresist layer, for example, a negative photoresist layer. This is achieved through a photolithography process, for example, in... Figure 2A In this process, the corresponding contact plugs MC_U and MC_L can be connected to the Nth gate electrode 130 from the top. When N is converted to binary form, the opening OP corresponding to the case where the third-to-last bit is 1 can be exposed. Next, through a third etching process, the four sacrificial insulating layers 118 and the four interlayer insulating layers 120 from the top can be removed to form the contact hole CTH or to extend the existing contact hole CTH in the Z direction.

[0141] Reference Figure 11F It can form a patterned sixth mask layer ML6, and can perform a fourth etching process to form or expand contact holes CTH.

[0142] First, the fifth mask layer ML5 can be removed to form the sixth mask layer ML6. The sixth mask layer ML6 can be a photoresist layer, for example, a negative photoresist layer. This is achieved through a photolithography process, for example, in... Figure 2A In this process, the corresponding contact plugs MC_U and MC_L can be connected to the Nth gate electrode 130 from the top. When N is converted to binary form, the opening OP corresponding to the case where the fourth-to-last bit is 1 can be at least partially exposed. Next, through a fourth etching process, the eight sacrificial insulating layers 118 and eight interlayer insulating layers 120 from the top can be removed to form the contact hole CTH or to extend the existing contact hole CTH in the Z direction.

[0143] Reference Figure 11G It can form a patterned seventh mask layer ML7, and can perform a fifth etching process to form or expand contact holes CTH.

[0144] First, the sixth mask layer ML6 can be removed to form the seventh mask layer ML7. The seventh mask layer ML7 can be a photoresist layer, for example, a negative photoresist layer. This is achieved through a photolithography process, for example, in... Figure 2A In this process, the corresponding contact plugs MC_U and MC_L can be connected to the Nth gate electrode 130 from the top. When N is converted to binary form, the opening OP corresponding to the fifth-to-last bit being 1 can be exposed. Next, through a fifth etching process, the 16 sacrificial insulating layers 118 and 16 interlayer insulating layers 120 from the top can be removed to form the contact hole CTH or to extend the existing contact hole CTH in the Z direction. Then, the seventh mask layer ML7 can be removed.

[0145] Through the above process, contact holes CTH of different depths can be ultimately formed in the mold structure PS. Depending on the number of sacrificial insulating layers 118 stacked in the mold structure PS, the etching 2 described above can be repeatedly performed. n The process of sacrificial insulating layers 118 (where n = 0, 1, 2, ...). In this example embodiment, the first to fifth etching processes are described as being performed sequentially starting from the case where n is 0, but the order of the etching processes can be varied.

[0146] Thus, by repeatedly performing etching processes like the first to fifth etching processes, the depth of the formed contact hole CTH can be varied. In each etching process, the third to seventh mask layers ML3, ML4, ML5, ML6, and ML7 can be formed to at least partially fill the opening OP and a portion of the contact hole CTH. In this case, as described above, because the sum of the depths of the contact hole CTH is... Figure 2A The first to sixth regions R1, R2, R3, R4, R5, and R6 are identical or similar to each other. Therefore, compared to the case where the contact hole CTH gradually deepens in the Z direction, the amount of material in the third to seventh mask layers ML3, ML4, ML5, ML6, and ML7, which at least partially fill the opening OP and the contact hole CTH, can be more uniform in the second contact region CT2. Consequently, the contours of the upper surfaces of the third to seventh mask layers ML3, ML4, ML5, ML6, and ML7 can have a relatively uniform shape by minimizing or reducing their step portions. Therefore, DOF can be ensured during the photolithography process, thereby improving process accuracy and the reliability of the semiconductor device.

[0147] Reference Figure 11HThe first mask layer ML1 can be removed, and a preliminary contact insulation layer 160P and a contact sacrificial layer 129 can be formed in the contact hole CTH.

[0148] The first mask layer ML1 can be removed by performing an etching process and / or a planarization process. The initial contact insulating layer 160P can be conformally formed to at least partially cover the sidewalls and bottom surface of the contact hole CTH. For example, the initial contact insulating layer 160P can be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes.

[0149] The contact sacrificial layer 129 may be formed to at least partially fill the contact hole CTH on the initial contact insulation layer 160P. The contact sacrificial layer 129 may include a material different from the initial contact insulation layer 160P, and may include, for example, carbon (C).

[0150] Reference Figure 11I It can form a channel structure CH and a dummy vertical structure DH, remove the sacrificial insulating layer 118, and form a gate electrode 130.

[0151] A mask layer can be formed that exposes only the region corresponding to the channel structure CH in the memory cell region MCA, and the exposed vertical sacrificial structure VS can be removed to form a channel via. At least a portion of the channel dielectric layer 145, the channel layer 140, the channel buried insulating layer 147, and the channel pad 149 can be sequentially deposited in the channel via to form the channel structure CH.

[0152] A mask layer can be formed to at least partially expose the region corresponding to the dummy vertical structure DH in the first contact region CT1 and the second contact region CT2. The dummy via can be formed by removing the exposed vertical sacrificial structure VS. A process can be performed to expand the dummy via by partially removing the mold structure PS surrounding it. The dummy vertical structure DH can be formed by filling the expanded dummy via with an insulating material.

[0153] Next, you can... Figure 1 The vertical sacrificial structure VS is removed at the location corresponding to the gate separation region MS to form a vertical via. By removing the portion of the stencil structure PS around the vertical via, the vertical vias can be expanded to connect with each other, thereby forming a trench-shaped opening corresponding to the gate separation region MS. The sacrificial insulating layer 118 exposed through the trench-shaped opening can be removed. The sacrificial insulating layer 118 can be selectively removed, for example, using wet etching relative to the interlayer insulating layer 120, the channel structure CH, the dummy vertical structure DH, and the initial contact insulating layer 160P.

[0154] The gate electrode 130 can be formed by depositing a conductive material in the region where the sacrificial insulating layer 118 has been removed. The conductive material may include metals, polysilicon, and / or metal silicides. In some example embodiments, a portion of the channel dielectric layer 145 may be formed prior to the formation of the gate electrode 130. Therefore, a gate structure GS comprising first to fourth stacked structures GS1, GS2, GS3, and GS4 can be formed. After the formation of the gate electrode 130, insulating material may be deposited in the trench-shaped opening to form... Figure 2B The gate separation region MS.

[0155] Reference Figure 11J The contact sacrificial layer 129 can be removed, a portion of the initial contact insulating layer 160P can be removed to form a contact spacer 160, conductive material can be deposited in the contact hole CTH to form contact plugs MC_U and MC_L, and a first upper separation region SS1 and a second upper separation region SS2 can be formed.

[0156] The contact sacrificial layer 129 can be selectively removed relative to the initial contact insulating layer 160P. Next, the initial contact insulating layer 160P exposed through the contact hole CTH can be partially removed from the bottom surface of the contact hole CTH. When the initial contact insulating layer 160P is partially removed, the exposed gate electrode 130 can also be partially recessed from the top surface. Therefore, contact spacers 160 can be formed only on the sidewalls of the contact hole CTH.

[0157] Contact plugs MC_U and MC_L can be formed together by depositing conductive material in the contact hole CTH. Contact plugs MC_U and MC_L can be physically connected and electrically connected to the gate electrode 130, respectively.

[0158] In separation and Figure 1 In the regions corresponding to the first upper separation region SS1 and the second upper separation region SS2, trenches can be formed by removing a portion of the gate structure GS to penetrate or extend through the upper gate electrode 130U. Within the trenches, the trench corresponding to the first upper separation region SS1 can be formed to extend while simultaneously cutting a portion of the channel structure CH in the memory cell region MCA. The trenches can be at least partially filled with an insulating material, and a planarization process can be performed to form the first upper separation region SS1 and the second upper separation region SS2. In some example embodiments, the first upper separation region SS1 and the second upper separation region SS2 can be formed in different process operations.

[0159] Reference Figure 11K A first semiconductor structure S1 can be formed by forming a stake 180, a unit interconnect line 185 and a first bonding structure, and a second semiconductor structure S2 can be formed. Then the first semiconductor structure S1 and the second semiconductor structure S2 can be bonded to each other.

[0160] A post 180 can be formed by forming a post hole that penetrates or extends through the insulation layer 194 of the second unit region to at least partially expose the channel structure CH and the contact plugs MC_U and MC_L, and then filling the post hole at least partially with a conductive material. Unit interconnects 185 can be formed on the post 180.

[0161] The first bonding path 195 and the first bonding metal layer 198, which are included in the first bonding structure, can be formed by additionally forming a second cell region insulating layer 194 and a first bonding insulating layer 199 on the cell interconnect 185, then removing a portion of it and filling the removed portion at least partially with a conductive material. The lower surface of the first bonding metal layer 198 can be at least partially exposed from the first bonding insulating layer 199. In this way, the first semiconductor structure S1 can be fabricated.

[0162] The second semiconductor structure S2 can be prepared by forming circuit elements 220, circuit interconnection structures and second bonding structures on substrate 201.

[0163] A device isolation layer 210 can be formed in substrate 201, and a circuit gate dielectric layer 222 and a circuit gate electrode 225 can be sequentially formed on substrate 201. The device isolation layer 210 can be formed, for example, by a shallow trench isolation (STI) process. The circuit gate dielectric layer 222 and the circuit gate electrode 225 can be formed using ALD or CVD. The circuit gate dielectric layer 222 can be formed of silicon oxide, and the circuit gate electrode 225 can be formed of at least one of polysilicon and metal silicide layers, but embodiments of this disclosure are not limited thereto. A spacer layer 224 and a source / drain region 205 can be formed on the two sidewalls of the circuit gate dielectric layer 222 and the circuit gate electrode 225. According to an exemplary embodiment, the spacer layer 224 can be formed of multiple layers. The source / drain region 205 can be formed during an ion implantation process.

[0164] The circuit contact plug 270 of the circuit interconnect structure and the second bonding passage 295 of the second bonding structure can be formed by forming a portion of the peripheral region insulating layer 290, then etching and removing a portion of the peripheral region insulating layer 290, and at least partially filling the removed portion with a conductive material. The circuit interconnect line 280 of the circuit interconnect structure and the second bonding metal layer 298 of the second bonding structure can be formed, for example, by depositing a conductive material and then patterning the conductive material. The second bonding metal layer 298 can be formed such that its upper surface is at least partially exposed through the second bonding insulating layer 299.

[0165] The peripheral region insulating layer 290 can be formed from multiple insulating layers. The peripheral region insulating layer 290 can be partially formed during the corresponding operations of forming the circuit interconnect structure and the second bonding structure. Through this operation, the second semiconductor structure S2 can be fabricated.

[0166] The first semiconductor structure S1 and the second semiconductor structure S2 can be connected by applying pressure to bond the first bonding metal layer 198 and the second bonding metal layer 298. Simultaneously, the first bonding insulating layer 199 and the second bonding insulating layer 299 can also be bonded by applying pressure. The first semiconductor structure S1 can be flipped over the second semiconductor structure S2, with the first bonding metal layer 198 facing downwards, and then bonding can be performed.

[0167] Reference Figure 11L It can remove the substrate SUB and expose the channel layer 140.

[0168] In the bonding structure of the first semiconductor structure S1 and the second semiconductor structure S2, the substrate SUB can be removed, and a portion of the exposed channel dielectric layer 145 can be removed, thereby exposing the channel layer 140.

[0169] Next, let's refer to... Figure 10B It can form a plate layer 101 connected to the channel layer 140, thereby manufacturing Figure 10B The semiconductor device 100i. In some example embodiments, the plate layer 101 may be formed as a conformal layer along the upper end of the channel structure CH and the upper end of the dummy vertical structure DH.

[0170] Figure 12 This is a schematic diagram of a data storage system including semiconductor devices according to an example embodiment.

[0171] Reference Figure 12 The data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 may be a solid-state drive (SSD) device including one or more semiconductor devices 1100, a universal serial bus (USB), a computing system, a medical device, or a communication device.

[0172] Semiconductor device 1100 may be a non-volatile memory device, and may be, for example, as described above. Figure 1 , Figure 2A , Figure 2B , Figure 3 , Figures 4A to 4C , Figures 5A to 5C , Figures 6A to 6B , Figures 7A to 7B , Figure 8 , Figure 9 and Figures 10A to 10B The described NAND flash memory device. Semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In an example embodiment, the first structure 1100F may be disposed adjacent to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including decoder circuitry 1110, page buffer 1120, and logic circuitry 1130. The second structure 1100S may be a memory cell structure including bit line BL, common source line CSL, word line WL, first upper gate line UL1 and second upper gate line UL2, first lower gate line LL1 and second lower gate line LL2, and a memory cell string CSTR between bit line BL and common source line CSL.

[0173] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary in various ways depending on the example embodiment.

[0174] In the example implementation, upper transistors UT1 and UT2 may include string select transistors, and lower transistors LT1 and LT2 may include ground select transistors. Lower gate lines LL1 and LL2 may be the gate electrodes of lower transistors LT1 and LT2, respectively. Word line WL may be the gate electrode of a memory cell transistor MCT, and upper gate lines UL1 and UL2 may be the gate electrodes of upper transistors UT1 and UT2, respectively.

[0175] In an example implementation, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 can be used for an erase operation to erase data stored in the memory cell transistor MCT by utilizing the GIDL phenomenon.

[0176] The common source line CSL, the first lower gate line LL1 and the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first interconnect 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second interconnect 1125 extending from the first structure 1100F to the second structure 1100S.

[0177] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 can be electrically connected to the logic circuit 1130 via an input / output interconnect 1135 extending from the first structure 1100F to the second structure 1100S.

[0178] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. According to an example embodiment, the data storage system 1000 may include a plurality of semiconductor devices 1100, in which case the controller 1200 may control the plurality of semiconductor devices 1100.

[0179] Processor 1210 can control the overall operation of data storage system 1000, including controller 1200. Processor 1210 can operate according to predetermined firmware and can control NAND controller 1220 to access semiconductor device 1100. NAND controller 1220 may include NAND interface 1221 for handling communication with semiconductor device 1100. Through NAND interface 1221, control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, and data to be read from memory cell transistors (MCTs) of semiconductor device 1100 can be transmitted. Host interface 1230 provides communication functionality between data storage system 1000 and external host. When a control command is received from external host through host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0180] Figure 13 This is a perspective view schematically illustrating a data storage system including semiconductor devices according to an example embodiment.

[0181] Reference Figure 13The data storage system 2000 may include a motherboard 2001, a controller 2002 mounted on the motherboard 2001, one or more semiconductor packages 2003 and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the controller 2002 via interconnect patterns 2005 formed on the motherboard 2001.

[0182] The motherboard 2001 may include a connector 2006, which includes a plurality of pins for connection to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. In an example embodiment, the data storage system 2000 may communicate with the external host via any of an interface such as Universal Serial Bus (USB), Peripheral Component Interconnect High Speed ​​(PCI-Express), Serial Advanced Technology Attachment (SATA), or M-Phy for Universal Flash Memory (UFS). In an example embodiment, the data storage system 2000 may operate via power supplied from the external host via the connector 2006. The data storage system 2000 may further include a power management integrated circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0183] The controller 2002 can write data to or read data from the semiconductor package 2003 and can improve the operating speed of the data storage system 2000.

[0184] DRAM 2004 can be a buffer memory used to mitigate the speed difference between the semiconductor package 2003, which serves as data storage space, and an external host. DRAM 2004 included in the data storage system 2000 can also function as a high-speed cache memory and can provide space for temporarily storing data during control operations on the semiconductor package 2003. When the data storage system 2000 includes DRAM 2004, in addition to including a NAND controller for controlling the semiconductor package 2003, controller 2002 may further include a DRAM controller for controlling DRAM 2004.

[0185] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 at least partially covering the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0186] The packaging substrate 2100 may be a printed circuit board including a package top pad 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to... Figure 12 The input / output pad 1101. Each semiconductor chip 2200 may include the above reference. Figure 1 , Figure 2A , Figure 2B , Figure 3 , Figures 4A to 4C , Figures 5A to 5C , Figures 6A to 6B , Figures 7A to 7B , Figure 8 , Figure 9 and Figures 10A to 10B The semiconductor device described.

[0187] In an example embodiment, the connection structure 2400 may be a bonding wire electrically connecting the input / output pad 2210 and the package pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via bonding wires and may be electrically connected to the package pad 2130 of the package substrate 2100. According to the example embodiment, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a connection structure 2400 that includes a through-silicon via (TSV) instead of a bonding wire connection structure.

[0188] In an example implementation, the controller 2002 and the semiconductor chip 2200 may be included in a single package. In another example implementation, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate, different from the motherboard 2001, and may be interconnected via interconnects formed on the interposer substrate.

[0189] This disclosure is not limited to the embodiments and drawings described above, but is defined by the appended claims. Therefore, those skilled in the art can make various substitutions, modifications, or alterations without departing from the scope of this disclosure as defined by the appended claims, and such substitutions, modifications, or alterations should be interpreted as being included within the scope of this disclosure.

[0190] This application claims priority to Korean Patent Application No. 10-2024-0145432, filed on October 23, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: A plate layer, including a memory cell region and a contact region on at least one side of the memory cell region; The gate electrodes are spaced apart from each other and stacked in a first direction perpendicular to the upper surface of the plate layer; A channel structure that extends through the gate electrode in the memory cell region and extends in the first direction; as well as Contact plugs, extending in the first direction within the contact area and electrically connected to the gate electrodes, respectively. Wherein, at least a portion of the contact plug extends through and contacts at least one of the gate electrodes. The contact plug includes a first contact plug and a second contact plug alternately arranged in a second direction perpendicular to the first direction, and The first contact plug has a corresponding depth that increases with the distance from the memory cell region in the second direction, and the second contact plug has a corresponding depth that decreases with the distance from the memory cell region in the second direction.

2. The semiconductor device according to claim 1, in, At least one of the second contact plugs has a depth greater than the depth of the two first contact plugs that are adjacent to each other in the second direction.

3. The semiconductor device according to claim 2, in, At least one of the second contact plugs has a depth smaller than that of the two first contact plugs that are adjacent to each other in the second direction.

4. The semiconductor device according to claim 1, in, The first contact plug has a corresponding depth that increases with a constant length as the distance from the memory cell region in the second direction increases.

5. The semiconductor device according to claim 1, in, The N gate electrodes are stacked in the first direction. Specifically, a pair of adjacent first and second contact plugs from the first and second contact plugs contact the A-th and B-th gate electrodes from the top of the gate electrodes. Where N, A, and B are natural numbers, and Where A+B<1.2N.

6. The semiconductor device according to claim 1, in, The first contact plug and the second contact plug, a pair of adjacent first contact plugs and second contact plugs respectively contact the Nth gate electrode and the MNth gate electrode from the top of the gate electrode. Where N and M are natural numbers, and M is greater than N.

7. The semiconductor device according to claim 1, in, The contact area includes a front area and a rear area arranged sequentially in the second direction, and Wherein, the first contact plug in the rear region that is closest to the front region has a lower depth in the first direction than the first contact plug in the front region that is closest to the rear region.

8. The semiconductor device according to claim 1, in, The contact plug further includes a third contact plug and a fourth contact plug, the third contact plug and the fourth contact plug being spaced apart from the first contact plug and the second contact plug in a third direction perpendicular to the first direction and the second direction, and being arranged alternately in the second direction. The third contact plug has a corresponding depth that decreases as the distance from the memory cell region in the second direction increases, and the fourth contact plug has a corresponding depth that increases as the distance from the memory cell region in the second direction increases.

9. The semiconductor device according to claim 8, in, The contact plug further includes a fifth contact plug, which is spaced apart from the first to the fourth contact plugs in the third direction and arranged in the second direction. The fifth contact plug has a depth that decreases or increases with the distance from the memory cell region in the second direction.

10. The semiconductor device according to claim 1, in, The diameter of the upper end of the corresponding contact plug with a first depth is greater than the diameter of the upper end of the corresponding contact plug with a second depth, wherein the second depth is less than the first depth.

11. The semiconductor device of claim 1, further comprising: A contact insulating layer is located between the side surface of the contact plug and the gate electrode through which the contact plug extends.

12. The semiconductor device according to claim 1, further comprising: A semiconductor structure, located below the plate layer in the first direction, includes a substrate and circuit elements on the substrate and electrically connected to the gate electrode and the channel structure.

13. A semiconductor device, comprising: A plate layer, including a memory cell region and a contact region on at least one side of the memory cell region; The gate electrodes are spaced apart from each other and stacked in a first direction perpendicular to the upper surface of the plate layer; A channel structure that extends through the gate electrode in the memory cell region and extends in the first direction; as well as Contact plugs are arranged upwards in the contact region in a second direction perpendicular to the first direction and in a third direction perpendicular to both the first and second directions, and extend in the first direction and are electrically connected to the gate electrode, respectively. The contact area includes a first area and a second area, wherein two or more contact plugs are respectively located in the first area and the second area, the first area and the second area are adjacent to each other in a plan view and have the same area. The sum of the layer numbers of the gate electrodes electrically connected to the contact plugs arranged in the first region is the same as the sum of the layer numbers of the gate electrodes electrically connected to the contact plugs arranged in the second region.

14. The semiconductor device according to claim 13, in, Two to 64 of the contact plugs are arranged in each of the first and second regions, and The number of contact plugs arranged in the first region is the same as the number of contact plugs arranged in the second region.

15. The semiconductor device according to claim 13, in, The contact plugs are arranged in a plurality of rows extending in the second direction and spaced apart from each other in the third direction, and Each of the first region and the second region includes one contact plug in each of the plurality of rows and extends upward from the third.

16. The semiconductor device according to claim 13, in, Each of the first region and the second region includes a plurality of said contact plugs arranged in the second direction and extending in the second direction.

17. The semiconductor device according to claim 13, in, The contact plugs include a first contact plug and a second contact plug alternately arranged in the second direction, and The first contact plug has a corresponding depth that increases in the first direction as the distance from the memory cell region in the second direction increases, and the second contact plug has a corresponding depth that decreases as the distance from the memory cell region in the second direction increases.

18. The semiconductor device according to claim 17, in, The difference in layer number between the gate electrodes connected to the first and second contact plugs that are adjacent to each other is 2 or more.

19. A data storage system, comprising: A semiconductor memory device includes a first semiconductor structure comprising circuit elements, a second semiconductor structure on the first semiconductor structure, and an input / output pad electrically connected to the circuit elements; as well as The controller is electrically connected to the semiconductor memory device via the input / output pad and configured to control the semiconductor memory device. The second semiconductor structure includes: A plate layer, including a memory cell region and a contact region on at least one side of the memory cell region; N gate electrodes are spaced apart from each other and stacked in a first direction perpendicular to the upper surface of the plate layer; A channel structure extending through the gate electrode in the memory cell region and extending in the first direction; and Contact plugs are arranged upwards in the contact region in a second direction perpendicular to the first direction and in a third direction perpendicular to both the first and second directions, and extend in the first direction and are electrically connected to the gate electrode, respectively. The contact area includes a first area and a second area, wherein two or more contact plugs are located in the first area and the second area respectively, and the first area and the second area are adjacent to each other in a plan view and have the same area. Wherein, the difference between the sum of the layer numbers of the gate electrodes electrically connected to the contact plugs arranged in the first region and the sum of the layer numbers of the gate electrodes electrically connected to the contact plugs arranged in the second region is 0.2N or less, and Where N is a natural number.

20. The data storage system according to claim 19, in, The contact plugs include a first contact plug and a second contact plug alternately arranged in the second direction, and The first contact plug has a corresponding depth that increases with the distance from the memory cell region in the second direction, and the second contact plug has a corresponding depth that decreases with the distance from the memory cell region in the second direction.

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