Semiconductor structure and preparation method thereof

Abstract

The invention discloses a semiconductor structure and a preparation method thereof. The method comprises the following steps: firstly, etching in an SOI substrate to form a groove which at least penetrates through a top semiconductor layer in the longitudinal direction; after isolation dielectric layers are formed on the side wall and the bottom of the groove, selectively removing the bottom isolation dielectric layer to expose the silicon substrate; if the bottom of the trench is located in the buried oxide layer, continuously etching the buried oxide layer until the silicon substrate is exposed after the isolation dielectric layer is removed; filling heavily-doped polycrystalline silicon or heavily-doped epitaxial monocrystalline silicon to form an electric conductor which is in ohmic contact with the silicon substrate; and finally forming a metal contact structure at the top of the conductor. According to the structure, the isolation dielectric layer on the side wall and the conductor in the center are integrated, integration of transverse electrical isolation and longitudinal conductive grounding is achieved, the integration degree and layout compactness of a chip are remarkably improved, meanwhile, high-voltage isolation, stable potential reference and an effective heat dissipation path are synchronously provided for an SOI-based high-voltage device, and the reliability of the chip is improved. And the voltage withstanding level, the anti-interference characteristic and the working reliability of the device are obviously improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a semiconductor structure and its preparation method. Background Technology

[0002] SOI (Silicon Oxide Insulator) substrate is a silicon-based substrate material widely used in advanced semiconductor manufacturing. It consists of a typical three-layer structure formed by introducing an insulating layer (usually silicon oxide, called buried oxide layer BOX) between the silicon layer and the substrate. This structure can effectively suppress parasitic capacitance and leakage current, significantly improve device performance, reduce power consumption and enhance radiation resistance.

[0003] However, in traditional SOI-based LDMOS (laterally diffused MOS) devices, the high potential in the high-voltage operating region couples through the substrate, causing a decrease in the device's breakdown voltage. For example, for a 100V NLDMOS (N-channel laterally diffused MOS) device, if the substrate potential is not controlled, its breakdown voltage may drop by approximately 8V. Therefore, traditional designs must introduce HWC (Handle Wafer Contact) substrate contact structures to fix the substrate potential, and simultaneously employ DTI (Deep Trench Isolation) structures for inter-device isolation. These discrete structures not only increase process complexity but also significantly increase the device layout area, limiting further improvements in chip integration density and hindering the realization of high-performance, highly integrated SOI-based high-voltage integrated circuits.

[0004] Therefore, designing a novel structure and fabrication method that balances electrical isolation, potential control, and high integration is a technical problem that needs to be solved.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor structure and its fabrication method, which aims to meet the requirements of electrical isolation, potential control and high integration.

[0007] To achieve the above and other related objectives, the present invention provides a semiconductor structure comprising:

[0008] SOI substrate, the SOI substrate comprising a top semiconductor layer, a buried oxide layer and a silicon substrate;

[0009] An isolation contact unit, the isolation contact unit being located within the SOI substrate, and comprising:

[0010] The trench extends downward from the upper surface of the SOI substrate, sequentially penetrating the top semiconductor layer and the buried oxide layer, and extending to the silicon substrate;

[0011] An isolation dielectric layer is located within the trench and at least covers the inner sidewall of the top semiconductor layer to provide lateral electrical isolation;

[0012] A conductor located within and filling the trench, the conductor being selected from heavily doped polycrystalline silicon or heavily doped epitaxial single-crystal silicon, and forming an ohmic contact with the silicon substrate to achieve a vertical electrical connection.

[0013] A metal contact structure is formed on the top of the conductor and electrically connected to the conductor.

[0014] Optionally, the doping concentration of the heavily doped polycrystalline silicon is at least 1e. 19 cm -3 The doping concentration of the heavily doped epitaxial single-crystal silicon is at least 1e. 19 cm -3 .

[0015] Optionally, the insulating dielectric layer comprises silicon oxide.

[0016] Optionally, the coverage area of ​​the isolation medium layer includes:

[0017] 1) Only the sidewall region of the trench within the top semiconductor layer is covered; or,

[0018] 2) Covering the sidewall region of the trench within the top semiconductor layer and the buried oxide layer; or,

[0019] 3) Covering the sidewall region of the trench within the top semiconductor layer, the buried oxide layer, and the silicon substrate.

[0020] Optionally, there are at least two isolation contact units, and in the top semiconductor layer, at least one active region is disposed within the area defined by the at least two isolation contact units.

[0021] Optionally, the ratio of the total width of the insulating dielectric layer to the width of the conductor ranges from 0.5 to 2.

[0022] This application also provides a method for fabricating a semiconductor structure, comprising the following steps:

[0023] S1, providing an SOI substrate, the SOI substrate comprising a top semiconductor layer, a buried oxide layer and a silicon substrate;

[0024] S2, forming a trench that extends downward from the upper surface of the SOI substrate and penetrates at least the top semiconductor layer;

[0025] S3, forming an isolation dielectric layer located within the trench and at least covering the inner sidewall of the top semiconductor layer;

[0026] S4, Perform a trench bottom processing step to expose the silicon substrate at the bottom of the trench;

[0027] S5, fill the trench with heavily doped polycrystalline silicon or grow heavily doped monocrystalline silicon through an epitaxial process to form a conductor, the conductor is located in the trench and fills the trench, and the bottom of the conductor forms an ohmic contact with the silicon substrate.

[0028] S6, a metal contact structure is formed on the top of the conductor, and the metal contact structure is electrically connected to the conductor.

[0029] Optionally, if the material exposed at the bottom of the trench in step S2 is the silicon substrate, then step S4 employs a highly selective cyclic etching process to remove the isolation dielectric layer covering the bottom of the trench.

[0030] If the material exposed at the bottom of the trench in step S2 is the buried oxide layer, then step S4 employs a patterned anisotropic etching process to etch downwards with the goal of penetrating the buried oxide layer and exposing the underlying silicon substrate.

[0031] Optionally, the cyclic etching process includes the following sub-steps:

[0032] S4-1, polymer deposition is performed, and due to the aspect ratio effect, the polymer selectively covers the surface of the SOI substrate and the top region of the sidewalls of the trench;

[0033] S4-2, perform anisotropic plasma etching to selectively etch the bottom of the trench, the isolation dielectric layer;

[0034] S4-3, Repeat steps S4-1 and S4-2 to remove the bottom of the isolation dielectric layer of the trench one by one until the silicon substrate is exposed;

[0035] S4-4, Perform a cleaning step to remove residual polymer.

[0036] Optionally, in step S5, the doping concentration of the heavily doped polycrystalline silicon is at least 1e. 19 cm -3The doping concentration of the heavily doped epitaxial single-crystal silicon is at least 1e. 19 cm -3 .

[0037] As described above, this application discloses a semiconductor structure and its fabrication method. First, a trench is etched in an SOI substrate to form a longitudinal trench that penetrates at least the top semiconductor layer. Then, an isolation dielectric layer is formed on the sidewalls and bottom of the trench, and the bottom isolation dielectric layer is selectively removed to expose the silicon substrate. If the bottom of the trench is located within the buried oxide layer, the buried oxide layer is etched further after removing the isolation dielectric layer until the silicon substrate is exposed. Next, heavily doped polycrystalline silicon or heavily doped epitaxial single-crystal silicon is filled to form a conductor that achieves ohmic contact with the silicon substrate. Finally, a metal contact structure is formed on top of the conductor. This semiconductor structure integrates the isolation dielectric layer on the sidewalls and the isolation contact unit of the conductor in the center within the trench, achieving integrated lateral electrical isolation and longitudinal conductive grounding. This solution can simultaneously provide SOI-based high-voltage devices with excellent high-voltage isolation capability, a stable potential reference, and an effective heat dissipation path, thereby significantly improving the device's withstand voltage level, anti-interference characteristics, and operational reliability. Attached Figure Description

[0038] Figure 1 The diagram shown is a schematic diagram of the semiconductor structure in an embodiment of the present invention, wherein the isolation contact unit extends from the surface of the silicon substrate on insulator to the surface of the silicon substrate.

[0039] Figure 2 The diagram shown is a schematic diagram of the semiconductor structure in an embodiment of the present invention, wherein the isolation contact unit extends from the surface of the silicon substrate on insulator to the inside of the silicon substrate.

[0040] Figure 3 The diagram shown is a schematic diagram of the semiconductor structure in an embodiment of the present invention, wherein the isolation dielectric layer extends from the surface of the silicon substrate on insulator to the buried oxide layer, and the conductor extends to the surface of the silicon substrate.

[0041] Figure 4 The diagram shows a schematic of the semiconductor structure fabrication process in an embodiment of the present invention.

[0042] Figure 5 The diagram shown is a schematic representation of the structure after providing a silicon-on-insulator substrate in an embodiment of the present invention.

[0043] Figure 6 The diagram shown is a schematic diagram of the structure after the trench is formed in an embodiment of the present invention, wherein the bottom of the trench exposes the surface of the silicon substrate.

[0044] Figure 7 The diagram shown is a schematic diagram of the structure after the trench is formed in an embodiment of the present invention, wherein the bottom of the trench exposes the interior of the silicon substrate.

[0045] Figure 8 The diagram shown is a structural schematic of the trench after it has been formed in an embodiment of the present invention, wherein the bottom of the trench exposes the surface of the buried oxygen layer.

[0046] Figure 9 The diagram shown is a structural schematic of the trench formed in an embodiment of the present invention, wherein the bottom of the trench exposes the interior of the buried oxygen layer.

[0047] Figure 10 The diagram shown is a schematic representation of the structure after the isolation medium layer is formed in an embodiment of the present invention.

[0048] Figure 11 The diagram shown is a schematic representation of the structure of the top semiconductor layer with the isolation dielectric layer removed in an embodiment of the present invention.

[0049] Figure 12 The diagram shows the structure after a polymer layer is formed on the surface of a silicon substrate on an insulator during the etching process in an embodiment of the present invention.

[0050] Figure 13 The diagram shows the structure after etching the isolation medium layer at the bottom of the trench in an embodiment of the present invention.

[0051] Figure 14 The diagram shown is a schematic representation of the structure after removing the residual polymer layer in an embodiment of the present invention.

[0052] Figure 15 The diagram shown is a schematic representation of the structure after the shallow isolation groove is formed in an embodiment of the present invention.

[0053] Figure 16 The diagram shown is a schematic representation of the structure of the high-voltage active device formed in an embodiment of the present invention.

[0054] Figure 17 The diagram shown is a schematic representation of the structure after the formation of the connecting metal contact structure in an embodiment of the present invention.

[0055] Explanation of reference numerals in the attached figures

[0056] 110, Silicon substrate; 120, Buried oxide layer; 130, Top semiconductor layer; 210, Trench; 220, Isolation dielectric layer; 230, Conductor; 240, Isolation contact unit; 250, Polymer layer; 310, Shallow isolation trench. Detailed Implementation

[0057] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0058] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0059] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, when a layer is referred to as “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0060] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0061] Example 1

[0062] This invention provides a method for fabricating a semiconductor structure, which will be described below in conjunction with... Figures 4-17 The method for fabricating the semiconductor structure in this embodiment is described, including the following steps:

[0063] First, refer to Figure 4 and Figure 5 Step S1 is performed to provide an SOI substrate, which includes a top semiconductor layer 130, a buried oxide layer 120, and a silicon substrate 110.

[0064] For details, please refer to Figure 5The SOI substrate comprises, from bottom to top, a silicon substrate 110, a buried oxide layer 120, and a top semiconductor layer 130. The silicon substrate 110 is heavily doped monocrystalline silicon of a first conductivity type (e.g., P-type or N-type), whose low resistance provides stable mechanical support and a uniform reference potential (typically ground or power supply potential) for the entire structure. As an example, the buried oxide layer 120 is silicon dioxide or other highly insulating dielectric layer used to achieve high-voltage electrical isolation or other types of voltage isolation between the top device and the substrate. The top semiconductor layer 130 is a lightly doped monocrystalline silicon layer of a first conductivity type or a second conductivity type, wherein the second conductivity type is opposite to the first conductivity type (e.g., if the substrate is P-type, the top layer can be P-type or N-type), and its crystal orientation is preferably (100), which facilitates obtaining high-quality device channels and gate oxide interfaces. Its thickness and resistivity can be optimized according to the withstand voltage level of the target high-voltage device. It is understood that the combination of conductivity types of the silicon substrate 110 and the top semiconductor layer 130 depends on the type of the core device ultimately integrated.

[0065] Before proceeding to the next step, the surface of the SOI substrate is cleaned using standard methods to obtain a clean starting surface.

[0066] Next, refer to Figure 4 and Figures 6-9 Step S2 is performed to form a trench 210, which extends downward from the upper surface of the SOI substrate and penetrates at least the top semiconductor layer 130.

[0067] Specifically, in one embodiment, a hard mask is sequentially deposited and patterned on the surface of the SOI substrate. Then, using the hard mask as a barrier layer, trenches 210 are etched in the SOI substrate using inductively coupled plasma etching (ICP-E). The depth of the trenches 210 at least completely penetrates the top semiconductor layer 130 and extends to the surface of the buried oxide layer 120. Figure 8 Or enter the oxygen layer to a certain depth within 120 ( Figure 9 ), or penetrate the buried oxide layer 120 to contact the silicon substrate 110 ( Figure 6 or Figure 7 Trench 210 has vertical sidewalls and a flat bottom. After etching, the hard mask is removed and the area is cleaned.

[0068] Furthermore, in one embodiment, see [reference] Figure 8 The trench 210 extends only to the surface of the buried oxide layer 120. This structure utilizes the isolation dielectric layer 220 on the sidewalls to provide basic lateral isolation. Further etching of the buried oxide layer 120 is required during subsequent trench 210 processing to reach at least the silicon substrate 110. In another embodiment, see [reference needed]. Figure 9The trench 210 penetrates to a certain depth into the buried oxide layer 120. The isolation dielectric layer 220 on the sidewall serves as a lateral isolation layer while simultaneously preserving a critical operating window for subsequent etching processes in this cycle, thus achieving controllable penetration of the buried oxide layer 120. In a preferred embodiment, see [reference needed]. Figure 6 or Figure 7 The trench 210 directly penetrates the buried oxide layer 120 and reaches the silicon substrate 110. In addition to the isolation function of the isolation dielectric layer 220 on the sidewall, it can also directly provide an interface for the subsequent formation of ohmic contacts.

[0069] Next, refer to Figure 4 and Figure 10 Step S3 is executed to form an isolation dielectric layer 220. The isolation dielectric layer 220 is located on the inner walls on both sides of the trench 210 and at least covers the corresponding inner sidewall of the top semiconductor layer 130.

[0070] Specifically, the isolation dielectric layer 220, acting as a high-resistivity insulator, blocks the leakage current path between the subsequent active region and the silicon substrate 110 or adjacent devices, forming the basis for lateral electrical isolation. In a preferred embodiment, the isolation dielectric layer 220 comprises silicon oxide. The silicon oxide acts as a mechanical buffer between the subsequent filling material (such as heavily doped polycrystalline silicon or heavily doped epitaxial single-crystal silicon) and the silicon substrate 110, absorbing thermal mismatch and process stress, providing an adhesion base for the subsequent filling structure, and ensuring the physical integrity of the isolation structure. Of course, the material of the isolation dielectric layer 220 is not limited.

[0071] As an example, the coverage of the isolation dielectric layer 220 includes covering only the sidewall region of the trench 210 within the top semiconductor layer 130; or covering the sidewall region of the trench 210 within the top semiconductor layer 130 and the buried oxide layer 120; or covering the sidewall region of the trench 210 within the top semiconductor layer 130, the buried oxide layer 120, and the silicon substrate 110.

[0072] Specifically, in one embodiment, corresponding to Figure 8 The trench 210 has an isolation dielectric layer 220 that only covers the sidewalls of the top semiconductor layer 130 within the trench 210. Its purpose is to isolate adjacent active devices within this layer and prevent lateral leakage. This process is simple, has the lowest cost, and is suitable for scenarios where isolation requirements are not high. In one specific embodiment, corresponding to... Figure 9 The trench 210, and the isolation dielectric layer 220 can extend downwards to cover the bottom sidewall of the buried oxide layer 120, further eliminating parasitic capacitance, leakage current, and latch-up effects. The key to this process is achieving the connection between the isolation dielectric layer 220 and the buried oxide layer 120, facilitating subsequent electrical connections to the silicon substrate 110. In another specific embodiment, corresponding to... Figure 6 and Figure 7The isolation dielectric layer 220 can further penetrate the buried oxide layer 120 and extend into the sidewalls of the silicon substrate 110. This approach is designed to provide ultimate isolation capabilities to block leakage paths that may propagate along the surface of the silicon substrate 110 and to enhance mechanical and thermal isolation.

[0073] In step S3, the isolation medium layer 220 can be formed by first generating a dense oxide layer on the sidewall of the trench 210 using a thermal oxidation process, followed by chemical vapor deposition, or by using chemical vapor deposition alone.

[0074] Specifically, the formation of the insulating dielectric layer 220 requires strict control of the process temperature while ensuring high-quality insulation, in order to minimize the thermal impact on the silicon substrate 110 and preserve interface integrity for the subsequent formation of high-performance ohmic contacts. Therefore, this invention abandons the traditional approach that relies entirely on high-temperature thermal oxidation processes.

[0075] Furthermore, the present invention can employ two low-temperature or medium-temperature process schemes. First, a low-temperature thermal oxidation process is used to generate a thin, dense oxide layer on the sidewall of trench 210 as a high-quality interface, followed by thick film filling using chemical vapor deposition. Alternatively, a chemical vapor deposition process with excellent step coverage can be directly employed. Preferred processes include: High-density plasma chemical vapor deposition (HDPCVD), which utilizes high-energy plasma to achieve complete dissociation of reactive gases under medium-temperature conditions, ensuring void-free and shape-preserving filling within the high aspect ratio trench 210. Helical wave plasma chemical vapor deposition (HAIPCVD) can deposit low-stress silicon oxide films at even lower temperatures using high-density, low-damage plasma.

[0076] By selecting the above-mentioned process, the present invention significantly reduces the formation temperature of the isolation dielectric layer 220, effectively controlling the overall thermal budget. This avoids damage to the doping profile of the silicon substrate 110 and the introduction of excessive stress, thus laying a crucial material and interface foundation for the subsequent formation of low-resistance, reliable ohmic contacts at the bottom of the trench 210.

[0077] As an example, see Figure 11 After the isolation dielectric layer 220 is formed, thinning processes such as chemical mechanical polishing, dry etching or wet etching are usually used to selectively remove the material of the isolation dielectric layer 220 that is over-deposited on the horizontal surface of the top semiconductor layer 130, so that only the required isolation dielectric layer 220 is retained in the trench 210, ensuring that the surface of the top semiconductor layer 130 is flat and clean, providing an ideal foundation for subsequent device manufacturing steps (such as gate formation or interconnection).

[0078] Next, refer to Figure 4 and Figures 12-13Step S4 is executed to perform a trench bottom processing step, which exposes the silicon substrate 110 at the bottom of the trench 210.

[0079] Specifically, in a preferred embodiment, in step S2, the material exposed at the bottom of the trench 210 is a silicon substrate 110, and the isolation dielectric layer 220 covering the sidewalls can achieve deeper electrical isolation. At this time, a highly selective cyclic etching process can be used to remove the isolation dielectric layer 220 covering the bottom of the trench 210 to achieve subsequent electrical contact.

[0080] As an example, the steps of a cyclic etching process include:

[0081] S4-1, see S4-1. Figure 12 A polymer layer 250 is deposited, which selectively covers the surface of the SOI substrate and the top region of the trench 210 sidewalls due to the aspect ratio effect.

[0082] In one specific embodiment, see Figure 12 The etching chamber is filled with a deposition gas to achieve deposition on the SOI substrate. By adjusting parameters such as the deposition gas flow rate, pressure, RF power, bias voltage, and deposition time, the polymer layer 250 is deposited. The deposition gas includes one or a combination of fluoromethane (CH3F), difluoromethane (CH2F2), and trifluoromethane (CHF3).

[0083] S4-2, perform anisotropic plasma etching to selectively etch the isolation dielectric layer 220 at the bottom of the trench 210.

[0084] For details, please refer to Figure 13 By precisely controlling the plasma chemical composition and bias power, and employing process conditions that have an extremely high etching selectivity for the isolation dielectric layer 220 (such as SiO2) relative to the silicon material, it is ensured that the isolation dielectric layer 220 at the bottom of the trench 210 is completely removed while the dielectric layer on the sidewall of the trench 210 is protected to the maximum extent.

[0085] As an example, in step S4-2, the vertical plasma etching of the isolation dielectric layer 220 uses an F-containing gas, such as one or a combination of C4F8, CH2F2, CHF3, and CF4. Generally, the concentration of F-containing free radicals affects the etching rate, and the etching rate can be further adjusted by the above-mentioned gas or combination.

[0086] S4-3, Repeat steps S4-1 to S4-2 to remove the bottom isolation dielectric layer 220 one by one until the silicon substrate 110 is exposed.

[0087] To completely remove the isolation dielectric layer 220 at the bottom of trench 210 and expose the silicon substrate 110, steps S4-1 to S4-2 (polymer layer deposition - anisotropic etching) need to be repeated. In each etching cycle, the newly deposited polymer layer 250 covers the periphery of trench 210, acting as a protective mask to ensure the vertical orientation of the plasma etching, thereby precisely removing only the bottom isolation dielectric layer 220. Through several such "deposition-etching" cycles, the bottom isolation dielectric layer 220 can be removed layer by layer. (See [reference]) Figure 14 Until finally the underlying silicon substrate 110 is exposed.

[0088] S4-4, perform dry cleaning to remove all polymer residues.

[0089] For details, please refer to Figure 14 In step S4-4, the gas used for dry cleaning includes oxygen-containing gas; of course, the gas used for dry cleaning may also include N2. Preferably, the flow rate of O2 ranges from 0 sccm to 2000 sccm; the flow rate of N2 ranges from 0 sccm to 2000 sccm. By adjusting the gas pressure, RF power, bias voltage, and cleaning time within the etching chamber, all polymers from the process are removed.

[0090] The highly selective cyclic etching process described above removes the isolation dielectric layer 220 at the bottom of trench 210. This process utilizes the high aspect ratio of trench 210; in each etching cycle, the polymer layer 250 deposited on the sidewalls ensures the vertical orientation of the etching, thus selectively removing only the bottom material. This not only provides space for the subsequent filling of the conductor 230, achieving integrated electrical isolation and electrical connection, but more importantly, compared to existing technologies that require separately defining the bottom etching window, this process eliminates an additional photolithography and etching step, thereby reducing the use of photomasks and significantly lowering production costs.

[0091] In another embodiment, in step S2, if the material exposed at the bottom of the trench 210 is the buried oxide layer 120, a patterned anisotropic etching process is used to perform downward etching with the goal of penetrating the buried oxide layer 120 and exposing the underlying silicon substrate 110.

[0092] Specifically, since the bottom of trench 210 has completely etched through the top semiconductor layer 130, and the exposed material is the buried oxide layer 120, a separate patterning process for the bottom is required to achieve specific device connections. Specifically, a temporary mask is first formed and patterned on the SOI substrate surface, opening only at the bottom of trench 210. Then, using this mask as a barrier layer, anisotropic etching with a high selectivity for SiO2 is employed to etch downwards to penetrate the buried oxide layer 120, stopping at or into the silicon substrate 110 as needed. The temporary mask is removed after etching. This process, through high-selectivity etching chemistry conditions (such as fluorine radical plasma with different etching rates for SiO2 and Si), forms a deeper dielectric isolation trench with superior electrical isolation characteristics, or prepares for subsequent substrate contact and other process steps.

[0093] Next, refer to Figure 4 and Figure 1 In step S5, heavily doped polycrystalline silicon is filled into trench 210 or heavily doped epitaxial single-crystal silicon is grown by epitaxial process to form conductor 230. Conductor 230 is located in trench 210 and fills trench 210. The bottom of conductor 230 forms an ohmic contact with silicon substrate 110.

[0094] Specifically, within the trench 210, heavily doped polycrystalline silicon or heavily doped epitaxial monocrystalline silicon is selectively filled to form an integrated conductor 230. When using heavily doped polycrystalline silicon, it is deposited at a medium-low temperature to achieve gapless filling of the trench 210 with a high aspect ratio, and ohmic contacts are formed through interdiffusion of interface dopants during rapid high-temperature annealing. When using heavily doped epitaxial monocrystalline silicon, it is selectively epitaxially grown on the exposed silicon substrate 110 at a medium-low temperature while simultaneously undergoing in-situ doping to maintain lattice continuity, thereby forming a low-resistivity ohmic interface.

[0095] As an example, see Figure 1 The insulating dielectric layer 220 has a first width W1 and a second width W2 on the two opposite sidewalls of the trench 210, respectively; the conductor 230 has a width Wc; wherein, the ratio of the total width W of the insulating dielectric layer 220 (W=W1+W2) to the width Wc of the conductor 230 is in the range of 0.5~2.

[0096] Specifically, in one embodiment, the conductor 230 is surrounded by an insulating dielectric layer 220, and the W / Wc ratio ranges from 0.5 to 2, for example, any number within this range such as 0.5, 0.8, 1, 1.5, or 2. This ratio range is set to simultaneously optimize conductivity and manufacturing robustness while ensuring reliable electrical isolation. When W / Wc ≥ 0.5, sufficient dielectric thickness is ensured to provide effective lateral electrical insulation and withstand the corresponding operating voltage. When W / Wc ≤ 2.0, excessive thickness of the insulating dielectric layer 220 avoids over-encroachment on the cross-sectional area of ​​the conductor 230, thereby ensuring the low resistance characteristics of the conductor 230 and preventing structural defects caused by stress mismatch in subsequent processes. Of course, W / Wc is not limited to this.

[0097] It should be noted that this invention integrates the functions of DTI and HWC in a traditional structure, making the structure more compact and reducing the total width occupied by DTI and HWC separately to the width of a single HWC, thereby significantly reducing the area footprint. This integrated design improves device layout efficiency and also provides room for further optimization of chip performance.

[0098] As an example, in step S5, the doping concentration of the heavily doped polycrystalline silicon is at least 1e. 19 cm -3 The doping concentration of heavily doped epitaxial single-crystal silicon is at least 1e. 19 cm -3 .

[0099] Specifically, the doping concentration of heavily doped polycrystalline silicon is not less than 1×10⁻⁶. 19 cm -3 This ensures that it has sufficiently low bulk resistance and conductivity comparable to that of a metal, thereby constructing an efficient potential conduction path in trench 210. Correspondingly, the doping concentration of the heavily doped epitaxial single-crystal silicon is also not less than 1×10⁻⁶. 19 cm -3 This ensures a tunnel current-dominated ohmic contact between the doping concentration and the underlying silicon substrate 110, significantly reducing interfacial contact resistance. This doping concentration threshold is set based on the principle of degenerate doping in semiconductor physics; when the doping concentration exceeds 1 × 10⁻⁶... 19 cm -3 At this point, the Fermi level enters the conduction band or valence band, allowing charge carriers to tunnel across the potential barrier, thus achieving linear current-voltage characteristics. In practical processes, polycrystalline silicon doping can be achieved through in-situ doping or ion implantation combined with annealing, while heavily doped epitaxial single-crystal silicon doping is mainly completed during the growth process through in-situ doping.

[0100] In this embodiment, the isolation dielectric layer 220 is first filled by a short-time thermal oxidation process and a low-temperature deposition dielectric layer (e.g., HDPCVD), rather than relying solely on high-temperature thermal oxidation. Then, polycrystalline silicon is selectively epitaxially or in-situ doped at the bottom of the trench 210 to form single crystal or heavily doped polycrystalline silicon at a relatively low temperature, and ohmic contacts are immediately formed by rapid thermal annealing, thus avoiding damage to the contact interface caused by prolonged high temperatures.

[0101] As an example, see Figure 1 Excess material of the conductor 230 on the surface of the SOI substrate is removed by one or a combination of grinding or CMP processes, so that the top surface of the conductor 230 is flush with the surface of the top semiconductor layer 130.

[0102] Specifically, when using a grinding process, large-sized protrusions in heavily doped polycrystalline silicon or heavily doped epitaxial single-crystal silicon are rapidly removed by mechanical grinding, preparing for subsequent fine polishing. When using a CMP process, the synergistic effect of chemical etching and mechanical grinding is utilized to achieve high-precision removal while obtaining an atomically smooth surface. In a preferred embodiment, a grinding process is first used for rough planarization to improve efficiency, followed by a CMP process for fine planarization to ensure surface quality and thickness uniformity. This step ensures that the conductor 230 remains only inside the trench 210, and its top surface is flush with the surface of the top semiconductor layer 130 of the SOI substrate, providing an ideal base plane for subsequent device fabrication and interconnect layer formation.

[0103] Next, refer to Figure 4 and Figure 17 Step S6 is executed to form a metal contact structure (not labeled) on the top of the conductor 230, and the metal contact structure is electrically connected to the conductor 230.

[0104] Specifically, after the conductor 230 completely fills the trench 210, a metal contact structure is formed on the surface of the conductor 230 to form an electrical connection on the top of the conductor 230 through a metallization process, thereby biasing it to a fixed potential (such as ground). Thus, the formed structure not only achieves the mechanical support and isolation function of the isolation contact unit 240, but also provides a stable potential reference and noise shielding for the device area through this low-resistance conductive path.

[0105] In one specific embodiment, prior to step S6, the fabrication of the semiconductor structure further includes: (Refer to...) Figures 15-17 At least one active region is formed in the top semiconductor layer 130 of the SOI substrate, and in the horizontal direction, at least one active region is disposed within a region defined by at least two isolation contact units 240.

[0106] In a specific embodiment, the active region is a high-voltage active region, which is horizontally surrounded and isolated by isolation contact units 240 on both sides. Conductors 230 within the isolation contact units 240 are electrically connected to ground potential, thereby providing potential fixation and noise shielding for the high-voltage active region. The high-voltage active region can be used to form at least one high-voltage device, such as a laterally diffused metal-oxide-semiconductor device, a double-diffused metal-oxide-semiconductor device, or an insulated-gate bipolar transistor. See also... Figures 15-16 To form a shallow isolation trench 310 in the high-voltage active area; Figure 17 To further develop the structure of each part of the high-voltage active region, the electrodes of the high-voltage device can be electrically connected to the external circuit through the subsequently formed interconnect layer. The high-voltage device not only obtains the excellent electrical isolation performance brought by the isolation contact unit 240, but also relies on the stable potential reference provided by the grounded conductor 230, thereby significantly improving its breakdown voltage, anti-interference capability, and overall performance during operation.

[0107] In other embodiments, to further optimize the electrical stability of the ohmic contact between the conductor 230 and the silicon substrate 110, particularly to reduce its resistance drift under high-temperature operating conditions, a doping concentration gradient region can be formed on a portion of the silicon substrate 110 corresponding to the trench 210. This gradient region has a higher concentration at the surface of the silicon substrate 110 than the bulk silicon substrate 110, gradually decreasing towards the bottom of the silicon substrate 110. This design achieves low contact resistance through ultra-high surface concentration and widens the depletion region using a concentration gradient decreasing towards the interior of the silicon substrate 110, thereby reducing the temperature sensitivity of the electrical properties in this region. This ensures the ohmic contact remains stable at high temperatures, reinforcing the potential anchoring reliability of the isolation contact unit 240.

[0108] It should be noted that this invention provides a universal isolation contact solution, the core concept of which is universally applicable. The conductivity type of the semiconductor region can be completely reversed to form complementary devices, and the isolation contact unit 240 adopts a modular design, which can be adapted to all power device architectures requiring lateral high-voltage isolation, regardless of its specific internal structure. This invention effectively improves the device's withstand voltage capability by optimizing the electric field distribution and potential anchoring, and is applicable to the entire voltage range. The high-voltage device listed in this embodiment is only an example. The principle of this integrated architecture, which utilizes the grounded isolation contact unit 240 to surround and shield the active region, is also applicable to other semiconductor devices that require fine electric field management or strict noise isolation. Any variations and combinations based on this core principle are within the protection scope of this invention.

[0109] Example 2

[0110] This embodiment proposes a semiconductor structure, which can be prepared according to Embodiment 1 or a similar method. (See reference...) Figures 1-3The semiconductor structure will now be described, and the semiconductor structure includes:

[0111] SOI substrate, the SOI substrate includes a top semiconductor layer 130, a buried oxide layer 120 and a silicon substrate 110;

[0112] Isolation contact unit 240, formed in SOI substrate, includes:

[0113] Trench 210 extends downward from the upper surface of the SOI substrate, passing through the top semiconductor layer 130 and the buried oxide layer 120 in sequence, and extending to the silicon substrate 110.

[0114] An isolation dielectric layer 220 is located within the trench 210 and at least covers the inner sidewall of the top semiconductor layer 130 to provide lateral electrical isolation.

[0115] Conductor 230 is located in and fills the trench 210. Conductor 230 is selected from heavily doped polycrystalline silicon or heavily doped epitaxial single-crystal silicon and forms an ohmic contact with the silicon substrate 110 to achieve vertical electrical connection.

[0116] A metal contact structure is formed on the top of the conductor 230 and electrically connected to the conductor 230.

[0117] Specifically, this embodiment is an integrated isolation contact unit 240 based on an SOI substrate. A trench 210 extends from top to bottom through the top semiconductor layer 130, the buried oxide layer 120, and the silicon substrate 110. The sidewalls of the trench 210 are covered with an isolation dielectric layer 220 to achieve lateral electrical isolation between devices. The center of the trench 210 is filled with heavily doped polycrystalline silicon or heavily doped epitaxial single-crystal silicon as a conductor 230. The bottom of the conductor 230 forms an ohmic contact with the silicon substrate 110, constituting a vertical conductive path. A metal contact interface is provided at the top of the isolation contact unit 240, forming a composite structure that combines lateral isolation and vertical electrical connection functions.

[0118] This structure significantly improves performance by integrating lateral isolation and potential fixation. The longitudinally continuous arrangement of the isolation contact unit 240 enhances isolation withstand voltage; simultaneously, the low-resistance grounding path provided by the conductor 230 establishes a stable potential reference and an efficient noise discharge path for adjacent devices, effectively suppressing crosstalk and switching noise. Furthermore, the conductor 230 also forms an additional heat dissipation channel, helping to alleviate the inherent self-heating effect of the SOI structure, improving the reliability of power devices. The overall structure is compatible with standard CMOS processes, facilitating modular layout and integration in integrated circuits.

[0119] As an example, the doping concentration of heavily doped polycrystalline silicon is at least 1e.19 cm -3 The doping concentration of heavily doped epitaxial single-crystal silicon is at least 1e. 19 cm -3 .

[0120] Specifically, the doping concentration of heavily doped polycrystalline silicon is not less than 1×10⁻⁶. 19 cm -3 This ensures that it has sufficiently low bulk resistance and conductivity comparable to that of a metal, thereby constructing an efficient potential conduction path in trench 210. Correspondingly, the doping concentration of the heavily doped epitaxial single-crystal silicon is also not less than 1×10⁻⁶. 19 cm -3 This ensures a tunnel current-dominated ohmic contact between the doping concentration and the underlying silicon substrate 110, significantly reducing interfacial contact resistance. This doping concentration threshold is set based on the principle of degenerate doping in semiconductor physics; when the doping concentration exceeds 1 × 10⁻⁶... 19 cm -3 At this point, the Fermi level enters the conduction band or valence band, allowing charge carriers to tunnel across the potential barrier, thus achieving linear current-voltage characteristics. In practical processes, doping of polycrystalline silicon can be achieved through in-situ doping or ion implantation combined with annealing, while doping of epitaxial single-crystal silicon is mainly completed during the growth process through in-situ doping.

[0121] In a preferred embodiment of the present invention, the material of the isolation dielectric layer 220 is silicon oxide (SiO2). The isolation dielectric layer 220 can be formed by first generating a dense oxide layer on the sidewall of the trench 210 using a thermal oxidation process, followed by chemical vapor deposition, or by using chemical vapor deposition alone.

[0122] As an example, the coverage of the isolation dielectric layer 220 includes covering only the sidewall region of the trench 210 within the top semiconductor layer 130; or covering the sidewall region of the trench 210 within the top semiconductor layer 130 and the buried oxide layer 120; or covering the sidewall region of the trench 210 within the top semiconductor layer 130, the buried oxide layer 120, and the silicon substrate 110.

[0123] Specifically, in one embodiment, see [reference] Figure 3 The isolation dielectric layer 220 only covers the sidewalls of the top semiconductor layer 130 within the trench 210. Its purpose is to isolate adjacent active devices within this layer and prevent lateral leakage. Its process is simple, cost-effective, and suitable for scenarios with low isolation requirements. In one specific embodiment, see [reference needed]. Figure 1 The isolation dielectric layer 220 can extend downwards to cover the buried oxide layer 120, thereby further eliminating parasitic capacitance, leakage current, and latch-up effects. The key to this process is achieving the connection between the isolation dielectric layer 220 and the buried oxide layer 120, facilitating subsequent electrical connections to the silicon substrate 110. In another specific embodiment, see [reference needed]. Figure 2 The isolation dielectric layer 220 can further penetrate the buried oxide layer 120 and extend into the interior of the silicon substrate 110. This approach is designed to provide ultimate isolation capabilities to block leakage paths that may propagate along the surface of the silicon substrate 110 and to enhance mechanical and thermal isolation.

[0124] As an example, the insulating dielectric layer 220 has a first width W1 and a second width W2 on the two opposite sidewalls of the trench 210, respectively; the conductor 230 has a width Wc; wherein the ratio of the total width W of the insulating dielectric layer 220 (W=W1+W2) to the width Wc of the conductor 230 is in the range of 0.5~2.

[0125] For details, please refer to Figure 1 The W / Wc ratio ranges from 0.5 to 2, for example, any number within this range such as 0.5, 0.8, 1, 1.5, or 2. This ratio range is set to simultaneously optimize conductivity and manufacturing robustness while ensuring reliable electrical isolation. When W / Wc ≥ 0.5, sufficient dielectric thickness is ensured to provide effective lateral electrical insulation and withstand the corresponding operating voltage. When W / Wc ≤ 2.0, excessive thickness of the isolation dielectric layer 220 avoids over-encroachment on the cross-sectional area of ​​the conductor 230, thus ensuring the low resistance characteristics of the conductor 230 and preventing structural defects caused by stress mismatch in subsequent processes. Of course, W / Wc is not limited to this. This setting does not require additional chip area, significantly improving the integration and layout compactness of SOI-based chips.

[0126] As an example, the semiconductor structure also includes at least two isolation contact units 240, and in the top semiconductor layer 130, at least one active region is disposed within the area defined by the at least two isolation contact units 240.

[0127] For details, please refer to Figures 15-17 The active region is a high-voltage active region, which is horizontally surrounded and isolated by isolation contact units 240 on both sides. Conductors 230 within the isolation contact units 240 are electrically connected to ground potential, thereby providing potential fixation and noise shielding for the high-voltage active region. The high-voltage active region can be used to form at least one high-voltage device, such as a laterally diffused metal-oxide-semiconductor device, a double-diffused metal-oxide-semiconductor device, or an insulated-gate bipolar transistor. The electrodes of the high-voltage device can be electrically connected to external circuits through subsequently formed interconnect layers. The high-voltage device not only benefits from the excellent electrical isolation provided by the isolation contact units 240, but also benefits from the stable potential reference provided by the grounded conductor 230, thereby significantly improving its breakdown voltage, interference immunity, and overall reliability during operation.

[0128] The materials used in the structures involved in this embodiment are similar to those in Embodiment 1, and will not be described in detail here.

[0129] In summary, this invention provides a semiconductor structure and its fabrication method. First, a trench is etched in an SOI substrate to form a longitudinal trench that penetrates at least the top semiconductor layer. Then, an isolation dielectric layer is formed on the sidewalls and bottom of the trench, and the bottom isolation dielectric layer is selectively removed to expose the silicon substrate. If the bottom of the trench is located within a buried oxide layer, the buried oxide layer is etched further after removing the isolation dielectric layer until the silicon substrate is exposed. Next, heavily doped polycrystalline silicon or epitaxial single-crystal silicon is filled to form a conductor that achieves ohmic contact with the silicon substrate. Finally, a metal contact structure is formed on top of the conductor. The semiconductor structure is a composite unit integrating the sidewall isolation dielectric layer and the central conductor within the trench, achieving integrated lateral electrical isolation and longitudinal conductive grounding. This eliminates the need for additional chip area, simplifies the process, and significantly improves the integration density and layout compactness of SOI-based chips. This solution can simultaneously provide excellent high-voltage isolation capability, a stable potential reference, and an effective heat dissipation path for SOI-based high-voltage devices, thereby significantly improving the device's withstand voltage level, anti-interference characteristics, and operational reliability. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0130] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A semiconductor structure, characterized in that, include: SOI substrate, the SOI substrate comprising a top semiconductor layer, a buried oxide layer and a silicon substrate; An isolation contact unit, wherein the isolation contact unit is located within the SOI substrate, and the isolation contact unit comprises: The trench extends downward from the upper surface of the SOI substrate, sequentially penetrating the top semiconductor layer and the buried oxide layer, and extending to the silicon substrate; An isolation dielectric layer is located within the trench and at least covers the inner sidewall of the top semiconductor layer to provide lateral electrical isolation; A conductor located within and filling the trench, the conductor being selected from heavily doped polycrystalline silicon or heavily doped epitaxial single-crystal silicon, and forming an ohmic contact with the silicon substrate to achieve a vertical electrical connection. A metal contact structure is formed on the top of the conductor and electrically connected to the conductor.

2. The semiconductor structure according to claim 1, characterized in that: The doping concentration of the heavily doped polycrystalline silicon is at least 1e. 19 cm -3 The doping concentration of the heavily doped epitaxial single crystal silicon is at least 1e. 19 cm -3 .

3. The semiconductor structure according to claim 1, characterized in that: The insulating dielectric layer comprises silicon oxide.

4. The semiconductor structure according to claim 1, characterized in that, The coverage area of ​​the isolation medium layer includes: 1) Only the sidewall region of the trench within the top semiconductor layer is covered; or, 2) Covering the sidewall region of the trench within the top semiconductor layer and the buried oxide layer; or, 3) Covering the sidewall region of the trench within the top semiconductor layer, the buried oxide layer, and the silicon substrate.

5. The semiconductor structure according to claim 1, characterized in that: The isolation contact unit is at least two, and in the top semiconductor layer, at least one active region is disposed within the area defined by the at least two isolation contact units.

6. The semiconductor structure according to claim 1, characterized in that, include: The ratio of the total width of the isolation dielectric layer to the width of the conductor ranges from 0.5 to 2.

7. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: S1, providing an SOI substrate, the SOI substrate comprising a top semiconductor layer, a buried oxide layer and a silicon substrate; S2, forming a trench that extends downward from the upper surface of the SOI substrate and penetrates at least the top semiconductor layer; S3, forming an isolation dielectric layer located within the trench and at least covering the inner sidewall of the top semiconductor layer; S4, Perform a trench bottom processing step to expose the silicon substrate at the bottom of the trench; S5, fill the trench with heavily doped polycrystalline silicon or grow heavily doped monocrystalline silicon by epitaxial process to form a conductor, the conductor is located in the trench and fills the trench, and the bottom of the conductor forms an ohmic contact with the silicon substrate. S6, a metal contact structure is formed on the top of the conductor, and the metal contact structure is electrically connected to the conductor.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: If the material exposed at the bottom of the trench in step S2 is the silicon substrate, then step S4 employs a highly selective cyclic etching process to remove the isolation dielectric layer covering the bottom of the trench. If the material exposed at the bottom of the trench in step S2 is the buried oxide layer, then step S4 employs a patterned anisotropic etching process to etch downwards with the goal of penetrating the buried oxide layer and exposing the underlying silicon substrate.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The cyclic etching process includes the following sub-steps: S4-1, polymer deposition is performed, and due to the aspect ratio effect, the polymer selectively covers the surface of the SOI substrate and the top region of the sidewalls of the trench; S4-2, perform anisotropic plasma etching to selectively etch the bottom of the trench, the isolation dielectric layer; S4-3, Repeat steps S4-1 and S4-2 to remove the bottom of the isolation dielectric layer of the trench one by one until the silicon substrate is exposed; S4-4, Perform a cleaning step to remove residual polymer.

10. The method for preparing a semiconductor structure according to claim 7, characterized in that: In step S5, the doping concentration of the heavily doped polycrystalline silicon is at least 1e. 19 cm -3 The doping concentration of the heavily doped epitaxial single crystal silicon is at least 1e. 19 cm -3 .

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