Semiconductor chip and semiconductor package

Abstract

The invention relates to a semiconductor chip and a semiconductor package. The invention relates to a semiconductor chip including a through electrode and a semiconductor package including the same. A semiconductor chip according to an embodiment includes: a body portion having a front surface and a rear surface, the body portion being oriented in such a manner that the rear surface is above the front surface; a first through electrode and a second through electrode penetrating through the main body portion and having protrusions protruding above a rear surface of the main body portion; a wiring portion formed below a front surface of the body portion; a power pattern formed over a rear surface of the body portion and spaced apart from the protrusion; an interlayer insulating layer filling a space between the power supply pattern and the protrusion; and first and second rear connection electrodes formed over the interlayer insulating layer and connected to the first and second through electrodes, respectively, in which the first rear connection electrode is simultaneously connected to the first through electrode and a portion of the power supply pattern adjacent to the first through electrode.

Description

[0001] This application is a divisional application of the original patent application No. 202111049634.2 (filed on September 8, 2021, entitled "Semiconductor Chip with Through Electrode and Semiconductor Package with the Same"). Technical Field

[0002] This patent document relates to semiconductor technology, and more specifically, to a semiconductor chip including a through electrode and a semiconductor package including the semiconductor chip. Background Technology

[0003] Even as electronic products become smaller, they still require massive amounts of data processing. Therefore, the semiconductor chips used in these products also need to be thin and small. Furthermore, semiconductor packages that embed multiple semiconductor chips have been manufactured.

[0004] Multiple semiconductor chips can be stacked vertically and electrically connected to each other using through electrodes that pass through the semiconductor chips. Summary of the Invention

[0005] In one embodiment, a semiconductor chip may include: a body portion having a front surface and a rear surface, the body portion being oriented such that the rear surface is above the front surface; a first through electrode and a second through electrode penetrating the body portion and having a protrusion extending above the rear surface of the body portion; a power pattern formed above the rear surface of the body portion and spaced apart from the protrusion; an interlayer insulating layer filling the space between the power pattern and the protrusion; and a first rear connection electrode and a second rear connection electrode formed above the interlayer insulating layer and respectively connected to the first through electrode and the second through electrode, wherein the first rear connection electrode is simultaneously connected to both the first through electrode and a portion of the power pattern adjacent to the first through electrode.

[0006] In another embodiment, a semiconductor package may include: a first semiconductor chip including a body portion having a front surface and a rear surface; a first through electrode and a second through electrode penetrating the body portion and having protrusions extending above the rear surface of the body portion; a power pattern formed above the rear surface of the body portion and spaced apart from the protrusions; an interlayer insulating layer filling the space between the power pattern and the protrusions; a first rear connection electrode and a second rear connection electrode formed above the interlayer insulating layer and respectively connected to the first through electrode and the second through electrode; and a rear insulating layer formed above the interlayer insulating layer and the power pattern and filling the space between the first rear connection electrode and the second rear connection electrode, wherein the body portion is oriented with the rear surface above the front surface, and wherein the first rear connection electrode is simultaneously connected to the first through electrode and a portion of the power pattern adjacent to the first through electrode; and a second semiconductor chip including a plurality of front connection electrodes directly bonded to the first rear connection electrode and the second rear connection electrode, and a front insulating layer directly bonded to the rear insulating layer while filling the space between the plurality of front connection electrodes.

[0007] In another embodiment, a semiconductor chip may include: a body portion having a front surface and a rear surface, the body portion being oriented such that the rear surface is above the front surface; a first through electrode and a second through electrode penetrating the body portion; a power pattern formed above the rear surface of the body portion and spaced apart from the first through electrode and the second through electrode; a first connection pattern and a second connection pattern formed above the rear surface of the body portion and respectively connected to the first through electrode and the second through electrode; an interlayer insulating layer filling the space between the power pattern and the first connection pattern and the second connection pattern; and a first rear connection electrode and a second rear connection electrode formed above the interlayer insulating layer and respectively connected to the first connection pattern and the second connection pattern, wherein the first rear connection electrode is simultaneously connected to a portion of the first connection pattern and the power pattern adjacent to the first connection pattern.

[0008] In another embodiment, a semiconductor package may include: a first semiconductor chip including a body portion having a front surface and a rear surface, a first through electrode and a second through electrode penetrating the body portion, a power pattern formed above the rear surface of the body portion and spaced apart from the first through electrode and the second through electrode, a first connection pattern and a second connection pattern formed above the rear surface of the body portion and respectively connected to the first through electrode and the second through electrode, an interlayer insulating layer filling the space between the power pattern and the first connection pattern and the second connection pattern, a first rear connection electrode and a second rear connection electrode formed above the interlayer insulating layer and respectively connected to the first connection pattern and the second connection pattern, and a rear insulating layer formed above the interlayer insulating layer and the power pattern and filling the space between the first rear connection electrode and the second rear connection electrode, wherein the body portion is oriented such that the rear surface is above the front surface, wherein the first rear connection electrode is simultaneously connected to the first through electrode and a portion of the power pattern adjacent to the first through electrode; and a second semiconductor chip including a plurality of front connection electrodes respectively directly bonded to the first rear connection electrode and the second rear connection electrode, and a front insulating layer directly bonded to the rear insulating layer while filling the space between the plurality of front connection electrodes. Attached Figure Description

[0009] Figure 1A and Figure 1B This is a diagram illustrating a semiconductor chip according to an embodiment of the present disclosure.

[0010] Figure 2 This is a cross-sectional view illustrating a stacked semiconductor chip according to an embodiment of the present disclosure.

[0011] Figures 3A to 3F This is a cross-sectional view illustrating a method for manufacturing a semiconductor chip according to an embodiment of the present disclosure.

[0012] Figures 4A to 4D This is a cross-sectional view illustrating a method for manufacturing a semiconductor chip according to another embodiment of the present disclosure.

[0013] Figure 5A and Figure 5B This is a diagram illustrating a semiconductor chip according to another embodiment of the present disclosure.

[0014] Figures 6A to 6D This is a cross-sectional view illustrating a method for manufacturing a semiconductor chip according to another embodiment of the present disclosure.

[0015] Figures 7A to 7C This is a cross-sectional view illustrating a method for manufacturing a semiconductor chip according to another exemplary embodiment of the present disclosure.

[0016] Figure 8A block diagram illustrating an electronic system employing a memory card including a semiconductor package according to an embodiment is shown.

[0017] Figure 9 A block diagram illustrating another electronic system including a semiconductor package according to an embodiment is shown. Detailed Implementation

[0018] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0019] The accompanying drawings are not necessarily drawn to scale. In some cases, the scale of at least some structures in the drawings may have been exaggerated in order to clearly show specific features of the described embodiments. When a particular example of a multilayer structure with two or more layers is presented in the drawings or description, the relative positioning of these layers or the order of their arrangement reflects a specific implementation of the described or illustrated example, and different relative positioning or order of layer arrangement may be possible. Furthermore, the described or illustrated example of a multilayer structure may not reflect all the layers present in that particular multilayer structure (e.g., one or more additional layers may exist between two illustrated layers). As a specific example, when the first layer in a described or illustrated multilayer structure is referred to as "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be formed directly on the second layer or the substrate, but it may also indicate a structure in which one or more other intermediate layers may exist between the first layer and the second layer or the substrate.

[0020] In the following description of the implementation, when a parameter is referred to as “predetermined,” it may be intended to mean that the value of the parameter is predetermined when it is used in a process or algorithm. The value of the parameter may be set at the start of the process or algorithm, or it may be set during a period of time when the process or algorithm is executed.

[0021] Figure 1A and Figure 1B This is a diagram illustrating a semiconductor chip according to an embodiment of the present disclosure. Figure 1A This is a plan view of the semiconductor chip in this embodiment as seen from above. Figure 1B It is along Figure 1A A cross-sectional view taken by line A-A'. Figure 1A In the diagram, for ease of description, the through electrode and power supply pattern located below the rear connection electrode are shown together with the rear connection electrode located at the top of the semiconductor chip in dashed lines.

[0022] Reference Figure 1A and Figure 1BThe semiconductor chip 100 of this embodiment may include a main body portion 110, a wiring portion 120, a front connection electrode 130, a front insulating layer 140, a through electrode 150, a power pattern 160, an interlayer insulating layer 170, a rear connection electrode 180, and a rear insulating layer 190.

[0023] The main body portion 110 may be formed of a semiconductor material such as silicon or germanium, and may have a front surface 111, a rear surface 112, and side surfaces that connect them to each other. The front surface 111 of the main body portion 110 may refer to the active surface on which the wiring portion 120 is provided, and the rear surface 112 of the main body portion 110 may refer to the surface located on the opposite side of the front surface 111.

[0024] Wiring portion 120 may be formed below the front surface 111 of body portion 110. Wiring portion 120 may include circuit / wiring structures electrically connected to through electrode 150. For ease of description, the circuit / wiring structure in wiring portion 120 is simply shown as lines, but is not limited to the case shown. In this case, the circuit / wiring structure may be implemented differently depending on the type of semiconductor chip 100. For example, when semiconductor chip 100 includes volatile memory such as dynamic random access memory (DRAM) and static random access memory (SRAM) or non-volatile memory such as NAND flash memory, resistive random access memory (RRAM), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), and ferroelectric random access memory (FRAM), the circuit / wiring structure may include a memory cell array having multiple memory cells.

[0025] A front connection electrode 130 may be formed below the wiring portion 120. The front connection electrode 130 can be used to electrically connect the semiconductor chip 100 to another component (not shown), such as another semiconductor chip or substrate, that will face the front surface 111. The front connection electrode 130 may comprise a metal such as copper (Cu), nickel (Ni), tin (Sn), gold (Au), silver (Ag), or a combination thereof, or a compound of such metals, and may have a single-layer or multi-layer structure. Specifically, when the front connection electrode 130 is directly bonded to the rear connection electrode of another semiconductor chip (not shown) to form a hybrid bonding structure, the front connection electrode 130 may comprise a metallic material that can be bonded to the rear connection electrode via interdiffusion through a high-temperature annealing process.

[0026] The front connection electrode 130 can be electrically connected to the wiring portion 120. In addition, the front connection electrode 130 can be electrically connected to the through electrode 150 through the wiring portion 120.

[0027] A front insulating layer 140 may be formed beneath the wiring portion 120 to fill the space between the front connection electrodes 130. The front insulating layer 140 may comprise various insulating materials. Specifically, when the front insulating layer 140 is directly bonded to the rear insulating layer of another semiconductor chip (not shown) to form a hybrid bonding structure, the front insulating layer 140 may comprise an insulating material that can be covalently bonded to the rear insulating layer through inter-insulating materials. For example, the front insulating layer 140 may comprise silicon oxide or silicon nitride. One surface of the front connection electrode 130 not facing the wiring portion 120 and one surface of the front insulating layer 140 may be substantially coplanar.

[0028] The through-electrode 150 may have a pillar shape extending from the front surface 111 of the body portion 110 to the rear surface 112 and penetrating the body portion 110. Additionally, the through-electrode 150 may protrude above the rear surface 112 of the body portion 110 to further penetrate the interlayer insulating layer 170 formed above the rear surface 112 of the body portion 110. As an example, the through-electrode 150 may include a TSV (Through Silicon Via). The through-electrode 150 may include various conductive materials. As an example, the through-electrode 150 may include metals or compounds of copper (Cu), tin (Sn), silver (Ag), tungsten (W), nickel (Ni), ruthenium (Ru), cobalt (Co), or combinations thereof. One end of the through-electrode 150 may be connected to a portion of the circuit / wiring structure of the wiring portion 120, and the other end of the through-electrode 150 may be connected to a rear connection electrode 180. In the plan view, the width of each through-electrode 150 is indicated by the reference numeral W1.

[0029] The through electrode 150 may include a first through electrode 150A electrically connected to the power pattern 160 and a second through electrode 150B not electrically connected to the power pattern 160. Power (e.g., various levels of power supply voltage or ground voltage) may be supplied through the first through electrode 150A. In this case, the power applied to the first through electrode 150A may be the same as the power applied to the power pattern 160. Alternatively, various levels of power may be supplied through the second through electrode 150B, or various signals required to drive the semiconductor chip 100 may be transmitted through the second through electrode 150B. In this case, the power applied to the second through electrode 150B may be different from the power applied to the first through electrode 150A and the power pattern 160. For example, the potential value applied to the second through electrode 150B may be different from the potential value applied to the first through electrode 150A and the power pattern 160.

[0030] A power pattern 160 may be formed above the rear surface 112 of the body portion 110, spaced horizontally from the through electrode 150. The power pattern 160 may be electrically connected to the first through electrode 150A via a first rear connection electrode 180A and may be electrically insulated from the second through electrode 150B. The power pattern 160 may comprise various conductive materials. As an example, the power pattern 160 may comprise metals such as copper (Cu), nickel (Ni), tin (Sn), gold (Au), silver (Ag), or combinations thereof, or compounds of such metals.

[0031] In this embodiment, in a planar view, the power pattern 160 may include a plurality of line patterns 160A arranged along one direction and an extension pattern 160B connecting the ends of the plurality of line patterns 160A to each other. An interlayer insulating layer 170 may fill the space between the plurality of line patterns 160A. That is, the plurality of line patterns 160A may be arranged alternately with the interlayer insulating layer 170. In this case, compared to the case of forming a power pattern with a flat plate shape, the area of ​​forming the interlayer insulating layer 170 can be increased, so that the adhesion properties between the layer forming the power pattern 160 and the layers formed thereon (e.g., the layer forming the post-connection electrode 180 and the post-insulating layer 190) can be improved. However, this disclosure is not limited thereto, and assuming that it is spaced apart from the through electrode 150, the power pattern 160 may have various planar shapes.

[0032] Through the power pattern 160A, two or more first through electrodes 150A can be electrically connected to each other to form a power distribution network (PDN), thus a stable power supply can be provided through the first through electrodes 150A.

[0033] An interlayer insulating layer 170 may be formed over the rear surface 112 of the body portion 110 to fill the space between the through electrode 150 and the power pattern 160. The interlayer insulating layer 170 may comprise various insulating materials such as silicon oxide, silicon nitride, or combinations thereof. Furthermore, the interlayer insulating layer 170 may have a single-layer or multi-layer structure. One surface of the through electrode 150 not facing the rear surface 112 of the body portion 110, one surface of the power pattern 160, and one surface of the interlayer insulating layer 170 may form substantially flat surfaces.

[0034] The rear connection electrode 180 may be formed above a flat surface formed based on a surface of the through electrode 150, a surface of the power pattern 160, and a surface of the interlayer insulating layer 170. The rear connection electrode 180 may be used to electrically connect the semiconductor chip 100 to another component (not shown), such as another semiconductor chip, that will face the rear surface 112. The rear connection electrode 180 may comprise a metal or compound of the metal, such as copper (Cu), nickel (Ni), tin (Sn), gold (Au), silver (Ag), or combinations thereof, and may have a single-layer or multi-layer structure. The rear connection electrode 180 may be formed of the same material as the front connection electrode 130. Specifically, when the rear connection electrode 180 is directly bonded to the front connection electrode of another semiconductor chip (not shown) to form a hybrid bonding structure, the rear connection electrode 180 may comprise a metallic material that can be bonded to the front connection electrode via interdiffusion through a high-temperature annealing process. In the plan view, the width of each rear connection electrode 180 is indicated by reference numeral W2.

[0035] The rear connection electrode 180 may include a first rear connection electrode 180A connected to the first through electrode 150A, a second rear connection electrode 180B connected to the second through electrode 150B, and a third rear connection electrode 180C not connected to the through electrode 150.

[0036] The first post-connection electrode 180A can be formed to overlap and connect with each of the first through electrodes 150A. The first post-connection electrode 180A can correspond one-to-one with the first through electrodes 150A. Furthermore, the first post-connection electrode 180A can simultaneously overlap and connect with the portion of the power supply pattern 160 adjacent to the first through electrode 150A (see P1). For this purpose, the width W2 of the first post-connection electrode 180A can be greater than the sum of the width W1 of the first through electrode 150A and the minimum distance D1 between the first through electrode 150A and the adjacent power supply pattern 160. As a result, the first post-connection electrode 180A can electrically connect the first through electrode 150A to the power supply pattern 160, and the power applied to the first through electrode 150A and the power supply pattern 160 can be supplied to the first post-connection electrode 180A.

[0037] The second post-connection electrode 180B may be formed to overlap and connect with each of the second through electrodes 150B. The second post-connection electrode 180B may correspond one-to-one with the second through electrodes 150B. The second post-connection electrode 180B may not overlap / connect with the power pattern 160 surrounding the second through electrodes 150B. Therefore, the power pattern 160 may be arranged such that the minimum distance D2 between the second through electrode 150B and its adjacent power pattern 160 is greater than the minimum distance D1 between the first through electrode 150A and its adjacent power pattern 160. That is, the width W2 of the second post-connection electrode 180B may be less than the sum of the width W1 of the second through electrode 150B and the minimum distance D2 between the second through electrode 150B and its adjacent power pattern 160. Power or signals applied to the second through electrode 150B may be supplied or transmitted to the second post-connection electrode 180B.

[0038] The third rear connection electrode 180C may be spaced apart from the first rear connection electrode 180A and the second rear connection electrode 180B, without overlapping or connecting to the through electrode 150. The third rear connection electrode 180C may be a dummy not used for signal transmission or power supply. In this embodiment, the third rear connection electrode 180C may be applied with the same power supply as the power pattern 160 by overlapping and connecting with it. However, if the third rear connection electrode 180C is in a floating state and not electrically connected to any wiring other than the power pattern 160, the third rear connection electrode 180C may not perform the function of signal transmission or power supply. Furthermore, as described later, even if the third rear connection electrode 180C is connected to the front connection electrode of another semiconductor chip (see...), Figure 2 In the case of the third rear connection electrode 180C being in a floating state where it is not electrically connected to any wiring other than the power pattern 160, the third rear connection electrode 180C may also not perform the functions of signal transmission or power supply. In another embodiment, unlike the example, the third rear connection electrode 180C may not overlap / connect with the power pattern 160. That is, the third rear connection electrode 180C may be formed in an area where the power pattern 160 does not exist, and therefore may have an electrically floating state. The third rear connection electrode 180C can perform various functions. As an example, the third rear connection electrode 180C can serve to facilitate the process, for example, as a stop layer during the planarization process when multiple semiconductor chips 100 are stacked. As another example, the third rear connection electrode 180C can serve to improve the heat dissipation characteristics in a semiconductor package having multiple semiconductor chips 100. The third rear connection electrode 180C may be omitted.

[0039] The front connecting electrode 130 and the rear connecting electrode 180 can have the same arrangement. That is, in a plan view, multiple front connecting electrodes 130 and multiple rear connecting electrodes 180 can overlap each other.

[0040] A rear insulating layer 190 may be formed above a flat surface formed based on one surface of the through electrode 150, one surface of the power pattern 160, and one surface of the interlayer insulating layer 170 to fill the space between the rear connection electrodes 180. The rear insulating layer 190 may include various insulating materials. The rear insulating layer 190 may be formed of the same material as the front insulating layer 140. Specifically, when the rear insulating layer 190 is directly bonded to the front insulating layer of another semiconductor chip (not shown) to form a hybrid bonding structure, the rear insulating layer 190 may include an insulating material that can be bonded to the front insulating layer through covalent bonding between insulating materials. For example, the rear insulating layer 190 may include silicon oxide or silicon nitride. One surface of the rear connection electrode 180 that does not face the aforementioned flat surface and one surface of the rear insulating layer 190 may be substantially coplanar.

[0041] According to the aforementioned semiconductor chip 100, the first rear connection electrode 180A can be simultaneously connected to the corresponding first through electrode 150A and the adjacent power pattern 160. Furthermore, the first rear connection electrode 180A can directly contact the corresponding first through electrode 150A and the adjacent power pattern 160. Therefore, since two or more first through electrodes 150A form a PDN through the first rear connection electrode 180A and the power pattern 160, power can be supplied easily and stably. Specifically, when multiple semiconductor chips 100 are stacked vertically, power supply through multiple semiconductor chips 100 can be performed more efficiently.

[0042] Additionally, when multiple semiconductor chips 100 are stacked vertically, a hybrid bonding structure can be provided that firmly bonds adjacent semiconductor chips 100 in the vertical direction. This will be referred to below. Figure 2 To describe in more detail.

[0043] Figure 2 This is a cross-sectional view illustrating a stacked semiconductor chip according to an embodiment of the present disclosure. Figure 2 This shows two semiconductor chips stacked vertically.

[0044] Reference Figure 2 The first semiconductor chip 100 can be connected with the above-mentioned Figure 1A and Figure 1B The semiconductor chip 100 is essentially the same. Therefore, it uses the same... Figure 1A and Figure 1B The same label as the label.

[0045] The second semiconductor chip 200 can also be connected to the above-mentioned Figure 1A and Figure 1B The second semiconductor chip 200 is substantially the same as the first semiconductor chip 100. Specifically, the second semiconductor chip 200 may include: a body portion 210 having a front surface 211 and a rear surface 212, wherein in this embodiment the body portion is oriented such that the rear surface 212 is above the front surface 211; a wiring portion 220 disposed above the front surface 211 of the body portion 210; a front connecting electrode 230 disposed above the wiring portion 220 and electrically connected to the through electrode 250 via the wiring portion 220; and a front insulating layer 240 disposed above the wiring portion 220 and filling the space between the front connecting electrodes 230. A through electrode 250 penetrates the main body portion 210 and protrudes above the rear surface 212 of the main body portion 210; a power pattern 260 is disposed above the rear surface 212 of the main body portion 210; an interlayer insulating layer 270 is disposed above the rear surface 212 of the main body portion 210 and fills the space between the through electrode 250 and the power pattern 260; a rear connecting electrode 280 is disposed above the interlayer insulating layer 270; and a rear insulating layer 290 is disposed above the interlayer insulating layer 270 and fills the space between the rear connecting electrodes 280. The through electrode 250 may include a first through electrode 250A electrically connected to the power pattern 260 and a second through electrode 250B not electrically connected to the power pattern 260. The rear connection electrode 280 may include a first rear connection electrode 280A that is simultaneously connected to the first through electrode 250A and the power pattern 260, a second rear connection electrode 280B that is connected to the second through electrode 250B but not connected to the power pattern 260, and a third rear connection electrode 280C that is not connected to the through electrode 250.

[0046] The second semiconductor chip 200 may be stacked on top of the first semiconductor chip 100, with the front surface 211 of the second semiconductor chip 200 facing the rear surface 112 of the first semiconductor chip 100. In this case, the rear connection electrode 180 of the first semiconductor chip 100 may be directly bonded to the front connection electrode 230 of the second semiconductor chip 200, and the rear insulating layer 190 of the first semiconductor chip 100 may be directly bonded to the front insulating layer 240 of the second semiconductor chip 200. This can be achieved by performing a high-temperature annealing process while the rear connection electrode 180 and the rear insulating layer 190 of the first semiconductor chip 100 are in contact with the front connection electrode 230 and the front insulating layer 240 of the second semiconductor chip 200, respectively. During the high-temperature annealing process, the metals used to form the rear connection electrode 180 of the first semiconductor chip 100 and the front connection electrode 230 of the second semiconductor chip 200 may bond to each other through interdiffusion of the metals (e.g., interdiffusion of copper). At this time, the insulating materials used to form the rear insulating layer 190 of the first semiconductor chip 100 and the front insulating layer 240 of the second semiconductor chip 200 can be bonded to each other through covalent bonding of the insulating materials (e.g., covalent bonding formed between silicon oxide and silicon nitride). Therefore, a hybrid bonding between the first semiconductor chip 100 and the second semiconductor chip 200 can be performed. That is, metal-to-metal bonding and insulating layer-to-insulating layer bonding can be performed in situ.

[0047] Each of the first to third rear connection electrodes 180A, 180B, and 180C of the first semiconductor chip 100 can be coupled to a corresponding front connection electrode 230 of the second semiconductor chip 200. In this case, the arrangement of the first to third rear connection electrodes 180A, 180B, and 180C can be substantially the same as the arrangement of the front connection electrode 230. In a plan view, each of the first to third rear connection electrodes 180A, 180B, and 180C can overlap with a corresponding front connection electrode 230. The third rear connection electrode 180C of the first semiconductor chip 100 can be omitted. In this case, the front connection electrode 230 of the second semiconductor chip 200 corresponding to the third rear connection electrode 180C can also be omitted. According to one embodiment, power is supplied to the first semiconductor chip 100 and the second semiconductor chip 200 through a first through electrode 150A, a power pattern 160, a first rear connection electrode 180A, and a front connection electrode 230 connected to the first rear connection electrode 180A. Signals are also transmitted to the first semiconductor chip 100 and the second semiconductor chip 200 through a second through electrode 150B, a second rear connection electrode 180B, and a front connection electrode 230 connected to the second rear connection electrode 180B. According to another embodiment, the power supplied to the first semiconductor chip 100 and the second semiconductor chip 200 through the first through electrode 150A, power pattern 160, first rear connection electrode 180A, and front connection electrode 230 connected to the first rear connection electrode 180A is different from the power supplied to the first semiconductor chip 100 and the second semiconductor chip 200 through the second through electrode 150B, second rear connection electrode 180B, and front connection electrode 230 connected to the second rear connection electrode 180B.

[0048] According to the above embodiment, a robust bond between the first semiconductor chip 100 and the second semiconductor chip 200 can be achieved by forming a hybrid bonding structure. Furthermore, since the electrical connection between the first semiconductor chip 100 and the second semiconductor chip 200 is achieved without connecting bumps, the power supply path or signal transmission path between them can be shortened. As a result, power supply delay or signal transmission delay can be reduced, thereby improving the operating characteristics of the first semiconductor chip 100 and the second semiconductor chip 200. Additionally, since the space between the first semiconductor chip 100 and the second semiconductor chip 200 for arranging bumps is not required, the reduction in heat transfer efficiency caused by filling the space with insulating material can be minimized.

[0049] Furthermore, by not setting the power patterns 160 and 260 on the surface, the impact on the interfacial bonding strength of the hybrid bonding structure can be minimized. The interfacial bonding strength of the hybrid bonding structure can be defined as the sum of the covalent bonding strength between insulating layers and the intermetallic bonding strength between metals. Since covalent bonding strength is stronger than intermetallic bonding strength, the total interfacial bonding strength can also be reduced when the area occupied by the insulating layer at the bonding interface is reduced. If the power pattern is formed at the same height as the rear connecting electrode (i.e., in the rear insulating layer), the contact area between the rear insulating layer of the lower semiconductor chip and the front insulating layer of the upper semiconductor chip can be reduced, thus reducing the interfacial bonding strength between them.

[0050] Figures 3A to 3F This is a cross-sectional view illustrating a method for manufacturing a semiconductor chip according to an embodiment of the present disclosure.

[0051] Reference Figure 3A A structure can be formed above a carrier substrate (not shown), the structure having: an initial body portion 310 having a front surface 311 and an initial rear surface 312 therein, wherein an initial through electrode 350 is formed; a wiring portion 320 formed below the front surface 311 of the initial body portion 310; and a front connecting electrode 330 and a front insulating layer 340 formed below the wiring portion 320. The initial through electrode 350 may include an initial conductive post 352 and initial spacers 354 surrounding the side and top surfaces of the initial conductive post 352. The method of forming this structure will be described in more detail below.

[0052] First, an initial body portion 310 with a front surface 311 and an initial rear surface 312 can be provided. The distance between the initial rear surface 312 and the front surface 311 is comparable. Figure 1B The rear surface 112 is large, therefore, the initial main body portion 310 can have a larger size than the rear surface 112. Figure 1B The main body has a thickness of 110.

[0053] Subsequently, the initial body portion 310 may be etched to form a hole 313 in the initial body portion 310. The hole 313 may be formed from the front surface 311 of the initial body portion 310 toward the initial rear surface 312 at a predetermined depth. The depth of the hole 313 may be less than the thickness of the initial body portion 310.

[0054] Subsequently, an initial spacer 354 can be formed along the inner wall of the hole 313, and the hole 313 with the initial spacer 354 can be filled with a conductive material to form an initial conductive post 352. Thus, an initial through electrode 350 can be formed. The initial conductive post 352 may include a metal or a metal compound, and the initial spacer 354 may include silicon oxide, silicon nitride, metal nitride, etc.

[0055] Subsequently, a wiring portion 320 can be formed below the front surface 311 of the initial main body portion 310 where the initial through electrode 350 is formed, and a front connecting electrode 330 and a front insulating layer 340 can be formed below the wiring portion 320. Therefore, a [comprehensive solution / process] can be obtained. Figure 3A The structure.

[0056] Reference Figure 3B A portion of the initial body portion 310 can be removed to form a body portion 310A that is thinner than the initial body portion 310. That is, a thinning process can be performed.

[0057] A thinning process can be performed on the initial rear surface 312 of the initial body portion 310. Therefore, the body portion 310A may have a front surface 311 and a rear surface 312A. The distance between the front surface 311 and the rear surface 312A of the body portion 310A may be smaller than the distance between the front surface 311 and the initial rear surface 312. The thinning process can be performed by grinding, chemical mechanical polishing (CMP), and / or etching back. Furthermore, a thinning process can be performed such that a portion of the initial through electrode 350 protrudes from the rear surface 312A of the body portion 310A. The portion of the initial through electrode 350 protruding from the rear surface 312A of the body portion 310A will be referred to as the protrusion of the initial through electrode 350 (see P2).

[0058] Reference Figure 3C An initial first interlayer insulating layer 372 may be formed over the rear surface 312A of the main body portion 310A and the protrusion of the initial through electrode 350. The initial first interlayer insulating layer 372 may be conformally formed along its lower contour. As an example, the initial first interlayer insulating layer 372 may include silicon nitride.

[0059] Subsequently, a stacked structure of initial second interlayer insulating layer 374 and initial third interlayer insulating layer 376 can be formed over the initial first interlayer insulating layer 372 along its lower contour. This stacked structure may have an opening OP, which provides space for forming a power supply pattern. The stacked structure can be formed by depositing insulating material layers for forming the initial second interlayer insulating layer 374 and initial third interlayer insulating layer 376 over the initial first interlayer insulating layer 372 along its lower contour and removing the insulating material layers in the regions corresponding to the opening OP by a masking and etching process. During this masking and etching process, the initial first interlayer insulating layer 372 can be used as an etch stop layer. As an example, the initial second interlayer insulating layer 374 and initial third interlayer insulating layer 376 may comprise silicon oxide and silicon nitride, respectively.

[0060] Reference Figure 3D , can be along its lower contour Figure 3CAn initial metal-containing thin film layer 362 is formed over the resulting structure. The initial metal-containing thin film layer 362 may include a metal or a metal compound and may have a single-layer or multi-layer structure. The initial metal-containing thin film layer 362 may be formed by deposition or the like and may be formed to a thin thickness with incomplete filling of the opening OP. The initial metal-containing thin film layer 362 may serve to improve the properties and / or formation process of the metal-containing layer 364, which will be described later.

[0061] Subsequently, an initial metal-containing layer 364 may be formed over the initial metal-containing thin film layer 362. The initial metal-containing layer 364 may include a metal or a metal compound and may have a single-layer structure or a multi-layer structure. The initial metal-containing layer 364 may be formed by deposition, electroplating, etc., and may be formed to have a thickness that sufficiently fills the opening OP on which the initial metal-containing thin film layer 362 is formed.

[0062] Reference Figure 3E , can be Figure 3D The resulting structure undergoes a planarization process. The planarization process can be performed by methods such as chemical mechanical polishing. Additionally, a planarization process can be performed such that, apart from the initial third interlayer insulating layer 376 present above the initial through electrode 350, the upper surface of the initial third interlayer insulating layer 376 (see [reference]) is planarized. Figure 3D The arrow ① in the image is exposed.

[0063] As a result of this process, a metal thin film layer 362A, a metal layer 364A, a first interlayer insulating layer 372A, a second interlayer insulating layer 374A, a third interlayer insulating layer 376A, and a through electrode 350A having a conductive pillar 352A and a spacer 354A can be formed. The metal thin film layer 362A, the metal layer 364A, the first interlayer insulating layer 372A, the second interlayer insulating layer 374A, the third interlayer insulating layer 376A, and the through electrode 350A can form a flat surface. The shape and function of the metal thin film layer 362A, the metal layer 364A, the first interlayer insulating layer 372A, the second interlayer insulating layer 374A, the third interlayer insulating layer 376A, and the through electrode 350A will be described in more detail below.

[0064] The through electrode 350A having conductive pillar 352A and spacer 354A can substantially correspond to Figure 1B The through electrode 150. The conductive post 352A can be used as a path for signal transmission / power supply. The spacer 354A can surround the sidewall of the conductive post 352A to electrically insulate the body portion 310A and the conductive post 352A and / or prevent metal diffusion from the conductive post 352A to the body portion 310A.

[0065] Metal thin film layer 362A and metal layer 364A can correspond to Figure 1BThe power supply pattern 160. Therefore, the metal thin film layer 362A and the metal layer 364A will be referred to as power supply pattern 360. The metal thin film layer 362A may be along the above-mentioned opening (see... Figure 3C The side and bottom surfaces of the OP (intermediate layer 364A) are formed, and a metal-containing layer 364A can be provided to fill the opening where the metal-containing thin film layer 362A is formed. Therefore, the side and bottom surfaces of the metal-containing layer 364A can be surrounded by the metal-containing thin film layer 362A. As described above, the metal-containing thin film layer 362A can be used to improve the properties and / or formation process of the metal-containing layer 364A. As an example, although not shown, the metal-containing thin film layer 362A can have a multilayer structure having a barrier layer and a seed layer disposed above the barrier layer. The barrier layer can include a metal or metal compound such as titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), nickel vanadium (NiV), etc., and the seed layer can include a metal such as copper (Cu). In this case, the barrier layer can prevent metal diffusion between the power patterns 360 that can occur through the second interlayer insulating layer 374A, and the seed layer can be used as a seed during electroplating for forming the metal-containing layer 364A.

[0066] The second interlayer insulation layer 374A and the third interlayer insulation layer 376A can essentially correspond to Figure 1B Interlayer insulation layer 170. First interlayer insulation layer 372A is not shown. Figure 1B In, but can be added Figure 1B The semiconductor chip. A first interlayer insulating layer 372A is formed along the rear surface 312A of the main body portion 310A and the side surface of the protrusion of the through electrode 350A. The first interlayer insulating layer 372A serves to prevent metal diffusion between the protrusions of the through electrode 350A or to prevent contamination by external metals. A second interlayer insulating layer 374A and a third interlayer insulating layer 376A are used to insulate the power pattern 360 from each other and to provide space for the power pattern 360 to be formed. In addition, the third interlayer insulating layer 376A serves to prevent metal diffusion between the power patterns 360 that can occur through the second interlayer insulating layer 374A.

[0067] Reference Figure 3F , can Figure 3E A rear insulating layer 390 is formed above the resulting structure, and the rear insulating layer 390 has an opening 392 providing space for the formation of the rear connection electrode. Although not shown, it can be achieved by... Figure 3E An insulating material layer is deposited over the resulting structure, and the insulating material layer in the area where the back connection electrode is to be formed is removed by a masking and etching process to form a back insulating layer 390. The back insulating layer 390 may include an insulating material such as silicon oxide.

[0068] Subsequently, a rear connection electrode 380 filling the opening 392 can be formed. The rear connection electrode 380 may include a metal-containing thin film layer 382 formed along the side and lower surfaces of the opening 392 and a metal-containing layer 384 filling the opening 392 where the metal-containing thin film layer 382 is formed. Although not shown, the rear connection electrode 380 may be formed by the following steps: depositing a thin metal material layer for forming the metal-containing thin film layer 382 along the upper surface of the rear insulating layer 390 and the side and lower surfaces of the opening 392; depositing another metal material layer with a thickness sufficient to fill the opening 392 over the thin metal material layer by deposition or electroplating; and performing a planarization process until the upper surface of the rear insulating layer 390 is exposed.

[0069] Therefore, it can be manufactured with Figure 1B The semiconductor chip 100 is basically the same as the semiconductor chip.

[0070] In addition, Figures 3A to 3F In one embodiment, the power pattern 360 and the rear connection electrode 380 can be formed entirely by patterning an insulating layer to form the space where the power pattern 360 and the rear connection electrode 380 are to be formed, and then filling the space with the conductive material used to form the power pattern 360 and the rear connection electrode 380. However, this disclosure is not limited thereto; a method can be used to form the power pattern and / or the rear connection electrode by patterning a conductive layer and then filling the space between the patterned conductive layers with an insulating material. This will be referred to below. Figures 4A to 4D Described exemplarily.

[0071] Figures 4A to 4D This is a cross-sectional view illustrating a method for manufacturing a semiconductor chip according to another embodiment of the present disclosure. The focus will be on... Figure 3A and Figure 3B The differences are described accordingly.

[0072] Reference Figure 4A A structure may be formed above a carrier substrate (not shown), the structure comprising: a main body portion 410 having a front surface 411 and a rear surface 412; an initial through electrode 450 penetrating the main body portion 410 and protruding above the rear surface 412 of the main body portion 410; a wiring portion 420 formed below the front surface 411 of the main body portion 410; and a front connecting electrode 430 and a front insulating layer 440 formed below the wiring portion 420. The initial through electrode 450 may include an initial conductive post 452 and initial spacers 454 surrounding the side and top surfaces of the initial conductive post 452.

[0073] Subsequently, a power pattern 460, consisting of a metal thin film layer 462 and a metal layer 464 stacked together, can be formed over the rear surface 412 of the main body portion 410. Although not shown, the power pattern 460 can be formed by depositing a material layer for forming the metal thin film layer 462 and the metal layer 464 over the rear surface 412 of the main body portion 410, and patterning the material layer using a mask and etching process. Alternatively, although not shown, the power pattern 460 can be formed by the following steps: depositing a material layer for forming the metal thin film layer 462 over the rear surface 412 of the main body portion 410, forming a photoresist pattern to provide space for forming the metal layer 464, forming the metal layer 464 in the space provided by the photoresist pattern by electroplating, removing the photoresist pattern, and removing the material layer exposed through the metal layer 464. In this case, the power pattern is similar to that of the embodiment described above (see...). Figure 3E Unlike 360 ​​in the previous example, the metal thin film layer 462 can only contact the lower surface of the metal layer 464.

[0074] Reference Figure 4B An initial first interlayer insulating layer 472 may be formed along its lower contour over the power supply pattern 460, the rear surface 412 of the main body portion 410, and the protrusion of the initial through electrode 450. As an example, the initial first interlayer insulating layer 472 may include silicon nitride.

[0075] Subsequently, an initial second interlayer insulating layer 474 may be formed over the initial first interlayer insulating layer 472 to a thickness sufficient to cover the protrusions of the power supply pattern 460 and the initial through electrode 450. As an example, the initial second interlayer insulating layer 474 may comprise silicon oxide.

[0076] Reference Figure 4C , can be Figure 4B The resulting structure undergoes a planarization process. This planarization process can be performed until the upper surface of the power pattern 460 is exposed.

[0077] As a result, a first interlayer insulating layer 472A and a second interlayer insulating layer 474A can be formed to fill the space between the power supply patterns 460, as well as a through electrode 450A having a conductive pillar 452A and a spacer 454A. The first interlayer insulating layer 472A can be formed along the rear surface 412 of the main body portion 410, the side surface of the power supply pattern 460, and the side surface of the protrusion of the through electrode 450A. The first interlayer insulating layer 472A can prevent metal diffusion between the protrusion of the through electrode 450A and the power supply pattern 460.

[0078] Reference Figure 4D , can Figure 4CA rear connection electrode 480 is formed on the resulting structure. The rear connection electrode 480 may include a stacked structure containing a metal thin film layer 482 and a metal layer 484. Although not shown, the rear connection electrode 480 can be formed by... Figure 4C A material layer for forming a metal thin film layer 482 and a metal layer 484 is deposited over the resulting structure, and the material layer is patterned by a masking and etching process. Alternatively, although not shown, the subsequent electrode 480 can be formed by the following steps: Figure 4C A material layer for forming a metal-containing thin film layer 482 is deposited over the resulting structure, a photoresist pattern is formed to provide space for the formation of the metal-containing layer 484, the metal-containing layer 484 is formed in the space provided by the photoresist pattern by electroplating, the photoresist pattern is removed, and the material layer exposed through the metal-containing layer 484 is removed. In this case, the rear connection electrode of the above embodiment (see...) Figure 3F Unlike 380 in the previous example, the metal thin film layer 482 can only contact the lower surface of the metal layer 484.

[0079] Subsequently, a rear insulating layer 490 can be formed to fill the space between the rear connection electrodes 480. Although not shown, the rear insulating layer 490 can be formed by... Figure 4C The resulting structure is deposited with a thickness sufficient to cover the insulating material layer of the rear connection electrode 480, and a planarization process is performed until the upper surface of the rear connection electrode 480 is exposed to form the structure.

[0080] Therefore, it can be manufactured with Figure 1B The semiconductor chip 100 is basically the same as the semiconductor chip.

[0081] Figure 5A and Figure 5B This is a diagram illustrating a semiconductor chip according to another embodiment of the present disclosure. Figure 5A This is a plan view of the semiconductor chip in this embodiment as seen from above. Figure 5B It is along Figure 5A A cross-sectional view taken by line B-B'. Figure 5A In the diagram, for ease of description, the through electrode, connection pattern, and power supply pattern located below the rear connection electrode are shown together with the rear connection electrode located at the top of the semiconductor chip in dashed lines. The focus will be on the connection to the aforementioned... Figure 1A and Figure 1B The different implementation methods will be described.

[0082] Reference Figure 5A and Figure 5BThe semiconductor chip 500 of this embodiment may include a main body portion 510, a wiring portion 520, a front connection electrode 530, a front insulating layer 540, a through electrode 550, a power pattern 560, a connection pattern 565, an interlayer insulating layer 570, a rear connection electrode 580, and a rear insulating layer 590.

[0083] The main body portion 510 may have a front surface 511 and a rear surface 512. A wiring portion 520 may be formed below the front surface 511 of the main body portion 510. A front connecting electrode 530 and a front insulating layer 540 may be formed below the wiring portion 520.

[0084] The through electrode 550 may have a cylindrical shape extending from the front surface 511 to the rear surface 512 of the body portion 510 to penetrate the body portion 510. One end of the through electrode 550 may be connected to the wiring portion 520, and the other end of the through electrode 550 may be connected to the connection pattern 565. In the plan view, the width of each through electrode 550 is indicated by the reference numeral W1. The through electrode 550 may include a first through electrode 550A electrically connected to the power pattern 560 and a second through electrode 550B not electrically connected to the power pattern 560.

[0085] A power pattern 560 may be formed above the rear surface 512 of the main body portion 510 to be horizontally spaced from the through electrode 550. The power pattern 560 may be electrically connected to the first through electrode 550A via the first rear connection electrode 580A and may be electrically insulated from the second through electrode 550B.

[0086] The connection pattern 565 may be formed vertically at the same height as the power supply pattern 560. That is, the connection pattern 565 may be formed above the rear surface 512 of the main body portion 510. The connection pattern 565 may be formed to overlap with and connect to each of the through electrodes 550. The connection pattern 565 and the through electrodes 550 may correspond one-to-one with each other. The connection pattern 565 may include a first connection pattern 565A connected to the first through electrode 550A and a second connection pattern 565B connected to the second through electrode 550B.

[0087] The width W3 of the connecting pattern 565 may be greater than the width W1 of the through electrode 550 and less than the width W2 of the subsequent connecting electrode 580. In this embodiment, the first connecting pattern 565A may be spaced apart from the adjacent power pattern 560 by a predetermined minimum distance D3, but this disclosure is not limited thereto; the side surface of the first connecting pattern 565A and the side surface of the adjacent power pattern 560 may be in contact with each other. On the other hand, the second connecting pattern 565B may be spaced apart from the adjacent power pattern 560. That is, the side surface of the second connecting pattern 565B and the side surface of the adjacent power pattern 560 may not be in contact. The connecting pattern 565 may be formed of the same metal or metal compound as the power pattern 560.

[0088] An interlayer insulating layer 570 may be formed above the rear surface 512 of the main body portion 510 to fill the space between the power supply pattern 560 and the connection pattern 565.

[0089] The rear connection electrode 580 may include a first rear connection electrode 580A connected to a first connection pattern 565A, a second rear connection electrode 580B connected to a second connection pattern 565B, and a third rear connection electrode 580C not connected to the connection pattern 565.

[0090] The first rear connection electrode 580A can be formed to overlap and connect with each of the first connection patterns 565A. Therefore, the first through electrode 550A can be electrically connected to the first rear connection electrode 580A through the first connection pattern 565A. Furthermore, the first rear connection electrode 580A can simultaneously overlap and connect with both the first connection pattern 565A and a portion of the adjacent power supply pattern 560. For this purpose, the width W2 of the first rear connection electrode 580A can be greater than the sum of the width W3 of the first connection pattern 565A and the minimum distance D3 between the first connection pattern 565A and the adjacent power supply pattern 560. As a result, the first rear connection electrode 580A can electrically connect the first connection pattern 565A to the power supply pattern 560.

[0091] The second rear connection electrode 580B may be formed to overlap and connect with each of the second connection patterns 565B. Therefore, the second through electrode 550B can be electrically connected to the second rear connection electrode 580B through the second connection pattern 565B. The second rear connection electrode 580B can be electrically insulated from the power supply pattern 560 by not overlapping / connecting with the power supply pattern 560 surrounding the second connection pattern 565B.

[0092] The third rear connection electrode 580C may be formed to be spaced apart from the first rear connection electrode 580A and the second rear connection electrode 580B, without overlapping or connecting with the connection pattern 565. That is, the third rear connection electrode 580C may be a dummy that is not used for signal transmission or power supply.

[0093] The rear insulating layer 590 may be formed above a flat surface formed based on a surface of the connection pattern 565, a surface of the power pattern 560 and a surface of the interlayer insulating layer 570 to fill the space between the rear connection electrodes 580.

[0094] Even using the semiconductor chip 500 described above, the semiconductor chip of the above embodiment can be obtained (see...). Figure 1A and Figure 1B The effect of (100) is that, since the first rear connection electrode 580A is simultaneously connected to the corresponding first connection pattern 565A and the adjacent power supply pattern 560, the power supply through these elements can be easily and stably executed.

[0095] Furthermore, when multiple semiconductor chips 500 are stacked in the vertical direction, a hybrid bonding structure can be provided for firmly bonding adjacent semiconductor chips 500 in the vertical direction. That is, since the power supply pattern 560 and the connection pattern 565 are disposed below the rear connection electrode 580, the power supply pattern 560 and the connection pattern 565 will not adversely affect the bonding when the rear connection electrode 580 and the rear insulating layer 590 are respectively bonded to the front connection electrode and the front insulating layer of another semiconductor chip (not shown).

[0096] Figures 6A to 6D This is a cross-sectional view illustrating a method for manufacturing a semiconductor chip according to another embodiment of the present disclosure.

[0097] Reference Figure 6A A structure may be formed above a carrier substrate (not shown), the structure having: a main body portion 610 having a front surface 611 and a rear surface 612; a wiring portion 620 formed below the front surface 611 of the main body portion 610; a front connecting electrode 630 and a front insulating layer 640 formed below the wiring portion 620; and an initial through electrode 650 penetrating the main body portion 610 and protruding above the rear surface 612 of the main body portion 610 while connecting to the wiring portion 620. The initial through electrode 650 may include an initial conductive post 652 and an initial spacer 654.

[0098] Subsequently, an initial first interlayer insulating layer 672 may be formed along its lower contour over the rear surface 612 of the body portion 610 and the protrusion of the initial through electrode 650. As an example, the initial first interlayer insulating layer 672 may include silicon nitride.

[0099] Reference Figure 6B By performing a planarization process to expose the upper surface of the initial first interlayer insulating layer 672 above the rear surface 612 of the initial body portion 610, a through electrode 650A having a conductive pillar 652A and a spacer 654A and a first interlayer insulating layer 672A can be formed.

[0100] As a result of this process, the through electrode 650A may have a pillar shape that penetrates the main body portion 610 and the first interlayer insulating layer 672A. The upper surface of the first interlayer insulating layer 672A and one surface of the through electrode 650A may form a flat surface.

[0101] Subsequently, a stacked structure of a second interlayer insulating layer 674 and a third interlayer insulating layer 676 can be formed over the first interlayer insulating layer 672A, having an opening OP providing space for forming power supply patterns and connection patterns. As an example, the second interlayer insulating layer 674 and the third interlayer insulating layer 676 may respectively comprise silicon oxide and silicon nitride.

[0102] Reference Figure 6C A power pattern 660 and a connection pattern 665 can be formed filling the openings in the second interlayer insulating layer 674 and the third interlayer insulating layer 676. The power pattern 660 may include a metal-containing thin film layer 662 and a metal-containing layer 664, with the metal-containing thin film layer 662 surrounding the side and bottom surfaces of the metal-containing layer 664. The connection pattern 665 may include a metal-containing thin film layer 666 and a metal-containing layer 668, with the metal-containing thin film layer 666 surrounding the side and bottom surfaces of the metal-containing layer 668.

[0103] Reference Figure 6D , can Figure 6C A rear insulating layer 690 and a rear connection electrode 680 are formed on the resulting structure. The rear insulating layer 690 has an opening providing space for forming the rear connection electrode 680, which is formed in the opening of the rear insulating layer 690. The rear connection electrode 680 may include a metal thin film layer 682 and a metal layer 684, and the metal thin film layer 682 may surround the side surface and the lower surface of the metal layer 684.

[0104] Therefore, it can be manufactured with Figure 5B The semiconductor chip 100 is basically the same as the semiconductor chip.

[0105] Figures 7A to 7C This is a cross-sectional view illustrating a method for manufacturing a semiconductor chip according to another exemplary embodiment of the present disclosure.

[0106] Reference Figure 7AA structure may be formed above a carrier substrate (not shown), the structure comprising: a main body portion 710 having a front surface 711 and a rear surface 712; a wiring portion 720 formed below the front surface 711 of the main body portion 710; a front connecting electrode 730 and a front insulating layer 740 formed below the wiring portion 720; a first interlayer insulating layer 772 formed above the rear surface 712 of the main body portion 710; and a through electrode 750 penetrating the main body portion 710 and the first interlayer insulating layer 772. The through electrode 750 may include a conductive post 752 and a spacer 754.

[0107] Subsequently, a power supply pattern 760 containing a metal thin film layer 762 and a metal layer 764, and a connection pattern 765 containing a metal thin film layer 766 and a metal layer 768 can be formed above the rear surface 712 of the main body 710.

[0108] Reference Figure 7B A second interlayer insulating layer 774 and a third interlayer insulating layer 776 may be formed to fill the space between the power pattern 760 and the connection pattern 765. The second interlayer insulating layer 774 may include, for example, silicon nitride, and may be formed along the side surface of the power pattern 760, the side surface of the connection pattern 765, and the upper surface of the first interlayer insulating layer 772. The third interlayer insulating layer 776 may include, for example, silicon oxide, and may have a side surface and a lower surface surrounded by the second interlayer insulating layer 774.

[0109] Reference Figure 7C , can Figure 7B A rear connection electrode 780 is formed on top of the resulting structure. The rear connection electrode 780 may include a stacked structure containing a metal thin film layer 782 and a metal layer 784.

[0110] Subsequently, a back insulating layer 790 can be formed to fill the space between the back connecting electrodes 780.

[0111] Therefore, it can be manufactured with Figure 5B The semiconductor chip 500 is basically the same as the semiconductor chip.

[0112] According to the above embodiments of this disclosure, a semiconductor chip that can improve operating characteristics and facilitate manufacturing processes, as well as a semiconductor package including the same, can be provided.

[0113] Figure 8A block diagram illustrating an electronic system including a memory card 7800 employing at least one of the semiconductor packages according to an embodiment is shown. The memory card 7800 includes a memory 7810, such as a non-volatile memory device, and a memory controller 7820. The memory 7810 and the memory controller 7820 are capable of storing or retrieving stored data. At least one of the memory 7810 and the memory controller 7820 may include at least one of the semiconductor packages according to the described embodiment.

[0114] The memory 7810 may include a non-volatile memory device to which the techniques of embodiments of the present disclosure are applied. The memory controller 7820 may control the memory 7810 such that, in response to a read / write request from the host 7830, stored data or stored data can be read.

[0115] Figure 9 A block diagram illustrating an electronic system 8710 including at least one of the semiconductor packages according to the described embodiments is shown. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be interconnected via a bus 8715 providing a path for data movement.

[0116] In embodiments, controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. Controller 8711 or memory 8713 may include one or more semiconductor packages according to embodiments of this disclosure. Input / output device 8712 may include at least one selected from keypads, keyboards, display devices, touchscreens, etc. Memory 8713 is a means for storing data. Memory 8713 may store data and / or commands, etc., to be executed by controller 8711.

[0117] The memory 8713 may include volatile memory devices such as DRAM and / or non-volatile memory devices such as flash memory. For example, flash memory may be installed in information processing systems such as mobile terminals or desktop computers. Flash memory may constitute a solid-state drive (SSD). In this case, the electronic system 8710 can stably store large amounts of data in the flash memory system.

[0118] The electronic system 8710 may also include an interface 8714 configured to transmit data to and receive data from a communication network. The interface 8714 may be wired or wireless. For example, the interface 8714 may include an antenna or a wired or wireless transceiver.

[0119] The electronic system 8710 can be implemented as a mobile system, a personal computer, an industrial computer, or a logical system performing various functions. For example, a mobile system can be any of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smartphone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information sending / receiving system.

[0120] If electronic system 8710 represents a device capable of performing wireless communication, then electronic system 8710 can be used in communication systems using technologies such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution), or Wibro (Wireless Broadband Internet).

[0121] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the teachings as defined in the following claims.

[0122] Cross-reference to related applications

[0123] This application claims priority to Korean Patent Application No. 10-2020-0186907, filed on December 30, 2020, the entirety of which is incorporated herein by reference.

Claims

1. A semiconductor chip, the semiconductor chip comprising: main body; A power supply pattern is located above the main body; A first through electrode and a second through electrode, wherein the first through electrode and the second through electrode penetrate the main body; as well as A first connecting electrode and a second connecting electrode are respectively located above the first through electrode and the second through electrode. Wherein, the first connecting electrode is electrically connected to the first through electrode and the power supply pattern, and The second connecting electrode is electrically connected to the second through electrode, and the second connecting electrode is electrically insulated from the power supply pattern.

2. The semiconductor chip according to claim 1, further comprising: An interlayer insulation layer, located above the main body. in, The interlayer insulation layer surrounds the side surface of the power supply pattern, and The first connecting electrode and the second connecting electrode are disposed above the interlayer insulating layer.

3. The semiconductor chip according to claim 2, in, The top surface of the power supply pattern is coplanar with the top surface of the interlayer insulation layer.

4. The semiconductor chip according to claim 2, further comprising: A first connection pattern is located between the first through electrode and the first connection electrode; as well as The second connection pattern is located between the second through electrode and the second connection electrode.

5. The semiconductor chip according to claim 4, in, The interlayer insulation layer includes: silicon oxide layer; and A silicon nitride layer, wherein the silicon nitride layer is located above the silicon oxide layer. The silicon nitride layer partially surrounds the side surfaces of the first connection pattern and the second connection pattern.

6. The semiconductor chip according to claim 2, in, Each of the first through electrode and the second through electrode penetrates the interlayer insulation layer.

7. The semiconductor chip according to claim 2, further comprising: The third connecting electrode is located above the interlayer insulating layer. The third connecting electrode is electrically connected to the power supply pattern, and the third connecting electrode is not electrically connected to the first through electrode and the second through electrode.

8. The semiconductor chip according to claim 1, further comprising: An upper insulating layer is located between the first connecting electrode and the second connecting electrode. The top surface of the upper insulating layer, the top surface of the first connecting electrode, and the top surface of the second connecting electrode are coplanar.

9. The semiconductor chip according to claim 1, wherein, In the top view, The first connection electrode overlaps with the power supply pattern portion, and The second connection electrode is spaced apart from the power supply pattern.

10. The semiconductor chip according to claim 1, wherein, In the top view, Each of the first connecting electrode and the second connecting electrode has a circular shape.

11. The semiconductor chip according to claim 1, in, The power supply pattern includes: Multiple line patterns, the multiple line patterns extending parallel to each other; and An extension pattern that connects the ends of the plurality of line patterns to each other.

12. The semiconductor chip according to claim 1, wherein, The first through electrode, the first connecting pattern, and the first connecting electrode are perpendicularly aligned with each other, and The second through electrode, the second connecting pattern, and the second connecting electrode are vertically aligned with each other.

13. The semiconductor chip according to claim 1, further comprising: A third connecting electrode and a fourth connecting electrode are located below the main body; as well as A lower insulating layer is located between the third connecting electrode and the fourth connecting electrode. The top surface of the lower insulating layer is coplanar with the top surface of the third connecting electrode and the top surface of the fourth connecting electrode.

14. A semiconductor package, the semiconductor package comprising: A first semiconductor chip and a second semiconductor chip, wherein the second semiconductor chip is stacked on top of the first semiconductor chip. The first semiconductor chip includes: First subject; A first power supply pattern is located above the first main body; A first through electrode and a second through electrode, the first through electrode and the second through electrode perpendicularly penetrating the first body; and A first connecting electrode and a second connecting electrode are respectively located above the first through electrode and the second through electrode. in, The first connecting electrode is electrically connected to the first through electrode and the first power pattern, and The second connecting electrode is electrically connected to the second through electrode, and the second connecting electrode is electrically insulated from the first power supply pattern; The second semiconductor chip includes: Second subject; A third connecting electrode and a fourth connecting electrode are located below the second main body. The first connecting electrode is electrically connected to the third connecting electrode. The second connection electrode is electrically connected to the fourth connection electrode.

15. The semiconductor package of claim 14, further comprising: A first insulating layer is located between the first connecting electrode and the second connecting electrode; as well as A second insulating layer is located between the third connecting electrode and the fourth connecting electrode. The first insulating layer and the second insulating layer are bonded to each other.

16. The semiconductor package according to claim 15, in, The first semiconductor chip also includes: Additional connection electrodes, The additional connection electrode is electrically connected to the first power pattern, and the additional connection electrode is not electrically connected to the first through electrode and the second through electrode.

17. The semiconductor package according to claim 14, in, The second semiconductor chip also includes: The third and fourth through electrodes penetrate the second main body perpendicularly. Wherein, the first through electrode is electrically connected to the third connecting electrode, and The second through electrode is electrically connected to the fourth connecting electrode.

18. The semiconductor package of claim 17, wherein, The second semiconductor chip also includes a second power supply pattern, which is located above the second body. The second power supply pattern is electrically connected to the third through electrode, and The second power supply pattern is electrically insulated from the fourth through electrode.

19. The semiconductor package of claim 18, wherein, The second semiconductor chip further includes a fifth connection electrode and a sixth connection electrode, the fifth connection electrode and the sixth connection electrode being located above the third through electrode and the fourth through electrode, respectively. The fifth connecting electrode is electrically connected to the third through electrode and the second power pattern, and The sixth connecting electrode is electrically connected to the fourth through electrode, and the sixth connecting electrode is electrically insulated from the second power pattern.

20. The semiconductor package according to claim 18, in, The second semiconductor chip also includes: Additional connection electrodes, The additional connection electrode is electrically connected to the second power pattern, and the additional connection electrode is not electrically connected to the third through electrode and the fourth through electrode.

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