Semiconductor chip adopting diamond heat sink and preparation method thereof

Abstract

The invention discloses a semiconductor chip adopting a diamond heat sink and a preparation method of the semiconductor chip, and the semiconductor chip comprises a power chip which is a high-power semiconductor chip with high energy density and high heating; the heat conduction substrate is a common heat sink substrate; the diamond deposition layer is a patterned diamond film deposited on the heat conduction substrate; the transition layer is arranged on the side, away from the heat conduction substrate, of the diamond deposition layer and used for enhancing the binding force and preventing interface reaction; and the graphical metallization layer is arranged on one side, far away from the diamond deposition layer, of the transition layer and is used for realizing welding or eutectic bonding with the power chip. A high-efficiency heat conduction path is adopted, a thick metal bonding area directly located below the chip provides a low-thermal-resistance vertical heat conduction channel, and a graphical stress buffer structure ensures transverse heat conduction and avoids huge thermal stress caused by full coverage of metal at the same time.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device heat dissipation technology, specifically to a semiconductor chip using a diamond heat sink and its fabrication method. Background Technology

[0002] As semiconductor technology advances towards higher power, higher density, and miniaturization, chip power density is increasing dramatically. The resulting heat has become a key factor limiting device performance, reliability, and lifespan. Heat sinks, as crucial components for rapidly conducting and dissipating heat generated by chips, effectively reduce the operating temperature of devices, thereby improving their performance and lifespan. Therefore, their performance is of paramount importance.

[0003] Diamond is considered an ideal heat sink material due to its extremely high thermal conductivity (up to 2200 W / m·K). Currently, there are two main technical approaches to common diamond heat sinks: one is to use single-crystal diamond as the heat sink, but the main problem with this approach is its high cost.

[0004] Another technical route for diamond heat sinking is the preparation of polycrystalline diamond thick films using chemical vapor deposition (CVD). However, existing technologies have the following problems:

[0005] 1. Reliability issues: Due to the significant difference in the coefficient of thermal expansion (CTE) between diamond and common metals or ceramics, enormous thermal stress is generated during temperature cycling, leading to interface cracking and delamination, which in turn causes device failure.

[0006] 2. Surface roughness: The surface of CVD diamond growth is usually relatively rough, which is not conducive to subsequent fine processing such as photolithography and metallization, and also increases the contact area of ​​the bonding interface, affecting heat conduction.

[0007] Therefore, there is an urgent need for a diamond heat sink structure and its preparation method that combines high thermal conductivity, low interfacial thermal resistance and high reliability.

[0008] To this end, a semiconductor chip using a diamond heat sink and its fabrication method are proposed. Summary of the Invention

[0009] The purpose of this invention is to provide a semiconductor chip using a diamond heat sink and a method for its fabrication, so as to solve the problems mentioned in the background art.

[0010] To achieve the above objectives, the present invention provides the following technical solution: a semiconductor chip employing a diamond heat sink, comprising:

[0011] Power chips are high-power semiconductor chips with high energy density and high heat generation.

[0012] Thermally conductive substrate, which is a commonly used heat sink substrate;

[0013] The diamond deposition layer is a patterned diamond film deposited on a thermally conductive substrate;

[0014] A transition layer is provided on the side of the diamond deposition layer away from the thermally conductive substrate to enhance adhesion and prevent interfacial reactions.

[0015] A patterned metallization layer is located on the side of the transition layer away from the diamond deposition layer, and is used to achieve welding or eutectic bonding with the power chip.

[0016] Preferably, the transition layer has a multi-layer structure, consisting of layers of titanium, platinum, and gold or chromium, platinum, and gold stacked sequentially. The titanium or chromium layer is a bonding layer used to form a strong bond with the diamond deposition layer, the platinum layer is a barrier layer, and the gold layer is an anti-oxidation and bonding layer.

[0017] Preferably, the thickness of the titanium or chromium layer is 50-200 nm, the thickness of the platinum layer is 100-300 nm, and the thickness of the gold layer is 100-500 nm.

[0018] Preferably, the patterned metallization layer includes a chip bonding region and a stress buffer structure;

[0019] The chip bonding region is the area used for welding or eutectic bonding with the power chip. The thickness of the metal layer in this region is 5 to 20 μm and is composed of gold or gold-tin.

[0020] Preferably, the stress buffer structure is used to effectively release and buffer the stress caused by thermal mismatch while ensuring thermal conductivity. The stress buffer structure is located on the periphery of the chip bonding area and has a thickness of 1 to 5 μm. The metal layer pattern of the structure is discontinuous, grid-like, or array-like.

[0021] Preferably, the thermally conductive substrate is a metal substrate, a ceramic substrate, or an AlN substrate.

[0022] Preferably, the thickness of the diamond deposition layer is 20–100 μm.

[0023] The fabrication method of the semiconductor chip using diamond heat sink as described in any of the above-mentioned methods includes the following steps:

[0024] S1. Substrate polishing and cleaning: The surface to be metallized and the diamond film to be deposited is finely polished, and then ultrasonically cleaned in acetone, ethanol and deionized water in sequence, and then dried with nitrogen.

[0025] S2. Spin-coat photoresist onto the cleaned substrate surface, expose it through a mask with a diamond pattern, immerse the exposed substrate in a developer to remove the photoresist in the exposed area, expose the diamond deposition area of ​​the substrate, deposit a 20-100μm diamond film in the diamond deposition area using the CVD method, and finely polish the surface of the deposited diamond film.

[0026] S3. Using electron beam evaporation or magnetron sputtering, a multilayer thin film of titanium, platinum, and gold or chromium, platinum, and gold is sequentially deposited on the polished diamond surface as a transition layer, wherein the thickness of the titanium or chromium layer is 50-200 nm, the thickness of the platinum layer is 100-300 nm, and the thickness of the gold layer is 100-500 nm.

[0027] S4. Spin-coat photoresist onto the transition layer, then expose it to ultraviolet light through a photomask with a pattern corresponding to the patterned metallization layer, and develop it to remove the photoresist in the area to be electroplated, exposing the underlying gold layer, which will serve as the seed layer for electroplating.

[0028] S5. Using an electroplating process, the metal layer is selectively thickened in the chip bonding area and stress buffer structure area exposed after development. The electroplated metal is gold or gold-tin alloy, so that the final thickness of the chip bonding area reaches 5-20 μm and the thickness of the stress buffer structure is 1-5 μm.

[0029] S6. Remove the remaining photoresist, and then use ion beam etching or wet etching to remove the transition layer area not covered by electroplated metal, thereby forming the final patterned metallization layer.

[0030] S7. A bonding process is used to bond the power chip and the patterned metallization layer together.

[0031] Preferably, in step S4, the photomask corresponding to the patterned metallization layer pattern includes a chip bonding area and a stress buffer structure.

[0032] Compared with the prior art, the beneficial effects of the present invention are:

[0033] 1. Efficient heat conduction path: The thick metal bonding area located directly under the chip provides a vertical heat conduction channel with low thermal resistance, while the patterned stress buffer structure ensures lateral heat conduction while avoiding the huge thermal stress caused by full metal coverage.

[0034] 2. Significantly reduced interfacial thermal resistance: Through finely polished diamond surfaces and optimized multi-layer metal transition layers, a high-strength, low-thermal-resistance bond is achieved between the metal and diamond.

[0035] 3. Excellent reliability: The unique graphic stress buffer structure can effectively absorb and disperse the stress generated by thermal cycling, prevent interface delamination and cracking, and greatly improve the service life of the heat sink under harsh working conditions.

[0036] 4. Good process compatibility: The process used in this invention is compatible with existing semiconductor micromachining processes, making it easy to achieve mass production and high-precision manufacturing. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the overall structure of the present invention;

[0038] Figure 2 This is a top view of the patterned metallization layer of the present invention. Detailed Implementation

[0039] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0040] Please see Figure 1-2 This invention provides a technical solution: a semiconductor chip using a diamond heat sink, comprising:

[0041] Power chips are high-energy-density, high-heat-generating high-power semiconductor chips, such as lasers (LDs), power semiconductor devices, and integrated circuits (ICs).

[0042] Thermally conductive substrates are commonly used heat sink substrates, used to provide basic support and assist in heat conduction. They can be metal substrates, ceramic substrates, or AlN substrates.

[0043] The diamond deposition layer is a patterned diamond film deposited on a thermally conductive substrate. The diamond film does not cover the entire area, but adopts a patterned design to cover only the heat-generating core area corresponding to the power chip, leaving the non-heat-generating areas blank to reduce internal stress in the structure. The thickness is 20-100μm.

[0044] A transition layer, located on the side of the diamond deposition layer away from the thermally conductive substrate, strengthens the adhesion between the diamond deposition layer and subsequent metallization layers, and blocks interfacial reactions between different materials. The transition layer has a multilayer structure, sequentially stacked with layers of titanium (Ti), platinum (Pt), gold (Au) or chromium (Cr), platinum (Pt), and gold (Au). The titanium (Ti) or chromium (Cr) layer is the bonding layer, with a thickness of 50–200 nm, forming chemical bonds with carbon atoms on the diamond deposition layer surface to achieve a strong mechanical bond with the diamond. The platinum (Pt) layer is a barrier layer, with a thickness of 100–300 nm, preventing metal atoms from diffusing into the diamond during subsequent processes and isolating the bonding layer from air, thus preventing oxidation failure. The gold (Au) layer is an anti-oxidation and bonding layer, with a thickness of 100–500 nm, possessing excellent conductivity, oxidation resistance, and solderability. It provides a uniform seed layer for subsequent electroplating processes while ensuring reliable bonding with the power chip.

[0045] The patterned metallization layer includes a chip bonding region and a stress buffer structure. Located on the side of the transition layer away from the diamond deposition layer, it is used for soldering or eutectic bonding with the power chip. The chip bonding region is the area used for soldering or eutectic bonding with the power chip. The metal layer in this region has a thickness of 5–20 μm and is composed of gold (Au) or gold-tin (AuSn), possessing a suitable eutectic temperature and excellent thermal and electrical conductivity.

[0046] Stress buffer structures are used to effectively release and buffer stress caused by thermal mismatch while ensuring thermal conductivity. These structures are located around the chip bonding area, with a thickness of 1–5 μm. The metal layer pattern of this structure is discontinuous, grid-like, or array-like, such as metal lattices or metal rings. While ensuring unobstructed lateral heat conduction channels, this structure can effectively release and buffer thermal stress caused by the difference in thermal expansion coefficients between diamond and metal materials through its own deformation characteristics. This prevents interface cracking, delamination, and other failure phenomena during temperature cycling, significantly improving device reliability.

[0047] A method for fabricating a semiconductor chip using a diamond heat sink includes the following steps:

[0048] S1. Substrate polishing and cleaning: The surface to be metallized and deposited with diamond film is finely polished, and then ultrasonically cleaned in acetone, ethanol and deionized water in sequence to thoroughly remove surface oil, dust and oxides, and then dried with nitrogen.

[0049] S2. Spin-coat photoresist onto the cleaned substrate surface, expose it through a mask with a diamond pattern, immerse the exposed substrate in a developer to remove the photoresist in the exposed area, expose the diamond deposition area of ​​the substrate, deposit a 20-100 μm diamond film in the diamond deposition area using the CVD method, and finely polish the surface of the deposited diamond film.

[0050] S3. Using electron beam evaporation or magnetron sputtering, a multilayer thin film of titanium (Ti), platinum (Pt), and gold (Au) or chromium (Cr), platinum (Pt), and gold (Au) is sequentially deposited on the polished diamond surface as a transition layer. The thickness of the titanium (Ti) or chromium (Cr) layer is 50-200 nm, the thickness of the platinum (Pt) layer is 100-300 nm, and the thickness of the gold (Au) layer is 100-500 nm.

[0051] S4. Spin-coat photoresist onto the transition layer, then expose it to ultraviolet light through a photomask with a patterned metallization layer pattern, including chip bonding areas and stress buffer structures, and develop it to remove the photoresist in the areas to be electroplated, exposing the underlying gold layer, which will serve as the seed layer for electroplating.

[0052] S5. Using an electroplating process, the metal layer is selectively thickened in the chip bonding area and stress buffer structure area exposed after development. The electroplated metal is gold (Au) or gold-tin (AuSn) alloy, so that the final thickness of the chip bonding area reaches 5-20μm and the thickness of the stress buffer structure is 1-5μm.

[0053] S6. Remove the remaining photoresist, and then use ion beam etching or wet etching to remove the transition layer area not covered by electroplated metal, thereby forming the final patterned metallization layer.

[0054] S7. Employ eutectic bonding or welding processes to precisely align and bond the power chip to the chip bonding area of ​​the patterned metallization layer.

[0055] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A semiconductor chip employing a diamond heat sink, characterized in that, include: Power chips are high-power semiconductor chips with high energy density and high heat generation. Thermally conductive substrate, which is a commonly used heat sink substrate; The diamond deposition layer is a patterned diamond film deposited on a thermally conductive substrate; A transition layer is provided on the side of the diamond deposition layer away from the thermally conductive substrate to enhance adhesion and prevent interfacial reactions. A patterned metallization layer is located on the side of the transition layer away from the diamond deposition layer, and is used to achieve welding or eutectic bonding with the power chip.

2. A semiconductor chip using a diamond heat sink according to claim 1, characterized in that: The transition layer has a multi-layer structure, consisting of layers of titanium, platinum, and gold or chromium, platinum, and gold stacked sequentially. The titanium or chromium layer is a bonding layer used to form a strong bond with the diamond deposition layer, the platinum layer is a barrier layer, and the gold layer is an anti-oxidation and bonding layer.

3. A semiconductor chip using a diamond heat sink according to claim 2, characterized in that: The thickness of the titanium or chromium layer is 50–200 nm, the thickness of the platinum layer is 100–300 nm, and the thickness of the gold layer is 100–500 nm.

4. A semiconductor chip using a diamond heat sink according to claim 1, characterized in that: The patterned metallization layer includes a chip bonding region and a stress buffer structure; The chip bonding region is the area used for welding or eutectic bonding with the power chip. The thickness of the metal layer in this region is 5 to 20 μm and is composed of gold or gold-tin.

5. A semiconductor chip using a diamond heat sink according to claim 4, characterized in that: The stress buffer structure is used to effectively release and buffer the stress caused by thermal mismatch while ensuring thermal conductivity. The stress buffer structure is located on the periphery of the chip bonding area and has a thickness of 1 to 5 μm. The metal layer pattern of the structure is discontinuous, grid-like, or array-like.

6. A semiconductor chip employing a diamond heat sink according to claim 1, characterized in that: The thermally conductive substrate is a metal substrate, a ceramic substrate, or an AlN substrate.

7. A semiconductor chip using a diamond heat sink according to claim 1, characterized in that: The thickness of the diamond deposition layer is 20–100 μm.

8. A method for fabricating a semiconductor chip using a diamond heat sink as described in any one of claims 1-7, characterized in that, Includes the following steps: S1. Substrate polishing and cleaning: The surface to be metallized and the diamond film to be deposited is finely polished, and then ultrasonically cleaned in acetone, ethanol and deionized water in sequence, and then dried with nitrogen. S2. Spin-coat photoresist onto the cleaned substrate surface, expose it through a mask with a diamond pattern, immerse the exposed substrate in a developer to remove the photoresist in the exposed area, expose the diamond deposition area of ​​the substrate, deposit a 20-100μm diamond film in the diamond deposition area using the CVD method, and finely polish the surface of the deposited diamond film. S3. Using electron beam evaporation or magnetron sputtering, a multilayer thin film of titanium, platinum, and gold or chromium, platinum, and gold is sequentially deposited on the polished diamond surface as a transition layer, wherein the thickness of the titanium or chromium layer is 50-200 nm, the thickness of the platinum layer is 100-300 nm, and the thickness of the gold layer is 100-500 nm. S4. Spin-coat photoresist onto the transition layer, then expose it to ultraviolet light through a photomask with a pattern corresponding to the patterned metallization layer, and develop it to remove the photoresist in the area to be electroplated, exposing the underlying gold layer, which will serve as the seed layer for electroplating. S5. Using an electroplating process, the metal layer is selectively thickened in the chip bonding area and stress buffer structure area exposed after development. The electroplated metal is gold or gold-tin alloy, so that the final thickness of the chip bonding area reaches 5-20 μm and the thickness of the stress buffer structure is 1-5 μm. S6. Remove the remaining photoresist, and then use ion beam etching or wet etching to remove the transition layer area not covered by electroplated metal, thereby forming the final patterned metallization layer. S7. A bonding process is used to bond the power chip and the patterned metallization layer together.

9. The preparation method according to claim 8, characterized in that: In step S4, the photomask corresponding to the patterned metallization layer pattern includes a chip bonding area and a stress buffer structure.

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