Heterogeneous integrated substrate and processing method thereof
By employing ultra-thin copper layer electroplating and selective flash etching in heterogeneous integrated substrates, combined with riveting technology, the problem of substrate damage during laser capping was solved, improving the substrate's processing quality and reliability, and enhancing packaging yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JIANGSU PROVISION ELECTRONICS CO LTD
- Filing Date
- 2025-12-17
- Publication Date
- 2026-04-24
AI Technical Summary
During the laser peeling process, existing heterogeneous integrated substrates are damaged due to the absence of copper in some areas of the bottom substrate, resulting in narrow grooves that are prone to trapping chemicals or moisture, leading to plating penetration or CAF failure, which poses a risk to product reliability.
An ultra-thin copper layer is electroplated to thicken and form a barrier layer. The inner layer circuit pattern is then fabricated using the mSAP process. Combined with selective flash etching and riveting techniques, an intermediate board is produced. During laser peeling, the barrier layer is used to protect the substrate body and prevent damage. The uncovered barrier layer is then etched away to form solder pads.
It effectively avoids damage to the substrate body during the laser peeling process, improves the processing quality and product reliability of heterogeneous integrated substrates, reduces the risk of plating failure or CAF failure, and improves packaging yield.
Smart Images
Figure CN121925134A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of advanced packaging technology, and in particular to a heterogeneous integrated substrate and its processing method. Background Technology
[0002] With the advent of the post-Moore's Law era, the trend of surpassing Moore's Law, guided by downstream advanced packaging, is gradually becoming the mainstream. One of the development routes for heterogeneous integration is to sink the chip into the packaging substrate, thereby improving substrate space utilization, shortening distance, increasing signal transmission rate, reducing loss, and meeting the needs of high-performance computing.
[0003] Currently, the commonly used method for processing heterogeneous integrated circuit boards in the industry is as follows: first, the bottom solder joints are fabricated, then high-precision riveting is performed, and laser capping is performed after the outer layer circuitry is completed. However, during laser capping, because some areas of the bottom substrate lack copper, they cannot block the laser, resulting in some damage to the bottom substrate and the formation of narrow grooves. In subsequent processes or end-use applications, these narrow grooves can easily trap chemicals or moisture, leading to plating penetration or CAF failure, posing a risk to product reliability.
[0004] In view of this, the present invention is hereby proposed. Summary of the Invention
[0005] To overcome the above-mentioned defects, the present invention provides a heterogeneous integrated substrate and its processing method. The processing method is reasonable, the process flow is simple, and it is easy to operate and implement. Moreover, the resulting heterogeneous integrated substrate has good quality, high reliability, and high packaging yield.
[0006] The technical solution adopted by this invention to solve its technical problem is: a method for processing heterogeneous integrated substrates, comprising: A first substrate with an ultra-thin copper layer on the surface is provided. The ultra-thin copper layer is electroplated to thicken it to form a barrier layer. Then, a pattern structure A containing an inner layer circuit pattern prototype and a pad prototype is fabricated on the barrier layer using the mSAP process. After the pad prototype and the barrier layer within a predetermined range are coated and protected, selective flash etching is performed to obtain the inner layer circuit pattern; the coating is removed to obtain the intermediate board A. A second substrate with a through groove and a third substrate with a copper layer A on one side are provided. The second substrate and the third substrate are stacked sequentially on one side of the intermediate plate A and riveted together to obtain an intermediate plate B with a cavity. The solder pad prototype is completely housed in the cavity, and at least a portion of the barrier layer located next to the solder pad prototype is embedded in the second substrate. Based on the copper layer A, an outer layer pattern is fabricated to obtain a pattern structure B containing an outer layer circuit pattern and a blocking pattern; and the projection of the obtained pattern structure B toward the intermediate plate A does not fall into the cavity. Partial removal of the third substrate is made to open the cavity on the side facing away from the intermediate plate A; then the blocking pattern and the blocking layer contained in the cavity are etched away to obtain the pad.
[0007] As a further improvement of the present invention, the ultrathin copper layer is electroplated using a flash plating process to thicken it, and the thickness of the resulting barrier layer is 6 to 13 μm.
[0008] As a further improvement of the present invention, the thickness of the ultrathin copper layer is 1 to 3 μm and the copper teeth are 0.9 to 1.5 μm.
[0009] As a further improvement of the present invention, when performing selective flash etching, the flash etching amount is controlled to be ≤15μm.
[0010] As a further improvement of the present invention, the second substrate is further provided with a board body consisting of an insulating intermediate layer and two adhesive layers respectively attached to opposite sides of the insulating intermediate layer, wherein the adhesive layers have the property of melting when heated. The through grooves are provided on the main body of the plate and penetrate through the two adhesive layers respectively.
[0011] As a further improvement of the present invention, in the intermediate plate B, at least a portion of the barrier layer located next to the pad prototype is embedded in the adhesive layer.
[0012] As a further improvement of the present invention, a UV laser is used to partially cut and remove the third substrate, and the processing parameters of the UV laser are: output power of 3 to 8 W, galvanometer speed of 800 to 1500 mm / s, and cutting processing times of 5 to 15 times.
[0013] As a further improvement of the present invention, a CO2 laser is used to partially cut and remove the third substrate, and the processing parameters of the CO2 laser are: laser energy of 2 to 6 mJ, pulse width of 4 to 6 μs, and number of laser shots of 1 to 5.
[0014] As a further improvement of the present invention, after the pads are obtained, conventional processes such as outer layer solder mask, surface treatment, molding, finished product electrical testing, and finished product inspection are performed in sequence to obtain a heterogeneous integrated substrate.
[0015] The present invention also provides a heterogeneous integrated substrate, which is manufactured using the heterogeneous integrated substrate processing method described in the present invention.
[0016] The beneficial effects of this invention are as follows: Compared with the prior art, the processing method for heterogeneous integrated substrates provided by this invention has the following advantages: ① Through process innovation, this invention sets up a barrier layer that can temporarily protect the substrate body A of the first substrate and can be selectively etched away subsequently. This ensures that the substrate body A is undamaged during laser capping, thereby effectively avoiding the risk of plating penetration or CAF failure caused by laser damage to the substrate body A, improving the processing quality and product reliability of the heterogeneous integrated substrate, and thus improving the packaging yield of the heterogeneous integrated substrate. ② Through process innovation, this invention also sets up a barrier pattern that can protect the substrate body B of the third substrate. This ensures that the substrate body B is undamaged during laser capping, thereby effectively reducing the risk of product appearance defects and particle defects, further improving the processing quality and product reliability of the heterogeneous integrated substrate, and improving the packaging yield of the heterogeneous integrated substrate. ③ The processing method for heterogeneous integrated substrates provided by this invention is reasonable, has a simple process flow, and is easy to operate and implement. Furthermore, this processing method also broadens the limitations of laser capping processes and improves the flexibility of processing and production. Attached Figure Description
[0017] Figure 1 This is a flowchart of the processing method for the heterogeneous integrated substrate described in Embodiment 1 of the present invention; Figure 2 This is a schematic cross-sectional view of the first substrate in Example 1; Figure 3 This is a schematic cross-sectional view of the first substrate after the ultrathin copper layer has been thickened by electroplating in Example 1. Figure 4 This is a schematic cross-sectional view of the graphic structure A obtained in Example 1; Figure 5 This is a schematic cross-sectional view of the intermediate plate A obtained in Example 1; Figure 6 This is a schematic cross-sectional view of the second substrate in Example 1; Figure 7 This is a schematic cross-sectional view of the intermediate plate B obtained in Example 1; Figure 8 for Figure 7 An enlarged structural diagram of part A shown in the image; Figure 9 This is a schematic cross-sectional view of the graphic structure B obtained in Example 1; Figure 10 This is a schematic cross-sectional view of the cavity after it is opened on the side facing away from the intermediate plate A in Example 1. Figure 11 This is a schematic cross-sectional view of the heterogeneous integrated substrate semi-finished product obtained in Example 1; Figure 12This is a schematic cross-sectional view of the obtained heterogeneous integrated substrate semi-finished product after solder resist treatment in Example 1. Figure 13 This is a schematic cross-sectional view of the heterogeneous integrated substrate obtained in Example 1.
[0018] Referring to the accompanying drawings, the following explanations are provided: 1. First substrate; 10. Ultra-thin copper layer; 11. Barrier layer; 12. Substrate body A; 20. Inner layer circuit pattern prototype; 21. Pad prototype; 30. Inner layer circuit pattern; 31. Pad; 4. Second substrate; 40. Through slot; 41. Insulating intermediate layer; 42. Adhesive layer; 5. Third substrate; 50. Copper layer A; 51. Substrate body B; 6. Cavity; 70. Outer layer circuit pattern; 71. Barrier pattern; 8. Solder resist layer; 9. Surface treatment layer; B1. Intermediate board A; B2. Intermediate board B; B3. Heterogeneous integrated substrate semi-finished product; B4. Heterogeneous integrated substrate. Detailed Implementation
[0019] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0020] Example 1
[0021] Please see the appendix Figure 1 To be continued Figure 13 As shown, this embodiment 1 provides a method for processing a heterogeneous integrated substrate, including the following processing steps: S1: A first substrate 1 with an ultra-thin copper layer 10 as its surface layer is provided. The ultra-thin copper layer 10 is first thickened by electroplating according to product processing requirements to form a barrier layer 11 with a copper thickness of 6–13 μm. Then, an mSAP process is used to fabricate a pattern structure A on the barrier layer 11, containing an inner layer circuit pattern prototype 20 and a pad prototype 21. See Appendix for details. Figure 2 To be continued Figure 4 As shown.
[0022] Furthermore, regarding the first substrate 1, its implementation structure is determined based on the design requirements of the heterogeneous integrated substrate, and this application does not impose any limiting requirements. However, in order to provide a clear and detailed description of the heterogeneous integrated substrate processing method provided in this application, this embodiment specifically illustrates the implementation structure of the first substrate 1 as follows: Please continue to refer to the appendix. Figure 2As shown, the first substrate 1 has a substrate body A12 and an ultra-thin copper layer 10 fixedly attached to one side of the substrate body A12. The substrate body A12 can be, but is not limited to, an "insulating substrate structure composed of multiple layers of PP glass fiber cloth" or a "composite substrate structure having a circuit layer and an insulating layer (such as a prepreg layer) covering the circuit layer." The thickness of the ultra-thin copper layer 10 is 1–3 μm, and the copper teeth are 0.9–1.5 μm. It is understood that the larger the copper teeth of the copper layer, the greater the amount of flash etching required to remove the copper layer in the subsequent process, resulting in greater damage to the sidewalls of the circuit pattern and hindering the formation of fine circuits. Therefore, this embodiment specifically optimizes the copper teeth of the ultra-thin copper layer 10 to reasonably reduce the amount of flash etching in the subsequent process and ensure a reasonable pad spacing in the subsequent process.
[0023] Based on the aforementioned ultrathin copper layer 10, this embodiment uses a flash plating process to deposit a copper plating layer with a thickness of 5-10 μm onto the surface of the ultrathin copper layer 10. That is, the ultrathin copper layer 10 is electroplated to a thickness of 5-10 μm through the flash plating process to obtain the barrier layer 11 with a copper thickness of 6-13 μm; for details, please refer to the appendix. Figure 3 As shown.
[0024] Note: In this embodiment, according to the processing requirements of the heterogeneous integrated substrate, the barrier layer 11 has at least the following functions: ① When the pattern structure A is fabricated, the barrier layer 11 serves as the base copper of the pattern structure A; ② When laser capping is performed in the subsequent process, the barrier layer 11 serves to prevent laser damage to the substrate body A12.
[0025] Furthermore, regarding the mSAP process, it is a commonly used circuit fabrication process in the field of PCB processing, so it will not be described in detail here, but only briefly: The mSAP process used in this embodiment includes the following sequential processes: pre-coating treatment (e.g., roughening, cleaning and drying the first substrate 1 after the electroplating thickening operation), coating with resist photosensitive film (i.e., applying the resist photosensitive dry film onto the barrier layer 11 using a vacuum laminator, the film thickness of which is determined according to the design requirements of the pattern structure A), exposure (using an LDI exposure machine), development, pattern electroplating and film removal, so as to create a pattern structure A containing the inner layer circuit pattern prototype 20 and the pad prototype 21 on the barrier layer 11.
[0026] Note: Based on the above mSAP process, the line width and line spacing of the obtained inner layer circuit pattern prototype 20 can reach 10-40μm (and can be further 20-30μm).
[0027] S2: The board obtained after processing S1 is subjected to pre-coating treatment (e.g., roughening, cleaning, and drying), coating with photoresist dry film (i.e., coating the photoresist dry film onto the pattern structure A using a vacuum laminator), exposure (using an LDI exposure machine), and development processing to achieve coating protection of the pad prototype 21 and the barrier layer 11 within a predetermined range next to it. The "predetermined range" is based on the size of the cavity 6 in the heterogeneous integrated substrate. This embodiment does not impose any restrictions; it only requires that "part of the retained barrier layer 11 is housed within the cavity 6, and part is embedded in the second substrate 4 described below." Then, selective flash etching is performed to etch away the barrier layer 11 not covered by the photoresist dry film, thus obtaining the inner layer circuit pattern 30. Subsequently, the photoresist dry film is removed using a stripping solution to obtain the intermediate board A B1. For details, please refer to the appendix. Figure 5 As shown.
[0028] Furthermore, in this embodiment, during selective flash etching, the amount of flash etching is controlled to ≤15μm based on the thickness of the barrier layer 11; this ensures that the barrier layer 11 not covered by the photosensitive dry film is fully etched away without causing excessive damage to the substrate body A12.
[0029] In addition, after the intermediate board A is manufactured, the inner layer circuit pattern 30 is subjected to AOI optical inspection to ensure the processing quality of the inner layer circuit pattern 30.
[0030] S3: Provides a second substrate 4 and a third substrate 5, please refer to the appendix. Figure 6 and attached Figure 7 As shown, the second substrate 4 has a main body composed of an insulating intermediate layer 41 and two adhesive layers 42 respectively attached to opposite sides of the insulating intermediate layer 41, and through grooves 40 disposed on the main body and penetrating the two adhesive layers 42 respectively, and the adhesive layers 42 have the property of melting upon heating; the third substrate 5 has a substrate body B51 and a copper layer A50 fixedly attached to one side of the substrate body B51; the second substrate 4 and the third substrate 5 are sequentially stacked on one side of the intermediate plate AB1, and then riveted together to obtain an intermediate plate BB2 with a cavity 6. Please continue to refer to the appendix. Figure 7 and attached Figure 8As shown, in the obtained intermediate board B, the pad prototype 21 is completely housed within the cavity 6. A portion of the barrier layer 11 located within a predetermined range adjacent to the pad prototype 21 is housed within the cavity 6, and a portion is embedded in the second substrate 4 (specifically, embedded in the adhesive layer 42). It is understandable that the above-described positional layout between the barrier layer 11 and the cavity 6 is designed so that, during subsequent laser decapsulation processes, the barrier layer 11 can provide optimal protection for the substrate body A12, preventing defects such as narrow grooves as seen in the prior art from forming on the substrate body A12.
[0031] Furthermore, in this embodiment, the insulating intermediate layer 41 may be, but is not limited to, PP fiberglass cloth, and the adhesive layer 42 may be pure adhesive or low-flow prepreg, and is applied to the insulating intermediate layer 41 through a pre-application process. Additionally, in this embodiment, the through groove 40 is processed on the board body using a UV laser cutting process.
[0032] In this embodiment, the substrate body B51 may also be made of, but is not limited to, PP glass fiber cloth, and the thickness of the copper layer A50 is not limited, depending on the outer layer pattern manufacturing process.
[0033] In this embodiment, after the second substrate 4 and the third substrate 5 are sequentially stacked on one side of the intermediate plate A B1, the intermediate plate B B2 can be obtained by hot riveting process. Alternatively, the second substrate 4, the third substrate 5 and the intermediate plate A B1 can be preliminarily connected together by hot pressing process before riveting to obtain the intermediate plate B.
[0034] S4: Based on the thickness of the copper layer A50, this embodiment can use mSAP process or subtractive process to fabricate the outer layer pattern, so as to obtain a pattern structure B containing outer layer circuit pattern 70 and blocking pattern 71; and the projection of the obtained pattern structure B toward the intermediate board A does not fall into the cavity 6, so as to facilitate laser peeling operation in subsequent processes; specifically, an attached... Figure 9 As shown.
[0035] Note: ① When this embodiment uses the mSAP process to fabricate the outer layer pattern, it includes sequential pre-coating treatment (e.g., roughening, cleaning, and drying the intermediate board B), coating with resist photosensitive film (i.e., applying the resist photosensitive dry film to the copper layer A50 using a vacuum laminator), exposure (using an LDI exposure machine), development, pattern electroplating, film removal, baking, and flash etching to obtain the pattern structure B. When this embodiment uses the subtractive process to fabricate the outer layer pattern, since the subtractive process is also a commonly used circuit fabrication process in the PCB manufacturing field, it will not be described in detail here, but only briefly: the subtractive process includes sequential pre-coating treatment (e.g., roughening, cleaning, and drying the intermediate board B), coating with resist photosensitive film (i.e., applying the resist photosensitive dry film to the copper layer A50 using a vacuum laminator), exposure (using an LDI exposure machine), development, etching, and film removal to obtain the pattern structure B. ② During the laser peeling process in the later stages, the blocking pattern 71 serves to prevent laser damage to the portion of the substrate body B51 that needs to be retained.
[0036] In addition, after the pattern structure B is obtained, it needs to be subjected to AOI optical inspection to ensure the processing quality of the outer circuit pattern 70.
[0037] S5: The substrate body A12 is protected by the barrier layer 11. In this embodiment, a UV laser or CO2 laser can be used to remove a portion of the third substrate 5 (specifically, a portion of the substrate body B51), so that the cavity 6 is open on the side facing away from the intermediate plate A. It can be understood that the operation of opening the side of the cavity 6 facing away from the intermediate plate A is called "laser peeling," as detailed in the appendix. Figure 10 As shown; then, the blocking pattern 71 and the blocking layer 11, which is housed in the cavity 6 and not covered by the pad prototype 21, are etched away using an etching process to obtain the pad 31. Figure 11 It can be clearly seen that the substrate body A12 located in the cavity 6 and the portion of the substrate body B51 that needs to be retained are well protected during laser decapsulation.
[0038] Furthermore, when the third substrate 5 (specifically the substrate body B51) is partially cut and removed using a UV laser in this embodiment, the processing parameters of the UV laser can be optimized as follows: output power of 3-8W, galvanometer speed of 800-1500mm / s, and number of cutting operations of 5-15 times.
[0039] When the third substrate 5 (specifically the substrate body B51) is partially cut and removed using a CO2 laser in this embodiment, the processing parameters of the CO2 laser can be optimized as follows: laser energy of 2-6 mJ, pulse width of 4-6 μs, number of laser shots of 1-5, mask of 1.5-2 mm, spot diameter of 100 μm, and spot pitch of 50 μm.
[0040] In addition, after the pad 31 is manufactured, it needs to be subjected to AOI optical inspection to ensure the processing quality of the pad 31.
[0041] Furthermore, for ease of description, this embodiment also defines the board obtained after completing the above S5 processing as heterogeneous integrated substrate semi-finished product B3.
[0042] S6: The obtained heterogeneous integrated substrate semi-finished product B3 is subjected to conventional outer layer solder resist treatment (i.e., a solder resist layer 8 is set at a preset position on the outer layer circuit pattern 70, see Appendix). Figure 12 As shown), surface treatment (i.e., a surface treatment layer 9 is provided on the surface of the outer circuit pattern 70, the surface treatment layer 9 including but not limited to electroplated soft gold layer, electroless nickel-palladium-gold layer or electroless nickel-gold layer, etc., see appendix). Figure 13 The heterogeneous integrated substrate B4 was produced through processes including molding, electrical testing of finished products, inspection of finished products, inspection before shipment, and packaging and shipping.
[0043] As can be seen from the above, compared with the prior art, the processing method of the heterogeneous integrated substrate provided in this embodiment 1 has the following advantages: ① Through process innovation, this embodiment sets up a barrier layer 11 that can temporarily protect the substrate body A of the first substrate 1 and can be selectively etched away subsequently. This ensures that the substrate body A is not damaged during the laser peeling operation, thereby effectively avoiding the risk of plating penetration or CAF failure caused by laser damage to the substrate body A, improving the processing quality and product reliability of the heterogeneous integrated substrate, and thus improving the packaging yield of the heterogeneous integrated substrate. ② Through process innovation, this embodiment also sets up a barrier pattern 71 that can protect the substrate body B of the third substrate 5. This ensures that the substrate body B is not damaged during the laser peeling operation, thereby effectively reducing the risk of product appearance defects and particle defects, further improving the processing quality and product reliability of the heterogeneous integrated substrate, and improving the packaging yield of the heterogeneous integrated substrate. ③ The processing method for the heterogeneous integrated substrate provided in this embodiment is reasonable, the process flow is simple, and it is easy to operate and implement. Furthermore, this processing method also broadens the limitations of laser peeling process and improves the flexibility of processing and production.
[0044] Example 2
[0045] Please see the appendix Figure 13As shown, this embodiment 2 provides a heterogeneous integrated substrate, which is manufactured using the heterogeneous integrated substrate processing method described in embodiment 1 above.
[0046] As can be seen from the above, by means of the heterogeneous integrated substrate processing method provided in this application, the heterogeneous integrated substrate obtained in this embodiment 2 has good quality, high product reliability, and high packaging yield, which well meets the packaging requirements.
[0047] Finally, the prefixes "first," "second," "third," etc. (such as first substrate, second substrate, third substrate, etc.) in the component names of this invention patent specification, and the suffixes "A," "B," etc. (such as substrate body A, substrate body B, etc.) in the component names are only for ease of description and are not intended to limit the scope of implementation of this invention patent.
[0048] Many specific details have been set forth in the foregoing description to provide a thorough understanding of the present invention. However, the above description is merely a preferred embodiment of the present invention, and the present invention can be implemented in many other ways different from those described herein. Therefore, the present invention is not limited to the specific embodiments disclosed above. Furthermore, any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the present invention. Any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the protection scope of the present invention.
Claims
1. A method for processing a heterogeneous integrated substrate, characterized in that: include: A first substrate (1) with an ultra-thin copper layer (10) is provided. The ultra-thin copper layer (10) is electroplated to thicken it to form a barrier layer (11). Then, a pattern structure A containing an inner layer circuit pattern prototype (20) and a pad prototype (21) is fabricated on the barrier layer (11) using the mSAP process. After the pad prototype (21) and the barrier layer (11) within a preset range next to it are coated and protected, selective flash etching is performed to obtain the inner layer circuit pattern (30); the film is removed to obtain the intermediate board A; A second substrate (4) with a through groove (40) and a third substrate (5) with a copper layer A (50) on one side are provided. The second substrate (4) and the third substrate (5) are stacked sequentially on one side of the intermediate plate A and riveted together to obtain an intermediate plate B with a cavity (6). The solder pad prototype (21) is completely contained in the cavity (6), and at least a portion of the barrier layer (11) located next to the solder pad prototype (21) is embedded in the second substrate (4). Based on the copper layer A (50), an outer layer pattern is fabricated to obtain a pattern structure B containing an outer layer circuit pattern (70) and a blocking pattern (71); and the projection of the obtained pattern structure B toward the intermediate plate A does not fall into the cavity (6). Partial removal of the third substrate (5) is made so that the cavity (6) is open on the side opposite to the intermediate plate A; then the blocking pattern (71) and the blocking layer (11) contained in the cavity (6) are etched away to obtain the pad (31).
2. The processing method of the heterogeneous integrated substrate according to claim 1, characterized in that: The ultrathin copper layer (10) is thickened by electroplating using a flash plating process, and the resulting barrier layer (11) has a thickness of 6 to 13 μm.
3. The processing method of the heterogeneous integrated substrate according to claim 2, characterized in that: The thickness of the ultrathin copper layer (10) is 1-3 μm, and the copper teeth are 0.9-1.5 μm.
4. The processing method of the heterogeneous integrated substrate according to claim 1, characterized in that: When performing selective flash etching, the flash etching amount is controlled to be ≤15μm.
5. The processing method of the heterogeneous integrated substrate according to claim 1, characterized in that: The second substrate (4) is further provided with a board body consisting of an insulating intermediate layer (41) and two adhesive layers (42) respectively attached to opposite sides of the insulating intermediate layer (41), wherein the adhesive layer (42) has the property of melting when heated; The through groove (40) is provided on the main body of the plate and passes through the two adhesive layers (42) respectively.
6. The method for processing heterogeneous integrated substrates according to claim 5, characterized in that: In the intermediate plate B, at least a portion of the barrier layer (11) located next to the pad prototype (21) is embedded in the adhesive layer (42).
7. The processing method of the heterogeneous integrated substrate according to claim 1, characterized in that: The third substrate (5) is partially cut and removed using a UV laser, and the processing parameters of the UV laser are: output power of 3 to 8 W, galvanometer speed of 800 to 1500 mm / s, and number of cutting operations of 5 to 15.
8. The processing method of the heterogeneous integrated substrate according to claim 1, characterized in that: The third substrate (5) is partially cut and removed using a CO2 laser, and the processing parameters of the CO2 laser are: laser energy of 2-6 mJ, pulse width of 4-6 μs, and number of laser shots of 1-5.
9. The processing method of the heterogeneous integrated substrate according to claim 1, characterized in that: After the pad (31) is obtained, conventional outer layer solder resist, surface treatment, molding, finished product electrical testing and finished product inspection processes are carried out in sequence to obtain heterogeneous integrated substrate.
10. A heterogeneous integrated substrate, characterized in that: It is manufactured using the processing method of any one of claims 1-9 for heterogeneous integrated substrates.