Efficient handling of restart index by graphics processing unit (GPU) during tile-based delayed rendering (TBDR)

Abstract

Efficient handling of a restart index by a graphics processing unit (GPU) during tile-based delayed rendering (TBDR) is disclosed herein. In some aspects, a processor circuit of a GPU determines a position of a restart index of a plurality of indices of an index buffer associated with a primitive topology during a tile ordering pass, and determines a skip count based on the primitive topology and the position of the restart index, the skip count indicating a number of indices to skip during a tile rendering pass. In some aspects, the processor circuit also determines a visibility state of a primitive corresponding to the primitive topology, and generates visibility data including the visibility state and a skip count. Then, during the tile rendering pass, the processor circuit bypasses the acquisition of the restart index based on the skip count. According to some aspects, the processor circuitry may also assemble primitives based on visibility data.

Description

[0001] Priority application

[0002] This application claims priority to U.S. Patent Application Serial No. 18 / 476,258, filed September 27, 2023, entitled “EFFICIENTLY HANDLING RESTARTINDICES DURING TILE-BASED DEFERRED RENDERING (TBDR) BY GRAPHICS PROCESSINGUNITS (GPUs)”, the entire contents of which are incorporated herein by reference. background

[0003] I. Technical Field

[0004] The technology disclosed herein relates generally to a graphics processing unit (GPU) in a processor-based device, and more specifically to optimizing the performance of a GPU performing tile-based deferred rendering (TBDR).

[0005] II. Background Technology

[0006] Modern processor-based devices include dedicated processing units called graphics processing units (GPUs) to accelerate the rendering of graphics and video data for display. GPUs can be implemented as integrated elements of a general-purpose central processing unit (CPU) in a processor-based device, or as discrete hardware components separate from the CPU. Typical GPU architectures offer support for a mode called tile-based deferred rendering (TBDR), used for rendering three-dimensional (3D) graphics. When using TBDR, the GPU divides the screen space into smaller grid regions (“tiles”) for processing, allowing the GPU to store the depth and color data of each tile in on-chip graphics memory. The rendering of the graphics is performed by the GPU one tile at a time, and is handled in two passes: a tile sorting pass and a tile rendering pass. During the tile sorting pass, the GPU determines the visibility of each “primitive,” which is the simplest geometry (such as a point, line, or triangle, as a non-limiting example) associated with a given primitive topology (e.g., as a non-limiting example, a list of points, a list of lines, a strip of lines, a loop of lines, a list of triangles, a strip of triangles, or a fan of triangles). The GPU also categorizes primitives within a tile into different groups or "boxes" and generates box-level primitive visibility information. During a tile rendering pass, the GPU uses this box-level primitive visibility information to render screen space one box at a time. To do this, the GPU retrieves primitives marked as visible for a given tile from memory, assembles the primitives, and performs any further necessary processing.

[0007] During tile sorting and tile rendering iterations, the GPU's index buffer sequentially stores indices pointing to data of one or more vertices that define the shape of primitives in a given primitive topology. The GPU processes each index to retrieve the corresponding vertex data and construct each primitive. To enable the storage of data for multiple instances of a primitive topology in the index buffer, typical GPU architectures support a "primitive restart" feature that defines a specific data value as an "index restart." When a restart index is encountered during index processing in the index buffer, the GPU begins assembling a new instance of the primitive topology from the next sequential index.

[0008] However, using primitive restart functionality comes with some drawbacks. For example, if a restart index exists in the index buffer, the GPU cannot use the primitive visibility information provided from the tile sorting pass to assemble primitives in the tile rendering pass because the presence of the restart index alters the GPU's interpretation of the indices used to form primitives. Conventional GPU architectures address this issue by marking all primitives as visible to all tiles after a restart index is detected during the tile sorting pass. Subsequently, in the tile rendering pass, when primitives are made visible, the GPU's input assembler fetches the restart index and all subsequent indices from the index buffer to correctly assemble all primitives. However, this approach can negatively impact GPU performance when a restart index is present, as it may require processing invisible primitives in the tile rendering pass. Furthermore, the presence of a restart index can limit throughput in GPUs with "slicing" GPU architectures capable of parallelizing index fetching and primitive assembly. Because a restart index can alter the assembly of primitives after a restart index, index fetching and primitive assembly must be performed sequentially.

[0009] Therefore, it may be expected that the GPU will handle the restart index more efficiently during TBDR. Summary of the Invention

[0010] The aspects disclosed in the detailed description include the efficient handling of restart indices by a graphics processing unit (GPU) during tile-based deferred rendering (TBDR). Related apparatus, methods, and computer-readable media are also disclosed. In this regard, the GPU is configured to provide information about how many indices in the index buffer need to be skipped during a tile rendering pass, so that the tile rendering pass can assemble primitives without acquiring the restart indices. In some exemplary aspects disclosed herein, the GPU's processor circuitry determines the position of the restart index among a plurality of indices in the index buffer associated with the primitive topology during a tile sorting pass. The processor circuitry then determines a skip count based on the primitive topology and the position of the restart index, the skip count indicating the number of indices to be skipped among the plurality of indices during the tile rendering pass. In some aspects, the processor circuitry also determines one or more visibility states corresponding to one or more primitives of the primitive topology and generates visibility data including the one or more visibility states and the skip count. Subsequently, during the tile rendering pass, the processor circuitry bypasses the acquisition of the restart index based on the skip count. According to some aspects, the processor circuitry may also assemble one or more primitives based on the visibility data.

[0011] In some aspects, determining the skip count may include determining that the position of the restart index is within the first V indices of a plurality of indices, wherein the primitive topology is defined by a minimum number of V indices among the plurality of indices. In response to determining that the position of the restart index is within the first V indices of a plurality of indices, in such aspects, the processor circuitry determines that the skip count is equal to the position of the restart index. According to some aspects, determining the skip count may include determining that the position of the restart index is after the ordinal first primitive in one or more primitives. In response to determining that the position of the restart index is after the ordinal first primitive in one or more primitives, in such aspects, the processor circuitry determines that the skip count is equal to one (1).

[0012] In another aspect, a GPU is disclosed. The GPU includes an index buffer associated with a primitive topology and comprising multiple indices. The GPU also includes processor circuitry configured to determine the position of a restart index among the multiple indices in the index buffer during a tile sorting pass. The processor circuitry is further configured to determine a skip count based on the primitive topology and the position of the restart index during the tile sorting pass, the skip count indicating the number of indices to be skipped among the multiple indices during a tile rendering pass. The processor circuitry is also configured to bypass the fetching of the restart index based on the skip count during a tile rendering pass.

[0013] In another aspect, a GPU is disclosed. This GPU includes components for determining the position of a restart index among multiple indices in an index buffer during a tile sorting pass. The GPU also includes components for determining a skip count based on the primitive topology and the position of the restart index during the tile sorting pass, the skip count indicating the number of indices to be skipped among the multiple indices during a tile rendering pass. The GPU further includes components for bypassing the acquisition of the restart index based on the skip count during a tile rendering pass.

[0014] On the other hand, a method for efficiently handling restart indices by a GPU during TBDR is disclosed. The method includes, during a tile sorting iteration, the GPU's processor circuitry determining the position of the restart index among multiple indices in an index buffer associated with the primitive topology. The method also includes, during a tile sorting iteration, the processor circuitry determining a skip count based on the primitive topology and the position of the restart index, the skip count indicating the number of indices to be skipped among the multiple indices during a tile rendering iteration. Furthermore, the method includes, during a tile rendering iteration, the processor circuitry bypassing the acquisition of the restart index based on the skip count.

[0015] In another aspect, a non-transitory computer-readable medium is disclosed. This non-transitory computer-readable medium stores computer-executable instructions that, when executed, cause a processor of a processor-based device to determine, during a tile sorting pass, the position of a restart index among a plurality of indices in an index buffer associated with the primitive topology. These computer-executable instructions also cause the processor to determine a skip count during the tile sorting pass based on the primitive topology and the position of the restart index, the skip count indicating the number of indices to be skipped among the plurality of indices during a tile rendering pass. These computer-executable instructions further cause the processor to bypass the fetching of the restart index during a tile rendering pass based on the skip count. Attached Figure Description

[0016] Figure 1 The above is a block diagram of an exemplary processor-based system according to some aspects, the processor-based system including a processor with a graphics processing unit (GPU) configured to efficiently handle restart indexes during tile-based deferred rendering (TBDR); Figures 2A to 2B This is an example of what can be done based on certain aspects. Figure 1 A block diagram of an exemplary primitive topology processed by the GPU during TBDR; Figure 3 This is an example of usage based on some aspects. Figure 1 The GPU's index buffer is used to restart the index to process the block diagram of two instances of the triangular fan primitive topology; Figure 4This is an example based on some aspects. Figure 1 The GPU generates exemplary visibility data during tile sorting iterations, including visibility state and skip counts, as well as data generated by... Figure 1 A diagram of the corresponding primitive assembly data generated by the GPU during tile rendering passes; Figures 5A to 5B Examples are provided based on some aspects. Figure 1 A flowchart illustrating exemplary operations performed by the GPU to efficiently handle restarted indexes during TBDR; and Figure 6 Yes, it can include Figure 1 An exemplary block diagram of a processor-based device. Detailed Implementation

[0017] Several exemplary aspects of this disclosure will now be described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or superior to other aspects. The terms “first,” “second,” etc., are used herein to distinguish similarly named elements and should not be construed as indicating an ordinal relationship between such elements unless so explicitly described herein.

[0018] The aspects disclosed in the detailed description include the efficient handling of restart indices by a graphics processing unit (GPU) during tile-based deferred rendering (TBDR). Related apparatus, methods, and computer-readable media are also disclosed. In this regard, the GPU is configured to provide information about how many indices in the index buffer need to be skipped during a tile rendering pass, so that the tile rendering pass can assemble primitives without acquiring the restart indices. In some exemplary aspects disclosed herein, the GPU's processor circuitry determines the position of the restart index among a plurality of indices in the index buffer associated with the primitive topology during a tile sorting pass. The processor circuitry then determines a skip count based on the primitive topology and the position of the restart index, the skip count indicating the number of indices to be skipped among the plurality of indices during the tile rendering pass. In some aspects, the processor circuitry also determines one or more visibility states corresponding to one or more primitives of the primitive topology and generates visibility data including the one or more visibility states and the skip count. Subsequently, during the tile rendering pass, the processor circuitry bypasses the acquisition of the restart index based on the skip count. According to some aspects, the processor circuitry may also assemble one or more primitives based on the visibility data.

[0019] In some aspects, determining the skip count may include determining that the position of the restart index is within the first V indices of a plurality of indices, wherein the primitive topology is defined by a minimum number of V indices among the plurality of indices. In response to determining that the position of the restart index is within the first V indices of a plurality of indices, in such aspects, the processor circuitry determines that the skip count is equal to the position of the restart index. According to some aspects, determining the skip count may include determining that the position of the restart index is after the ordinal first primitive in one or more primitives. In response to determining that the position of the restart index is after the ordinal first primitive in one or more primitives, in such aspects, the processor circuitry determines that the skip count is equal to one (1).

[0020] in this regard, Figure 1 This is a block diagram of an exemplary processor-based device 100. The processor-based device 100 includes a processor 102 (also referred to as a "processor core" or "CPU core"), which can be an ordered or unordered processor (OoP) and / or can be one of a plurality of processors 102 provided by the processor-based device 100. Examples of processor 102 may include, but are not limited to, digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field-programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits.

[0021] like Figure 1 As shown, processor 102 includes a graphics processing unit (GPU) 104, which provides processor circuitry 106 for performing graphics operations. As a non-limiting example, GPU 104 may include a dedicated hardware unit with fixed functionality and programmable components for rendering graphics and executing GPU applications. GPU 104 may also include a DSP, a general-purpose microprocessor, an ASIC, an FPGA, or other equivalent integrated or discrete logic circuitry; for clarity, these devices are... Figure 1 Not shown in the diagram. It should be noted that although processor 102 and GPU 104 are... Figure 1 In the examples, it is illustrated as a single unit, but in some examples, the processor 102 and GPU 104 can be implemented as separate hardware components. Although Figure 1 Not shown, but should be understood. Figure 1 The processor 102 can execute software applications or provide an application programming interface (API) that submits graphics instructions to the processor 102, based on which the graphics workload can be determined for processing by the GPU 104.

[0022] Figure 1The processor-based device 100 may encompass any of known digital logic elements, semiconductor circuits, processing cores, and / or memory structures, as well as other elements or combinations thereof. The aspects described herein are not limited to any particular arrangement of elements, and the disclosed techniques can be readily extended to various structures and layouts on semiconductor dies or packages. It will be understood that some aspects of the processor-based device 100 may include, in addition to… Figure 1 Elements other than those exemplified, and / or may include Figure 1 The illustrated components may be more or fewer. For example, processor-based device 100 may also include additional processor 102, processor core, cache, controller, communication bus, and / or persistent storage devices, which, for clarity, are described below. Figure 1 Omitted in .

[0023] To optimize physical design, clock frequency, design scalability, and workload imbalance, GPU 104 implements a sliced ​​GPU architecture in several aspects. In these aspects, GPU 104 can be configured to include multiple hardware slices (not shown), each providing hardware elements that offer functionality corresponding to the regular elements of the GPU's graphics pipeline. This sliced ​​GPU architecture enables GPU 104 to achieve higher throughput by performing operations such as index fetching and primitive assembly in parallel.

[0024] Figure 1 The GPU 104 is configured to support TBDR mode for rendering three-dimensional (3D) graphics. Operating in TBDR mode involves the GPU 104 dividing the graphics image into a regular grid and processing each part of the grid (i.e., a "tile") individually. This reduces the memory and bandwidth requirements for processing the image and allows the GPU 104 to store the depth and color data of each tile in on-chip graphics memory. Rendering of the graphics image is performed by the GPU one tile at a time, occurring in two passes: a tile sorting pass and a tile rendering pass. During the tile sorting pass, the GPU 104 determines the visibility of each "primitive," which is the simplest geometry (such as a point, line, or triangle) associated with a given primitive topology (e.g., as a non-limiting example, a list of points, a list of lines, a strip of lines, a loop of lines, a list of triangles, a strip of triangles, or a fan of triangles) within the tile being processed. The GPU also classifies primitives in a tile into different groups or "boxes" based on location and generates box-level primitive visibility information. During a tile rendering pass, the GPU uses box-level primitive visibility information to render screen space one box at a time. To do this, the GPU retrieves primitives marked as visible for a given tile from memory, assembles the primitives, and performs any further necessary processing.

[0025] To store primitive-defining data during tile sorting and tile rendering iterations, GPU 104 provides an index buffer 108 that stores multiple indices 110(0)-110(N). Each index in 110(0)-110(N) includes an integer offset to a vertex buffer 112 that stores data for multiple vertices 114(0)-114(V). Index buffer 108 is associated with a specific type of primitive topology, an example of which is described below regarding Figure 2A and Figure 2B This will be discussed in more detail. The indices 110(0)-110(N) of the index buffer 108 indicate a specific sequence of vertices 114(0)-114(V) to define the shape of one or more primitives of a given instance of a primitive topology. Thus, for example, if the index buffer is associated with a triangular fan primitive topology, the indices 110(0)-110(N) define the shape of one or more triangular primitives constituting an instance of the triangular fan primitive topology.

[0026] Indices 110(0)-110(N) of index buffer 108 can all be used to define a single instance of the primitive topology. Furthermore, the standard GPU architecture supports a "primitive restart" function, which allows data from multiple instances of the primitive topology to be stored in index buffer 108. The primitive restart function definition can be stored in index buffer 108 as one of the indices 110(0)-110(N) (i.e., the "restart index"). When a restart index is encountered during the processing of indices 110(0)-110(N) of index buffer 108, GPU 104 begins assembling a new instance of the primitive topology from the next sequential index. The following is about... Figure 3 The example of using a restart index to store data for two (2) instances of a triangular fan primitive topology in index buffer 108 is discussed in more detail.

[0027] However, as noted above, using the primitive restart feature has drawbacks. The presence of the restart index in index buffer 108 limits the GPU 104's ability to assemble primitives in a tile rendering pass using primitive visibility information provided from the tile sorting pass, because the presence of the restart index alters the interpretation of indices 110(0)–110(N) used to form primitives. A conventional approach to address this issue involves marking all primitives as visible to all tiles after a restart index is detected during the tile sorting pass, and then fetching the restart index and all subsequent indices from index buffer 108 to correctly assemble all primitives when making them visible. However, this approach can negatively impact GPU performance because it may require processing invisible primitives in a tile rendering pass. Additionally, because the restart index may alter the assembling of primitives after the restart index, index fetching and primitive assembling cannot be performed in parallel but must be done sequentially.

[0028] In this regard, GPU 104 is configured to provide efficient handling of restart indices during TBDR. In exemplary operation, processor circuitry 106 determines the position of a restart index (not shown) among a plurality of indices 110(0)-110(N) of the index buffer 108 associated with the primitive topology during a tile sorting pass. Processor circuitry 106 determines a skip count 116 based on the primitive topology and the position of the restart index, which indicates the number of indices to be skipped among the plurality of indices 110(0)-110(N) during a tile rendering pass. In some aspects, processor circuitry 106 also determines one or more visibility states (each visibility state in the specified range) of one or more primitives (not shown) corresponding to the primitive topology defined by indices 110(0)-110(N). Figure 1 The visibility states are labeled as "VIZ states" 118(0)-118(S). In this respect, processor circuitry 106 generates visibility data 120 including one or more visibility states 118(0)-118(S) and a skip count 116. During a tile rendering pass, processor circuitry 106 bypasses the fetching of the restart index based on the skip count 116, thereby enabling parallel index fetching and primitive assembly. In the above respect, processor circuitry 106 can also assemble one or more primitives based on the visibility data 120, which allows redundant processing of invisible primitives to be avoided during a tile rendering pass.

[0029] In some aspects, determining the skip count 116 may include determining that the position of the restart index is within the first V indices of a plurality of indices 110(0)-110(N), wherein the primitive topology is defined by a minimum number of V indices of the plurality of indices 110(0)-110(N). In response to determining that the position of the restart index is within the first V indices of the plurality of indices 110(0)-110(N), in such an aspect, processor circuitry 106 determines that the skip count 116 is equal to the position of the restart index. For example, if the restart index is at a first position within index buffer 108 (i.e., the first index 110(0)), then processor circuitry 106 determines that the skip count is equal to one (1). According to some aspects, determining the skip count 116 may include processor circuitry 106 determining that the position of the restart index is after an ordinal first primitive in one or more primitives defined by indices 110(0)-110(N). In response to determining that the position of the restart index is after an ordinal first primitive in one or more primitives, in such an aspect, processor circuitry 106 determines that the skip count 116 is equal to one (1). The following relates to Figure 4 Examples of visibility data 120 and skip count 116 that can be generated by processor circuitry 106 are discussed in more detail.

[0030] It should be understood that Figure 1The index buffer 108 has indices 110(0)-110(N) (where each index points to...) Figure 1 The vertices in vertex buffer 112 (vertices 114(0)-114(V)) can be defined as one or more instances of any of a plurality of different primitive topologies, depending on which primitive topology is associated with index buffer 108. In this respect, Figures 2A to 2B Examples of primitive topologies based on some aspects (each primitive topology in...) are given. Figures 2A to 2B The exemplary instances labeled “TOPOLOGY” (topology) 200(0)-200(10) are shown in the figure. These primitive topologies can be used by the topology when operating in TBDR mode. Figure 1 GPU104 rendering. Each instance of primitive topology 200(0)-200(10) includes a series of vertices whose order corresponds to the order of the reference vertices of each aspect associated with the primitive topology 200(0)-200(10) in index buffer 108.

[0031] First refer to Figure 2A The primitive topology 200(0) shown is a “point list” comprising multiple “point” primitives represented by corresponding vertices 202(0)-202(3). Each vertex in vertices 202(0)-202(3) defines a point primitive in the point list, and thus the number of vertices required to define an instance of the point list primitive topology 200(0) is one (1). Figure 2A The diagram also shows a primitive topology 200(1), which is a "line list" comprising a series of "line" primitives represented by vertices 204(0)-204(3). Each line primitive in the line primitives is defined by two vertices (2) of vertices 204(0)-204(3). Thus, in this example, vertices 204(0) and 204(1) define the first line primitive, while vertices 204(2) and 204(3) define the second line primitive. Because the line list consists of line primitives, the minimum number of vertices required to define an instance of the line list primitive topology 200(1) is two (2).

[0032] Figure 2A The primitive topology 200(2) shown is a “line strip” comprising a series of connected line primitives represented by vertices 206(0)-206(3). Therefore, as Figure 2A As shown in the example, vertices 206(0) and 206(1) define the first line primitive, vertices 206(1) and 206(2) define the second line primitive, and vertices 206(2) and 206(3) define the third line primitive. Similar to the line list primitive topology 200(1), the minimum number of vertices required to define an instance of the line strip primitive topology 200(2) is two (2).

[0033] Figure 2A The primitive topology 200(3) in the example is a “line loop” which consists of a series of connected line primitives represented by vertices 208(0)-208(4) that form a closed polygon. Thus, vertices 208(0) and 208(1) define the first line primitive, vertices 208(1) and 208(2) define the second line primitive, vertices 208(2) and 208(3) define the third line primitive, vertices 208(3) and 208(4) define the fourth line primitive, and finally vertices 208(4) and 208(0) define the fifth line primitive of the closed line loop. The minimum number of vertices required to define an instance of the line loop primitive topology 200(3) is two (2).

[0034] Figure 2A The diagram further illustrates a primitive topology 200(4) for a “triangle list”, where each group of three (3) vertices in vertices 210(0)-210(5) defines a separate “triangle” primitive. In this example, vertices 210(0)-210(2) define the first triangle primitive, while vertices 210(3)-210(5) define the second triangle primitive. Because a triangle list consists of triangle primitives, the minimum number of vertices required to define an instance of the triangle list primitive topology 200(4) is three (3).

[0035] Figure 2A The primitive topology 200(5) is a “triangle strip” consisting of a series of connected triangular primitives defined by vertices 212(0)-212(6). The first three vertices 212(0)-212(2) define the first triangular primitive, and each subsequent vertex 212(3)-212(6) defines an additional triangular primitive defined by that subsequent vertex and two (2) of the previous vertices. For example, vertices 212(3), 212(2) and 212(1) define the second triangular primitive, vertices 212(4), 212(3) and 212(2) define the third triangular primitive, and so on. The minimum number of vertices required to define an instance of the triangular strip primitive topology 200(5) is three (3).

[0036] Primitive topology 200(6) is a “triangle fan” comprising vertices 214(0)-214(4), where the first three vertices 214(0)-214(2) define the first triangle primitive, and each subsequent vertex 214(3)-214(4) defines an additional triangle primitive defined by that subsequent vertex, the previous vertex, and the first vertex 214(0). Thus, in this example, vertices 214(3), 214(2), and 214(0) define the second triangle primitive, and vertices 214(4), 214(3), and 214(0) define the third triangle primitive. Similar to triangle lists and triangle strips, the minimum number of vertices required to define an instance of triangle fan primitive topology 200(6) is three (3).

[0037] Now go to Figure 2B Examples of primitive topologies 200(7)-200(10) are shown. Primitive topologies 200(7)-200(10) are referred to as "adjacent" primitives because they include vertices that define the neighboring primitives surrounding the primitive to be rendered. Neighboring primitives provide the GPU 104 with additional information useful when performing tasks such as geometry shading. In this respect, Figure 2B An example of primitive topology 200(7) is given, referred to as a “list of lines with adjacency” and including vertices 216(0)–216(7) in this example. Vertices 216(1) and 216(2) define the first line primitive, while vertices 216(0) and 216(3) provide adjacency data. Similarly, vertices 216(5) and 216(6) define the second line primitive, while vertices 216(4) and 216(7) are included as adjacency data. The minimum number of vertices required to define an instance of primitive topology 200(7) with a list of lines with adjacency is four (4): two (2) vertices defining the line primitives and two (2) adjacent vertices.

[0038] exist Figure 2B In the example, primitive topology 200(8) is a “line strip with adjacency” including vertices 218(0)-218(5). Vertices 218(1) and 218(2) define the first line primitive, vertices 218(2) and 218(3) define the second line primitive, and vertices 218(3) and 218(4) define the third line primitive. Additionally, vertices 218(0) and 218(5) provide the adjacency data for the line strip. Similar to a list of lines with adjacency, the minimum number of vertices required to define an instance of primitive topology 200(8) with adjacency is four (4): two (2) vertices defining the line primitives and two (2) adjacent vertices.

[0039] Primitive topology 200(9) is a “list of triangles with adjacency” including vertices 220(0)-220(11). In the list of triangles with adjacency, adjacent vertices are provided for each pair of vertices of each triangle primitive. Thus, in this example, the first triangle primitive is defined by vertices 220(0), 220(2), and 220(4), where vertices 220(1), 220(3), and 220(5) provide the adjacency data. Similarly, vertices 220(6), 220(8), and 220(10) define the second triangle primitive, where vertices 220(7), 220(9), and 220(11) provide the adjacency data. The minimum number of vertices required to define an instance of primitive topology 200(9) with the list of triangles with adjacency is six (6): three (3) vertices defining the triangle primitive and three (3) adjacent vertices.

[0040] Finally, primitive topology 200(10) is "a triangular band with adjacency", and in Figure 2B The example includes vertices 222(0)-222(13). A triangle band with adjacency includes the adjacent vertices of each pair of vertices along the outer edge of the triangle band. Therefore, as... Figure 2B As shown, vertices 222(0), 222(2), and 222(4) define the first triangular primitive, vertices 222(2), 222(4), and 222(6) define the second triangular primitive, vertices 222(4), 222(6), and 222(8) define the third triangular primitive, and so on. In addition, vertices 222(1), 222(3), 222(5), 222(7), 222(9), 222(11), and 222(13) provide adjacency data. Similar to the list of triangles with adjacency, the minimum number of vertices required to define an instance of the triangular primitive topology 200(10) with adjacency is six (6): three (3) vertices defining the triangular primitive and three (3) adjacent vertices.

[0041] To illustrate the use of some aspects Figure 1 The restart index in the index buffer 108 of the GPU 104 is used for assembly. Figure 2A Two instances of the triangular fan primitive topology 200(6) are provided. Figure 3 .exist Figure 3 , exemplified Figure 1Index buffer 108 and indices 110(0)-110(N) (where N=11), wherein index buffer 108 is associated with the triangular fan primitive topology 200(6). Indices 110(0)-110(5) and 110(7)-110(11) of index buffer 108 point to the vertex data of the corresponding vertices 300(0)-300(5) and 300(7)-300(11). However, it should be noted that index 110(6) of index buffer 108 is a restart index, indicating that index 110(6) stores a specified data value that causes GPU 104 to start assembling new primitives from the next sequential index (index 110(7) in this example) when encountered during the processing of indices 110(0)-110(N).

[0042] If the restart index 110(6) points to vertex data, the GPU 104 processes the indices 110(0)-110(11) of the index buffer 108 as a single instance (not shown) of the triangular fan primitive topology 200(6). This single instance will include a first triangular primitive defined by the first three vertices indicated by indices 110(0)-110(2), where each subsequent index 110(3)-110(11) defines an additional triangular primitive defined by the vertices indicated by that subsequent index, the previous index, and the first index 110(0).

[0043] However, due to the presence of restart index 110(6), GPU 104 processes indices 110(0)-110(5) and 110(7)-110(11) as two separate triangle fan instances 302(0) and 302(1). Triangle fan instance 302(0) includes three vertices 300(0)-300(2) corresponding to indices 110(0)-110(2) and defining the triangle primitive 304(0). Vertex 300(3) (corresponding to index 110(3)) and vertices 300(2) and 300(0) also define triangle primitive 304(1), vertex 300(4) (corresponding to index 110(4)) and vertices 300(3) and 300(0) define triangle primitive 304(2), and vertex 300(5) (corresponding to index 110(5)) and vertices 300(4) and 300(0) define triangle primitive 304(3). Then, GPU 104 “reboots” by treating index 110(7) as the new center vertex of triangle fan instance 302(1). Thus, triangle fan instance 302(1) includes three vertices 300(7)-300(9) corresponding to indices 110(7)-110(9) and defining triangle primitive 304(4). Vertex 300(10) (corresponding to index 110(10)) and vertices 300(9) and 300(7) also define triangle primitive 304(5), and vertex 300(11) (corresponding to index 110(11)) and vertices 300(10) and 300(7) define triangle primitive 304(6).

[0044] Figure 4 Provided based on some aspects Figure 1 The skip count 116 and visibility data 120 generated by GPU 104 during tile sorting iterations (including visibility states 118(0)-118(6) (i.e., S=6 in this example)) and by Figure 1 An exemplary example of the corresponding exemplary primitive assembly data 400 generated by GPU 104 during a tile rendering pass. For illustrative purposes, the description... Figure 4 Referenced at the time Figure 3The vertices 300(0)-300(5) and 300(7)-300(11) and triangle primitives 304(0)-304(6). As previously discussed, during the tile sorting process, GPU 104 determines the position of the restart index 110(6) among the multiple indices 110(0)-110(N) of the index buffer 108, and determines a skip count 116 based on the position of the triangle fan primitive topology 200(6) and the restart index 110(6), which indicates the number of indices to be skipped among the multiple indices 110(0)-110(N) during a tile rendering pass. Subsequently, during a tile rendering pass, GPU 104 can bypass the fetching of the restart index 110(6) based on the skip count 116, thereby enabling parallel index fetching and primitive assembly.

[0045] In some respects, GPU 104 can determine the skip count 116 by determining the location of the restart index within the first V indices of a plurality of indices 110(0)-110(N), where V represents the minimum number of indices required to define the primitive topology associated with index buffer 108. If so, GPU 104 determines that the skip count 116 is equal to the location of the restart index. For example, the minimum number of indices (pointing to unique vertices) required to define the triangular fan primitive topology 200(6) is three (3) (V=3). Therefore, if GPU 104 determines that the location of the restart index is one of index 110(0), index 110(1), or index 110(2), GPU 104 will determine the skip count to be 1, 2, or 3, respectively. When GPU 104 begins processing index buffer 108 during a tile rendering pass, GPU 104 will bypass the acquisition of the indicated number of indices 110(0)-110(N) at the beginning of index buffer 108, including the restart index. In some aspects, GPU 104 may determine the skip count 116 by determining the position of the restart index after the ordinal first primitive in one or more primitives (e.g., triangle primitive 304(0) in triangle primitives 304(0)-304(6)). If so, then in such aspects, GPU 104 determines that the skip count is equal to one (1).

[0046] The value of skip count 116, which can be determined by GPU 104 for primitive topologies 200(0)-200(10) determined according to the above rules, is summarized in Table 1 below: Table 1

[0047] Apply the above rules Figure 3Given indices 110(0)-110(11) of the index buffer 108 shown, GPU 104 will first determine the position of restart index 110(6). Since the position of restart index 110(6) is not within the first three (3) positions of index buffer 108, GPU 104 will determine whether the position of restart index 110(6) follows the first ordinal primitive (i.e., the triangle primitive 304(0) defined by indices 110(0)-110(2)). Figure 3 In the example, the position of restart index 110(6) is after triangle primitive 304(0), so the value of skip count 116 is set to one (1) (by...). Figure 4 The heading "SKIP 1" indicates this.

[0048] As noted above, during the tile sorting iteration, Figure 1 The GPU 104 also checks the visibility of each triangle primitive in triangle primitives 304(0)-304(6) and generates a visibility state 118(0)-118(6) (in Figure 4 The visibility state 120 is labeled “VIZ / INVIZ”. The visibility data 120 is then used during tile rendering passes to assemble triangle primitives 304(0)-304(3) and 304(4)-304(6). In normal operation, the GPU 104 marks subsequent triangle primitives (e.g., primitives 304(4)-304(6) in this example) as visible for all tiles when it encounters a restart index 110(6). However, in some aspects disclosed herein, the GPU 104 determines the appropriate visibility states 118(0)-118(6) for all triangle primitives 304(0)-304(6) and generates visibility data 120 that includes the visibility states 118(0)-118(6) and a skip count 116.

[0049] During the tile rendering pass, GPU 104 assembles triangle primitives 304(0)-304(6) based on visibility data 120, thereby generating primitive assembly data 400. Figure 4 In the example, primitive assembly data 400 includes vertex data for each of the triangle primitives 304(0)-304(6), and also includes a skip count 116 to indicate that the retrieval of restart index 110(6) should be bypassed.

[0050] To illustrate, based on some aspects, Figure 1 The exemplary operations performed by the GPU 104 for efficiently handling restarted indexes during TBDR are as follows. Figures 5A to 5B A flowchart illustrating exemplary operation 500 is provided. For clarity, in the description... Figures 5A to 5B Referenced at the time Figure 1 , Figure 2A and Figure 2B The elements. It should be understood that, in some respects, some exemplary operations in Exemplary Operation 500 may be performed in a different order than that illustrated herein and / or may be omitted.

[0051] Example operation 500 in Figure 5A The processor circuitry that begins with the GPU (e.g., Figure 1 The processor circuitry 106 of the GPU 104 performs operations during the tile sorting iteration (box 502). During the tile sorting iteration, the processor circuitry 106 determines the primitive topology (such as...) Figure 2A The triangular fan primitive topology 200(6)) is associated with multiple indices in the index buffer (e.g., Figure 1 and Figure 3 The restart index (such as index 110(0)-110(N)) in the index buffer 108) Figure 3 The location of the restart index 110(6) (box 504). The processor circuit 106 then determines the skip count (e.g., based on the primitive topology 200(6) and the location of the restart index 110(6)). Figure 1 and Figure 4 The skip count (116) indicates the number of indices to be skipped in a plurality of indices 110(0)-110(N) during a tile rendering pass (box 506).

[0052] In some aspects, the operation of block 506 for determining skip count 116 may include processor circuitry 106 determining that the position of restart index 110(6) is within the first V indices of a plurality of indices 110(0)-110(N), wherein primitive topology 200(6) is defined by a minimum number of V indices of the plurality of indices 110(0)-110(N) (block 508). In response to determining that the position of restart index 110(6) is within the first V indices of the plurality of indices 110(0)-110(N), in such an aspect, processor circuitry 106 determines that skip count 116 is equal to the position of restart index 110(6) (block 510). According to some aspects, the operation of block 506 for determining skip count 116 may include processor circuitry 106 determining that the position of restart index 110(6) is within one or more primitives (such as... Figure 3 The ordinal first primitive in the triangular primitives 304(0)-304(6)) (e.g., Figure 3Following the triangular primitive 304(0) (box 512). In response to determining that the position of the restart index 110(6) follows the ordinal first primitive 304(0) in one or more primitives 304(0)-304(6), in such respect, the processor circuitry 106 determines that the skip count 116 equals one (1) (box 514). In some aspects, exemplary operation 500 can then be performed Figure 5B Continue at frame 516.

[0053] Now for reference Figure 5B Some aspects allow for the performance of further operations during tile sorting iterations (box 502). In some aspects, processor circuitry 106 can determine one or more visibility states (such as...) corresponding to one or more primitives 304(0)-304(6). Figure 4 The visibility states 118(0)-118(6) (box 516). The processor circuit 106 then generates visibility data (such as visibility states 118(0)-118(6) and skip count 116) including one or more visibility states 118(0)-118(6) and skip count 116. Figure 4 Visibility data 120 (box 518).

[0054] Processor circuit 106 then performs operations during tile rendering iterations (box 520). Processor circuit 106 bypasses the acquisition of restart index 110(6) based on skip count 116 (box 522). According to some aspects, processor circuit 106 may also assemble one or more primitives 304(0)-304(6) based on visibility data 120 (box 524).

[0055] Based on the information disclosed in this article and referenced Figure 1 The GPUs discussed in these aspects can be set up or integrated into any processor-based device. Examples, without limitation, include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, laptops, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multi-rotor aircraft.

[0056] in this regard, Figure 6 Examples are given regarding Figure 1 An example of a processor-based device 600 is illustrated and described. In this example, it functionally corresponds to... Figure 1 The processor-based device 100 and the processor-based device 600 include a central processing unit (CPU) 602, which includes one or more processors 604 coupled to a cache memory 606. The processors 604 are also coupled to a system bus 608 and can be interactively coupled to devices included in the processor-based device 600. It is known that the processors 604 communicate with these other devices by exchanging address, control, and data information on the system bus 608. For example, the processors 604 can communicate bus transaction requests to a memory controller 610. Although in Figure 6 Not illustrated, but multiple system buses 608 may be provided, each of which constitutes a different architecture.

[0057] Other devices can be connected to system bus 608. For example... Figure 6 As illustrated, these devices may include a memory system 612, one or more input devices 614, one or more output devices 616, one or more network interface devices 618, and one or more display controllers 620. Input devices 614 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output devices 616 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Network interface devices 618 may be any device configured to allow data exchange to and from network 622. Network 622 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), and Bluetooth. ™ Networks and the Internet. Network interface device 618 can be configured to support any type of communication protocol desired. Memory system 612 may include a memory controller 610 coupled to one or more memory arrays 624. Display controller may include, for example... Figure 1 GPU 104.

[0058] The processor 604 may also be configured to access the display controller 620 via the system bus 608 to control the transmission of information to one or more displays 630. The display controller 620 transmits information to be displayed to the displays 630 via one or more video processors 632, which process the information to be displayed into a format suitable for the displays 630. The displays 630 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc.

[0059] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. As an example, the master and slave devices described herein can be employed in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, the functionality of the various exemplary components, blocks, modules, circuits, and steps has been generally described above. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0060] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic unit, discrete hardware component, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0061] The aspects disclosed herein may be embodied in hardware and instructions stored in the hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0062] It should also be noted that the operational steps described in any of the exemplary aspects of this document are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than the order illustrated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps illustrated in the flowcharts. Those skilled in the art will also understand that any of a variety of different techniques and arts can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0063] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0064] Specific implementation examples are described in the following numbered clauses: 1. A graphics processing unit (GPU), the graphics processing unit (GPU) comprising: An index buffer, which is associated with the primitive topology and includes multiple indices; and Processor circuitry, the processor circuitry being configured to: During the tile sorting iteration: Determine the location of the restart index among the plurality of indices in the index buffer; and A skip count is determined based on the primitive topology and the position of the restart index, the skip count indicating the number of indices to be skipped among the plurality of indices during a tile rendering pass; and During the tile rendering iteration, the retrieval of the restart index is bypassed based on the skip count.

[0065] 2. The GPU according to Clause 1, wherein the primitive topology includes one of a point list, a line list, a line strip, a line loop, a triangle list, a triangle strip, a triangle fan, a line list with adjacencies, a line strip with adjacencies, a triangle list with adjacencies, and a triangle strip with adjacencies.

[0066] 3. The GPU according to any one of Clauses 1 to 2, wherein the plurality of indexes define one or more primitives of the primitive topology.

[0067] 4. The GPU according to Clause 3, wherein the processor circuitry is further configured to: Determine one or more visibility states corresponding to the one or more primitives; and Generate visibility data that includes the one or more visibility states and the skip count.

[0068] 5. The GPU as described in Clause 4, wherein the processor circuitry is further configured to assemble the one or more primitives based on the visibility data during the tile rendering pass.

[0069] 6. The GPU according to any one of clauses 3 to 5, wherein: The primitive topology is defined by the minimum number V indices among the plurality of indices; and The processor circuitry is configured to determine the skip count by being configured to perform the following operations: The position of the restart index is determined to be within the first V indexes of the plurality of indexes; and In response to determining that the position of the restart index is within the first V indices of the plurality of indices, the position where the skip count is equal to the restart index is determined.

[0070] 7. The GPU according to any one of clauses 3 to 6, wherein the processor circuitry is configured to determine the skip count by being configured to perform the following operations: The position of the restart index is determined to be after the ordinal first primitive in the one or more primitives; and In response to determining that the position of the restart index is after the ordinal first primitive of the one or more primitives, the skip count is determined to be equal to one (1).

[0071] 8. The GPU according to any one of Clauses 1 to 7, wherein the GPU is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; phablets; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multirotor aircraft.

[0072] 9. A graphics processing unit (GPU), the graphics processing unit (GPU) comprising: A component used to determine the location of the restart index among multiple indices in the index buffer during tile sorting iterations; A component for determining a skip count based on primitive topology and the position of the restart index during the tile sorting pass, the skip count indicating the number of indices to be skipped among the plurality of indices during the tile rendering pass; and A component for bypassing the acquisition of the restart index based on the skip count during the tile rendering cycle.

[0073] 10. A method for efficiently disposing of a restart index by a graphics processing unit (GPU) during tile-based deferred rendering (TBDR), the method comprising: During the tile sorting iteration: The GPU's processor circuitry determines the location of the restart index among multiple indices in the index buffer associated with the primitive topology; and The processor circuitry determines a skip count based on the primitive topology and the position of the restart index, the skip count indicating the number of indices to be skipped among the plurality of indices during a tile rendering pass; and During the tile rendering iteration, the processor circuitry bypasses the acquisition of the restart index based on the skip count.

[0074] 11. The method according to Clause 10, wherein the primitive topology includes one of a point list, a line list, a line strip, a line loop, a triangle list, a triangle strip, a triangle sector, a line list with adjacencies, a line strip with adjacencies, a triangle list with adjacencies, and a triangle strip with adjacencies.

[0075] 12. The method according to any one of Clauses 10 to 11, wherein the plurality of indexes define one or more primitives of the primitive topology.

[0076] 13. The method according to Clause 12, further comprising: Determine one or more visibility states corresponding to the one or more primitives; and Generate visibility data that includes the one or more visibility states and the skip count.

[0077] 14. The method according to Clause 13, further comprising assembling the one or more primitives based on the visibility data during the tile rendering pass.

[0078] 15. The method according to any one of clauses 12 to 14, wherein: The primitive topology is defined by the minimum number V indices among the plurality of indices; and Determining the skip count includes: The position of the restart index is determined to be within the first V indexes of the plurality of indexes; and In response to determining that the position of the restart index is within the first V indices of the plurality of indices, the position where the skip count is equal to the restart index is determined.

[0079] 16. The method according to any one of clauses 12 to 15, wherein determining the skip count comprises: The position of the restart index is determined to be after the ordinal first primitive in the one or more primitives; and In response to determining that the position of the restart index is after the ordinal first primitive of the one or more primitives, the skip count is determined to be equal to one (1).

[0080] 17. A non-transitory computer-readable medium storing computer-executable instructions that, when executed, cause a processor of a processor-based device to: During the tile sorting iteration: Determine the location of the restart index among multiple indices in the index buffer associated with the primitive topology; and A skip count is determined based on the primitive topology and the position of the restart index, the skip count indicating the number of indices to be skipped among the plurality of indices during a tile rendering pass; and During the tile rendering iteration, the retrieval of the restart index is bypassed based on the skip count.

[0081] 18. The non-transitory computer-readable medium according to Clause 17, wherein the primitive topology includes one of a point list, a line list, a line strip, a line loop, a triangle list, a triangle strip, a triangle sector, a line list with adjacencies, a line strip with adjacencies, a triangle list with adjacencies, and a triangle strip with adjacencies.

[0082] 19. A nontransitory computer-readable medium according to any one of Clauses 17 to 18, wherein the plurality of indexes define one or more primitives of the primitive topology.

[0083] 20. The non-transitory computer-readable medium according to Clause 19, wherein the computer-executable instructions further cause the processor to: Determine one or more visibility states corresponding to the one or more primitives; and Generate visibility data that includes the one or more visibility states and the skip count.

[0084] 21. The non-transitory computer-readable medium according to Clause 20, wherein the computer-executable instructions further cause the processor to assemble the one or more primitives based on the visibility data during the tile rendering pass.

[0085] 22. A non-transitory computer-readable medium according to any one of clauses 19 to 21, wherein: The primitive topology is defined by the minimum number V indices among the plurality of indices; and The computer-executable instructions cause the processor to determine the skip count by causing the processor to perform the following operations: The position of the restart index is determined to be within the first V indexes of the plurality of indexes; and In response to determining that the position of the restart index is within the first V indices of the plurality of indices, the position where the skip count is equal to the restart index is determined.

[0086] 23. A non-transitory computer-readable medium according to any one of clauses 19 to 22, wherein the computer-executable instructions cause the processor to determine the skip count by causing the processor to perform the following: The position of the restart index is determined to be after the ordinal first primitive in the one or more primitives; and In response to determining that the position of the restart index is after the ordinal first primitive of the one or more primitives, the skip count is determined to be equal to one (1).

Claims

1. A graphics processing unit (GPU), the graphics processing unit (GPU) comprising: An index buffer, which is associated with the primitive topology and includes multiple indices; and Processor circuitry, the processor circuitry being configured to: During the tile sorting iteration: Determine the location of the restart index among the plurality of indexes in the index buffer; as well as A skip count is determined based on the primitive topology and the position of the restart index, the skip count indicating the number of indices to be skipped among the plurality of indices during a tile rendering pass; as well as During the tile rendering iteration, the retrieval of the restart index is bypassed based on the skip count.

2. The GPU of claim 1, wherein the primitive topology includes one of a point list, a line list, a line strip, a line loop, a triangle list, a triangle strip, a triangle fan, a line list with adjacencies, a line strip with adjacencies, a triangle list with adjacencies, and a triangle strip with adjacencies.

3. The GPU of claim 1, wherein the plurality of indexes define one or more primitives of the primitive topology.

4. The GPU of claim 3, wherein the processor circuitry is further configured to: Determine one or more visibility states corresponding to the one or more primitives; and Generate visibility data that includes the one or more visibility states and the skip count.

5. The GPU of claim 4, wherein the processor circuitry is further configured to assemble the one or more primitives based on the visibility data during the tile rendering pass.

6. The GPU according to claim 3, wherein: The primitive topology is defined by the minimum number V indices among the plurality of indices; and The processor circuitry is configured to determine the skip count by being configured to perform the following operations: The position of the restart index is determined to be within the first V indexes of the plurality of indexes; as well as In response to determining that the position of the restart index is within the first V indices of the plurality of indices, the position where the skip count is equal to the restart index is determined.

7. The GPU of claim 3, wherein the processor circuitry is configured to determine the skip count by being configured to perform the following operations: The position of the restart index is determined to be after the ordinal first primitive in the one or more primitives; and In response to determining that the position of the restart index is after the ordinal first primitive of the one or more primitives, the skip count is determined to be equal to one (1).

8. The GPU of claim 1, wherein the GPU is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multi-rotor aircraft.

9. A graphics processing unit (GPU), the graphics processing unit (GPU) comprising: A component used to determine the location of the restart index among multiple indices in the index buffer during tile sorting iterations; A component for determining a skip count based on primitive topology and the position of the restart index during the tile sorting cycle, the skip count indicating the number of indices to be skipped among the plurality of indices during the tile rendering cycle; and A component for bypassing the acquisition of the restart index based on the skip count during the tile rendering cycle.

10. A method for efficiently disposing of a restart index by a graphics processing unit (GPU) during tile-based deferred rendering (TBDR), the method comprising: During the tile sorting iteration: The GPU's processor circuitry determines the location of the restart index among multiple indices in the index buffer associated with the primitive topology; as well as The processor circuitry determines a skip count based on the primitive topology and the position of the restart index, the skip count indicating the number of indices to be skipped among the plurality of indices during a tile rendering pass; as well as During the tile rendering iteration, the processor circuitry bypasses the acquisition of the restart index based on the skip count.

11. The method of claim 10, wherein the primitive topology includes one of a point list, a line list, a line strip, a line loop, a triangle list, a triangle strip, a triangle sector, a line list with adjacencies, a line strip with adjacencies, a triangle list with adjacencies, and a triangle strip with adjacencies.

12. The method of claim 10, wherein the plurality of indexes define one or more primitives of the primitive topology.

13. The method according to claim 12, further comprising: Determine one or more visibility states corresponding to the one or more primitives; as well as Generate visibility data that includes the one or more visibility states and the skip count.

14. The method of claim 13, further comprising assembling the one or more primitives based on the visibility data during the tile rendering pass.

15. The method according to claim 12, wherein: The primitive topology is defined by the minimum number V indices among the plurality of indices; and Determining the skip count includes: The position of the restart index is determined to be within the first V indexes of the plurality of indexes; as well as In response to determining that the position of the restart index is within the first V indices of the plurality of indices, the position where the skip count is equal to the restart index is determined.

16. The method of claim 12, wherein determining the skip count comprises: The position of the restart index is determined to be after the ordinal first primitive in one or more primitives; as well as In response to determining that the position of the restart index is after the ordinal first primitive of the one or more primitives, the skip count is determined to be equal to one (1).

17. A non-transitory computer-readable medium storing computer-executable instructions that, when executed, cause a processor of a processor-based device to: During the tile sorting iteration: Determine the location of the restart index among multiple indices in the index buffer associated with the primitive topology; and A skip count is determined based on the primitive topology and the position of the restart index, the skip count indicating the number of indices to be skipped among the plurality of indices during a tile rendering pass; and During the tile rendering iteration, the retrieval of the restart index is bypassed based on the skip count.

18. The non-transitory computer-readable medium of claim 17, wherein the primitive topology includes one of a point list, a line list, a line strip, a line loop, a triangle list, a triangle strip, a triangle sector, a line list with adjacent elements, a line strip with adjacent elements, a triangle list with adjacent elements, and a triangle strip with adjacent elements.

19. The non-transitory computer-readable medium of claim 17, wherein the plurality of indexes define one or more primitives of the primitive topology.

20. The non-transitory computer-readable medium of claim 19, wherein the computer-executable instructions further cause the processor to: Determine one or more visibility states corresponding to the one or more primitives; and Generate visibility data that includes the one or more visibility states and the skip count.

21. The non-transitory computer-readable medium of claim 20, wherein the computer-executable instructions further cause the processor to assemble the one or more primitives based on the visibility data during the tile rendering pass.

22. The non-transitory computer-readable medium according to claim 19, wherein: The primitive topology is defined by the minimum number V indices among the plurality of indices; and The computer-executable instructions cause the processor to determine the skip count by causing the processor to perform the following operations: The position of the restart index is determined to be within the first V indexes of the plurality of indexes; as well as In response to determining that the position of the restart index is within the first V indices of the plurality of indices, the position where the skip count is equal to the restart index is determined.

23. The non-transitory computer-readable medium of claim 19, wherein the computer-executable instructions cause the processor to determine the skip count by causing the processor to perform the following operations: The position of the restart index is determined to be after the ordinal first primitive in the one or more primitives; and In response to determining that the position of the restart index is after the ordinal first primitive of the one or more primitives, the skip count is determined to be equal to one (1).

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