Voltage regulation method, electronic equipment and readable storage medium

Abstract

The invention discloses a voltage regulation method, electronic equipment and a readable storage medium, and belongs to the field of electronic equipment. The method comprises the steps that in response to abnormal operation of the electronic equipment, first voltage of a chip in the electronic equipment is obtained, and the first voltage is voltage causing the abnormal operation or default working voltage of the chip; boosting the first voltage of the chip to a second voltage; and controlling the chip to work by taking the second voltage as a working voltage.

Description

Technical Field

[0001] This application belongs to the field of electronic devices, specifically relating to a voltage regulation method, an electronic device, and a readable storage medium. Background Technology

[0002] During chip manufacturing, due to variations in die distribution across the wafer, chips exhibit inherent quality differences. Under identical external conditions and when operating the same application, some chips with lower quality require higher operating voltages to function stably. Therefore, chip manufacturers perform quality testing on each chip before shipping, calibrating appropriate voltage values ​​based on the chip's inherent quality. For example, higher voltage values ​​are calibrated for chips with lower quality to ensure stable operation.

[0003] However, the accuracy rate of current chip quality calibration cannot reach 100%, meaning it cannot be guaranteed that the quality calibration results for every chip will be accurate. Consequently, in electronic devices manufactured based on these chips, a small percentage may malfunction due to insufficient calibrated voltage values, resulting in abnormal phenomena such as crashes, restarts, or screen glitches. For example, out of one million mobile phones produced, perhaps 100 may be unable to function stably.

[0004] Currently, related technologies typically ignore abnormal phenomena in a small number of electronic devices, which means that these devices may still experience stability issues. Summary of the Invention

[0005] This application provides a voltage regulation method, an electronic device, and a readable storage medium, which can solve the stability problem caused by insufficient voltage in related electronic devices.

[0006] In a first aspect, embodiments of this application provide a voltage regulation method, including: In response to an operational malfunction in the electronic device, a first voltage of a chip within the electronic device is acquired. The first voltage is either the voltage that caused the operational malfunction or the default operating voltage of the chip. Increase the first voltage of the chip to the second voltage; The chip is controlled to operate using the second voltage as its working voltage.

[0007] In a second aspect, embodiments of this application provide an electronic device, including a processor and a memory, wherein the memory stores a program or instructions, which, when executed by the processor, implement the method described in the first aspect.

[0008] Thirdly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the method described in the first aspect.

[0009] Fourthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the method described in the first aspect.

[0010] In this embodiment, in response to an operational malfunction in the electronic device, a first voltage of a chip within the electronic device is acquired. This first voltage is either the voltage that caused the malfunction or the chip's default operating voltage. The first voltage of the chip is then increased to a second voltage. The chip is then controlled to operate using the second voltage. Thus, by increasing the operating voltage of the electronic device, the stability problem caused by insufficient operating voltage can be resolved. Furthermore, this embodiment only adjusts the voltage of the malfunctioning electronic device. Compared to related technologies that directly increase the operating voltage of all electronic devices, this embodiment does not cause unnecessary power consumption to other normally operating electronic devices. It can solve the stability problem caused by insufficient voltage in a small number of electronic devices without sacrificing the power consumption benefits of most electronic devices. Attached Figure Description

[0011] Figure 1 This is a flowchart of a voltage regulation method provided in an embodiment of this application; Figure 2 This is a flowchart of another voltage regulation method provided in the embodiments of this application; Figure 3 This is an example flowchart of a voltage regulation method provided in an embodiment of this application; Figure 4 This is a flowchart of another voltage regulation method provided in the embodiments of this application; Figure 5 This is an example flowchart of another voltage regulation method provided in the embodiments of this application; Figure 6 This is a flowchart of another voltage regulation method provided in the embodiments of this application; Figure 7 This is a flowchart of another voltage regulation method provided in the embodiments of this application; Figure 8 This is an example flowchart of another voltage regulation method provided in the embodiments of this application; Figure 9 This is a detailed flowchart of a voltage regulation method provided in an embodiment of this application; Figure 10 This is a structural block diagram of a voltage regulation device provided in an embodiment of this application; Figure 11 This is a structural block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0012] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0013] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0014] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0015] The following is a brief introduction to multi-power domain design of chips, taking a System-on-Chip (SoC) chip as an example. An SoC chip is a chip that integrates many functional modules, typically including a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a memory controller, a Multi-media module, a Display Processing Unit (DPU), a Vision Processing Unit (VPU), and a communication module, etc. The aim is to integrate as many functions as possible onto a single chip to achieve high integration and reduce chip area.

[0016] As manufacturing processes evolve from 20 nanometers (nm) to 14 nanometers (nm), then to 7 nanometers (nm), then to 5 nanometers (nm), and finally to 3 nanometers (nm), different processes require different operating voltages. Modules that support systems need to evolve with the manufacturing process to achieve higher transistor density, improve computing power, and reduce energy consumption, such as CPUs and GPUs. Modules that do not support systems, such as Inter-Integrated Circuit (I2C) bus interfaces, Serial Peripheral Interface (SPI), and Universal Serial Bus (USB) interfaces, have operating speeds constrained by protocols and do not need to be as fast as possible. Therefore, a standard process such as 14 nanometers (nm) is sufficient. Therefore, for power consumption considerations, the CPU and I / O interfaces need to be powered by two separate power domains, which is the multi-power-domain design. However, it should be noted that the embodiments in this application do not limit the chip to using a multi-power-domain power strategy; it can also be applied to voltage regulation of chips using a single power domain.

[0017] Due to consistency issues in chip manufacturing, chips exhibit inherent variations, typically falling into the categories of Fast N-type Metal Oxide Semiconductor Field Effect Transistor (FF), Slow N-type Metal Oxide Semiconductor Field Effect Transistor (SS), Fast Nmos (Slow Pmos), and Slow Nmos (Fast Pmos), and Fast Pmos (SF). At the same operating frequency, the voltage and current required to drive an FF chip are lower than those required to drive an SS chip. Conversely, with the same voltage and current, chips with FF chips operate at higher frequencies than those with SS chips. In other words, chips with FF chips have better energy efficiency than those with SS chips. To leverage the advantages of FF, chip manufacturers test the chips during manufacturing and mark the properties of each chip and its required operating voltage.

[0018] Currently, the accuracy of chip quality calibration is limited, making it impossible to precisely pinpoint the quality of each individual chip; the accuracy rate is approximately 99.99%. Assuming a mobile phone manufacturer produces 1 million phones using these chips, roughly 100 phones will experience instability issues due to inaccurate chip calibration voltage, such as crashes, restarts, and screen glitches. This will lead to customer complaints and returns, negatively impacting the manufacturer's reputation and incurring significant analysis and repair costs.

[0019] The voltage regulation method provided in this application is applied to electronic devices that exhibit abnormal phenomena (such as system crashes, screen flickering, and restarts). It can increase the operating voltage of the chip in the electronic device exhibiting abnormal phenomena to solve the stability problem caused by insufficient operating voltage of the chip in the electronic device. It can also minimize the occurrence of the same abnormal phenomena in subsequent electronic devices and solve a series of problems caused by the stability issues of the aforementioned electronic devices.

[0020] The voltage regulation method provided in this application embodiment can be executed by an electronic device, wherein the electronic device can be an electronic device equipped with a chip, such as a mobile phone, tablet, laptop computer and other terminal devices.

[0021] The voltage regulation method provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0022] Please refer to Figure 1 , Figure 1 This is a flowchart of a voltage regulation method provided in an embodiment of this application. Figure 1 As shown, the method includes the following steps: Step 110: In response to an operational malfunction in the electronic device, obtain the first voltage of the chip inside the electronic device. The first voltage is either the voltage that caused the operational malfunction or the default operating voltage of the chip.

[0023] In this embodiment, operational anomalies include, for example, system crashes, screen glitches, or restarts. The triggering cause of these anomalies is, for example, insufficient operating voltage of the chip. The chip can be a chip using a single power domain power strategy or a chip using a multi-power domain power strategy. Taking a chip using a single power domain power strategy as an example, the first voltage can be the calibration voltage of a single power domain in the chip. The calibration voltage is the default operating voltage calibrated for that single power domain during the chip's body calibration process. This embodiment does not limit the specific type of chip; the chip can be, for example, a SoC chip. The first voltage can be a voltage that potentially causes operational anomalies; that is, insufficient first voltage may cause operational anomalies in the electronic device. In one example, the first voltage is the voltage that causes the operational anomaly, and the first voltage is the chip's default operating voltage. In another example, the first voltage is merely the chip's default operating voltage, and the operational anomaly is not caused by insufficient first voltage.

[0024] Step 120: Increase the first voltage of the chip to the second voltage.

[0025] In this embodiment, the chip's operating voltage boost is performed when the electronic device experiences an operational malfunction. That is, in response to an operational malfunction, the chip's first voltage can be boosted to a second voltage. By boosting the chip's operating voltage from the first voltage to the second voltage, subsequent malfunctions caused by insufficient chip operating voltage can be avoided. During the boosting process, the second voltage can be determined by the sum of the first voltage and a preset voltage boost value. The specific value of the voltage boost is not limited; for example, a voltage boost value of 30 millivolts (mV) can be used. Furthermore, excessively large or small voltage boost values ​​can be avoided. If the voltage boost value is too large, the chip's power consumption will be too high; if the voltage boost value is too small, the stability problem of the electronic device may not be completely resolved, increasing the likelihood of subsequent operational malfunctions.

[0026] Step 130: The control chip operates using the second voltage as its working voltage.

[0027] Taking a chip using a single power domain power strategy as an example, the initial voltage is 1.0 volt (V), with a voltage boost of 30 millivolts (mV). In the event of an electronic device malfunction, the chip's operating voltage can be increased from 1.0 volt (V) to 1.03 volt (V). The chip then continues to operate at 1.03 volt (V). If the chip's operating voltage is sufficient at this point, the subsequent electronic device will no longer experience the malfunction.

[0028] In this embodiment, in response to an malfunction in the electronic device, a first voltage of the chip within the electronic device is acquired. This first voltage is either the voltage that caused the malfunction or the chip's default operating voltage. The first voltage of the chip is then increased to a second voltage. The chip is then controlled to operate using the second voltage. Thus, by increasing the operating voltage of the electronic device, the stability problem caused by insufficient operating voltage can be resolved. Furthermore, this embodiment only adjusts the voltage of the malfunctioning electronic device. Compared to related technologies that directly increase the operating voltage of all electronic devices, this embodiment does not cause unnecessary power consumption to other normally operating electronic devices. It can solve the stability problem caused by insufficient voltage in a small number of electronic devices without sacrificing the power consumption benefits of most electronic devices.

[0029] Please see Figure 2 , Figure 2 This is a flowchart of another voltage regulation method provided in an embodiment of this application. For example... Figure 2 As shown, the method includes the following steps: Step 210: In response to an operational malfunction in the electronic device, obtain the first voltage of the chip inside the electronic device. The chip includes N power domains, where N is an integer greater than 1.

[0030] In this embodiment, the chip is divided into N power domains. Taking a SoC chip as an example, the SoC chip can be divided into multiple independent power supply areas, each of which is a power domain. Each independent power domain has its own power supply pins and ground lines, and can be independently powered on, powered off, and have its voltage or frequency adjusted. Generally, an SoC chip can provide one independent power domain for high-performance computing units such as the CPU, and another independent power domain for I / O interfaces, to achieve fine-grained power management.

[0031] Step 220: Increase the first voltage of the chip to the second voltage. The first voltage is the default operating voltage of the target power domain among the N power domains.

[0032] In the embodiments of this application, the target power domain can be one or more power domains from N power domains. That is, the operating voltage of one power domain from the N power domains can be increased, or the operating voltage of multiple power domains from the N power domains can be increased. If the target power domain includes multiple power domains from the N power domains, then during the process of increasing the first voltage of the chip to the second voltage, the operating voltage of multiple power domains can be increased simultaneously; or, the operating voltage of one power domain can be increased at a time, and multiple voltage increase operations can be performed.

[0033] Step 230: The module located in the target power domain on the control chip operates using the second voltage as its working voltage.

[0034] In this embodiment, the module can be a functional module located within the target power domain on the chip, such as the CPU, GPU, or I / O interface described above. Since the modules located within the target power domain are powered by the same power domain, after the operating voltage of the target power domain is increased from the first voltage to the second voltage, all modules within the target power domain can operate using the second voltage as their operating voltage. However, it should be noted that after controlling the modules located within the target power domain on the chip to operate using the second voltage as their operating voltage in step 230, the operating voltage of the modules located within the target power domain in this embodiment can still be finely adjusted according to factors such as temperature and load, i.e., dynamic voltage frequency adjustment is supported.

[0035] In the embodiments of this application, the chip designed for multiple power domains can increase the operating voltage of the target power domain within the chip only when the electronic device equipped with the chip malfunctions, without having to adjust the operating voltage of all power domains within the chip. This can solve the malfunction of the electronic device while minimizing the chip's power consumption.

[0036] For example, in one embodiment of this application, the target power domain includes M power domains, where M is an integer greater than 1 and less than N. The first voltage includes M first sub-voltages corresponding to the M power domains; the second voltage includes M second sub-voltages corresponding to the M power domains. Step 220, raising the chip's first voltage to the second voltage, includes raising all M first sub-voltages corresponding to the M power domains to obtain M second sub-voltages. Step 230, controlling the modules located within the target power domain on the chip to operate using the second voltage as their working voltage, includes controlling the modules within each of the M power domains to operate according to the corresponding second sub-voltage of each power domain. In this way, by simultaneously raising the working voltages of the M power domains, operational abnormalities caused by insufficient chip working voltage in electronic devices can be resolved more quickly.

[0037] In this embodiment, the M first sub-voltages are the default operating voltages of the M power domains, and the M second sub-voltages are the operating voltages of the M power domains. The voltage boost values ​​corresponding to each power domain can be the same or different. For example, the operating voltages of all M power domains are boosted by 30 millivolts (mV); or the operating voltages of some of the M power domains are boosted by 30 millivolts (mV), while the operating voltages of another portion of the M power domains are boosted by 20 millivolts (mV). For any one of the M power domains, this embodiment does not limit the method for determining the voltage boost value corresponding to that power domain. For example, the voltage boost value corresponding to that power domain can be a preset fixed value; or, the voltage boost value of that power domain can be determined by multiplying the first sub-voltage corresponding to that power domain by a preset ratio.

[0038] The following will describe two methods for determining the target power domain provided in the embodiments of this application.

[0039] In one embodiment of this application, step 210, obtaining the first voltage of the chip in the electronic device, includes: obtaining the probability of each power domain causing an anomaly in N power domains; selecting M power domains from the N power domains as target power domains in descending order of the probability of each power domain causing an anomaly; where M is a positive integer less than N; and obtaining the first voltage of the target power domains.

[0040] Generally, malfunctions in electronic devices are usually caused by a few power domains within the chip, which to some extent confirms the pervasive nature of the Pareto Principle (Pareto Principle). The Pareto Principle states that in many cases, approximately 80% of the results come from 20% of the causes. Simply put, a few key factors have the major impact. Based on this, we can first identify the power domain from N power domains that is most likely to cause malfunctions in the electronic device, defining it as the target power domain. When the electronic device malfunctions, we can infer that the malfunction was caused by the target power domain.

[0041] The probability of each power domain causing anomalies within N power domains can be determined based on experience and chip design. In one example, for chip model A, the probability of power domain A causing stability problems in the first two generations of model A chips was 60%, meaning that most stability problems in the first two generations of model A chips were caused by power domain A. It can be inferred that the probability of power domain A causing stability problems in the next generation of model A chips will still be 60%, meaning that most stability problems in the next generation of model A chips will still be caused by power domain A. In another example, for chip model B, when engineers design chip model B, they can estimate the probability of each power domain causing anomalies based on the specific design of the chip; for example, estimating the probability of power domain B causing anomalies to be 40%.

[0042] In this embodiment, the target power domain can be one or more power domains. If the target power domain is one power domain, the power domain with the highest probability of causing an anomaly among the N power domains can be determined as the target power domain. For example, if 65% of the anomalies in an electronic device are caused by power domain C in the chip, meaning that power domain C in the chip has a 65% probability of causing stability problems, then power domain C can be determined as the target power domain. If the target power domain is multiple power domains, M power domains can be selected from the N power domains in descending order of the probability of causing an anomaly. Here, the value of M is not restricted. For example, if M is 2, two power domains with probabilities of causing an anomaly of 65% and 20% respectively can be selected from the N power domains and determined as the target power domains.

[0043] In one embodiment of this application, step 210, obtaining the first voltage of a chip within the electronic device, includes: if target text exists in the target fault log, obtaining the power domain corresponding to the target text from a pre-established mapping table, and determining the power domain corresponding to the target text as the target power domain; wherein, the target fault log is a fault log generated during the operation of the electronic device, and the target text is text used to indicate the abnormality; the mapping table contains the mapping relationship between the target text and the power domain; and obtaining the first voltage of the target power domain. In this way, by performing text detection in the target fault log, the power domain causing the abnormality can be clearly located, and the obtained target power domain is more closely matched to the operation abnormality of the electronic device, resulting in a better effect in resolving the operation abnormality of the electronic device.

[0044] In this embodiment, the abnormal phenomena caused by insufficient operating voltage in different power domains are usually different, and different abnormal keywords (i.e., target text) are usually generated in the fault log. For each power domain in the electronic device, the target text corresponding to each power domain can be obtained. If the target fault log shows the target text corresponding to a certain power domain, it can be determined that the current abnormal operation of the electronic device is caused by the power domain corresponding to that target text. Taking a certain power domain (VSRAM_CORE power domain) in the chip as an example, if the operating voltage of this power domain is insufficient, it may cause the electronic device to crash, which is recorded as "VCP" in the fault log. In this case, if "VCP" appears in the target fault log when the electronic device is malfunctioning, it can be considered that the abnormal operation of the electronic device is caused by insufficient operating voltage of the VSRAM_CORE power domain, and the VSRAM_CORE power domain can be identified as the target power domain, and the operating voltage of the VSRAM_CORE power domain can be increased.

[0045] In one embodiment of this application, the process of establishing the mapping table includes: performing a buck test on any one of the N power domains; if a test anomaly occurs in the power domain during the buck test, obtaining the target text associated with the test anomaly; and establishing a mapping relationship between the power domain and the target text in the mapping table. In this way, various abnormal phenomena that may occur in electronic devices can be predicted in advance through buck testing. Since the mapping table is obtained by performing a buck test on the chip in advance, it better matches the actual operating state of the chip, and the target power domain obtained through the mapping table is more accurate.

[0046] In this embodiment, during the step-down test of the power domain, the operating voltage of the power domain can be reduced from a first voltage to a test voltage. Specifically, the difference between the first voltage of the power domain and a preset voltage reduction value can be determined as the test voltage. The power domain is then controlled to operate using the test voltage as its operating voltage. The system detects whether any test anomalies occur during the step-down test, such as system crashes, screen glitches, or abnormal shutdowns. If a test anomaly occurs during the step-down test, target text associated with the anomaly can be obtained, thereby establishing a mapping relationship between the target text and the power domain, and storing this mapping relationship in a mapping table. In this embodiment, the target text is associated with the test anomaly, which can be understood as follows: when an electronic device experiences a certain test anomaly, the target text will appear in the fault log generated during the test anomaly. It should be noted that this embodiment does not limit the specific content of the target text; it only needs to ensure that the target text is text used to indicate an anomaly.

[0047] For example, a chip is divided into power domain A and power domain B. A step-down test is performed on power domain A. During this test, insufficient voltage in power domain A causes the electronic device to display a distorted screen. The text associated with this distorted screen is "AAA," and a mapping relationship is established between the text "AAA" and power domain A. Similarly, a step-down test is performed on power domain B. During this test, insufficient voltage in power domain B causes the electronic device to restart abnormally. The text associated with this abnormal restart is "BBB," and a mapping relationship is established between the text "BBB" and power domain B.

[0048] For reference Figure 3 , Figure 3This is an example flowchart of a voltage regulation method provided in this application embodiment. Taking a mobile phone manufacturer conducting a voltage reduction test as an example, after receiving the chip from the chip manufacturer, the manufacturer can perform a voltage reduction test on each power domain of the chip to obtain the abnormal phenomena caused by insufficient operating voltage in each power domain and the text associated with the abnormal phenomena, thereby establishing a mapping relationship between each power domain and the target text. For example, power domain A corresponds to the text "AAA", and power domain B corresponds to the text "BBB". After the mobile phone leaves the factory, the user can use the phone normally. If, during the user's use of the phone, abnormal phenomena related to stability issues such as freezing, abnormal restarts, or screen flickering occur, such as the phone freezing, the phone can automatically save a fault log. After the phone freezes and restarts, the target fault log of the phone can be detected and parsed to determine whether the text corresponding to a certain power domain appears in the target fault log. If it appears, the operating voltage of that power domain is increased to solve the stability problem of the phone. For example, if the text "VCP" is detected in the target fault log, the operating voltage of the VSRAM_CORE power domain can be increased by 30 mV; if the text "AAA" is detected in the target fault log, the operating voltage of power domain A can be increased by 30 mV; and if the text "BBB" is detected in the target fault log, the operating voltage of power domain B can be increased by 30 mV. After voltage adjustment, the user end no longer experiences stability issues, and the mobile phone can operate stably.

[0049] Please see Figure 4 , Figure 4 This is a flowchart of another voltage regulation method provided in an embodiment of this application. For example... Figure 4 As shown, the method includes the following steps: Step 410: In response to an operational malfunction in the electronic device, obtain the first voltage of the chip inside the electronic device. The first voltage is the default operating voltage of the chip.

[0050] Step 420: Increase the first voltage of the chip to the second voltage. The operation of increasing the first voltage of the chip to the second voltage is performed based on the voltage boosting command.

[0051] In this embodiment, the voltage boost command includes a voltage boost value. That is, in response to an operational malfunction in the electronic device, a voltage boost value can be obtained. Based on the voltage boost value, a voltage boost command is obtained; based on the voltage boost command, the chip's operating voltage is boosted from a first voltage to a second voltage.

[0052] Step 430: Store the pressure-release command in the target storage space; wherein the pressure-release command in the target storage space remains after the electronic device performs the target operation, the target operation including at least one of the following: restart operation, power-on operation, and system software upgrade operation.

[0053] In this embodiment, after the voltage boost command is activated in the chip via software, it may become invalid after the electronic device performs the target operation. For example, the voltage boost command may fail after the user actively restarts the electronic device, the electronic device restarts due to depleted battery, or the electronic device undergoes a system software upgrade via Over-the-Air (OTA). In this case, the voltage boost command will only be generated again using the method of this embodiment when the electronic device experiences another operational anomaly.

[0054] To address this issue, this application embodiment stores the pressure-up command in a target storage space after receiving it. The data stored in the target storage space will not be overwritten after the electronic device performs the target operation. This application embodiment does not limit the location of the target storage space; for example, the target storage space may be located outside the chip, such as on the flash memory chip of the electronic device. The target storage space may include read-only memory (ROM), such as electrically erasable programmable read-only memory (EEPROM). However, it should be noted that the target storage space in this application embodiment is not limited to ROM and may also be other storage spaces that will not be overwritten.

[0055] Step 440: During the process of the electronic device performing a restart or power-on operation, read the voltage boost command from the target storage space to boost the chip's first voltage to the second voltage.

[0056] In this embodiment, to ensure that the pressure-raising command is always effective during the operation of the electronic device, the pressure-raising configuration file (including the pressure-raising command) can be read from the target storage space during the restart or power-on operation of the electronic device. It should be noted that step 440 is not limited to being executed before step 450; in fact, step 440 can also be executed after step 450. It is only necessary to ensure that step 440 is executed during the restart or power-on operation of the electronic device, that is, the pressure-raising command can be read from the target storage space within the restart or power-on logic of the electronic device.

[0057] Step 450: The control chip operates using the second voltage as its working voltage.

[0058] For reference Figure 5 , Figure 5 This is an example flowchart of another voltage regulation method provided in the embodiments of this application. Figure 5 Zhongyu Figure 3 The same steps will not be repeated here; please refer to the previous text. Figure 3 The following introduction is only for... Figure 5 The newly added section is expanded upon. In this embodiment, a storage space that remains after the electronic device performs a system software upgrade can be selected on the user end. The target storage space is, for example, partition A on a flash memory chip. Furthermore, in the restart and power-on logic of the electronic device, voltage configuration files (including voltage boost commands) can be read from the target storage space. Figure 5 As shown, after raising the operating voltage of the target power domain, the voltage boost command can be modified and stored in partition A on the flash memory chip. The data stored in partition A will not be overwritten after a system software upgrade. Furthermore, the voltage configuration information can be read from partition A during the phone's boot or restart process. This ensures that even if the user performs a system software upgrade or power-on / off operation, the voltage boost command remains effective throughout the phone's operation, guaranteeing stable subsequent operation.

[0059] Please see Figure 6 , Figure 6 This is a flowchart of another voltage regulation method provided in an embodiment of this application. For example... Figure 6 As shown, the method includes the following steps: Step 610: In response to an operational malfunction in the electronic device, obtain the first voltage of the chip inside the electronic device. The first voltage is the default operating voltage of the chip.

[0060] Step 620: Increase the first voltage of the chip to the second voltage.

[0061] Step 630: The control chip operates using the second voltage as its working voltage.

[0062] Step 640: If the electronic device malfunctions again and the difference between the second voltage and the first voltage is less than the threshold, the second voltage is increased to the third voltage.

[0063] In this embodiment, the threshold value can be used to represent a preset upper limit for voltage boost, and the second and third voltages are both used to represent the chip's operating voltage. If the difference between the second and first voltages is less than the threshold value, it indicates that the voltage boost for the chip's operating voltage has not yet reached the upper limit. If the electronic device still malfunctions at this point, the reason for the malfunction may be that the voltage boost for the chip's operating voltage is insufficient. Therefore, the chip's operating voltage can be further increased from the second voltage to the third voltage. For example, the threshold value can be 50 millivolts (mV). After increasing the chip's operating voltage by 30 millivolts (mV), it can be detected whether the electronic device still malfunctions within a week. If the electronic device still malfunctions within a week, since the increase in the chip's operating voltage has not yet reached 50 millivolts (mV), the chip's operating voltage can be further increased.

[0064] Step 650: The control chip operates using the third voltage as its working voltage.

[0065] In this embodiment, after the chip's operating voltage is increased from the second voltage to the third voltage, the chip can be controlled to operate using the third voltage as its operating voltage. In one embodiment, the chip can be divided into N power domains, where N is an integer greater than 1, and the second voltage is the operating voltage of the target power domain among the N power domains. Step 650, controlling the chip to operate using the third voltage, includes controlling the modules on the chip located within the target power domain to operate using the third voltage as their operating voltage. The process for determining the target power domain can be referred to the preceding text and will not be elaborated here.

[0066] In other words, this application supports multi-level voltage regulation of the chip's operating voltage. This multi-level regulation is not limited to the previously mentioned two-stage regulation; three-stage or even more regulation is also possible, as long as the increase in the chip's operating voltage does not exceed a threshold. Furthermore, this application does not require that the voltage increase value be the same for each regulation. That is, the voltage increase values ​​for multiple regulation stages can be the same or different. For example, the first regulation can increase the chip's operating voltage from 1 volt (V) to 1.03 volt (V), a voltage increase of 30 millivolts (mV); the second regulation can increase the chip's operating voltage from 1.03 volt (V) to 1.05 volt (V), a voltage increase of 20 millivolts (mV). In this way, the chip's operating voltage can be finely adjusted through multiple regulation stages, avoiding excessively high power consumption due to an excessively high adjusted operating voltage.

[0067] Furthermore, in one embodiment, the operation of raising the first voltage of the chip to the second voltage is performed based on a voltage-raising command. After raising the second voltage to the third voltage in step 640, the voltage adjustment method, in addition to steps 610-650 above, further includes: updating the voltage-raising command to obtain an updated voltage-raising command, the updated voltage-raising command being used to instruct the first voltage of the chip to be raised to the third voltage. The updated voltage-raising command is stored in a target memory space; wherein the updated voltage-raising command in the target memory space remains after the electronic device performs a target operation, the target operation including at least one of a restart operation, a power-on operation, and a system software upgrade operation; during the electronic device performing a restart operation or a power-on operation, the updated voltage-raising command is read from the target memory space to raise the first voltage of the chip to the third voltage.

[0068] In one embodiment of this application, after the control chip operates with the second voltage as its working voltage in step 630, the voltage adjustment method, in addition to steps 610-650 described above, further includes: if the electronic device experiences another malfunction and the difference between the second voltage and the first voltage is greater than or equal to a threshold, restoring the chip's working voltage to the first voltage. In this way, for malfunctions not caused by insufficient chip working voltage, the chip's working voltage can be restored to its default working voltage, preventing excessive chip power consumption.

[0069] In this embodiment, if the difference between the second voltage and the first voltage is greater than or equal to a threshold, it indicates that the operating voltage boost for the chip has reached its upper limit. If the electronic device still malfunctions at this point, it means that the malfunction is unrelated to the chip's operating voltage, i.e., it is not caused by chip consistency issues. The malfunction can be characterized as an unknown software anomaly, and the cause can be further investigated.

[0070] Furthermore, embodiments of this application also support combining the two methods described above (fault log detection and the Pareto principle) to determine the target power domain. Specifically, refer to... Figure 7 , Figure 7 This is a flowchart of another voltage regulation method provided in an embodiment of this application. For example... Figure 7 As shown, the method includes the following steps: Step 710: In response to an operational anomaly in the electronic device, obtain the target fault log.

[0071] Step 720: Determine if the target text exists in the target fault log; the chip inside the electronic device includes N power domains.

[0072] Where N is an integer greater than 1, the target fault log is the fault log generated during the operation of the electronic device, and the target text is the text used to indicate the abnormality. If the target text is determined to exist in the target fault log, step 730 can be executed. If the target text is determined not to exist in the target fault log, step 740 can be executed.

[0073] Step 730: Obtain the power domain corresponding to the target text from the pre-established mapping table, and determine the power domain corresponding to the target text as the target power domain.

[0074] In this embodiment, the mapping table contains the mapping relationship between target text and power domains. When the target text is clearly detected in the target fault log, the target power domain causing the anomaly can be located by searching the mapping table. This method of determining the target power domain has a high accuracy rate. The process of establishing the mapping table can be referred to the previous text and will not be elaborated here.

[0075] Step 740: Obtain the probability of each power domain causing an anomaly among the N power domains; select M power domains from the N power domains as target power domains according to the order of the probability of each power domain causing an anomaly from largest to smallest.

[0076] In this embodiment, M is a positive integer greater than 1 and less than N. In practical implementation environments, some correspondences between power domains and text in fault logs remain difficult to detect; that is, the mapping table cannot completely cover all correspondences between power domains and text in fault logs. Therefore, when the target text cannot be detected in the target fault log, the Pareto principle (80 / 20 rule) can be followed to determine one or more power domains with the highest probability of causing the anomaly as the target power domain. This method of determining the target power domain is logically simpler and has a wider range of applications.

[0077] Step 750: Obtain the first voltage of the target power domain. The first voltage is the default operating voltage of the target power domain among N power domains.

[0078] Step 760: Increase the first voltage of the chip to the second voltage.

[0079] Step 770: The module located in the target power domain on the control chip operates using the second voltage as its working voltage.

[0080] To better understand the entire process, please refer to... Figure 8 , Figure 8 This is an example flowchart of another voltage regulation method provided in an embodiment of this application. The following uses an electronic device as an example. Figure 8 Taking mobile phones as an example, Figure 8 Zhongyu Figure 3 , Figure 5 The same steps will not be repeated here; please refer to the previous section for details. Figure 3 and Figure 5 The following introduction is only for... Figure 8 The newly added section will be expanded upon. For example... Figure 8 As shown, if target text is detected in the target fault log, the operating voltage of the power supply domain corresponding to the target text can be increased. If target text is not detected in the target fault log, the operating voltage of the power supply domain with the highest probability of causing the anomaly can be increased, for example... Figure 8 Increase the operating voltage of power domain A by 30 millivolts (mV). After increasing the operating voltage of a power domain, it can be tested whether the phone still exhibits abnormal operation within a week. If the phone still exhibits abnormal operation, the abnormal operation can be characterized as an unknown software anomaly rather than a chip consistency issue, and the voltage increase action can be rolled back, that is, the chip's operating voltage can be restored to the default operating voltage.

[0081] exist Figure 8 After raising the operating voltage of power domain A by 30 millivolts (mV), or after confirming that the phone will not experience any operational abnormalities for a week, the voltage increase command can be modified and stored in a target storage space, such as partition A in the phone's flash memory chip. This partition A will not be overwritten after a system software upgrade. Furthermore, after the phone is powered on or restarted, the voltage configuration information (including the voltage increase command) can be read from partition A. In this way, provided that the phone will not experience any operational abnormalities for a week, this voltage increase scheme can take effect during user upgrades and power-on / off cycles, ensuring stable operation of the phone.

[0082] In this application embodiment, by combining fault log detection and the Pareto principle, a more suitable method can be selected to determine the target power domain according to the scenario adaptability. Compared with using fault log detection or the Pareto principle alone, the method provided in this application embodiment has stronger versatility and better voltage regulation effect.

[0083] Please see Figure 9 , Figure 9 This is a flowchart illustrating a voltage regulation method provided in an embodiment of this application. Figure 9 As shown, the method includes the following steps: Step 910: In response to an operational anomaly in the electronic device, obtain the target fault log.

[0084] Step 920: Determine if the target text exists in the target fault log; the chip inside the electronic device includes N power domains.

[0085] Where N is an integer greater than 1, the target fault log is the fault log generated during the operation of the electronic device, and the target text is the text used to indicate the abnormality. If it is determined that the target fault log contains the target text, proceed to step 930; if it is determined that the target fault log does not contain the target text, proceed to step 940.

[0086] Step 930: Obtain the power domain corresponding to the target text from the pre-established mapping table, and determine the power domain corresponding to the target text as the target power domain.

[0087] In this embodiment of the application, the process of establishing the mapping relationship table includes: performing a step-down test on any one of the N power domains; if a test anomaly occurs in the power domain during the step-down test, obtaining the target text associated with the test anomaly; and establishing a mapping relationship between the power domain and the target text in the mapping relationship table.

[0088] Step 940: Obtain the probability of each power domain causing an anomaly among the N power domains; select M power domains from the N power domains as target power domains according to the order of the probability of each power domain causing an anomaly from largest to smallest.

[0089] Where M is a positive integer less than N.

[0090] Step 950: Obtain the first voltage of the target power domain. The first voltage is the default operating voltage of the target power domain among N power domains.

[0091] Step 960: Increase the first voltage of the chip to the second voltage. The operation of increasing the first voltage of the chip to the second voltage is performed based on the voltage boosting command.

[0092] Step 970: Store the pressure command to the target storage space.

[0093] The pressure-relief commands in the target storage space remain after the electronic device performs the target operation, which includes at least one of the following: restart operation, power-on operation, and system software upgrade operation.

[0094] Step 980: During the restart or power-on operation of the electronic device, read the voltage boost command from the target storage space to boost the chip's first voltage to the second voltage.

[0095] In this embodiment of the application, steps 970-980 are not limited to being performed before step 990. Figure 9 The flowchart shown is only an example, and the process shown in steps 970-980 can also be performed after step 990.

[0096] Step 990: The module located in the target power domain on the control chip operates using the second voltage as its working voltage.

[0097] After the module located in the target power domain on the control chip operates with the second voltage as the working voltage, the voltage adjustment method, in addition to steps 910-990 above, may also include: if the electronic device malfunctions again and the difference between the second voltage and the first voltage is less than a threshold, the second voltage is increased to a third voltage; and the control chip operates with the third voltage as the working voltage.

[0098] After the module located in the target power domain on the control chip operates with the second voltage as the operating voltage, the voltage adjustment method, in addition to steps 910-990 mentioned above, may also include: restoring the chip's operating voltage to the first voltage when the electronic device malfunctions again and the difference between the second voltage and the first voltage is greater than or equal to a threshold.

[0099] In this embodiment, in response to an malfunction in the electronic device, a first voltage of the chip within the electronic device is acquired. This first voltage is either the voltage that caused the malfunction or the chip's default operating voltage. The first voltage of the chip is then increased to a second voltage. The chip is then controlled to operate using the second voltage. Thus, by increasing the operating voltage of the electronic device, the stability problem caused by insufficient operating voltage can be resolved. Furthermore, this embodiment only adjusts the voltage of the malfunctioning electronic device. Compared to related technologies that directly increase the operating voltage of all electronic devices, this embodiment does not cause unnecessary power consumption to other normally operating electronic devices. It can solve the stability problem caused by insufficient voltage in a small number of electronic devices without sacrificing the power consumption benefits of most electronic devices.

[0100] It is important to understand that Figures 1 to 9 The explanations of the same or corresponding steps can be cross-referenced. For example, Figure 1 The explanation of step 110 is applicable to Figure 4 Step 410 and Figure 6 Step 610 in the process.

[0101] Meanwhile, it should be understood that the embodiments of this application are used to compensate for the chip voltage at the overall system level (i.e., to increase the voltage) when the yield rate of the chips provided by the chip manufacturer cannot be changed. This improves the stability of the single machine without sacrificing the power consumption of other chips. Based on the understanding of the relationship between voltage and stability and the accumulation of case experience, the embodiments of this application provide a solution to improve the stability problem caused by abnormal chip quality calibration. In situations where the industry cannot completely solve the problem of accurate quality calibration, it solves the stability problem of 0.01% of chips without sacrificing the power consumption benefits of 99.99% of the chips through overall voltage increase, providing users with a better user experience and improving the company's reputation.

[0102] Please see Figure 10 , Figure 10 This is a structural block diagram of a voltage regulation device provided in an embodiment of this application. Figure 10 As shown in the figure, this application embodiment provides a voltage regulation device 1000, which includes: an acquisition module 1010, an adjustment module 1020, and a control module 1030.

[0103] The acquisition module 1010 is used to acquire the first voltage of the chip in the electronic device in response to an operational abnormality. The first voltage is either the voltage that caused the operational abnormality or the default operating voltage of the chip. The adjustment module 1020 is used to increase the first voltage of the chip to the second voltage; The control module 1030 is used to control the chip to operate using the second voltage as the working voltage.

[0104] In this embodiment, in response to an malfunction in the electronic device, a first voltage of the chip within the electronic device is acquired. This first voltage is either the voltage that caused the malfunction or the chip's default operating voltage. The first voltage of the chip is then increased to a second voltage. The chip is then controlled to operate using the second voltage. Thus, by increasing the operating voltage of the electronic device, the stability problem caused by insufficient operating voltage can be resolved. Furthermore, this embodiment only adjusts the voltage of the malfunctioning electronic device. Compared to related technologies that directly increase the operating voltage of all electronic devices, this embodiment does not cause unnecessary power consumption to other normally operating electronic devices. It can solve the stability problem caused by insufficient voltage in a small number of electronic devices without sacrificing the power consumption benefits of most electronic devices.

[0105] The voltage regulation device provided in this application embodiment can realize the various processes implemented in the above method embodiments, and will not be described again here to avoid repetition.

[0106] like Figure 11As shown, this application embodiment also provides an electronic device 1100. The electronic device 1100 includes a processor 1110 and a memory 1120. The memory 1120 stores programs or instructions, which, when executed by the processor 1110, implement the steps of any of the methods described above. For example, when the program is executed by the processor 1110, it implements the following process: in response to an operational abnormality in the electronic device, a first voltage of a chip within the electronic device is obtained, where the first voltage is the voltage that caused the operational abnormality or the chip's default operating voltage; the first voltage of the chip is increased to a second voltage; and the chip is controlled to operate using the second voltage as its operating voltage. Thus, by increasing the operating voltage of the electronic device, the stability problem caused by insufficient operating voltage of the electronic device can be solved. Furthermore, this application embodiment only adjusts the voltage of the electronic device experiencing the abnormality. Compared to the method in related technologies that directly increases the operating voltage of all electronic devices, this application embodiment does not cause unnecessary power consumption to other normally operating electronic devices, and can solve the stability problem caused by insufficient voltage in a small number of electronic devices without sacrificing the power consumption benefits of most electronic devices.

[0107] This application also provides a readable storage medium storing a program or instructions that, when executed by a processor, implement the steps of various embodiments of the voltage regulation method and achieve the same technical effect. To avoid repetition, these steps will not be repeated here.

[0108] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0109] This application also provides a chip, which includes a processor and a communication interface. The communication interface and the processor are coupled. The processor is used to run programs or instructions to implement the various processes of the above method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0110] This application provides a computer program product that is stored in a storage medium and executed by at least one processor to implement the various processes of the above method embodiments and achieve the same technical effects. To avoid repetition, further details are omitted here.

[0111] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0112] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0113] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A voltage regulation method, characterized in that, include: In response to an operational malfunction in the electronic device, a first voltage of a chip within the electronic device is acquired, wherein the first voltage is either the voltage that caused the operational malfunction or the default operating voltage of the chip; Increase the first voltage of the chip to the second voltage; The chip is controlled to operate using the second voltage as its working voltage.

2. The method according to claim 1, characterized in that, The chip includes N power domains, where N is an integer greater than 1, and the first voltage is the default operating voltage of the target power domain among the N power domains. The control of the chip to operate using the second voltage as the working voltage includes: The module located in the target power domain on the chip is controlled to operate using the second voltage as its operating voltage.

3. The method according to claim 2, characterized in that, The step of obtaining the first voltage of the chip within the electronic device includes: Obtain the probability of each power domain triggering an anomaly among the N power domains; According to the order of probability of each power domain causing anomalies from largest to smallest, M power domains are selected as target power domains from the N power domains; where M is a positive integer less than N. Obtain the first voltage of the target power domain.

4. The method according to claim 2, characterized in that, The step of obtaining the first voltage of the chip within the electronic device includes: If target text exists in the target fault log, the power domain corresponding to the target text is obtained from a pre-established mapping table, and the power domain corresponding to the target text is determined as the target power domain; wherein, the target fault log is a fault log generated during the operation of the electronic device, and the target text is text used to indicate the abnormality; the mapping table contains the mapping relationship between the target text and the power domain; Obtain the first voltage of the target power domain.

5. The method according to claim 4, characterized in that, The step of obtaining the first voltage of the chip inside the electronic device further includes: If the target text is not present in the target fault log, obtain the probability of each power domain in the N power domains causing an anomaly. According to the order of probability of each power domain causing anomalies from largest to smallest, M power domains are selected as target power domains from the N power domains; where M is a positive integer less than N.

6. The method according to claim 2, characterized in that, The target power domain includes M power domains, where M is an integer greater than 1 and less than N. The first voltage includes M first sub-voltages corresponding to the M power domains; the second voltage includes M second sub-voltages corresponding to the M power domains. The step of boosting the first voltage of the chip to the second voltage includes: boosting all M first sub-voltages corresponding to the M power domains to obtain M second sub-voltages; The control of the module located in the target power domain on the chip to operate with the second voltage as the operating voltage includes: controlling the module in each of the M power domains to operate according to the second sub-voltage corresponding to each power domain.

7. The method according to claim 1, characterized in that, The operation of raising the first voltage of the chip to the second voltage is performed based on a voltage-raising command; After increasing the first voltage of the chip to the second voltage, the method further includes: The pressure-release command is stored in the target storage space; wherein the pressure-release command in the target storage space remains after the electronic device performs the target operation, the target operation including at least one of the restart operation, power-on operation, and system software upgrade operation; During the process of the electronic device performing the restart operation or the power-on operation, the voltage boosting command is read from the target storage space to boost the first voltage of the chip to the second voltage.

8. The method according to claim 1, characterized in that, After controlling the chip to operate using the second voltage as the working voltage, the method further includes: If the electronic device experiences the malfunction again and the difference between the second voltage and the first voltage is less than a threshold, the second voltage is increased to a third voltage. The chip is controlled to operate using the third voltage as its working voltage.

9. The method according to claim 1, characterized in that, After controlling the chip to operate using the second voltage as the working voltage, the method further includes: If the electronic device experiences the malfunction again, and the difference between the second voltage and the first voltage is greater than or equal to a threshold, the operating voltage of the chip will be restored to the first voltage.

10. An electronic device, characterized in that, It includes a processor and a memory, the memory storing a program or instructions that, when executed by the processor, implement the method as described in any one of claims 1 to 9.

11. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the method as described in any one of claims 1 to 9.

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