Configuration information writing method, device and system and electronic equipment

Abstract

The invention provides a configuration information writing method, device and system and electronic equipment, relates to the field of chips, and is mainly technically characterized by comprising the following steps: in response to a received test demand, writing an identifier of a chip into a first storage area of the chip; collecting test data of the chip in each test stage, associating the test data with the identifier according to the test stage and then sending the test data to a server, so that the server associates all the test data in different test stages according to the identifier, and generates a configuration data packet based on all the test data; the configuration data packet corresponding to the identifier is obtained from the server, and the configuration data packet is written into the second storage area of the chip, so that the writing frequency of the storage area of the chip is reduced, the utilization efficiency of the storage area is improved, the area and cost of the chip are reduced, and the reliability of the chip is improved. And meanwhile, the writing reliability and the production yield of the configuration information are improved.

Description

Technical Field

[0001] This disclosure relates to the field of chips, and more particularly to a method, apparatus, system, and electronic device for writing configuration information. Background Technology

[0002] During the integrated circuit manufacturing process, a one-time programmable memory area is usually set inside the chip to store the chip's configuration information.

[0003] Currently, chip configuration information is typically written in multiple testing phases. After collecting relevant test data in each testing phase, the test equipment incrementally writes the collected test data into the chip's storage area.

[0004] However, because the above writing method is independent of each test stage, it is impossible to predict the amount of data to be written in subsequent test stages. To avoid write conflicts, redundant bits need to be reserved, resulting in low space utilization of the storage area. In order to accommodate the data written in multiple stages, the capacity of the storage area needs to be expanded, which increases the manufacturing cost of the chip. Multiple write operations affect the reliability of the storage area. Summary of the Invention

[0005] This disclosure provides a method, apparatus, system, and electronic device for writing configuration information. Its main objective is to solve the problems in the prior art where chip configuration information needs to be written to the storage area multiple times during multi-stage testing, resulting in low storage space utilization, high chip cost, and low reliability.

[0006] According to a first aspect of this disclosure, a method for writing configuration information is provided, the method being applied to a test device, comprising:

[0007] In response to a received test request, the chip's identifier is written into the chip's first memory area; The test data of the chip is collected at each test stage, and the test data is associated with the identifier according to the test stage and sent to the server. The server associates all the test data of different test stages according to the identifier and generates a configuration data package based on all the test data. The configuration data packet corresponding to the identifier is obtained from the server, and the configuration data packet is written into the second storage area of ​​the chip.

[0008] In some embodiments, the step of collecting test data of the chip at each test stage, and associating the test data with the identifier according to the test stage and sending it to the server includes: After the completion of any target test phase in each of the test phases, the target test data generated in that target test phase is collected. The target test data is associated with the identifier and then sent to the server until all test phases are completed.

[0009] In some embodiments, the identifier is generated by combining at least two of the following: wafer identification information, chip coordinate location information, production batch number information, and test version number information.

[0010] In some embodiments, after writing the configuration data packet to a second storage area of ​​the chip, the method further includes: Perform data verification on the written data to verify its integrity.

[0011] According to a second aspect of this disclosure, a method for writing configuration information is provided, the method being applied to a server, comprising: Receive test data of the chip collected by the test equipment at each test stage; wherein the test data is associated with the chip's identifier, and the identifier is located in the chip's first storage area; Associate all test data in each test phase with the identifiers, and generate a configuration data package based on all the test data; In response to a request for acquisition carrying an identifier sent by the test device, the configuration data packet corresponding to the identifier is sent to the test device so that the test device writes the configuration data packet into the second storage area of ​​the chip.

[0012] In some embodiments, associating all test data in each test phase according to the identifier and generating a configuration data package based on all the test data includes: Aggregate all test data associated with the identifier to obtain aggregated test data; The aggregated test data is compressed to obtain compressed test data. All the compressed test data are mapped to a predefined storage bit template according to a preset mapping rule to generate the configuration data packet; wherein the predefined storage bit template is defined according to the capacity and bit structure of the second storage area of ​​the chip.

[0013] According to a third aspect of this disclosure, a configuration information writing device is provided, the device being configured in a test device, comprising: The first write unit is used to write the chip's identifier into the first storage area of ​​the chip in response to a received test request. The first sending unit is used to collect test data of the chip in each test stage, associate the test data with the identifier according to the test stage and send it to the server, so that the server associates all test data of different test stages according to the identifier and generates a configuration data packet based on all the test data; The second writing unit is used to obtain the configuration data packet corresponding to the identifier from the server and write the configuration data packet into the second storage area of ​​the chip.

[0014] In some embodiments, the first transmitting unit includes: The acquisition module is used to acquire the target test data generated by the target test stage after the completion of any target test stage in each of the test stages. The sending module is used to associate the target test data with the identifier and send it to the server until all test phases are completed.

[0015] In some embodiments, the identifier is generated by combining at least two of the following: wafer identification information, chip coordinate location information, production batch number information, and test version number information.

[0016] In some embodiments, the apparatus further includes: The verification unit is used to perform data verification on the written data after the second writing unit writes the configuration data packet into the second storage area of ​​the chip, and to verify the integrity of the written data.

[0017] According to a fourth aspect of this disclosure, a configuration information writing device is provided, the device being configured in a server, comprising: A receiving unit is used to receive test data of the chip collected by the test equipment at various test stages; wherein the test data is associated with the chip's identifier, and the identifier is located in the chip's first storage area; A generation unit is configured to associate all test data in each test phase with the identifier and generate a configuration data package based on all the test data. The second sending unit is configured to send the configuration data packet corresponding to the identifier to the test device in response to the acquisition request carrying the identifier sent by the test device, so that the test device writes the configuration data packet into the second storage area of ​​the chip.

[0018] In some embodiments, the generating unit includes: The aggregation module is used to aggregate all test data associated with the identifier to obtain aggregated test data. The compression module is used to compress all the aggregated test data to obtain compressed test data. The generation module is used to map all the compressed test data to a predefined storage bit template according to a preset mapping rule, thereby generating the configuration data packet; wherein the predefined storage bit template is defined according to the capacity and bit structure of the second storage area of ​​the chip.

[0019] According to a fifth aspect of this disclosure, a system for writing configuration information is provided, the system comprising a test device and a server, wherein: The testing equipment includes the apparatus as described in the third aspect above; The server includes the apparatus described in the fourth aspect above.

[0020] According to a sixth aspect of this disclosure, an electronic device is provided, comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the method described in either the first aspect or the second aspect described above.

[0021] According to a seventh aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are configured to cause the computer to perform the method described in either the first or second aspect described above.

[0022] According to the eighth aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the method as described in either the first or second aspect described above.

[0023] In summary, the configuration information writing method, apparatus, system, and electronic device provided in this disclosure include: responding to a received test request by writing a chip identifier into a first storage area of ​​the chip; collecting test data of the chip at each test stage, associating the test data with the identifier according to the test stage, and sending the data to a server, so that the server associates all test data of different test stages according to the identifier and generates a configuration data packet based on all the test data; obtaining the configuration data packet corresponding to the identifier from the server, and writing the configuration data packet into a second storage area of ​​the chip. Compared with related technologies, the solution of this disclosure can achieve unified association of chip data across all test stages through the collaborative cooperation of test equipment and server, relying on the identifier, and completing the one-time writing after generating the configuration data packet based on the full amount of test data. This reduces the number of writes to the chip storage area, improves the utilization efficiency of the storage area, thereby reducing chip area and cost, while improving the reliability and production yield of configuration information writing.

[0024] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0025] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein: Figure 1 A flowchart illustrating a method for writing configuration information provided in an embodiment of this disclosure; Figure 2 A flowchart illustrating another method for writing configuration information provided in an embodiment of this disclosure; Figure 3 A flowchart illustrating another method for writing configuration information provided in an embodiment of this disclosure; Figure 4 This is a schematic diagram of an eFuse logic control circuit provided in an embodiment of the present disclosure; Figure 5 A flowchart illustrating a method for writing configuration information provided in an embodiment of this disclosure; Figure 6 A flowchart illustrating another method for writing configuration information provided in an embodiment of this disclosure; Figure 7 This is a schematic diagram of the structure of a configuration information writing device provided in an embodiment of the present disclosure; Figure 8 A schematic diagram of another configuration information writing device provided in an embodiment of this disclosure; Figure 9This is a schematic diagram of the structure of a configuration information writing device provided in an embodiment of the present disclosure; Figure 10 A schematic diagram of another configuration information writing device provided in an embodiment of this disclosure; Figure 11 This is a schematic diagram of the structure of a configuration information writing system provided in an embodiment of the present disclosure; Figure 12 This is a schematic block diagram of an example electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0026] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0027] The following description, with reference to the accompanying drawings, outlines a method, apparatus, system, and electronic device for writing configuration information according to embodiments of this disclosure.

[0028] Figure 1 This is a flowchart illustrating a method for writing configuration information according to an embodiment of the present disclosure, the method being applied to a test device.

[0029] like Figure 1 As shown, the method includes steps 101-103.

[0030] Step 101: In response to the received test request, the chip's identifier is written into the chip's first storage area.

[0031] In some embodiments, upon receiving a test request, the test equipment begins initialization testing of the chip. The test equipment establishes a communication connection with the chip through a test interface, which includes, but is not limited to, a JTAG interface, an I2C interface, or an SPI interface. The test equipment generates an identifier, which uniquely identifies the chip instance throughout its entire lifecycle. The identifier can be a code generated by the test equipment according to preset rules (e.g., a combination of at least one of the following: identification information of the wafer to which the chip belongs, chip location information on the wafer, production batch information, or test version information); this disclosure does not specifically limit this. The test equipment sends a write command and identifier data to the chip through the test interface. The chip's internal write control logic responds to the write command by writing the identifier data into a first storage area within the chip. The first storage area is a one-time programmable storage area within the chip, such as an eFuse.

[0032] Using the above method, the testing equipment establishes a unique identifier for the chip in the initial stage of chip testing, which facilitates the association and management of subsequent test data.

[0033] Step 102: Collect test data of the chip in each test stage, associate the test data with the identifier according to the test stage and send it to the server, so that the server associates all test data of different test stages according to the identifier and generates a configuration data package based on all the test data.

[0034] In some embodiments, after the chip completes the identifier writing, it enters multiple subsequent testing phases. The testing phases may include wafer probing, aging testing, final testing, system-level testing, etc. This disclosure does not limit the specific type and number of testing phases.

[0035] In each testing phase, the testing equipment performs corresponding test operations on the chip according to preset test vectors and collects the test data generated by the chip in that phase. The test data may include functional test data, performance parameter data, etc., such as signature data required for memory repair, minimum operating voltage data, leakage current data, process parameter data, etc.

[0036] After each test phase, the test equipment associates the test data collected in that phase with the identifier written to the chip in step 101 to form associated test data. The association method includes, but is not limited to, encapsulating the identifier as part of the data packet along with the test data, or attaching the identifier field during transmission; this disclosure does not specifically limit this method.

[0037] The test equipment sends the associated test data to the server via a secure communication channel (such as HyperText Transfer Protocol Secure (HTTPS) or Message Queuing Telemetry Transport (MQTT)). The server receives the test data from the test equipment, each carrying an identifier, and categorizes and stores the received test data according to the identifier; that is, all test data corresponding to the same identifier are associated together. After obtaining all the test data corresponding to the same identifier, the server processes this test data to generate a configuration data packet. The configuration data packet is an optimized and encoded set of configuration information ultimately written to the chip.

[0038] Using the above method, the test equipment uploads the test data generated in each test stage to the server according to the test stage, realizing the centralized aggregation of test data and providing a data foundation for the server to generate optimized configuration data packets.

[0039] Step 103: Obtain the configuration data packet corresponding to the identifier from the server, and write the configuration data packet into the second storage area of ​​the chip.

[0040] In some embodiments, after the chip completes all testing stages, the test device reads the identifier written in step 101 from the chip through a test interface. Based on the read identifier, the test device sends a request to the server to retrieve the configuration data packet corresponding to that identifier. Upon receiving the request, the server locates the configuration data packet associated with that identifier and returns it to the test device. Upon receiving the configuration data packet, the test device sends a write command and configuration data packet data to the chip through the test interface. The chip's internal write control logic responds to the write command and writes the configuration data packet data to the second storage area within the chip. The second storage area is a one-time programmable storage area within the chip. It should be noted that the "first storage area" and "second storage area" in this embodiment are actually logical divisions within the same physical storage area.

[0041] Using the above method, the test equipment performs a write operation only once in the final stage of chip testing, writing the optimized configuration data packet generated by the server into the chip, reducing the number of writes to the chip's storage area and improving the utilization efficiency of the storage area.

[0042] In summary, the configuration information writing method provided in this disclosure can achieve the association and unification of chip data throughout the entire testing phase through the collaborative cooperation of the test equipment and the server, relying on identifiers. After generating a configuration data packet based on the full amount of test data, the method completes the one-time writing, reducing the number of writes to the chip storage area, improving the utilization efficiency of the storage area, thereby reducing the chip area and cost, and improving the reliability and production yield of configuration information writing.

[0043] Figure 2 A flowchart illustrating a method for writing configuration information provided in an embodiment of this disclosure is further illustrated. Based on Figure 1 The illustrated embodiment further explains step 102. Figure 2 This may include the following steps: Step 201: After the completion of any target test phase in each of the test phases, collect the target test data generated by the target test phase.

[0044] In some embodiments, after the chip completes the identifier writing, it sequentially enters multiple test stages for testing. These test stages may include a wafer probing stage, an aging test stage, a final test stage, and a system-level test stage, etc. This disclosure does not limit the specific type, number, or order of the test stages. Each test stage has independent test objectives and test content, and the test equipment performs corresponding test operations on the chip according to preset test vectors. When the test process of any target test stage (e.g., the wafer probing stage) is completed, the test equipment automatically collects the test data generated in that stage as the target test data. The target test data may include all raw data or pre-processed data obtained from that stage of testing, such as memory repair signatures, minimum operating voltage values, leakage current values, process parameters, etc.

[0045] Step 202: After associating the target test data with the identifier, send it to the server until all test phases are completed.

[0046] In some embodiments, after acquiring the target test data, the test device reads the identifier written in step 101 from the chip through the test interface. The test device associates the read identifier with the target test data to form associated data. The association method may be to append the identifier as a data header before the target test data, or to encapsulate the identifier and the target test data in the same data packet; this disclosure does not specifically limit the method.

[0047] The testing equipment sends the associated data to the server via a secure communication channel (such as HTTPS or MQTT). Upon receiving the data, the server categorizes and stores it according to identifiers, grouping data from different test stages corresponding to the same identifier together. Subsequently, the chip enters the next test stage (e.g., an aging test stage). After this stage ends, the testing equipment collects the target test data for that stage again, repeating the association and sending operations. This cycle continues until all preset test stages are completed. The criteria for determining the completion of all test stages can be that the testing equipment receives a test end command or detects that the chip has passed the last test stage; however, this disclosure does not limit the specific criteria.

[0048] Using the above method, the testing equipment can collect and send data in batches according to the testing phase, ensuring the correct association between test data and identifiers, avoiding data confusion, and realizing real-time aggregation of test data.

[0049] Optionally, the identifier is generated by combining at least two of the following: wafer identification information, chip coordinate location information, production batch number information, and test version number information.

[0050] In some embodiments, the identifier generated by the testing equipment can be composed of a combination of various information to ensure the uniqueness of the identifier throughout the chip's lifecycle. Wafer identification information identifies the wafer to which the chip belongs, and may include a wafer number, wafer batch number, etc. Chip coordinate position information identifies the specific location of the chip on the wafer, typically including X-axis and Y-axis coordinates. Production batch number information identifies the chip's production batch, facilitating traceability of relevant information during the production process. Test version number information identifies the version of the test process the chip has undergone, facilitating the differentiation of data from different test stages or under different test conditions. The testing equipment can select at least two of the above information and combine them to generate the identifier. For example, the testing equipment can combine wafer identification information with chip coordinate position information to form a string. The combination method can be direct concatenation, encryption encoding, hash operation, etc., and this disclosure does not specifically limit this.

[0051] In this way, the identifier generated by the test equipment can uniquely identify each chip instance, which makes it easy for the server to accurately associate test data of different test stages according to the identifier, avoid data confusion, and provide a reliable index basis for the subsequent generation of configuration data packages.

[0052] Figure 3 A flowchart illustrating a method for writing configuration information provided in an embodiment of this disclosure is further illustrated. For example... Figure 3 As shown, the method includes steps 301-304.

[0053] Step 301: In response to the received test request, the chip's identifier is written into the chip's first storage area.

[0054] Step 302: Collect test data of the chip in each test stage, associate the test data with the identifier according to the test stage and send it to the server, so that the server associates all test data of different test stages according to the identifier and generates a configuration data package based on all the test data.

[0055] Step 303: Obtain the configuration data packet corresponding to the identifier from the server, and write the configuration data packet into the second storage area of ​​the chip.

[0056] For explanations of steps 301-303, please refer to [link / reference needed]. Figure 1 The detailed descriptions of the relevant embodiments are not repeated here.

[0057] Step 304: Perform data verification on the written data to verify the integrity of the written data.

[0058] In some embodiments, after the test device writes the configuration data packet to the second storage area of ​​the chip, the written data needs to be verified to ensure the correctness and integrity of the data. The test device sends a read command to the chip through a test interface to read the written configuration data from the chip's second storage area. The test device compares the read data with the original configuration data packet stored locally to determine whether the two are consistent. The comparison method can be byte-by-byte comparison or comparison by calculating the feature values ​​of the data. This disclosure does not limit the specific verification method, as long as it can verify the integrity of the data.

[0059] Using the above method, the testing equipment can verify the accuracy of the writing result in a timely manner after the data is written, ensuring that the configuration data stored in the second storage area of ​​the chip is completely consistent with the configuration data packet generated by the server, thereby ensuring the correctness and reliability of the configuration information during the subsequent use of the chip.

[0060] In some implementations, the writing process can be controlled by dedicated eFuse logic circuitry (such as...). Figure 4 The implementation (shown) includes a power module 401, a current control unit 402, a logic control unit 403, and an eFuse array 404. The power module 401 provides the high voltage required for the write operation, which is higher than the chip's normal operating voltage to meet the voltage requirements for fuse detonation. The current control unit precisely controls the current magnitude and duration during the write process to ensure the fuse detonates stably under preset conditions. The logic control unit 403 receives write commands and configuration data packets from the test equipment and, based on each bit of the configuration data packet, controls the current control unit 402 to apply write current to the corresponding fuse in the eFuse array 404. The eFuse array 404 is a one-time programmable memory array composed of multiple fuse units, each corresponding to a memory bit. The logic control unit 403 determines whether to detonate the corresponding fuse based on the bit value of the configuration data packet: if the bit value is 1, it controls the current control unit 402 to apply write current to the fuse to detonate it; if the bit value is 0, no write current is applied, and the fuse remains in its original state. Through precise control of the above circuit structure, accurate write current and high consistency of fuse breaking can be ensured, thereby achieving highly reliable one-time configuration.

[0061] Figure 5 This is a flowchart illustrating a method for writing configuration information according to an embodiment of the present disclosure, wherein the method is applied to a server.

[0062] like Figure 5 As shown, the method includes the following steps: Step 501: Receive test data of the chip collected by the test equipment at each test stage; wherein the test data is associated with the chip's identifier, and the identifier is located in the chip's first storage area.

[0063] In some embodiments, the server establishes a connection with the testing equipment via a network communication interface, listening to and receiving data sent by the testing equipment. After each testing phase of the chip is completed, the testing equipment associates the collected test data with the chip's identifier and sends it to the server. Each piece of test data received by the server carries identifier information. This identifier is a unique code written by the testing equipment to the chip's first storage area at the beginning of chip testing, used to uniquely identify the chip instance throughout its lifecycle. After receiving the test data, the server parses the data, extracting the identifier and test data content. The server temporarily stores the parsed test data in a receive buffer, awaiting further processing.

[0064] Step 502: Associate all test data in each test phase with the identifier, and generate a configuration data package based on all the test data.

[0065] In some embodiments, after receiving multiple batches of test data from the test device, the server categorizes and stores the test data according to the identifiers carried in the data. The server establishes a storage structure indexed by the identifiers, grouping all test data corresponding to the same identifier together to form a complete test dataset for the chip. The complete test dataset contains test data generated at all stages of the chip's testing, from initial testing to final testing. After obtaining all test data corresponding to the same identifier, the server processes this test data to generate a configuration data packet. The configuration data packet is a set of optimized and encoded configuration information, whose data structure and length match the storage structure of the chip's second storage area.

[0066] Step 503: In response to the acquisition request carrying an identifier sent by the test device, the configuration data packet corresponding to the identifier is sent to the test device so that the test device writes the configuration data packet into the second storage area of ​​the chip.

[0067] In some embodiments, after the chip completes all testing phases, the test device reads an identifier from the chip and sends a request to the server based on the read identifier, requesting to retrieve the configuration data packet corresponding to that identifier. Upon receiving the request, the server parses the identifier carried in the request and searches for the corresponding configuration data packet in its storage structure. Once the configuration data packet is found, the server encapsulates it into response data and sends it back to the test device via a secure communication channel. Upon receiving the configuration data packet, the test device sends a write command to the chip through the test interface, writing the configuration data packet to the chip's second storage area.

[0068] Using the above method, the server can receive and aggregate test data collected by the test equipment at each test stage, associate all the data according to the identifier, generate an optimized configuration data package, and provide the configuration data package in response to the test equipment's request in the final test stage, thus realizing centralized processing of test data and efficient distribution of configuration information.

[0069] For example, a certain AI accelerator card chip generates ~6K bits (data varies depending on the product) of memory repair signature data in each test process. To improve chip yield, the repair signatures need to be merged in different test processes. However, the used space in efuse cannot be rewritten, so the merged data in each test process requires an additional ~6K bits of efuse space. The method provided in this disclosure allows for cloud storage, and the merged repair signature is written to efuse in the final test process, thereby achieving data compression and saving chip area. Saving chip area further improves chip yield.

[0070] Taking a typical system-on-a-chip (SoC) as an example, using the method provided in this disclosure, the test equipment writes a 64-bit identifier to the first storage area of ​​the chip during the initial testing phase, and writes approximately 8 KB of configuration data packets to the second storage area of ​​the chip during the final testing phase. Compared with the related technologies that require writing approximately 16 KB of data cumulatively across multiple testing phases, this disclosure reduces the total number of bits written to the chip's storage area by approximately 50%, corresponding to a saving of approximately 0.007 to 0.01 square millimeters of chip area. Simultaneously, the number of write operations is reduced from at least 4 to 6 times in the related technologies (which increases with chip size and testing procedures) to 1 to 2 times in this disclosure, improving reliability by approximately 30%, effectively reducing chip manufacturing costs and improving testing efficiency.

[0071] Figure 6 A flowchart illustrating a method for writing configuration information provided in this disclosure embodiment is further illustrated. Figure 5The illustrated embodiment further explains step 502. Figure 6 This may include the following steps: Step 601: Aggregate all test data associated with the identifier to obtain all aggregated test data.

[0072] In some embodiments, after receiving test data sent by the test device at various test stages, the server categorizes and stores the data according to identifiers. For all test data corresponding to the same identifier, the server performs an aggregation operation. Aggregation refers to combining multiple test data points from the same chip received at different times and in different test stages to form a complete test dataset for the chip. Aggregation methods include, but are not limited to, arranging the data according to the chronological order of the test stages to form a time-series data sequence; or classifying and organizing data from different test stages according to data type. During the aggregation process, the server may need to perform preprocessing such as deduplication, cleaning, and format standardization to ensure data accuracy and consistency. All aggregated test data contains all test information generated by the chip from the initial test to the final test, providing a complete data foundation for subsequent compression and mapping.

[0073] Step 602: Compress all the aggregated test data to obtain compressed test data.

[0074] In some embodiments, the server performs compression processing on the aggregated test data to reduce the data volume, enabling the final configuration data package to fit the limited capacity of the chip's second storage area. The compression processing can employ various data compression algorithms (e.g., lossless or lossy compression algorithms), which are not specifically limited in this disclosure. For binary test data, such as memory repair signatures and configuration flags, hash operations can be used to map longer data sequences to shorter hash values, or algorithms such as run-length encoding can be used for compression. For numerical test data, such as voltage, current, and temperature values, quantization encoding can be used to map continuous values ​​to discrete code values, or differential encoding can be used to record the changes between values ​​rather than their absolute values. Through compression processing, the server can remove redundant information from the test data, retaining key configuration information, thereby significantly reducing the data volume. All compressed test data is a simplified representation of the original test data, but still contains the key information required to generate the final chip configuration.

[0075] Step 603: Map all the compressed test data to a predefined storage bit template according to a preset mapping rule to generate the configuration data packet; wherein, the predefined storage bit template is defined according to the capacity and bit structure of the second storage area of ​​the chip.

[0076] In some embodiments, the server maps the compressed test data to a predefined storage bit template according to a preset mapping rule, generating the final configuration data packet. The storage bit template is a data layout template predefined according to the capacity and bit structure of the chip's second storage area. For example, for an eFuse array with N storage bits, the storage bit template defines the configuration information type and position corresponding to each bit.

[0077] The mapping rules specify how the compressed test data is filled into each bit of the storage bit template, such as which data corresponds to which bit, the order of the data bits, and whether fixed values ​​or check bits need to be filled.

[0078] The server fills the compressed test data bit by bit into the storage template according to the mapping rules, forming a complete binary data sequence, which is the configuration data packet. The bit width of the configuration data packet matches the capacity of the chip's second storage area, and its content contains all the configuration information required for the chip to operate normally.

[0079] Using the above method, the server aggregates, compresses, and maps the test data, generating an optimized configuration data package suitable for the chip's second storage area. This ensures the integrity of the configuration information while maximizing the utilization efficiency of the storage space.

[0080] Corresponding to the above-described method for writing configuration information, this invention also proposes a device for writing configuration information. Since the device embodiments of this invention correspond to the method embodiments described above, details not disclosed in the device embodiments can be referred to in the method embodiments described above, and will not be repeated here.

[0081] Figure 7 This is a schematic diagram of the structure of a configuration information writing device provided in an embodiment of the present disclosure, as shown below. Figure 7 As shown, the device is configured in the testing equipment and includes: The first writing unit 71 is used to write the chip's identifier into the first storage area of ​​the chip in response to a received test request. The first sending unit 72 is used to collect test data of the chip in each test stage, and associate the test data with the identifier according to the test stage and send it to the server, so that the server associates all test data of different test stages according to the identifier and generates a configuration data packet based on all the test data. The second writing unit 73 is used to obtain the configuration data packet corresponding to the identifier from the server and write the configuration data packet into the second storage area of ​​the chip.

[0082] This device can achieve unified association of chip data throughout the entire testing phase by working together with the test equipment and the server and relying on identifiers. After generating a configuration data packet based on the full amount of test data, it completes the one-time writing, reducing the number of writes to the chip storage area, improving the utilization efficiency of the storage area, thereby reducing the chip area and cost, while improving the reliability of configuration information writing and production yield.

[0083] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 8 As shown, the first transmitting unit 72 includes: The acquisition module 721 is used to acquire the target test data generated by the target test stage after the completion of any target test stage in each of the test stages. The sending module 722 is used to associate the target test data with the identifier and send it to the server until all test stages are completed.

[0084] Furthermore, in one possible implementation of this disclosure, the identifier is generated by combining at least two of the following: wafer identification information, chip coordinate location information, production batch number information, and test version number information.

[0085] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 8 As shown, the device further includes: The verification unit 74 is used to perform data verification on the written data after the second writing unit 73 writes the configuration data packet into the second storage area of ​​the chip, and to verify the integrity of the written data.

[0086] Figure 9 This is a schematic diagram of the structure of a configuration information writing device provided in an embodiment of the present disclosure, as shown below. Figure 9 As shown, the device is configured on a server and includes: The receiving unit 81 is used to receive test data of the chip collected by the test equipment in each test stage; wherein the test data is associated with the identifier of the chip, and the identifier is located in the first storage area of ​​the chip; The generation unit 82 is used to associate all test data in each test phase according to the identifier, and to generate a configuration data package based on all the test data; The second sending unit 83 is configured to send the configuration data packet corresponding to the identifier to the test device in response to the acquisition request carrying the identifier sent by the test device, so that the test device writes the configuration data packet into the second storage area of ​​the chip.

[0087] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 10 As shown, the generation unit 82 includes: Aggregation module 821 is used to aggregate all test data associated with the identifier to obtain all aggregated test data; Compression module 822 is used to compress all the aggregated test data to obtain compressed test data. The generation module 823 is used to map all the compressed test data to a predefined storage bit template according to a preset mapping rule to generate the configuration data packet; wherein the predefined storage bit template is defined according to the capacity and bit structure of the second storage area of ​​the chip.

[0088] It should be noted that the foregoing explanation of the method embodiments also applies to the apparatus of the embodiments of this disclosure, and the principle is the same. Therefore, the embodiments of this disclosure are not limited thereto.

[0089] Figure 11 This is a schematic diagram of the structure of a configuration information writing system provided in an embodiment of the present disclosure, such as... Figure 11 As shown, the configuration information writing system includes test equipment and a server, wherein: The testing equipment 11 includes, for example: Figure 8 The apparatus shown; The server 12 includes, for example: Figure 10 The apparatus shown.

[0090] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0091] Figure 12 A schematic block diagram of an example electronic device 900 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0092] like Figure 12As shown, the electronic device 900 includes a computing unit 901, which can perform various appropriate actions and processes based on a computer program stored in ROM (Read-Only Memory) 902 or a computer program loaded from storage unit 908 into RAM (Random Access Memory) 903. The RAM 903 can also store various programs and data required for the operation of the electronic device 900. The computing unit 901, ROM 902, and RAM 903 are interconnected via bus 904. An I / O (Input / Output) interface 905 is also connected to bus 904.

[0093] Multiple components in electronic device 900 are connected to I / O interface 905, including: input unit 906, such as keyboard, mouse, etc.; output unit 907, such as various types of displays, speakers, etc.; storage unit 908, such as disk, optical disk, etc.; and communication unit 909, such as network card, modem, wireless transceiver, etc. Communication unit 909 allows electronic device 900 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0094] The computing unit 901 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 901 include, but are not limited to, CPUs (Central Processing Units), GPUs (Graphics Processing Units), various special-purpose AI (Artificial Intelligence) computing chips, various computing units running machine learning model algorithms, DSPs (Digital Signal Processors), and any suitable processor, controller, microcontroller, etc. The computing unit 901 performs the various methods and processes described above, such as the method of writing configuration information. For example, in some embodiments, the method of writing configuration information may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as storage unit 908. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 900 via ROM 902 and / or communication unit 909. When the computer program is loaded into RAM 903 and executed by the computing unit 901, one or more steps of the methods described above may be performed. Alternatively, in other embodiments, the computing unit 901 may be configured to perform the aforementioned configuration information writing method by any other suitable means (e.g., by means of firmware).

[0095] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, FPGAs (Field Programmable Gate Arrays), ASICs (Application-Specific Integrated Circuits), ASSPs (Application-Specific Standard Products), SOCs (System-on-Chips), CPLDs (Complex Programmable Logic Devices), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0096] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0097] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, RAM, ROM, EPROM (Electrically Programmable Read-Only Memory) or flash memory, optical fiber, CD-ROM (Compact Disc Read-Only Memory), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0098] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (Cathode-Ray Tube) or LCD (Liquid Crystal Display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0099] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include LANs (Local Area Networks), WANs (Wide Area Networks), the Internet, and blockchain networks.

[0100] Computer systems can include clients and servers. Clients and servers are generally geographically separated and typically interact via communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. A server can be a cloud server, also known as a cloud computing server or cloud host, a hosting product within the cloud computing service system that addresses the shortcomings of traditional physical hosts and VPS (Virtual Private Server) services, such as high management difficulty and weak business scalability. Servers can also be servers for distributed systems or servers incorporating blockchain technology.

[0101] It's important to note that artificial intelligence (AI) is the study of enabling computers to simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, and planning). It encompasses both hardware and software technologies. AI hardware technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, and big data processing. AI software technologies primarily include computer vision, speech recognition, natural language processing, machine learning / deep learning, big data processing, and knowledge graph technologies.

[0102] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0103] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for writing configuration information, characterized in that, The method is applied to a testing device and includes: In response to a received test request, the chip's identifier is written into the chip's first storage area; The test data of the chip is collected at each test stage, and the test data is associated with the identifier according to the test stage and sent to the server. The server associates all the test data of different test stages according to the identifier and generates a configuration data package based on all the test data. The configuration data packet corresponding to the identifier is obtained from the server, and the configuration data packet is written into the second storage area of ​​the chip.

2. The method according to claim 1, characterized in that, The process of collecting test data from the chip at each testing stage, associating the test data with the identifier according to the testing stage, and then sending the data to the server includes: After the completion of any target test phase in each of the test phases, the target test data generated in that target test phase is collected. The target test data is associated with the identifier and then sent to the server until all test phases are completed.

3. The method according to claim 1 or 2, characterized in that, The identifier is generated by combining at least two of the following: wafer identification information, chip coordinate location information, production batch number information, and test version number information.

4. The method according to claim 1, characterized in that, After writing the configuration data packet to the second storage area of ​​the chip, the method further includes: Perform data verification on the written data to verify its integrity.

5. A method for writing configuration information, characterized in that, The method is applied to a server and includes: Receive test data of the chip collected by the test equipment at each test stage; wherein the test data is associated with the chip's identifier, and the identifier is located in the chip's first storage area; Associate all test data in each test phase with the identifiers, and generate a configuration data package based on all the test data; In response to a request for acquisition carrying an identifier sent by the test device, the configuration data packet corresponding to the identifier is sent to the test device so that the test device writes the configuration data packet into the second storage area of ​​the chip.

6. The method according to claim 5, characterized in that, The step of associating all test data in each test phase according to the identifier, and generating a configuration data package based on all the test data, includes: Aggregate all test data associated with the identifier to obtain aggregated test data; The aggregated test data is compressed to obtain compressed test data. All the compressed test data are mapped to a predefined storage bit template according to a preset mapping rule to generate the configuration data packet; wherein the predefined storage bit template is defined according to the capacity and bit structure of the second storage area of ​​the chip.

7. A device for writing configuration information, characterized in that, The device is configured in the testing equipment and includes: The first write unit is used to write the chip's identifier into the first storage area of ​​the chip in response to a received test request. The first sending unit is used to collect test data of the chip in each test stage, associate the test data with the identifier according to the test stage and send it to the server, so that the server associates all test data of different test stages according to the identifier and generates a configuration data packet based on all the test data; The second writing unit is used to obtain the configuration data packet corresponding to the identifier from the server and write the configuration data packet into the second storage area of ​​the chip.

8. A device for writing configuration information, characterized in that, The device is configured on a server and includes: A receiving unit is used to receive test data of the chip collected by the test equipment at various test stages; wherein the test data is associated with the chip's identifier, and the identifier is located in the chip's first storage area; A generation unit is configured to associate all test data in each test phase with the identifier and generate a configuration data package based on all the test data. The second sending unit is configured to send the configuration data packet corresponding to the identifier to the test device in response to the acquisition request carrying the identifier sent by the test device, so that the test device writes the configuration data packet into the second storage area of ​​the chip.

9. A system for writing configuration information, characterized in that, The system includes testing equipment and a server, wherein: The testing equipment includes the apparatus as described in claim 7; The server includes the apparatus as described in claim 8.

10. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-4 or 5-6.

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