A transmitting channel circuit based on 1 / 4 rate structure SERDES

Abstract

This invention discloses a transmit channel circuit based on a 1 / 4 rate SERDES structure, belonging to the field of integrated circuit design technology. The circuit includes: a common phase-locked loop (PLL) for generating a four-phase transmit clock, the four phases of which are sequentially phased by 1 UI; at least one transmit channel, each connected to the PLL for receiving the four-phase transmit clock; each transmit channel includes: an input register for receiving parallel input data; and an encoder connected to the output of the input register for encoding the data. This invention achieves fast clock alignment of the SERDES transmit channel with relatively low circuit resource overhead, with an accuracy controlled to approximately two UI, meeting the requirements of protocols such as PCIe and USB. For higher-speed applications, it supports frequency division to improve the timing margin of cross-clock data interaction, thereby enhancing system reliability.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, specifically relating to a transmission channel circuit based on a 1 / 4 rate structure SERDES. Background Technology

[0002] As SerDes speeds gradually increase, quarter-rate clock structures have gained widespread application due to their lower power consumption and design complexity compared to full-rate and half-rate structures. Taking 8B / 10B SerDes as an example... Figure 1 As shown, the SERDES transmit channel mainly consists of an input register, an 8B / 10B encoder, a parallel-to-serial converter, a serial transmitter, and a phase-locked loop (PLL). The PLL circuit, besides generating a high-precision four-phase transmit clock, is also responsible for achieving phase alignment between multiple channels in multi-channel SERDES circuit scenarios. However, the clock locking time required by PLL circuits is generally long, posing a challenge for applications like PCIe that have strict requirements for recovery time under different operating states. Furthermore, since each SERDES channel requires an independent PLL circuit, as the number of channels in the SERDES chip increases (x2, x4, x8, x16), the circuit resource overhead and power consumption introduced by the PLL also increase.

[0003] Besides the distributed phase-locked loop (PLL) structure mentioned above, the "shared PLL + distributed phase interpolator" structure is also quite common. For example... Figure 2 As shown, the multiphase high-speed transmission clocks for all SERDES transmission channels are provided by the same phase-locked loop (PLL) circuit. Each transmission channel has a phase interpolator for phase adjustment of the internal transmission clock, while the digital control section generates control codewords based on the phase detection results. During operation, the digital control circuit first selects two suitable phases from the multiphase input clocks through phase detection and control of the phase interpolator, and then synthesizes the target phase clock by changing the current weight ratio of the two clocks. Compared with the distributed PLL scheme, this structure simplifies the circuit design to some extent. However, the phase interpolator, as one of the more complex modules in the clock generation circuit, is significantly affected by linearity issues and phase noise. Furthermore, clock phase adjustment in this architecture is generally divided into coarse adjustment and fine adjustment. The goal of fine adjustment is to select two suitable phase clocks from the multiphase clock inputs based on the phase detection results and digital algorithms as inputs for the next fine adjustment step. Fine adjustment involves adjusting the weights of the selected two phase clocks using digitally controlled phase adjustment codewords to finally obtain the target phase clock. The binary search method is a common codeword adjustment strategy, but the clock phase convergence time is relatively long.

[0004] Overall, the two SERDES transmit channel structures mentioned above have certain advantages in clock performance, but they have significant shortcomings in circuit resource consumption, design complexity, and circuit settling time. In practical applications, further optimization is needed based on specific clock performance requirements, design costs, and phase alignment speed. Summary of the Invention

[0005] The purpose of this invention is to provide a transmit channel circuit based on a 1 / 4 rate SERDES structure, which can achieve rapid alignment of transmit clock phases between channels with less resource overhead and lower complexity. The theoretical alignment accuracy is controlled within 2*UI, meeting the protocol requirements including PCIe, and has strong practicality. It can solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a transmission channel circuit based on a 1 / 4 rate structure SERDES, the circuit comprising:

[0007] A common phase-locked loop is used to generate a four-phase transmit clock, wherein the phases of the four-phase transmit clocks are sequentially separated by 1 UI;

[0008] At least one transmission channel, each transmission channel being connected to the common phase-locked loop, is used to receive the four-phase transmission clock;

[0009] The transmission channel includes:

[0010] Input register, used to receive parallel input data;

[0011] An encoder, connected to the output of the input register, is used to encode data;

[0012] A clock phase shifting circuit, connected to the common phase-locked loop, is used to phase shift the local transmitted clock in fixed steps, wherein the fixed steps are 2 UI;

[0013] The digital control unit is connected to the clock phase shift circuit and the external input clock respectively. It is used to asynchronously sample the local clock output by the clock phase shift circuit and the external input clock, and generate a phase shift control signal based on the sampling result to control the clock phase shift circuit to perform phase shifting until the phase of the local clock and the external input clock are aligned.

[0014] A parallel-to-serial converter is connected to the output of the encoder and the output of the clock phase-shifting circuit, respectively, and is used to convert parallel data into serial data under the control of the local transmission clock after phase shifting;

[0015] A serial transmitter, connected to the output of the parallel-to-serial converter, is used to transmit serial data.

[0016] Preferably, the digital control unit includes:

[0017] An asynchronous sampling circuit is used to asynchronously sample the local clock and the external input clock, and output the sampling result.

[0018] A state machine circuit, connected to the asynchronous sampling circuit, is used to generate a phase-shift control signal according to the sampling result and a three-step control logic.

[0019] The digital control under the three-step control logic includes the following states:

[0020] IDLE state: Waiting for the local clock and external input clock to stabilize;

[0021] STEP1 state: When the sampling result is logic "1", the control clock phase shift circuit performs a phase shift once until the sampling result becomes logic "0";

[0022] STEP2 state: The control clock phase shift circuit continues to shift phases until the sampling result changes from logic "0" to logic "1";

[0023] STEP3 state: Based on phase alignment, perform additional phase shifts according to a preset number of times to allow for timing margin.

[0024] Preferably, the clock phase-shifting circuit includes:

[0025] Four clock switching modules are connected to the four-phase transmit clock output terminal of the common phase-locked loop, respectively, and are used to switch the output of the four-phase transmit clock under the control of the phase shift control signal;

[0026] Each time the phase shift control signal is triggered, the four clock switching modules simultaneously switch the current output clock phase to the next phase, achieving phase delay for the two UIs.

[0027] Preferably, the clock switching module is a glitch-free clock switching circuit, used to avoid generating glitches during clock switching.

[0028] Preferably, the digital control unit further includes a frequency divider circuit, which is connected to both a local clock and an external input clock, and is used to perform frequency division processing on the clock in high-speed application scenarios. The asynchronous sampling circuit samples the frequency-divided clock.

[0029] Preferably, the asynchronous sampling circuit includes at least three series-connected D flip-flops for slapping the sampling results to reduce metastability.

[0030] Preferably, the clock path deviation from the common phase-locked loop to each transmission channel is less than 200 ps.

[0031] Preferably, the transmitting channel circuit adopts a quarter-clock rate architecture, and the frequency of the four-phase transmitting clock is one-quarter of the serial data rate.

[0032] Compared with the prior art, the beneficial effects of the present invention are:

[0033] This invention enables faster clock alignment of the SERDES transmission channel with minimal circuit resource overhead, achieving an accuracy of approximately two UIs, thus meeting the requirements of protocols such as PCIe and USB. For higher-speed applications, it supports frequency division to increase the timing margin for cross-clock data interaction, thereby improving the reliability of the system. Attached Figure Description

[0034] Figure 1 This is a diagram of the 8B10B SERDES transmit channel structure based on a distributed phase-locked loop.

[0035] Figure 2 This is a diagram of the 8B10B SERDES transmit channel structure based on a common phase-locked loop.

[0036] Figure 3 An improved SERDES transmission channel structure diagram provided for embodiments of the present invention.

[0037] Figure 4 This is a schematic diagram of the state transition of the digital control "three-step control logic" provided in an embodiment of the present invention.

[0038] Figure 5 The digital "three-step control logic" phase adjustment timing diagram provided for embodiments of the present invention.

[0039] Figure 6 The timing diagram of the clock phase shift circuit based on clock switching provided in the embodiment of the present invention.

[0040] Figure 7 This is a schematic diagram of the key circuit implementation for the digital part of an embodiment of the present invention.

[0041] Figure 8 This is a diagram of a clock phase-shifting circuit provided in an embodiment of the present invention.

[0042] Figure 9 The circuit structure diagram of the GLCM module provided in the embodiment of the present invention. Detailed Implementation

[0043] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0044] To shorten clock phase calibration time and simplify the complexity of related circuit designs, such as Figure 3 The diagram shows adjustments to the transmit channel structure based on a common phase-locked loop (PLL). The analog section replaces the complex phase interpolator with a simple clock phase-shifting circuit, digitally controlled to shift the phase by a fixed 2 UI (Unit Interval) each time. The digital section handles asynchronous sampling-based phase detection and analog phase-shift control. For lower-speed applications, the local clock generated by the PLL, after frequency division, is used to directly perform simple asynchronous sampling of the external input clock at the same frequency (no frequency division is performed by the digital section). The sampling result is sent to the digital control state machine for analog phase-shift control. Without considering the setup and hold time of the asynchronous sampling trigger (typically in the picosecond range, which can be controlled by selecting appropriate device types), the error is determined by the phase-shifting step of the analog circuit, i.e., 2*UI. For higher-speed applications, the external input clock and the local digital clock need to be frequency-divided first, and then the divided low-frequency clock is used for the same phase alignment process, thus relaxing the circuit timing margin.

[0045] It should be noted that, Figure 3 The "D" marking shown represents the D flip-flops that make up the input register. Specifically, the input register consists of multiple parallel D flip-flops. Each D flip-flop receives one bit of parallel input data at its data terminal, receives the local clock at its clock terminal, and its output terminal is connected to the corresponding input terminal of the encoder. The D flip-flops latch the input data and output it on the rising edge (or falling edge) of the local clock, ensuring that the data is transmitted to the encoder within a stable clock domain.

[0046] Figure 3 The two 2:1 selectors shown are used for data path selection. The first 2:1 selector is located after the encoder. Its two inputs receive the encoder's output data and the unencoded raw data, respectively, and its control terminal receives an encoding mode selection signal (e.g., 8B / 10B_EN). When encoding is enabled, the selector selects the encoded data; when encoding is bypassed, it selects the raw data. The second 2:1 selector is located after the first selector and before the parallel-to-serial converter. Its two inputs receive data from the first selector and data from other data sources, respectively, and its control terminal receives a working mode signal. In normal transmission mode, it selects data from the first 2:1 selector; in test mode, it selects test data. Through the configuration of these two 2:1 selectors, the transmission channel can flexibly adapt to different encoding requirements and testing needs.

[0047] The digital system employs a three-step control logic approach for phase-shift control, and the state machine's state transition diagram is as follows: Figure 4As shown. Digital control is divided into 4 states: "IDLE" is the initial state, where the phase relationship between the local transmit clock and the external input clock is random. After both clocks stabilize, it enters the "STEP1" state. In the "STEP1" state, the asynchronous sampling result of the local clock and the external input clock is judged (for high-speed applications, the clock frequency can be down-clocked first before sampling). When the sampling result is logic "1", the clock phase shift circuit is controlled to perform a clock phase shift of 2*UI step until the sampling result is logic "0", and then enters the "STEP2" state. In the "STEP2" state, the clock phase shift is controlled until the asynchronous sampling result changes from logic "0" to "1", and then enters the "STEP3" state. The initial state of "STEP3" is the state where the local clock and the external clock are "aligned". If sufficient timing margin is required for cross-clock interaction between the input clock and the local clock, then the local clock needs to be phase shifted a certain number of times.

[0048] Since the phase adjustment step is 2 UI, for common data widths of 16 / 20 / 32 / 40 bits, this "three-step control logic" has a significant advantage in phase adjustment speed compared to the "bisection method" centered on a phase interpolator. Taking a 16-bit PCIe Gen3 (8G) as an example, the data width after 8B / 10B encoding is 20 bits. The external input clock and the local SerDes clock frequency before digital division are both 8G / 20=400MHz. To achieve a more relaxed timing margin, the input clock and the local clock are digitally divided by 200MHz (40 UI per clock cycle). Then, the "three-step control logic" is used to adjust the phase of the divided clock. The "STEP3" stage performs 10 phase shifts. Figure 5 The clock processing details for each stage are presented.

[0049] Figure 5This is a timing diagram for phase adjustment of the digital "three-step control logic". In the diagram, tx_clk_in and tx_clk_in_div2 are the external input clock and its corresponding divide-by-two clock, respectively. tx_clk_int and tx_clk_int_div2 are the local clock with the same frequency as the external input tx_clk_in and its corresponding divide-by-two clock, respectively. async_q is the result of asynchronously sampling tx_clk_in_div2. In the "STEP1" stage, the local clock is phase-shifted until "0" is sampled. The most pessimistic scenario requires a half-sampling clock cycle (20 UIs, 10 phase shifts) to sample "0". "STEP2" also requires a half-sampling clock cycle to sample "1", requiring 10 phase shifts before entering "STEP3". In "STEP3", to allow sufficient timing margin for subsequent cross-clock data interaction, another half-sampling clock cycle is phase-shifted to align the rising edge of the local sampling clock with the falling edge of the external input frequency divider clock. The phase adjustment process ends, and the digital state machine re-enters the "IDLE" state. In practical applications, the frequency divide-by-two processing of the digital section can be bypassed as needed, halving the number of phase shifts in each stage to further accelerate convergence.

[0050] The analog circuitry for implementing a 2*UI clock phase shift is fundamental to this design. The fastest local clock in a quarter-architecture SerDes is CLK_DIV4, making it impossible to achieve a 2*UI phase delay step directly through clock timing. Fine-grained phase delays can be achieved by inserting delay units into the clock path; however, certain types of delay units are significantly affected by PVT, making precise delay control difficult. Furthermore, for low-speed applications, achieving a 2*UI delay granularity requires inserting numerous delay units into the clock path, increasing power consumption and area. Considering the fixed phase relationship between each pair of the four-phase input clocks (CLK_00, CLK_90, CLK_180, and CLK_270 phases differ by one UI), a clock switching method is used to implement the clock phase shift function. Figure 6 For this phase-shifting circuit's timing diagram, each time SHIFT changes from low to high, it triggers a switch from CLK_00 to CLK_180, CLK_90 to CLK_270, CLK_180 to CLK_00, and CLK_270 to CLK_90. After the switch, the clock phase is delayed by 2 UI.

[0051] Figure 7This is the circuit implementation diagram for the digital part. Here, `tx_data` represents the 8B / 10B encoded data (for PCIE Gen3 and above, this corresponds to 128 / 130B encoded data). The local clock asynchronously samples the external input clock using a three-step sampling method to reduce the impact of metastability. The asynchronous sampling circuit sends the asynchronous sampling result to the digital "three-step" state machine (state machine circuit) to generate a SHIFT signal, which is then sent to the analog circuit for phase shift control of the local clock. There is asynchronous interaction between the external input clock and the local clock along the data path. The phase adjustment result of the local clock ensures the correctness of this data interaction. Down-clocking the input and local clocks before phase adjustment helps improve timing margin. Due to the large phase adjustment step, the entire algorithm converges quickly.

[0052] Figure 8 This is a diagram of a clock phase-shifting circuit. In the diagram, SHIFT is the digital control signal for analog clock phase shifting, generated by the aforementioned "three-step method" control state machine (state machine circuit). Each high pull triggers a clock switch in the clock selection circuit. CLK_00, CLK_90, CLK_180, and CLK_270 are four-phase transmit clocks with phases differing by 1 UI, respectively. The phase-shifted four-phase transmit clocks CLK_00_SHIFT, CLK_90_SHIFT, CLK_180_SHIFT, and CLK_270_SHIFT are generated by four clock switching modules (GLCM). To avoid glitches during clock switching, the GLCM employs... Figure 9 The circuit structure shown is shown.

[0053] For different channels within SerDes, clock phase processing for each channel is performed independently. That is, the local clock in each channel is independently phase-adjusted with reference to the externally input common clock. The skew from the external common clock to the entry point of each channel should be as small as possible. For example, in PCIe applications, it is usually required to be within 200ps.

[0054] The following are the Chinese explanations for the English terms in the attached diagram:

[0055] tx_clk_in External input clock;

[0056] tx_clk_in_div2 is an external clock divided by two;

[0057] tx_clk_int Local clock;

[0058] tx_clk_int_div2 is a local clock divided by two;

[0059] async_q represents the asynchronous sampling result;

[0060] SHIFT phase shift control signal;

[0061] CLK_00 0-degree clock;

[0062] CLK_90 is a 90-degree clock.

[0063] CLK_180 is a 180-degree clock.

[0064] CLK_270 270-degree clock;

[0065] GLCM glitch-free clock switching module;

[0066] rst is the reset signal.

[0067] clk clock signal;

[0068] Data;

[0069] tx_data sends data;

[0070] PLL (Phase-Locked Loop)

[0071] PI phase interpolator.

[0072] This invention enables faster clock alignment of the SERDES transmission channel with minimal circuit resource overhead, achieving an accuracy of approximately two UIs, thus meeting the requirements of protocols such as PCIe and USB. For higher-speed applications, it supports improving the timing margin of cross-clock data interaction through frequency division, thereby enhancing system reliability. This processing approach also offers valuable insights for non-quarter-architecture SERDES systems.

[0073] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0074] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A transmit path circuit based on a 1 / 4 rate structure SERDES, characterized by, The circuit includes: A common phase-locked loop is used to generate a four-phase transmission clock, wherein the phases of the four-phase transmission clocks are sequentially separated by 1 UI; At least one transmission channel, each transmission channel being connected to the common phase-locked loop, is used to receive the four-phase transmission clock; The transmission channel includes: The input register is used to receive parallel input data; An encoder, connected to the output of the input register, is used to encode data; A clock phase shifting circuit, connected to the common phase-locked loop, is used to phase shift the local transmitted clock in fixed steps, wherein the fixed steps are 2 UI. The digital control unit is connected to the clock phase shift circuit and the external input clock respectively. It is used to asynchronously sample the local clock output by the clock phase shift circuit and the external input clock, and generate a phase shift control signal based on the sampling result to control the clock phase shift circuit to perform phase shifting until the phase of the local clock and the external input clock are aligned. A parallel-to-serial converter is connected to the output of the encoder and the output of the clock phase-shifting circuit, respectively, and is used to convert parallel data into serial data under the control of the local transmission clock after phase shifting; A serial transmitter, connected to the output of the parallel-to-serial converter, is used to transmit serial data; The digital control unit includes: An asynchronous sampling circuit is used to asynchronously sample the local clock and the external input clock, and output the sampling result. A state machine circuit, connected to the asynchronous sampling circuit, is used to generate a phase-shift control signal according to the sampling result and a three-step control logic. The digital control under the three-step control logic includes the following states: IDLE state: Waiting for the local clock and external input clock to stabilize; STEP1 state: When the sampling result is logic "1", the control clock phase shift circuit performs a phase shift once until the sampling result becomes logic "0"; STEP2 state: The control clock phase shift circuit continues to shift phases until the sampling result changes from logic "0" to logic "1"; STEP3 state: Based on phase alignment, perform additional phase shifts according to a preset number of times to allow for timing margin; The asynchronous sampling circuit includes at least three series-connected D flip-flops for slapping the sampling results to reduce metastability.

2. The transmit channel circuit based on a 1 / 4 rate SERDES structure according to claim 1, characterized in that, The clock phase shifting circuit includes: Four clock switching modules are connected to the four-phase transmit clock output terminal of the common phase-locked loop, respectively, and are used to switch the output of the four-phase transmit clock under the control of the phase shift control signal; Each time the phase shift control signal is triggered, the four clock switching modules simultaneously switch the current output clock phase to the next phase, achieving phase delay for the two UIs.

3. The transmit channel circuit based on a 1 / 4 rate SERDES structure according to claim 2, characterized in that, The clock switching module is a glitch-free clock switching circuit, used to avoid generating glitches during clock switching.

4. The transmit channel circuit based on a 1 / 4 rate SERDES structure according to claim 1, characterized in that, The digital control unit also includes a frequency divider circuit, which is connected to a local clock and an external input clock respectively, and is used to divide the clock in high-speed application scenarios. The asynchronous sampling circuit samples the divided clock.

5. The transmit channel circuit based on a 1 / 4 rate SERDES structure according to claim 1, characterized in that, The clock path deviation from the common phase-locked loop to each transmission channel is less than 200 ps.

6. The transmit channel circuit based on a 1 / 4 rate SERDES structure according to claim 1, characterized in that, The transmitting channel circuit adopts a quarter-clock rate architecture, and the frequency of the four-phase transmitting clock is one-quarter of the serial data rate.

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