Data driver and display device including the same

Abstract

The present disclosure relates to a data driver and a display device including the same, the data driver including: a register unit configured to sample and output sequentially input image data in each horizontal period; a latch unit configured to latch the image data output from the register unit, and output the image data in synchronization with a latch output control signal; a digital-to-analog converter configured to convert the image data output from the latch unit into a gamma compensation voltage so as to generate a data voltage; a plurality of output buffers configured to sequentially output the data voltage generated by the digital-to-analog converter to a data line; buffer switching elements that connect the output buffers to the data lines, respectively, in response to source output enable signals; a charge sharing circuit configured to control a connection between at least one charge sharing line and the data line; and a calculation unit configured to generate a control signal based on a gradation value of the image data output by the latch unit, the control signal configured to control the charge sharing circuit.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0147315, filed on October 25, 2024, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure relates to data drives and display devices including data drives. Background Technology

[0004] With the development of the information society, various types of display devices have been developed. Recently, various types of display devices, such as liquid crystal displays (LCDs), plasma display panels (PDPs), and organic light-emitting diode (OLED) devices, have been utilized.

[0005] The display device may consist of a display panel having pixels thereon, a data driver configured to apply data voltage to the pixels, a gate driver configured to apply gate signals to the pixels, and a timing controller configured to control the operating timing of the data driver and the gate driver.

[0006] As display devices become larger and their resolutions increase, charge-sharing operation methods have been researched and developed to reduce heat generation and power consumption of data drivers and improve reliability. In charge-sharing operation methods, sufficient charging time and charge amount are ensured for each data line by providing an average voltage before outputting the data voltage in each horizontal period and at the time of polarity change, and electrically connecting the data lines. Summary of the Invention

[0007] An embodiment provides a data driver configured to perform charge-sharing operations based on the grayscale values ​​of image data and a display device including the data driver.

[0008] The embodiment provides a data driver configured to perform charge sharing operation in a display device where the polarity of the data voltage is not reversed, and a display device including the data driver.

[0009] The embodiment provides a data driver configured to operate in a charge-sharing mode by defining multiple grayscale regions and electrically connecting data lines to be applied with data voltages in the same grayscale regions, and a display device including the data driver.

[0010] One embodiment is a data driver comprising: a register unit configured to sample and output sequentially input image data in each horizontal time interval; a latch unit configured to latch the image data output from the register unit and output the image data synchronously with a latch output control signal; a digital-to-analog converter configured to convert the image data output from the latch unit into a gamma-compensated voltage to generate a data voltage; a plurality of output buffers configured to sequentially output the data voltage generated by the digital-to-analog converter to data lines; a buffer switching element responsive to a source output enable signal to connect the output buffers to the data lines respectively; a charge-sharing circuit configured to control the connection between at least one charge-sharing line and the data lines; and a computing unit configured to generate a control signal based on the grayscale value of the image data output from the latch unit, the control signal being configured to control the charge-sharing circuit.

[0011] The charge-sharing circuit may include: the at least one charge-sharing line; and at least one charge-sharing switching element, the at least one charge-sharing switching element being connected between the at least one charge-sharing line and the data line, and each of the charge-sharing switching elements being capable of connecting the corresponding data line to the corresponding charge-sharing line in response to the control signal being at an on level.

[0012] Each of the charge-sharing switch elements can be connected between the corresponding data line and the corresponding charge-sharing line and can be configured as a transistor, the gate electrode of which is connected to the computing unit and configured to receive the control signal.

[0013] The computing unit can select at least one data line to operate in charge-sharing mode based on the grayscale value of the image data, and output the control signal at the on level to the charge-sharing switching element connected to the selected data line.

[0014] The computing unit can define multiple grayscale regions, select image data whose grayscale values ​​are included in the same grayscale region, and control the charge-sharing switch element to connect the data line of the selected image data to the same charge-sharing line.

[0015] The computing unit can select image data whose grayscale values ​​include high grayscale regions and low grayscale regions, and controls the charge-sharing switch element to connect the data line of the selected image data to the same charge-sharing line.

[0016] When the gray values ​​of the previous image data and the next image data are contained in different gray-scale regions in the sequentially input image data, the computing unit can select the data line to be applied to the next image data to operate in the charge-sharing mode.

[0017] When the grayscale value of the previous image data is included in a high grayscale region and the grayscale value of the next image data is included in a low grayscale region in the sequentially input image data, the computing unit can select the data line to be applied to the next image data to operate in the charge-sharing mode.

[0018] When the grayscale value of the previous image data is included in a low grayscale region and the grayscale value of the next image data is included in a high grayscale region in the sequentially input image data, the computing unit can select the data line to be applied to the next image data to operate in the charge-sharing mode.

[0019] During the (n-1)th level time period, a data voltage corresponding to the (n-1)th image data can be applied to the data line. During the charge-sharing time period, the voltage can be redistributed between data lines connected to the same charge-sharing line. During the nth level time period, a data voltage corresponding to the difference between the voltage corresponding to the nth image data and the redistributed voltage can be applied to the data line, where n is a natural number equal to or greater than 2.

[0020] During the charge-sharing period, data lines connected to the same charge-sharing line can be charged to the average voltage of the data lines connected to the same charge-sharing line during the (n-1)th level period.

[0021] During the (n-1)th level time period, the source output enable signal at the on level can be applied; during the charge sharing time period, the source output enable signal at the off level can be applied; and during the nth level time period, the source output enable signal at the on level can be applied.

[0022] At least one charge-sharing line can be provided corresponding to the number of the plurality of grayscale regions.

[0023] Another embodiment is a display device, comprising: a display panel having arranged pixels; a data driver configured to apply a data voltage to the pixels via data lines; a gate driver configured to apply a scan signal to the pixels via scan lines; and a timing controller configured to apply image data and a data drive control signal to the data driver, the data driver including: a register unit configured to sample and output the image data; a latch unit configured to latch the image data output from the register unit and output the image data synchronously with a latch output control signal; and a digital-to-analog converter configured to... The image data output from the latch unit is converted into a gamma-compensated voltage to generate a data voltage; a plurality of output buffers are configured to sequentially output the data voltage generated by the digital-to-analog converter to the data lines; a buffer switching element connects the output buffers to the data lines respectively in response to a source output enable signal; a charge-sharing circuit having a charge-sharing switching element configured to control the connection between at least one charge-sharing line and the data lines; and a calculation unit configured to generate a control signal based on the grayscale value of the image data output from the latch unit, the control signal being configured to control the charge-sharing switching element.

[0024] The computing unit can define multiple grayscale regions, select image data whose grayscale values ​​are included in the same grayscale region, and control the charge-sharing switch element to connect the data line of the selected image data to the same charge-sharing line.

[0025] The computing unit can select image data whose grayscale values ​​include high grayscale regions and low grayscale regions, and controls the charge-sharing switch element to connect the data line of the selected image data to the same charge-sharing line.

[0026] When the grayscale values ​​of the previous image data and the next image data are contained in different grayscale regions in the sequentially input image data, the computing unit can control the charge-sharing switch element to connect the data line to which the next image data is to be applied to one of the charge-sharing lines.

[0027] When the grayscale value of the previous image data is included in a high grayscale region and the grayscale value of the next image data is included in a low grayscale region in the sequentially input image data, the computing unit can control the charge-sharing switch element to connect the data line to which the next image data is to be applied to one of the charge-sharing lines.

[0028] According to the embodiments, the data driver and the display device including the data driver allow not only display devices with reversed data voltage polarity (e.g., liquid crystal display devices), but also display devices with non-reversed data voltage polarity (e.g., organic light-emitting display (OLED) devices) to perform charge-sharing operations.

[0029] The data driver and the display device including the data driver according to the embodiment can improve power consumption by performing charge sharing operation relative to the data line according to the gray value of the data voltage.

[0030] The data driver and display device including the data driver according to the embodiments can reduce the heat generation of the data driver and improve reliability under large-format and high-resolution conditions. Attached Figure Description

[0031] Figure 1 This is a block diagram illustrating the configuration of a display device according to an embodiment.

[0032] Figure 2 This is a circuit diagram of the pixel according to an embodiment.

[0033] Figure 3 This shows the operation. Figure 2 The timing diagram shows the method for the pixel shown.

[0034] Figure 4 This is a block diagram illustrating the configuration of the source driver IC according to the first embodiment.

[0035] Figure 5 This is a block diagram illustrating the configuration of the source driver IC according to the second embodiment.

[0036] Figure 6 The grayscale area is shown according to an embodiment.

[0037] Figure 7 This is a waveform diagram showing the signals applied to the pixel and source driver IC according to an embodiment.

[0038] Figure 8This shows an example of how the grayscale value of the data voltage changes between horizontal time periods.

[0039] Figure 9 Showing according to Figure 8 An embodiment of the operation state of the charge-sharing circuit in the embodiment.

[0040] Figure 10 Showing according to Figure 8 Another embodiment of the operation state of the charge-sharing circuit in the embodiment.

[0041] Figures 11 to 14 This demonstrates the effect of improving power consumption based on charge-sharing operation.

[0042] Figure 15 This is a block diagram illustrating the configuration of the source driver IC according to the third embodiment.

[0043] [Figure Labels]

[0044] 1: Display device

[0045] 10: Timer Controller

[0046] 20: Gate driver

[0047] 30: Data Driver

[0048] 40: Power Supply Unit

[0049] 50: Display panel Detailed Implementation

[0050] Details of some implementation methods are included in the following description and figures.

[0051] The advantages and features of this disclosure, as well as the methods for achieving these advantages and features, will become more apparent from the embodiments described in detail with reference to the accompanying drawings. However, this disclosure is not limited to the disclosed embodiments, but can be implemented in various different ways. In the following description, when a component is referred to as being "connected" to another component, it can be directly connected to the other component, or it can be electrically connected to the other component by inserting another intermediate element therebetween. Furthermore, for clarity of description, parts unrelated to this disclosure are omitted in the drawings, and the same reference numerals denote the same elements throughout the drawings and written description.

[0052] Figure 1 This is a block diagram illustrating the configuration of a display device according to an embodiment.

[0053] refer to Figure 1 The display device 1 includes a timing controller 10, a gate driver 20, a data driver 30, a power supply unit 40, and a display panel 50.

[0054] The timing controller 10 can control the timing of the operation of the gate driver 20 and the data driver 30. The timing controller 10 can receive video signals RGB and control signals CS from an external host system, etc. The video signal RGB can include multiple grayscale data. The control signal CS can include, for example, a horizontal synchronization signal, a vertical synchronization signal, and a master clock signal.

[0055] The timing controller 10 processes the video signal RGB and the control signal CS to suit the operating conditions of the display panel 50, and can generate and output image data DATA, gate drive control signal CONT1, light emission drive control signal CONT2, data drive control signal CONT3 and power control signal CONT4.

[0056] The gate driver 20 may include a scan drive circuit 20A configured to generate a scan signal based on a signal output from the timing controller 10. The scan drive circuit 20A can provide the generated scan signal to the pixel PX via multiple scan lines GL. In an embodiment, a pixel PX can be configured to receive multiple scan signals with different waveforms. In such an embodiment, the scan drive circuit 20A can provide multiple scan signals to the pixel PX via their respective scan lines GL.

[0057] The gate driver 20 may further include a light-emitting driving circuit 20B, which is configured to generate a light-emitting control signal based on a signal output from the timing controller 10. The light-emitting driving circuit 20B can provide the generated light-emitting control signal to the pixel PX via the light-emitting line EL.

[0058] The gate driver 20 can be configured such that it is mounted on the display panel 50 as an in-panel gate. As shown, the gate driver 20 can be disposed on one side of the display panel 50, or on both sides of the display panel 50 (e.g., left and right). Depending on the driving method, panel design, etc., the gate driver 20 can be disposed on both sides of the display panel 50 (e.g., left and right), or it can be connected to two or more of the four sides of the display panel 50.

[0059] The data driver 30 can generate a data signal based on the data drive control signal CONT3 output from the timing controller 10 and the image data DATA. In an embodiment, the data drive control signal CONT3 may include a source output enable signal, a latch output control signal, and information indicating data packet processing options (e.g., equalization level, receiver resistance, etc.). The data driver 30 can provide the generated data signal to the pixel PX through multiple data lines DL.

[0060] The data driver 30 may include at least one source driver IC. The source driver IC may be mounted in a flexible film in a chip-on-film (COF) or chip-on-plastic (COP) manner to connect to one side of the display panel 50.

[0061] The power supply unit 40 can generate a high-potential driving voltage ELVDD and a low-potential driving voltage ELVSS to be supplied to the display panel 50 based on the power control signal CONT4. The power supply unit 40 can supply the generated driving voltages ELVDD and ELVSS to the pixel PX through the corresponding power lines PL1 and PL2. In addition, the power supply unit 40 can also generate the initialization voltage Vini required to drive the pixel PX, and supply the initialization voltage Vini to the pixel PX through the corresponding voltage line ViniL.

[0062] A plurality of pixels PX (or subpixels) are provided on the display panel 50. Pixels may be arranged on the display panel 50, for example, in a matrix. Pixels arranged in a pixel row are connected to the same scan line GL and light emission line EL, and pixels arranged in a pixel column are connected to the same data line DL. Pixel PX can emit light at a brightness corresponding to the data signal and scan signal provided by the scan line GL and data line DL in response to a light emission control signal applied through the light emission line EL.

[0063] In one embodiment, each pixel PX can display one of the colors red, green, and blue. In another embodiment, each pixel PX can display one of the colors cyan, magenta, and yellow. In still other embodiments, each pixel PX can display one of the colors red, green, blue, and white.

[0064] exist Figure 1 In this diagram, gate driver 20 and data driver 30 are shown as components separate from display panel 50; however, at least one of gate driver 20 and data driver 30 can be configured in an in-panel manner integrated into display panel 50. For example, gate driver 20 can be integrated into display panel 50 in a gate-in-panel (GIP) manner.

[0065] The timing controller 10, gate driver 20, data driver 30, and power supply unit 40 can be configured as separate integrated circuits (ICs), or at least some of their components can be integrated together to form an integrated circuit. For example, the timing controller 10, data driver 30, and power supply unit 40 can be configured as a driver chip in the form of an integrated circuit (IC). The driver chip can be implemented, for example, in the form of a flexible printed circuit board (FPCB).

[0066] Figure 2 This is a circuit diagram of the pixels according to an embodiment. Figure 2The image shows an example of a pixel PX set in the nth pixel row.

[0067] refer to Figure 2 According to an embodiment, a pixel PX may include a driving transistor DT, a light-emitting diode LD connected to the driving transistor DT, and control circuitry configured to control the amount of drive current to be applied to the light-emitting diode LD through the driving transistor DT. For example, the control circuitry may include first transistors T1 through sixth transistors T6 and a storage capacitor Cst.

[0068] The first electrode of the driving transistor DT is configured to receive a high-potential driving voltage ELVDD (connected to the high-potential driving voltage line PL1) through the second node N2, and the second electrode of the driving transistor DT is connected to the third node N3. The gate electrode of the driving transistor DT is connected to the first node N1. The driving transistor DT can be turned on according to the voltage applied to the first node N1, and the amount of driving current flowing to the light-emitting diode LD can be controlled.

[0069] The first electrode of the first transistor T1 is connected to the gate electrode of the driving transistor DT through a first node N1, and the second electrode of the first transistor T1 is connected to the second electrode of the driving transistor DT through a third node N3. The gate electrode of the first transistor T1 can be connected to the nth scan line GLn and can receive the nth scan signal SCn. The first transistor T1 can be turned on according to the nth scan signal SCn applied to the nth scan line GLn, and the gate electrode and the second electrode of the driving transistor DT can be connected to each other. Such a first transistor T1 can be called a compensation transistor.

[0070] The first electrode of the second transistor T2 is connected to the data line DL, and the second electrode of the second transistor T2 is connected to the first electrode of the driving transistor DT through the second node N2. The gate electrode of the second transistor T2 can be connected to the nth scan line GLn and can receive the nth scan signal SCn. The second transistor T2 can be turned on according to the nth scan signal SCn applied to the nth scan line GLn, and can deliver the data voltage Vdata applied to the data line DL to the second node N2. Such a second transistor T2 can be called a switching transistor.

[0071] The first electrode of the third transistor T3 is configured to receive a high-potential drive voltage ELVDD (connected to the high-potential drive voltage line PL1), and the second electrode of the third transistor T3 is connected to the driving transistor DT through the second node N2. The gate electrode of the third transistor T3 can be connected to the light-emitting line EL and can receive the light-emitting control signal EMn. The third transistor T3 can connect the high-potential drive voltage line PL1 and the driving transistor DT to each other in response to the light-emitting control signal EMn applied to the light-emitting line ELn.

[0072] The first electrode of the fourth transistor T4 can be connected to the driving transistor DT through the third node N3, and the second electrode of the fourth transistor T4 can be connected to the light-emitting diode LD through the fourth node N4. The gate electrode of the fourth transistor T4 can be connected to the light-emitting line ELn and can receive the light-emitting control signal EMn. The fourth transistor T4 can connect the driving transistor DT and the light-emitting diode LD to each other in response to the light-emitting control signal EMn applied to the light-emitting line ELn.

[0073] When the third transistor T3 and the fourth transistor T4 are turned on, a current path is formed between the high-potential drive voltage ELVDD and the low-potential drive voltage ELVSS, and the drive current flows to the light-emitting diode LD, thus enabling the light-emitting diode LD to emit light. Such a third transistor T3 and a fourth transistor T4 can be called light-emitting transistors.

[0074] The first electrode of the fifth transistor T5 is configured to receive the initialization voltage Vini (connected to the initialization voltage line ViniL), and the second electrode of the fifth transistor T5 is connected to the first node N1. The gate electrode of the fifth transistor T5 can be connected to the (n-1)th scan line GLn-1 and can receive the (n-1)th scan signal SCn-1. The fifth transistor T2 can be turned on according to the (n-1)th scan signal SCn-1 applied to the (n-1)th scan line GLn-1, and can deliver the initialization voltage Vini to the first node N1. Such a fifth transistor T5 can be called an initialization transistor.

[0075] The first electrode of the sixth transistor T6 is configured to receive the initialization voltage Vini (connected to the initialization voltage line ViniL), and the second electrode of the sixth transistor T6 is connected to the anode of the light-emitting diode LD through the fourth node N4. The gate electrode of the sixth transistor T6 can be connected to the nth scan line GLn and can receive the nth scan signal SCn. The sixth transistor T6 can be turned on according to the nth scan signal SCn applied to the nth scan line GLn, and can deliver the initialization voltage Vini to the anode of the light-emitting diode LD. Such a sixth transistor T6 can be called an anode initialization transistor.

[0076] The storage capacitor Cst is connected between the first node N1 and the high-potential drive voltage ELVDD (high-potential drive voltage line PL1). The storage capacitor Cst can store the voltage corresponding to the voltage difference between the first node N1 and the high-potential drive voltage ELVDD.

[0077] The anode of the light-emitting diode (LD) can be connected to the fourth node N4, and the cathode can be connected to the low-level drive voltage ELVSS. When the drive transistor DT, the fourth transistor T4, and the fifth transistor T5 are turned on, a current path is formed between the high-level drive voltage ELVDD and the low-level drive voltage ELVSS, and the drive current can flow to the LD. The LD can emit light with a brightness corresponding to the amount of drive current applied to it.

[0078] exist Figure 2 In the illustrated embodiment, the pixel PX can be configured as a low-temperature polycrystalline silicon (LTPS) thin-film transistor. An LTPS thin-film transistor includes a gate electrode, a source electrode, and a drain electrode. The LTPS thin-film transistor has an active layer formed of polycrystalline silicon. Such an LTPS thin-film transistor can be configured as a P-type thin-film transistor. LTPS thin-film transistors have high electron mobility, thus exhibiting fast drive characteristics.

[0079] However, the embodiments are not limited thereto. In various other embodiments, the pixel PX as a whole may be configured as an oxide semiconductor thin-film transistor, or may be configured as a hybrid of both LTPS thin-film transistors and oxide semiconductor thin-film transistors.

[0080] An oxide semiconductor thin-film transistor (OSBMT) includes a gate electrode, a source electrode, and a drain electrode. The OSBMT has an active layer formed of oxide semiconductor. Here, the oxide semiconductor can be either amorphous or crystalline. The OSBMT can be configured as an n-type transistor. OSBMTs can be formed using low-temperature processes and have lower charge mobility than low-temperature polycrystalline silicon (LTPS) thin-film transistors. Such OSBMTs exhibit excellent cutoff current characteristics.

[0081] Figure 3 This shows the operation. Figure 2 The timing diagram shows the method for the pixel shown.

[0082] refer to Figure 3 Regarding the method for manipulating pixels according to the embodiment, a frame may include an initialization period t1, a sampling and programming period t2, and an emission period t3. Pixel PX is initialized in the initialization period t1, a data voltage Vdata that compensates for the threshold voltage Vth of the driving transistor DT is applied to the first node N1 in the sampling and programming period t2, and the light-emitting diode LD can emit light at a brightness corresponding to the compensated data voltage Vdata in the emission period t3.

[0083] During the initialization period t1, the (n-1)th scan signal SCn-1, which is at an on-level (e.g., low level), is applied, and the fifth transistor T5 is turned on. At this time, the initialization voltage Vini is applied to the first node N1 through the turned-on fifth transistor T5, and the voltage of the gate electrode of the driving transistor DT can be initialized. The voltage corresponding to the difference between the high-potential driving voltage ELVDD and the initialization voltage Vini can be stored in the storage capacitor Cst.

[0084] During the sampling and programming period t2, the nth scan signal SCn, which is at the on level, can be applied. At this time, the first transistor T1, the second transistor T2, and the sixth transistor T6 can be turned on.

[0085] Through the conducting second transistor T2, the data voltage Vdata applied to the data line DL can be applied to the second node N2, that is, the source electrode of the driving transistor DT.

[0086] With the first transistor T1 turned on, the gate and drain electrodes of the driving transistor DT can be electrically connected to each other. Therefore, the driving transistor DT, which is in the on state, enters the diode connection state.

[0087] In this scenario, because the voltage difference between the gate and source electrodes of the driving transistor DT (Vgs = Vini - Vdata) is greater than the threshold voltage Vth, the driving transistor DT enters the on state, and a current path is formed when the voltage difference Vgs between the gate and source electrodes reaches the threshold voltage Vth. The voltage at the gate electrode of the driving transistor rises to a voltage Vdata - Vth corresponding to the difference between the data voltage Vdata and the threshold voltage Vth. When the driving transistor DT is P-type, the threshold voltage Vth can be set to a negative value.

[0088] Simultaneously, through the conducting sixth transistor T6, the initialization voltage Vini can be applied to the fourth node N4, and the voltage at the anode of the light-emitting diode LD can be initialized to the initialization voltage Vini.

[0089] During the light-emitting period t3, a light-emitting control signal EM at the on-level can be applied. At this time, the third transistor T3 and the fourth transistor T4 can be turned on.

[0090] A current path is formed by the conducting third transistor T3 and fourth transistor T4, starting from the high-potential drive voltage ELVDD, passing through the drive transistor DT, and reaching the light-emitting diode LD. The drive transistor DT can apply a drive current to the light-emitting diode LD corresponding to the voltage programmed in the previous period (i.e., the voltage Vdata-Vth corresponding to the difference between the data voltage Vdata and the threshold voltage Vth). At this time, the light-emitting diode LD can emit light corresponding to the programmed voltage.

[0091] Figure 4 This is a block diagram illustrating the configuration of the source driver IC according to the first embodiment. Figure 5 This is a block diagram illustrating the configuration of the source driver IC according to the second embodiment. Figure 6 The grayscale area is shown according to an embodiment.

[0092] refer to Figure 4 The source driver IC SDIC may include register unit 31, latch units 321 and 322, digital-to-analog converter 33, one or more output buffers 341, 342, 343, 344, 345 and 346, and buffer switching element BSW.

[0093] Register unit 31 can sequentially sample and output data from timing controller 10 ( Figure 1 (The number of bits in the received image data.)

[0094] Latch units 321 and 322 can latch the image data DATA received from register unit 31, and can simultaneously output the bits of the image data DATA in sync with the latch output control signals CLAT1 and CLAT2 received from timing controller 10.

[0095] In this embodiment, multiple latching units 321 and 322 may be configured. For example, latching units 321 and 322 may include a first latching unit 321 and a second latching unit 322 connected in series.

[0096] The first latch unit 321 is connected between the register unit 31 and the second latch unit 322. The first latch unit 321 may include switching elements that are respectively connected to the channels of the second latch unit 322. The first latch unit 321 can be turned on according to the first latch output control signal CLAT1, and can output the image data DATA stored in the first latch unit 321 to the second latch unit 322.

[0097] The second latch unit 322 is connected between the first latch unit 321 and the digital-to-analog converter 33. The second latch unit 322 may include switching elements respectively connected to the channels of the digital-to-analog converter 33. The second latch unit 322 can be turned on according to the second latch output control signal CLAT2, and can output the image data DATA stored in the second latch unit 322 to the digital-to-analog converter 33.

[0098] The digital-to-analog converter 33 converts the image data DATA received from the latch units 321 and 322 into a gamma voltage and generates a data voltage Vdata.

[0099] Output buffers 341, 342, 343, 344, 345, and 346 can be configured in multiples. Each of the output buffers 341, 342, 343, 344, 345, and 346 can buffer and amplify the data voltage Vdata output from the digital-to-analog converter 33 and output that voltage. The output terminal of each of the output buffers 341, 342, 343, 344, 345, and 346 can be connected to a buffer switching element BSW, which turns on / off in response to a source output enable signal SOE.

[0100] A buffer switch element BSW is connected between output buffers 341, 342, 343, 344, 345, and 346 and data lines DL1, DL2, DL3, DL4, DL5, and DL6. The buffer switch element BSW can, for example, respond to the source output enable signal SOE by outputting the data voltage Vdata from output buffers 341, 342, 343, 344, 345, and 346 to the data line DL.

[0101] In an embodiment, the source driver IC SDIC may further include a computing unit 35 and a charge sharing circuit 36.

[0102] The charge sharing circuit 36 ​​may include at least one charge sharing line CSL1, CSL2, and CSL3, and charge sharing switching elements SW11 to SW63 configured to control the connection between the charge sharing lines CSL1, CSL2, and CSL3 and the data lines DL1, DL2, DL3, DL4, DL5, and DL6. The charge sharing circuit 36 ​​may be embedded in the source driver IC SDIC or provided independently.

[0103] exist Figure 4 The diagram shows three charge-sharing lines CSL1, CSL2, and CSL3; however, the embodiment is not limited thereto. The charge-sharing circuit 36 ​​may include fewer or more charge-sharing lines CSL1, CSL2, and CSL3.

[0104] In an embodiment, the number of charge-sharing lines CSL1, CSL2, and CSL3 can be determined based on the number of grayscale regions defined in the calculation unit 35, which will be described below. For example, the charge-sharing circuit 36 ​​can be configured to include the same or fewer number of charge-sharing lines CSL1, CSL2, and CSL3 as the number of grayscale regions defined in the calculation unit 35. However, the embodiment is not limited thereto.

[0105] Charge-sharing switching elements SW11 to SW63 can be independently turned on / off according to the control signal CS. Data lines DL1, DL2, DL3, DL4, DL5, and DL6 can be connected to their corresponding charge-sharing lines CSL1, CSL2, and CSL3 via the turned-on charge-sharing switching elements SW11 to SW63.

[0106] Charge-sharing switching elements SW11 to SW63 can be configured as random circuit elements for controlling the electrical connections between charge-sharing lines CSL1, CSL2, and CSL3 and data lines DL1, DL2, DL3, DL4, DL5, and DL6. For example, as Figure 5 As shown, the charge-sharing switching elements SW11 to SW63 can be configured as transistors, but are not limited thereto. When the charge-sharing switching elements SW11 to SW63 are configured as transistors, each of the charge-sharing switching elements SW11 to SW63 is connected between data lines DL1, DL2, DL3, DL4, DL5 and DL6 and their corresponding charge-sharing lines CSL1, CSL2 and CSL3, and can be configured such that its gate electrode is connected to the computing unit 35 and receives the control signal CS.

[0107] Data lines DL1, DL2, DL3, DL4, DL5, and DL6 connected to a charge-sharing line CSL1, CSL2, and CSL3 via charge-sharing switching elements SW11 to SW63 can operate in charge-sharing mode. That is, during a predetermined charge-sharing period, data lines DL1, DL2, DL3, DL4, DL5, and DL6 connected to a charge-sharing line CSL1, CSL2, and CSL3 can share the charging voltage. Through charge sharing, the voltage of data lines DL1, DL2, DL3, DL4, DL5, and DL6 charged to a relatively high voltage value can be applied to data lines DL1, DL2, DL3, DL4, DL5, and DL6 charged to a relatively low voltage value. After charge sharing, the voltage of data lines DL1, DL2, DL3, DL4, DL5, and DL6 connected to a charge-sharing line CSL1, CSL2, and CSL3 can converge to the average value of the voltage charged before charge sharing (e.g., the average value of the voltage applied to the corresponding data lines).

[0108] After charge sharing, data lines DL1, DL2, DL3, DL4, DL5, and DL6 can quickly reach the required voltage. Specifically, data lines DL1, DL2, DL3, DL4, DL5, and DL6, which must be charged to a high voltage value in response to high grayscale, can be charged to the desired voltage value through charge sharing within a short charging time. Furthermore, since data lines DL1, DL2, DL3, DL4, DL5, and DL6 are charged to a predetermined voltage value through charge sharing, the voltage required to reach the desired voltage value after charge sharing is reduced. This configuration effectively reduces the power consumption of the source driver IC (SDIC).

[0109] The calculation unit 35 can generate a control signal CS based on the grayscale value of the image data DATA output from the latch units 321 and 322. The control signal CS can be, for example, a signal having a predetermined voltage or logic level for turning on or off the charge-sharing switching elements SW11 to SW63 of the charge-sharing circuit 36.

[0110] More specifically, the calculation unit 35 can select at least one data line DL1, DL2, DL3, DL4, DL5, and DL6 to undergo charge sharing based on the grayscale value of the image data DATA output from the first latch unit 321. The calculation unit 35 can output a control signal CS to charge sharing switching elements SW11 to SW63, such that the selected data lines DL1, DL2, DL3, DL4, DL5, and DL6 are connected to the same charge sharing lines CSL1, CSL2, and CSL3.

[0111] In this embodiment, the calculation unit 35 can define multiple grayscale regions and select data lines DL1, DL2, DL3, DL4, DL5, and DL6 of image data DATA to be applied to the same grayscale region to operate in charge-sharing mode. Multiple grayscale regions can be defined as including one or more grayscale values ​​between the minimum and maximum grayscale values, encompassing both the minimum and maximum grayscale values.

[0112] For example, multiple grayscale regions can be like Figure 6 The diagram shows four grayscale regions. The first grayscale region A1 (low grayscale region) includes gray levels 0 to 62; the second grayscale region A2 includes gray levels 63 to 126; the third grayscale region A3 includes gray levels 127 to 190; and the fourth grayscale region A4 (high grayscale region) includes gray levels 191 to 255.

[0113] However, grayscale areas are not limited to Figure 6The grayscale regions shown are grayscale regions. In various other embodiments, grayscale regions may be defined to be provided in fewer or more numbers than those shown. Each grayscale region may be configured to include the same or different numbers of grayscale values.

[0114] In this embodiment, the calculation unit 35 can determine which grayscale region the grayscale value of the image data DATA output from the first latch unit 321 is included in. The calculation unit 35 can select data lines DL1, DL2, DL3, DL4, DL5, and DL6 of the image data DATA to be applied to the same grayscale region to operate in charge-sharing mode.

[0115] For example, the computing unit 35 can control the charge-sharing switching elements SW13 to SW63 to make them to be applied Figure 6 The image data lines DL1, DL2, DL3, DL4, DL5, and DL6 of the first grayscale region A1 are connected to the third charge-sharing line CSL3. Additionally, the calculation unit 35 can control charge-sharing switch elements SW11 to SW61 to connect the image data lines DL1, DL2, DL3, DL4, DL5, and DL6 of the image data to be applied to the second grayscale region A2 to the first charge-sharing line CSL1. Furthermore, the calculation unit 35 can control charge-sharing switch elements SW12 to SW62 to connect the image data lines DL1, DL2, DL3, DL4, DL5, and DL6 of the image data to be applied to the third grayscale region A3 to the second charge-sharing line CSL2. Furthermore, the calculation unit 35 can control charge-sharing switch elements SW13 to SW63 to connect the image data lines DL1, DL2, DL3, DL4, DL5, and DL6 of the image data to be applied to the fourth grayscale region A4 to the third charge-sharing line CSL3. Here, the data lines DL1, DL2, DL3, DL4, DL5, and DL6 of the image data DATA to be applied to the high grayscale region (fourth grayscale region A4) and the low grayscale region (first grayscale region A1) are connected to the same third charge-sharing line CSL3. However, the embodiment is not limited to this.

[0116] In one embodiment, the calculation unit 35 can determine which grayscale region the grayscale values ​​of the continuously output image data DATA from the first latch unit 321 are included in, and determine whether to perform charge sharing for the next image data DATA based on the grayscale region of the previous image data DATA. Alternatively, the calculation unit 35 can determine whether to perform charge sharing based on the changes in the grayscale regions of the continuously output image data DATA.

[0117] The method of controlling the charge-sharing circuit 36 ​​by the computing unit 35 will now be described in detail with reference to the accompanying drawings.

[0118] Figure 7 This is a waveform diagram showing the signals applied to the pixel and source driver IC according to an embodiment.

[0119] Let's refer to each other. Figure 2 , Figure 4 and Figure 7 During the (n-1)th horizontal time period 1Hn-1, the (n-1)th scan signal SCn-1 can be applied to the pixel PX located in the (n-1)th pixel row. Additionally, the source output enable signal SOE, which is at an on level (e.g., low level), can be applied to the data driver IC SDIC. At this time, the buffer switching element BWS can be turned on, and the data voltage Vdata output from the output buffers 341, 342, 343, 344, 345, and 346 can be applied to the pixel PX located in the (n-1)th pixel row. At this time, each data line DL1, DL2, DL3, DL4, DL5, and DL6 can be charged using the applied data voltage Vdata.

[0120] During the charge-sharing period (CSP), the source output enable signal SOE can be switched to a shutdown level (e.g., high level). At this time, the buffer switching element BSW can be turned off, and the output buffers 341, 342, 343, 344, 345, and 346 can be electrically disconnected from the data lines DL1, DL2, DL3, DL4, DL5, and DL6.

[0121] During the charge-sharing period (CSP), the control signal CS can be applied to the charge-sharing switching elements SW11 to SW63 via the calculation unit 35. In this case, the control signal CS at the on level can be applied to the charge-sharing switching elements SW11 to SW63 connected to the data lines DL1, DL2, DL3, DL4, DL5, and DL6 operating in charge-sharing mode. Conversely, the control signal CS at the off level can be applied to the charge-sharing switching elements SW11 to SW63 connected to the data lines DL1, DL2, DL3, DL4, DL5, and DL6 not operating in charge-sharing mode.

[0122] During the charge-sharing period (CSP), voltages can be distributed among data lines DL1, DL2, DL3, DL4, DL5, and DL6 connected to a charge-sharing line CSL1, CSL2, and CSL3. That is, voltages can be redistributed from data lines DL1, DL2, DL3, DL4, DL5, and DL6 charged to a high data voltage Vdata during the (n-1)th level period 1Hn-1 to data lines DL1, DL2, DL3, DL4, DL5, and DL6 charged to a low data voltage Vdata. After the charge-sharing period (CSP), the voltages of data lines DL1, DL2, DL3, DL4, DL5, and DL6 connected to a charge-sharing line CSL1, CSL2, and CSL3 can converge to the average value of the voltages charged before charge sharing.

[0123] exist Figure 7 For example, the example shows a case where the second data line DL2 and the third data line DL3 are charge-shared. During the (n-1)th level time period 1Hn-1, the second data line DL2, charged to 5V, and the third data line DL3, charged to 3V, can be charged to 4V as the average voltage value after charge sharing.

[0124] During the nth horizontal time period 1Hn, the nth scan signal SCn can be applied to the pixel PX located in the nth pixel row. Additionally, the source output enable signal SOE, which is at an on level (e.g., low level), can be applied to the data driver IC. At this time, the buffer switching element BSW can be turned on, and the data voltage Vdata output from the output buffers 341, 342, 343, 344, 345, and 346 can be applied to the pixel PX located in the nth pixel row. At this time, each data line DL1, DL2, DL3, DL4, DL5, and DL6 can be charged using the applied data voltage Vdata.

[0125] To charge data lines DL1, DL2, DL3, DL4, DL5, and DL6 to the voltage corresponding to the desired image data DATA, a data voltage Vdata, corresponding to the difference between the previously charged voltage (i.e., the redistributed voltage) and the desired charging voltage, can be applied to each data line DL1, DL2, DL3, DL4, DL5, and DL6. In this case, when the difference between the previously charged voltage and the desired charging voltage is large, the magnitude of the differential voltage applied to data lines DL1, DL2, DL3, DL4, DL5, and DL6 increases, thus potentially increasing the power consumption of the source driver IC SDIC. Conversely, when the difference between the previously charged voltage and the desired charging voltage is small, the magnitude of the differential voltage applied to data lines DL1, DL2, DL3, DL4, DL5, and DL6 decreases, thus potentially reducing the power consumption of the source driver IC SDIC.

[0126] For example, when the charge-sharing mode is not applied, if the required charging voltage for the third data line DL3 in the nth level time period 1Hn is 5V, then a voltage increase of 2V is needed in the third data line DL3. However, when the charge-sharing mode is applied, a voltage increase of only 1V is sufficient for the third data line DL3 to reach the required charging voltage, thus reducing the power consumption of the source driver IC SDIC.

[0127] By using the charge-sharing mode provided in the manner described above, the voltage output to data lines DL1, DL2, DL3, DL4, DL5, and DL6 can quickly reach the target data voltage, thereby improving image quality degradation and enhancing image quality.

[0128] Figure 8 This shows an example of how the grayscale value of the data voltage changes between horizontal time periods. Figure 9 Showing according to Figure 8 An embodiment of the operation state of the charge-sharing circuit in the embodiment.

[0129] exist Figure 8 and Figure 9 In the embodiments, together with reference to Figure 4 The calculation unit 35 can determine which grayscale region the grayscale value of the image data DATA output from the first latch unit 321 is included in, and can control the charge sharing switch elements SW11 to SW63 to connect the data lines DL1, DL2, DL3, DL4, DL5 and DL6 of the image data DATA to be applied to the same grayscale region to the same charge sharing lines CSL1, CSL2 and CSL3.

[0130] More in detail, Figure 8 In this embodiment, the calculation unit 35 can determine, corresponding to the nth horizontal time period 1Hn, which grayscale region the grayscale value of the image data DATA output from the first latch unit 321 is included in. The calculation unit 35 can select data lines DL1, DL2, DL3, DL4, DL5 and DL6 of the image data DATA to be applied with the same grayscale region to operate in charge-sharing mode.

[0131] refer to Figure 9The calculation unit 35 can output a control signal CS to activate the 63rd charge-sharing switch element SW63, so that the sixth data line DL6 of the image data DATA to be applied to the first grayscale region A1 can be connected to the third charge-sharing line CSL3. The calculation unit 35 can output a control signal CS to activate the 41st charge-sharing switch element SW41 and the 51st charge-sharing switch element SW51, so that the fourth data line DL4 and the fifth data line DL5 of the image data DATA to be applied to the second grayscale region A2 can be connected to the first charge-sharing line CSL1. The calculation unit 35 can output a control signal CS to activate the 32nd charge-sharing switch element SW32, so that the third data line DL3 of the image data DATA to be applied to the third grayscale region A3 can be connected to the second charge-sharing line CSL2. Additionally, the computing unit 35 can output a control signal CS to turn on the 13th charge-sharing switch element SW13 and the 23rd charge-sharing switch element SW23, so that the first data line DL1 and the second data line DL2 of the image data DATA to be applied to the fourth grayscale region A4 can be connected to the third charge-sharing line CSL3.

[0132] The fourth data line DL4 and the fifth data line DL5, connected to the first charge-sharing line CSL1 in response to the control signal CS, can be charged by sharing the voltage charged in the previous period. Additionally, the third data line DL3, connected to the second charge-sharing line CSL2, can be charged by sharing the voltage charged in the previous period with the connected data lines. Furthermore, the first data line DL1, the second data line DL2, and the sixth data line DL6, connected to the third charge-sharing line CSL3, can be charged by sharing the voltage charged in the previous period.

[0133] Figure 10 Showing according to Figure 8 Another embodiment of the operation state of the charge-sharing circuit in the embodiment.

[0134] exist Figure 8 and Figure 10 In the embodiments, together with reference to Figure 4 The calculation unit 35 can determine which grayscale region the grayscale value of the image data DATA output from the first latch unit 321 is included in, and can control the charge sharing switch elements SW11 to SW63 to connect the data lines DL1, DL2, DL3, DL4, DL5 and DL6 of the image data DATA to be applied and included in the same grayscale region to the same charge sharing lines CSL1, CSL2 and CSL3.

[0135] In this scenario, the calculation unit 35 can determine which grayscale region the grayscale values ​​of the continuously output image data DATA from the first latch unit 321 fall within, and determine whether to perform charge sharing on the next image data DATA based on the grayscale region of the previous image data DATA. Alternatively, the calculation unit 35 can determine whether to perform charge sharing based on the changes in the grayscale regions of the continuously output image data DATA.

[0136] More in detail, Figure 8 In this embodiment, the calculation unit 35 can determine, corresponding to the (n-1)th (n is a natural number) horizontal time period 1Hn-1, which grayscale region (hereinafter, the previous grayscale region) the grayscale value of the image data DATA continuously output from the first latch unit 321 is included in. Additionally, the calculation unit 35 can determine, corresponding to the nth horizontal time period 1Hn, which grayscale region (hereinafter, the next grayscale region) the grayscale value of the image data DATA continuously output from the first latch unit 321 is included in.

[0137] In this embodiment, when the current grayscale region and the next grayscale region are the same, the calculation unit 35 may not apply the charge-sharing mode to the data lines DL1, DL2, DL3, DL4, DL5, and DL6 to which the corresponding image data DATA is to be applied. In the illustrated embodiment, during the (n-1)th horizontal time period 1Hn-1, the image data DATA of the second grayscale region A2 is output to the fourth data line DL4, and during the nth horizontal time period 1Hn, the image data DATA of the second grayscale region A2 is output to the fourth data line DL4. In such an embodiment, the calculation unit 35 may output a control signal CS to turn off the charge-sharing switching elements SW41, SW42, and SW43 connected to the fourth data line DL4, so that the fourth data line DL4 does not operate in charge-sharing mode.

[0138] In the embodiment, when the current grayscale region and the next grayscale region correspond to predetermined conditions, the calculation unit 35 can apply a charge-sharing mode to the data lines DL1, DL2, DL3, DL4, DL5 and DL6 to which the corresponding image data DATA is to be applied.

[0139] For example, when the next grayscale region is the fourth grayscale region A4 and the previous grayscale region is the first grayscale region A1, the calculation unit 35 can apply a charge-sharing mode to the data lines DL1, DL2, DL3, DL4, DL5, and DL6 to which corresponding image data DATA is to be applied. In the illustrated embodiment, during the (n-1)th horizontal time period 1Hn-1, the image data DATA of the third grayscale region A3 can be output to the first data line DL1, and during the nth horizontal time period 1Hn, the image data DATA of the fourth grayscale region A4 can be output to the first data line DL1. The next grayscale region to be applied to the first data line DL1 is the fourth grayscale region A4; however, the previous grayscale region is not the first grayscale region A1. Therefore, the calculation unit 35 can output a control signal to turn off the 13th charge-sharing switch element SW13.

[0140] In the illustrated embodiment, during the (n-1)th horizontal time period 1Hn-1, the image data DATA of the first grayscale region A1 can be output to the second data line DL2, and during the nth horizontal time period 1Hn, the image data DATA of the fourth grayscale region A4 can be output to the second data line DL2. The next grayscale region to be applied to the second data line DL2 is the fourth grayscale region A4, and its preceding grayscale region is the first grayscale region A1. Therefore, the calculation unit 35 can output a control signal CS to turn on the 23rd charge-sharing switch element SW23.

[0141] For example, when the next grayscale region is the first grayscale region A1 and the previous grayscale region is the fourth grayscale region A4, the calculation unit 35 can apply a charge-sharing mode to the data lines DL1, DL2, DL3, DL4, DL5, and DL6 to which corresponding image data DATA is to be applied. In the illustrated embodiment, during the (n-1)th horizontal time period 1Hn-1, the image data DATA of the fourth grayscale region A4 can be output to the sixth data line DL6, and during the nth horizontal time period 1Hn, the image data DATA of the first grayscale region A1 can be output to the sixth data line DL6. The next grayscale region of the image data DATA to be applied to the sixth data line DL6 is the first grayscale region A1, and its previous grayscale region is the fourth grayscale region A4. Therefore, the calculation unit 35 can output a control signal CS to turn on the 63rd charge-sharing switch element SW63.

[0142] Based on the predetermined conditions described above, the calculation unit 35 can select data lines DL1, DL2, DL3, DL4, DL5, and DL6 of the image data DATA to be applied to the same grayscale region to operate in charge-sharing mode. More specifically, the calculation unit 35 can select data lines DL2 and DL6 of the image data DATA to be applied to the first grayscale region A1 and the fourth grayscale region A4 that satisfy the above conditions to operate in charge-sharing mode, such that data lines DL2 and DL6 are connected to a charge-sharing line CSL3. Additionally, the calculation unit 35 can select data line DL3 of the image data DATA to be applied to the third grayscale region A3 that satisfies the above conditions to operate in charge-sharing mode, such that data line DL3 is connected to a charge-sharing line CSL2. Furthermore, the calculation unit 35 can select data line DL5 of the image data DATA to be applied to the second grayscale region A2 that satisfies the above conditions to operate in charge-sharing mode, such that data line DL5 is connected to a charge-sharing line CSL1.

[0143] refer to Figure 10 The computing unit 35 can output a control signal CS to turn on the 23rd charge-sharing switch element SW23 and the 63rd charge-sharing switch element SW63, so that the sixth data line DL6 and the second data line DL2 of the image data DATA to be applied to the first gray area A1 and the fourth gray area A4 can be connected to the third charge-sharing line CSL3.

[0144] The computing unit 35 can output a control signal CS to turn on the 51st charge-sharing switch element SW51, so that the fifth data line DL5 of the image data DATA to be applied to the second grayscale region A2 can be connected to the first charge-sharing line CSL1.

[0145] The computing unit 35 can output a control signal CS to activate the 32nd charge-sharing switch element SW32, allowing the third data line DL3 of the image data DATA to be applied to the third grayscale region A3 to be connected to the second charge-sharing line CSL2. Additionally, the computing unit 35 can output a control signal CS to activate the 23rd charge-sharing switch element SW23, allowing the second data line DL2 of the image data DATA to be applied to the fourth grayscale region A4 to be connected to the third charge-sharing line CSL3. The third data line DL3 can perform charge sharing with the data line of the image data DATA to be applied to the third grayscale region A3.

[0146] Figures 11 to 14 This demonstrates the effect of improving power consumption based on charge-sharing operation.

[0147] first, Figure 11The effect of improving power consumption is shown when the data line of image data DATA corresponding to the second grayscale region A2 is operated in charge-sharing mode.

[0148] exist Figure 11 In (a), during the (n-1)th horizontal time period 1Hn-1, the data voltage Vdata corresponding to the image data DATA in the fourth grayscale region A4 can be charged to nine data lines, and the data voltage Vdata corresponding to the image data DATA in the first grayscale region A1 can be charged to one data line. In an embodiment, the data voltage Vdata included in the fourth grayscale region A4 can be 5V, and the data voltage Vdata included in the first grayscale region A1 can be 2V.

[0149] When the charging voltage is distributed between the data lines through charge sharing, the average value of the charged voltage (i.e., (5*9+2) / 10=4.7V) is charged to each data line.

[0150] During the nth horizontal time period 1Hn, the data line can be charged to the data voltage Vdata corresponding to the image data DATA of the second grayscale region A2. In an embodiment, the data voltage Vdata corresponding to the second grayscale region A2 can be 3V.

[0151] When charge sharing is not performed, during the nth level time period 1Hn, a voltage of 1V must be further applied to the data line that has already been charged to the data voltage Vdata corresponding to the first grayscale region A1. However, due to charge sharing, a voltage of 4.7V is pre-charged to the corresponding data line, so during the nth level time period 1Hn, the corresponding data line may need to discharge to 3V. Similarly, other data lines may need to discharge to 3V. Therefore, the power consumption of the source driver IC SDIC can be reduced by up to approximately 1V.

[0152] exist Figure 11 In (b), during the (n-1)th horizontal time period 1Hn-1, the 5V data voltage Vdata corresponding to the image data DATA of the fourth grayscale region A4 can be charged to the five data lines, and the 2V data voltage Vdata corresponding to the image data DATA of the first grayscale region A1 can be charged to the five data lines.

[0153] When the charging voltage is distributed between the data lines through charge sharing, the average value of the charged voltage (i.e., (5*5+2*5) / 10=3.5V) is charged to each data line.

[0154] During the nth level time period 1Hn, the data lines can be charged to the data voltage Vdata corresponding to the image data DATA of the second grayscale region A2. When charge sharing is not performed, during the nth level time period 1Hn, a further 1V voltage must be applied to the data lines that have already been charged to the data voltage Vdata corresponding to the first grayscale region A1, and a total of 5V data voltage Vdata must be applied to the five data lines.

[0155] However, due to charge sharing, the corresponding data line is pre-charged to 3.5V, and during the nth level period 1Hn, the corresponding data line may need to discharge to 3V. Therefore, the power consumption of the source driver IC SDIC can be reduced by up to approximately 5V.

[0156] exist Figure 11 In (c), during the (n-1)th horizontal time period 1Hn-1, the data voltage Vdata corresponding to the image data DATA of the fourth grayscale region A4 can be charged to one data line, and the data voltage Vdata corresponding to the image data DATA of the first grayscale region A1 can be charged to nine data lines.

[0157] When the charging voltage is distributed between the data lines through charge sharing, the average value of the charged voltage (i.e., (5+2*9) / 10=2.3V) is charged to each data line.

[0158] During the nth level time period 1Hn, the data lines can be charged to the data voltage Vdata corresponding to the image data DATA of the second grayscale region A2. When charge sharing is not performed, during the nth level time period 1Hn, a further 1V voltage must be applied to the data lines already charged to the data voltage Vdata corresponding to the first grayscale region A1, and a total of 9V of data voltage Vdata must be applied to the nine data lines. The data lines already charged to the data voltage Vdata corresponding to the fourth grayscale region A4 need to be discharged to 3V.

[0159] Because charge sharing is performed, a voltage of 2.3V is pre-charged to the corresponding data line. Therefore, in the nth level period 1Hn, a data voltage of 0.7V Vdata must be applied to the corresponding data line, and a voltage of 7V is required for all data lines.

[0160] As a result, when charge sharing is performed, the power consumption of the source driver IC SDIC can be reduced by up to approximately 2V.

[0161] Figure 12 The effect of improving power consumption is shown when the data line of image data DATA corresponding to the third grayscale region A3 is operated in charge-sharing mode.

[0162] exist Figure 12 In (a), during the (n-1)th horizontal time period 1Hn-1, the data voltage Vdata corresponding to the image data DATA of the fourth grayscale region A4 can be charged to eight data lines, the data voltage Vdata corresponding to the image data DATA of the second grayscale region A2 can be charged to one data line, and the data voltage Vdata corresponding to the image data DATA of the first grayscale region A1 can be charged to one data line. In an embodiment, the data voltage Vdata corresponding to the fourth grayscale region A4 can be 5V, the data voltage Vdata corresponding to the second grayscale region A2 can be 3V, and the data voltage Vdata corresponding to the first grayscale region A1 can be 2V.

[0163] When the charging voltage is distributed between the data lines through charge sharing, the average value of the charged voltage (i.e., (5*8+3+2) / 10=4.5V) is charged to each data line.

[0164] During the nth horizontal time period 1Hn, the data line can be charged to the data voltage Vdata corresponding to the image data DATA of the third grayscale region A3. In an embodiment, the data voltage Vdata corresponding to the third grayscale region A3 can be 4V.

[0165] When charge sharing is not performed, during the nth level time period 1Hn, a voltage of 1V must be further applied to the data line that has been charged to the data voltage Vdata corresponding to the second grayscale region A2, and a voltage of 2V must be further applied to the data line that has been charged to the data voltage Vdata corresponding to the first grayscale region A1. The data line that has been charged to the data voltage Vdata corresponding to the fourth grayscale region A4 may need to be discharged to 4V.

[0166] Because of charge sharing, the corresponding data line is pre-charged to 4.5V. Therefore, during the nth level period 1Hn, the corresponding data line may need to discharge to 4V. As a result, the power consumption of the source driver IC SDIC can be reduced by up to approximately 3V.

[0167] exist Figure 12 In (b), during the (n-1)th horizontal time period 1Hn-1, the data voltage Vdata corresponding to the image data DATA of the fourth grayscale region A4 can be charged to one data line, the data voltage Vdata corresponding to the image data DATA of the second grayscale region A2 can be charged to eight data lines, and the data voltage Vdata corresponding to the image data DATA of the first grayscale region A1 can be charged to one data line.

[0168] When the charging voltage is distributed between the data lines through charge sharing, the average value of the charged voltage (i.e., (5+3*8+2) / 10=3.1V) is charged to each data line.

[0169] During the nth level time period 1Hn, the data lines can be charged to the data voltage Vdata corresponding to the image data DATA of the third grayscale region A3. When charge sharing is not performed, during the nth level time period 1Hn, a further 1V voltage must be applied to the data lines already charged to the data voltage Vdata corresponding to the second grayscale region A2, and a total of 8V Vdata must be applied to the eight data lines. Additionally, a further 2V voltage must be applied to the data lines already charged to the data voltage Vdata corresponding to the first grayscale region A1. Data lines already charged to the data voltage Vdata corresponding to the fourth grayscale region A4 may need to be discharged to 4V. That is, a total of 10V must be applied to all data lines.

[0170] Because charge sharing is performed, a voltage of 3.1V is pre-charged to the corresponding data line. Therefore, in the nth level period 1Hn, a data voltage of 0.9V Vdata must be applied to the corresponding data line, and a voltage of 9V is required for all data lines.

[0171] As a result, when charge sharing is performed, the power consumption of the source driver IC SDIC can be reduced by up to approximately 1V.

[0172] exist Figure 12 In (c), during the (n-1)th horizontal time period 1Hn-1, the data voltage Vdata corresponding to the image data DATA of the fourth gray-scale region A4 can be charged to one data line, the data voltage Vdata corresponding to the image data DATA of the second gray-scale region A2 can be charged to one data line, and the data voltage Vdata corresponding to the image data DATA of the first gray-scale region A1 can be charged to eight data lines.

[0173] When the charging voltage is distributed between the data lines through charge sharing, the average value of the charged voltage (i.e., (5+3+2*8) / 10=2.4V) is charged to each data line.

[0174] During the nth level time period 1Hn, the data lines can be charged to the data voltage Vdata corresponding to the image data DATA of the third grayscale region A3. When charge sharing is not performed, during the nth level time period 1Hn, a voltage of 1V must be further applied to the data lines already charged to the data voltage Vdata corresponding to the second grayscale region A2. Additionally, a voltage of 2V must be further applied to the data lines already charged to the data voltage Vdata corresponding to the first grayscale region A1, and a voltage of 16V must be applied to all eight data lines. The data lines already charged to the data voltage Vdata corresponding to the fourth grayscale region A4 may need to be discharged to 4V. That is, a total of 17V must be applied to all data lines.

[0175] Because charge sharing is performed, a voltage of 2.4V is pre-charged to the corresponding data line. Therefore, in the nth level period 1Hn, a data voltage of 1.6V Vdata must be applied to the corresponding data line, and a voltage of 16V is required for all data lines.

[0176] As a result, when charge sharing is performed, the power consumption of the source driver IC SDIC can be reduced by up to approximately 1V.

[0177] Figure 13 The effect of improving power consumption is shown when the data lines of image data DATA corresponding to the first grayscale region A1 and the fourth grayscale region A4 are operated in charge-sharing mode.

[0178] exist Figure 13 In (a), during the (n-1)th horizontal time period 1Hn-1, the data voltage Vdata corresponding to the image data DATA of the fourth grayscale region A4 can be charged to nine data lines, and the data voltage Vdata corresponding to the image data DATA of the first grayscale region A1 can be charged to one data line. In an embodiment, the data voltage Vdata corresponding to the fourth grayscale region A4 can be 5V, and the data voltage Vdata corresponding to the first grayscale region A1 can be 2V.

[0179] When the charging voltage is distributed between the data lines through charge sharing, the average value of the charged voltage (i.e., (5*9+2) / 10=4.7V) is charged to each data line.

[0180] In the nth horizontal time period 1Hn, the data voltage Vdata corresponding to the image data DATA of the first grayscale region A1 can be charged to nine data lines, and the data voltage Vdata corresponding to the image data DATA of the fourth grayscale region A4 can be charged to one data line.

[0181] When charge sharing is not performed, during the nth level time period 1Hn, a voltage of 3V must be further applied to the data line that has been charged to the data voltage Vdata corresponding to the first grayscale region A1. The data line that has been charged to the data voltage Vdata corresponding to the fourth grayscale region A4 may need to be discharged to 2V.

[0182] Because charge sharing is performed, a voltage of 4.7V is pre-charged to the corresponding data line. Therefore, in the nth level period 1Hn, a data voltage of 0.3V Vdata must be further applied to the data line that was previously charged to the data voltage Vdata corresponding to the first grayscale region A1.

[0183] As a result, when charge sharing is performed, the power consumption of the source driver IC SDIC can be reduced by up to approximately 2.7V.

[0184] exist Figure 13 In (b), during the (n-1)th horizontal time period 1Hn-1, the data voltage Vdata corresponding to the image data DATA of the fourth grayscale region A4 can be charged to the five data lines, and the data voltage Vdata corresponding to the image data DATA of the first grayscale region A1 can be charged to the five data lines.

[0185] When the charging voltage is distributed between the data lines through charge sharing, the average value of the charged voltage (i.e., (5*5+2*5) / 10=3.5V) is charged to each data line.

[0186] During the nth horizontal time period 1Hn, the data voltage Vdata corresponding to the image data DATA of the first grayscale region A1 can be charged to the five data lines, and the data voltage Vdata corresponding to the image data DATA of the fourth grayscale region A4 can also be charged to the five data lines.

[0187] When charge sharing is not performed, during the nth level time period 1Hn, a voltage of 3V must be further applied to the data lines that have been charged to the data voltage Vdata corresponding to the first grayscale region A1, and a voltage of 15V must be further applied to the five data lines. The data lines that have been charged to the data voltage Vdata corresponding to the fourth grayscale region A4 may need to be discharged to 2V.

[0188] Because charge sharing is performed, a voltage of 3.5V is pre-charged to the corresponding data lines. Therefore, in the nth level period 1Hn, a data voltage of 1.5V Vdata must be further applied to the data lines that were previously charged to the data voltage Vdata corresponding to the first grayscale region A1, and a voltage of 7.5V must be further applied to the five data lines.

[0189] As a result, when charge sharing is performed, the power consumption of the source driver IC SDIC can be reduced by up to approximately 7.5V.

[0190] exist Figure 13 In (c), during the (n-1)th horizontal time period 1Hn-1, the data voltage Vdata corresponding to the image data DATA of the fourth grayscale region A4 can be charged to one data line, and the data voltage Vdata corresponding to the image data DATA of the first grayscale region A1 can be charged to nine data lines.

[0191] When the charging voltage is distributed between the data lines through charge sharing, the average value of the charged voltage (i.e., (5+2*9) / 10=2.3V) is charged to each data line.

[0192] In the nth horizontal time period 1Hn, the data voltage Vdata corresponding to the image data DATA of the first grayscale region A1 can be charged to one data line, and the data voltage Vdata corresponding to the image data DATA of the fourth grayscale region A4 can be charged to nine data lines.

[0193] When charge sharing is not performed, during the nth level time period 1Hn, a voltage of 3V must be further applied to the data lines that have already been charged to the data voltage Vdata corresponding to the first grayscale region A1, and a voltage of 27V must be further applied to the nine data lines. The data lines that have already been charged to the data voltage Vdata corresponding to the fourth grayscale region A4 may need to be discharged to 2V.

[0194] Because charge sharing is performed, a voltage of 2.3V is pre-charged to the corresponding data lines. Therefore, in the nth level period 1Hn, a data voltage of 2.7V Vdata must be further applied to the data lines that were previously charged to the data voltage Vdata corresponding to the first grayscale region A1, and a voltage of 24.3V must be further applied to the nine data lines.

[0195] As a result, when charge sharing is performed, the power consumption of the source driver IC SDIC can be reduced by up to approximately 2.7V.

[0196] Figure 14 The effect of improved power consumption is shown when the data lines connected to the 2160 output buffer channels operate in charge-sharing mode.

[0197] exist Figure 14In (a), during the (n-1)th horizontal time period 1Hn-1, the data voltage Vdata corresponding to the image data DATA of the fourth grayscale region A4 can be charged to 1080 data lines, and the data voltage Vdata corresponding to the image data DATA of the first grayscale region A1 can be charged to the remaining 1080 data lines. In an embodiment, the data voltage Vdata corresponding to the fourth grayscale region A4 can be 5V, and the data voltage Vdata corresponding to the first grayscale region A1 can be 2V.

[0198] When the charging voltage is distributed between the data lines through charge sharing, the average value of the charged voltage (i.e., (5*1080+2*1080) / 2160=3.5V) is charged to each data line.

[0199] In the nth horizontal time period 1Hn, the data voltage Vdata corresponding to the image data DATA of the first grayscale region A1 can be charged to 1080 data lines, and the data voltage Vdata corresponding to the image data DATA of the fourth grayscale region A4 can be charged to the remaining 1080 data lines.

[0200] When charge sharing is not performed, during the nth horizontal time period 1Hn, a voltage of 3V must be further applied to the data lines that have been charged to the data voltage Vdata corresponding to the first grayscale region A1, and a total voltage of 3240V must be applied to the 1080 data lines. When the capacitance of the data line is 32pF, during a 4.5us horizontal time period, the current applied to the data lines is 23.04mA, with the data voltage output through the 1080 channels in a time-division manner. The data lines that have been charged to the data voltage Vdata corresponding to the fourth grayscale region A4 may only need to be discharged.

[0201] Due to charge sharing, the data lines are pre-charged with a voltage of 3.5V. Therefore, during the nth horizontal time period 1Hn, a further 1.5V data voltage Vdata must be applied to the data lines previously charged to the data voltage Vdata corresponding to the first grayscale region A1, and a total voltage of 1620V must be applied to the 1080 data lines. When the capacitance of the data lines is 32pF and a horizontal time period is 4.5us, the current applied to the data lines is 11.52mA.

[0202] When six source driver ICs SDIC are configured in the data driver 30, the power consumption reduction achieved by implementing charge sharing throughout the source driver ICs SDIC can be 69.12 mW.

[0203] exist Figure 14In (b), during the (n-1)th horizontal time period 1Hn-1, the data voltage Vdata corresponding to the image data DATA of the fourth grayscale region A4 can be charged to 100 data lines, the data voltage Vdata corresponding to the image data DATA of the second grayscale region A2 can be charged to the other 100 data lines, and the data voltage Vdata corresponding to the image data DATA of the first grayscale region A1 can be charged to the remaining 1960 data lines. In an embodiment, the data voltage Vdata corresponding to the fourth grayscale region A4 can be 5V, the data voltage Vdata corresponding to the second grayscale region A2 can be 3V, and the data voltage Vdata corresponding to the first grayscale region A1 can be 2V.

[0204] When the charging voltage is distributed between the data lines through charge sharing, the average value of the charged voltage (i.e., (5*100+3*100+2*1960) / 2160=2.2V) is charged to each data line.

[0205] During the nth horizontal time period 1Hn, the data voltage Vdata corresponding to the image data DATA of the third grayscale region A3 can be charged to the data line. In this embodiment, the data voltage Vdata corresponding to the third grayscale region A3 can be 4V.

[0206] When charge sharing is not performed, in the nth level time period 1Hn, a voltage of 1V must be further applied to the data lines that have been charged to the data voltage Vdata corresponding to the second grayscale region A2, and a total voltage of 100V must be applied to 100 data lines. Additionally, a voltage of 2V must be further applied to the data lines that have been charged to the data voltage Vdata corresponding to the first grayscale region A1, and a total voltage of 3920V must be further applied to 1960 data lines. As a result, a total voltage of 4020V must be applied to all data lines.

[0207] When the data line capacitance is 32pF, the data voltage is output through 1080 channels in a time-division manner during a 4.5µs horizontal period. If this pattern is repeated between two horizontal periods, the current applied to the data line is 14.65mA. The data line that has been charged to the data voltage Vdata corresponding to the fourth grayscale region A4 may only need to be discharged.

[0208] Because charge sharing is implemented, a 2.2V voltage is pre-charged to the corresponding data lines. Therefore, in the nth level period 1Hn, a 1.8V data voltage Vdata must be applied to the corresponding data lines, and a total of 3888V must be applied to 2160 data lines. When the capacitance of the data lines is 32pF and a level period is 4.5us, if this pattern is repeated in two level periods, the current applied to the data lines is 14.18mA.

[0209] When six source driver ICs SDIC are configured in the data driver 30, the power consumption reduction achieved by charge sharing across the entire source driver IC SDIC can be 2.82mW.

[0210] Figure 15 This is a block diagram illustrating the configuration of the source driver IC according to the third embodiment. In addition to providing four charge-sharing lines CSL1, CSL2, CSL3, and CSL4, Figure 15 The embodiments and Figure 4 The embodiments are substantially the same, therefore, the same reference numerals will be used for the same elements, and their detailed descriptions will be omitted.

[0211] refer to Figure 15 The source driver IC SDIC may include register unit 31, latch units 321 and 322, digital-to-analog converter 33, one or more output buffers 341, 342, 343, 344, 345 and 346, and buffer switching element BSW. The source driver IC SDIC may also include calculation unit 35 and charge sharing circuit 36.

[0212] The charge-sharing circuit 36 ​​may include at least one charge-sharing line CSL1, CSL2, CSL3, and CSL4, and charge-sharing switching elements SW11 to SW64 configured to control the connection between the charge-sharing lines CSL1, CSL2, CSL3, and CSL4 and the data lines DL1, DL2, DL3, DL4, DL5, and DL6. The charge-sharing circuit 36 ​​may be embedded in the source driver IC SDIC or provided independently.

[0213] exist Figure 15 The diagram shows four charge-sharing lines CSL1, CSL2, CSL3, and CSL4; however, the embodiment is not limited thereto. The charge-sharing circuit 36 ​​may include fewer or more charge-sharing lines CSL1, CSL2, CSL3, and CSL4.

[0214] In an embodiment, the number of charge-sharing lines CSL1, CSL2, CSL3, and CSL4 can be determined based on the number of grayscale regions defined in the calculation unit 35. For example, the charge-sharing circuit 36 ​​can be configured to include the same or fewer charge-sharing lines CSL1, CSL2, CSL3, and CSL4 as the number of grayscale regions defined in the calculation unit 35. However, the embodiment is not limited thereto.

[0215] Charge-sharing switching elements SW11 to SW64 can be independently turned on / off according to the control signal CS. Data lines DL1, DL2, DL3, DL4, DL5, and DL6 can be connected to one of the corresponding charge-sharing lines CSL1, CSL2, CSL3, and CSL4 via the turned-on charge-sharing switching elements SW11 to SW64.

[0216] Data lines DL1, DL2, DL3, DL4, DL5, and DL6 connected to a charge-sharing line CSL1, CSL2, CSL3, and CSL4 via charge-sharing switching elements SW11 to SW64 can operate in charge-sharing mode. That is, data lines DL1, DL2, DL3, DL4, DL5, and DL6 connected to a charge-sharing line CSL1, CSL2, CSL3, and CSL4 can share the charging voltage during a predetermined charge-sharing period. Through charge sharing, the voltage of data lines DL1, DL2, DL3, DL4, DL5, and DL6 charged to a relatively high voltage value can be applied to data lines DL1, DL2, DL3, DL4, DL5, and DL6 charged to a relatively low voltage value. After charge sharing, the voltage of data lines DL1, DL2, DL3, DL4, DL5, and DL6 connected to a charge-sharing line CSL1, CSL2, CSL3, and CSL4 can converge to the average value of the charging voltage before charge sharing.

[0217] After charge sharing, data lines DL1, DL2, DL3, DL4, DL5, and DL6 can quickly reach the required voltage. Specifically, data lines DL1, DL2, DL3, DL4, DL5, and DL6, which must be charged to a high voltage value in response to high grayscale, can be charged to the desired voltage value through charge sharing. Furthermore, by pre-charging data lines DL1, DL2, DL3, DL4, DL5, and DL6 to a predetermined voltage value through charge sharing, the voltage required to reach the desired voltage value after charge sharing is reduced. This configuration effectively reduces the power consumption of the source driver IC (SDIC).

[0218] The calculation unit 35 can generate a control signal CS based on the grayscale value of the image data DATA output from the latch units 321 and 322. The control signal CS can be, for example, a signal having a predetermined voltage or logic level for turning on or off the charge-sharing switching elements SW11 to SW64 of the charge-sharing circuit 36.

[0219] More specifically, the calculation unit 35 can select at least one data line DL1, DL2, DL3, DL4, DL5, and DL6 to undergo charge sharing based on the grayscale value of the image data DATA output from the first latch unit 321. The calculation unit 35 can output a control signal CS to charge sharing switching elements SW11 to SW64, such that the selected data lines DL1, DL2, DL3, DL4, DL5, and DL6 are connected to the same charge sharing lines CSL1, CSL2, CSL3, and CSL4.

[0220] In this embodiment, the calculation unit 35 can define multiple grayscale regions and select data lines DL1, DL2, DL3, DL4, DL5, and DL6 of the image data DATA to be applied in the same grayscale region to operate in charge-sharing mode. Multiple grayscale regions can be defined as including one or more grayscale values ​​between the minimum and maximum grayscale values, encompassing both the minimum and maximum grayscale values.

[0221] For example, multiple grayscale regions can be like Figure 6 The diagram shows four grayscale regions. The first grayscale region A1 (low grayscale region) includes grayscale levels 0 to 62, the second grayscale region A2 includes grayscale levels 63 to 126, the third grayscale region A3 includes grayscale levels 127 to 190, and the fourth grayscale region A4 includes grayscale levels 191 to 255.

[0222] However, grayscale areas are not limited to Figure 6 The grayscale region is shown in the diagram. In various other embodiments, the grayscale region may be defined to be provided in a smaller or larger amount than shown. Each grayscale region may be configured to include the same or different number of grayscale values.

[0223] In this embodiment, the calculation unit 35 can determine which grayscale region the grayscale value of the image data DATA output from the first latch unit 321 is included in. The calculation unit 35 can select data lines DL1, DL2, DL3, DL4, DL5, and DL6 of the image data DATA to be applied to the same grayscale region to operate in charge-sharing mode.

[0224] For example, the computing unit 35 can control the charge-sharing switching elements SW11 to SW61 to apply the charge-sharing switch. Figure 6The image data lines DL1, DL2, DL3, DL4, DL5, and DL6 of the first grayscale region A1 are connected to the first charge-sharing line CSL1. Additionally, the calculation unit 35 can control charge-sharing switching elements SW12 to SW62 to connect the image data lines DL1, DL2, DL3, DL4, DL5, and DL6 of the image data to be applied to the second grayscale region A2 to the second charge-sharing line CSL2. Furthermore, the calculation unit 35 can control charge-sharing switching elements SW13 to SW63 to connect the image data lines DL1, DL2, DL3, DL4, DL5, and DL6 of the image data to be applied to the third grayscale region A3 to the third charge-sharing line CSL3. Furthermore, the calculation unit 35 can control charge-sharing switching elements SW14 to SW64 to connect the image data lines DL1, DL2, DL3, DL4, DL5, and DL6 of the image data to be applied to the fourth grayscale region A4 to the fourth charge-sharing line CSL4. However, the embodiment is not limited to this.

[0225] In one embodiment, the calculation unit 35 can determine which grayscale region the grayscale values ​​of the continuously output image data DATA from the first latch unit 321 are included in, and determine whether to perform charge sharing for the next image data DATA based on the grayscale region of the previous image data DATA. Alternatively, the calculation unit 35 can determine whether to perform charge sharing based on the changes in the grayscale regions of the continuously output image data DATA.

[0226] Those skilled in the art will recognize that this disclosure may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The described embodiments are to be considered in all respects as illustrative rather than restrictive. Therefore, the scope of this disclosure is indicated by the appended claims rather than the foregoing description. All modifications within the meaning and scope of equivalents of the claims are included within the scope of this disclosure.

Claims

1. A data driver, comprising: A register unit configured to sample and output sequentially input image data in each horizontal time interval; A latch unit is configured to latch the image data output from the register unit and output the image data synchronously with a latch output control signal; A digital-to-analog converter configured to convert the image data output from the latch unit into a gamma-compensated voltage to generate a data voltage; Multiple output buffers, configured to sequentially output the data voltage generated by the digital-to-analog converter to data lines; A buffer switching element, which connects the output buffer to the data lines respectively in response to a source output enable signal; A charge-sharing circuit, the charge-sharing circuit being configured to control the connection between at least one charge-sharing line and the data line; as well as A computing unit configured to generate a control signal based on the grayscale value of the image data output by the latching unit, the control signal being configured to control the charge-sharing circuit.

2. The data driver according to claim 1, in, The charge-sharing circuit includes: The at least one charge-sharing line; and At least one charge-sharing switching element is connected between the at least one charge-sharing line and the data line. Each of the charge-sharing switching elements connects the corresponding data line to the corresponding charge-sharing line in response to the control signal at the on level.

3. The data driver according to claim 2, in, Each of the charge-sharing switch elements is connected between the corresponding data line and the corresponding charge-sharing line and is configured as a transistor, the gate electrode of the transistor being connected to the computing unit and configured to receive the control signal.

4. The data driver according to claim 2, in, The computing unit selects at least one data line to operate in charge-sharing mode based on the grayscale value of the image data, and outputs the control signal at the on level to the charge-sharing switching element connected to the selected data line.

5. The data driver according to claim 4, in, The computing unit defines multiple grayscale regions, selects image data whose grayscale values ​​are included in the same grayscale region, and controls the charge-sharing switch element to connect the data line of the selected image data to the same charge-sharing line.

6. The data driver according to claim 5, in, The computing unit selects image data whose grayscale values ​​include those in high grayscale and low grayscale regions, and controls the charge-sharing switch element to connect the data line to which the selected image data is to be applied to the same charge-sharing line.

7. The data driver according to claim 5, in, When the gray values ​​of the previous image data and the next image data are contained in different gray-scale regions in the sequentially input image data, the computing unit selects the data line to be applied to the next image data and operates in the charge-sharing mode.

8. The data driver according to claim 5, in, When the grayscale value of the previous image data is included in a high grayscale region and the grayscale value of the next image data is included in a low grayscale region in the sequentially input image data, the computing unit selects the data line to be applied to the next image data to operate in the charge-sharing mode.

9. The data driver according to claim 5, in, When the grayscale value of the previous image data is included in a low grayscale region and the grayscale value of the next image data is included in a high grayscale region in the sequentially input image data, the computing unit selects the data line to be applied to the next image data to operate in the charge-sharing mode.

10. The data driver according to claim 5, in, During the (n-1)th horizontal time period, a data voltage corresponding to the (n-1)th image data is applied to the data line, where n is a natural number equal to or greater than 2. During the charge-sharing period, voltage is redistributed among data lines connected to the same charge-sharing line. Specifically, during the nth horizontal time period, a data voltage corresponding to the difference between the voltage corresponding to the nth image data and the redistributed voltage is applied to the data line.

11. The data driver according to claim 10, in, During the charge-sharing period, data lines connected to the same charge-sharing line are charged to the average voltage of the data lines connected to the same charge-sharing line during the (n-1)th level period.

12. The data driver according to claim 10, in, During the (n-1)th level time period, an enable signal is applied to the source output at the on level. During the charge sharing period, an enable signal is applied to the source output at the off level. Specifically, during the nth level time period, an enable signal for the source output, which is at the on level, is applied.

13. The data driver according to claim 5, in, At least one charge-sharing line is provided corresponding to the number of the plurality of grayscale regions.

14. A display device, comprising: A display panel having arranged pixels; A data driver configured to apply a data voltage to the pixel via a data line; A gate driver configured to apply a scan signal to the pixel via a scan line; as well as A timing controller configured to apply image data and data drive control signals to the data driver. The data driver includes: A register unit configured to sample and output the image data; A latch unit is configured to latch the image data output from the register unit and output the image data synchronously with a latch output control signal; A digital-to-analog converter configured to convert the image data output from the latch unit into a gamma-compensated voltage to generate a data voltage; Multiple output buffers, the multiple output buffers being configured to sequentially output the data voltage generated by the digital-to-analog converter to the data line; A buffer switching element, which connects the output buffer to the data lines respectively in response to a source output enable signal; A charge-sharing circuit, the charge-sharing circuit having a charge-sharing switching element configured to control the connection between at least one charge-sharing line and the data line; and A computing unit configured to generate a control signal based on the grayscale value of the image data output by the latching unit, the control signal being configured to control the charge-sharing switching element.

15. The display device according to claim 14, in, The computing unit defines multiple grayscale regions, selects image data whose grayscale values ​​are included in the same grayscale region, and controls the charge-sharing switch element to connect the data line of the selected image data to the same charge-sharing line.

16. The display device according to claim 15, in, The computing unit selects image data whose grayscale values ​​include those in high grayscale and low grayscale regions, and controls the charge-sharing switch element to connect the data line to which the selected image data is to be applied to the same charge-sharing line.

17. The display device according to claim 15, in, When the grayscale values ​​of the previous image data and the next image data are contained in different grayscale regions in the sequentially input image data, the computing unit controls the charge-sharing switch element to connect the data line to which the next image data is to be applied to one of the charge-sharing lines.

18. The display device according to claim 15, in, When, in sequentially input image data, the grayscale value of the previous image data is located in a high grayscale region and the grayscale value of the next image data is located in a low grayscale region, the computing unit controls the charge-sharing switching element to connect the data line to which the next image data is to be applied to one of the charge-sharing lines. Specifically, when the grayscale value of the previous image data is included in a low grayscale region and the grayscale value of the next image data is included in a high grayscale region in the sequentially input image data, the computing unit controls the charge-sharing switch element to connect the data line to which the next image data is to be applied to one of the charge-sharing lines.

Images