Layout structure of gallium nitride switching circuit in multi-layer PCB (Printed Circuit Board)

Abstract

The invention provides a layout structure of a gallium nitride switch circuit in a multi-layer PCB (Printed Circuit Board), which comprises a first gallium nitride device and a first switch controller which are arranged on the surface layer of the multi-layer PCB, and the output end of the first switch controller is connected with a grid pin of the first gallium nitride device through a grid connecting copper sheet on the surface layer; the input capacitor is arranged on the multi-layer PCB and is close to the first gallium nitride device; a drain electrode pin of the first gallium nitride device is connected through a drain electrode connecting copper sheet on the surface layer, a source electrode pin of the first gallium nitride device is connected through a source electrode connecting copper sheet on the surface layer, and the source electrode connecting copper sheet and the drain electrode connecting copper sheet are provided with a plurality of via holes connected to the inner layer of the multi-layer PCB; the first inner layer is arranged adjacent to the surface layer, the first inner layer comprises a layer of copper sheet, and the copper sheet is electrically connected with a source electrode pin of the first gallium nitride device through a via hole. According to the invention, the areas of a gallium nitride gate drive loop and a high-frequency high-power loop are reduced, and mutual interference is reduced.

Description

Technical Field

[0001] This invention relates to the field of gallium nitride switching circuit technology, and more specifically, to a layout structure of gallium nitride switching circuits in a multilayer PCB board. Background Technology

[0002] Gallium nitride (GaN) is widely used in various switching circuits due to its significantly lower on-resistance and parasitic capacitance compared to traditional silicon MOS. However, GaN MOS typically operates at extremely high switching speeds (nanosecond levels), making its circuits susceptible to parasitic parameters (inductance and capacitance). For example, parasitic inductance exists on the common path from the source to the drive ground and power ground of GaN devices. This inductance reduces switching speed, increases switching losses, and exacerbates ringing and overshoot at the switching node. Therefore, optimizing these parasitic parameters and improving EMC performance has become a significant challenge.

[0003] Patent application CN109994456A discloses a gallium nitride (GaN) device and a GaN packaging structure. The GaN device includes: a silicon chip mounted face-mounted on the top surface of a double-sided PCB substrate; a GaN chip flip-mounted on the top surface of the double-sided PCB substrate; and at least one pad electrode of the GaN device formed on the top surface of the double-sided PCB substrate via a cascaded cascade method. Each of the pad electrodes extends to the bottom surface of the double-sided PCB substrate via a via, and on the top surface of the double-sided PCB substrate, the projection area of ​​the via is completely covered or overlaps with the projection area of ​​the pad electrode. However, this patent cannot completely solve the existing technical problems, nor can it meet the needs of this invention. Summary of the Invention

[0004] In view of the deficiencies in the prior art, the purpose of this invention is to provide a layout structure for gallium nitride switching circuits in multilayer PCB boards.

[0005] The layout structure of the gallium nitride switching circuit in the multilayer PCB board provided by the present invention includes: a first gallium nitride device, a first switching controller, and an input capacitor; The first gallium nitride device and the first switch controller are arranged on the surface layer of a multilayer PCB board, and the output terminal of the first switch controller is connected to the gate pin of the first gallium nitride device through the gate connection copper foil on the surface layer. The input capacitor is arranged on the multilayer PCB board and close to the first gallium nitride device; The drain pin of the first gallium nitride device is connected through a drain connection copper layer on the surface, and the source pin of the first gallium nitride device is connected through a source connection copper layer on the surface. Multiple vias connecting to the inner layer of the multilayer PCB board are provided on the source connection copper layer and the drain connection copper layer. The multilayer PCB board also includes a first inner layer disposed adjacent to the surface layer. The first inner layer includes a copper foil that is electrically connected to the source pin of the first gallium nitride device through the via.

[0006] Preferably, the first switch controller is arranged on the PCB surface in close proximity to the first gallium nitride device.

[0007] Preferably, the vias at the source pin and the drain pin of the first gallium nitride device are arranged adjacent to each other at their projected positions on the surface of the multilayer PCB board.

[0008] Preferably, the input capacitor is arranged on the bottom layer of the multilayer PCB board; the positive terminal of the input capacitor is connected to the drain connection copper of the first gallium nitride device through an inner layer trace or via, and the negative terminal of the input capacitor is connected to the source connection copper of the first inner layer through an inner layer trace or via.

[0009] Preferably, it further includes a second gallium nitride device and a second switch controller, the second gallium nitride device and the second switch controller being disposed on the surface layer of the multilayer PCB board; In this configuration, the source copper layer of the first gallium nitride device and the drain copper layer of the second gallium nitride device are directly connected on the surface layer.

[0010] Preferably, the first switch controller is arranged close to the first gallium nitride device, the second switch controller is arranged close to the second gallium nitride device, and the first gallium nitride device and the second gallium nitride device are arranged adjacent to each other.

[0011] Preferably, the multilayer PCB board has a four-layer structure, which consists of, from top to bottom: surface layer, first inner layer, second inner layer and bottom layer; The gate connection copper foil of the first gallium nitride device and the second gallium nitride device is arranged on the surface layer; The first inner layer is provided with a first source plane copper foil that is electrically connected to the source electrode of the first gallium nitride device; The second inner layer is provided with the drain plane copper of the first gallium nitride device and the drain plane copper of the second gallium nitride device. The drain plane copper of the first gallium nitride device is connected to the positive terminal of the input capacitor, and the drain plane copper of the second gallium nitride device is connected to the source terminal of the first gallium nitride device.

[0012] Preferably, the projection area of ​​the first source plane copper foil of the first inner layer, in the direction perpendicular to the surface of the multilayer PCB board, does not overlap with the projection of the high-power copper foil area where the drain of the first gallium nitride device is located in the surface layer.

[0013] Preferably, the first inner layer is spaced between the second inner layer and the outer layer, such that the gate connection copper of the first gallium nitride device and the second gallium nitride device are separated from their respective drain plane copper by a vertical distance.

[0014] Preferably, the input capacitor is arranged on the bottom layer, and on the projection surface of the bottom layer, the position of the input capacitor is adjacent to the projection position of the first gallium nitride device on the bottom layer.

[0015] Compared with the prior art, the present invention has the following beneficial effects: (1) By closely aligning the switch controller with the gallium nitride device and optimizing the gate trace (short and wide), the physical area of ​​the gate drive circuit is effectively reduced, thereby significantly reducing the parasitic inductance of the circuit. (2) By placing the input capacitor close to the gallium nitride device and using the adjacent inner layers separated by an extremely thin dielectric layer as the main return path, the area of ​​the high-frequency high-power loop is greatly reduced, and the parasitic inductance of the loop is reduced. (3) By closely arranging the vias at the source and drain pins of the gallium nitride device, the current flowing through them is in opposite directions, and the magnetic fields generated can cancel each other out, further reducing the equivalent parasitic inductance of the power loop. (4) By designing the gate drive circuit and the high-frequency high-power loop to be perpendicular to each other in space, and by implementing projection isolation in the inner layer layout (such as the first source plane copper skin and the surface high-power copper skin not overlapping), the magnetic field coupling and interference between the two loops are effectively reduced. (5) By using the stacked design of multilayer PCB, the gate signal layer (surface layer) and the drain maximum current layer (such as the second inner layer) are separated in vertical distance, which increases the spacing between the two and helps to reduce the parasitic capacitance between the gate and the drain. (6) For the layout of dual gallium nitride devices, the power path is optimized by arranging the two devices adjacent to each other and sharing the connection, and by placing the input capacitor at the corresponding projection position of the bottom layer, so as to minimize the overall high-power loop area. Attached Figure Description

[0016] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 The switch controller is a gallium nitride switch control circuit; Figures 2a-2d The stack-up distribution for gallium nitride (GaN) packages; Figure 3a and Figure 3b This is a schematic diagram of the layout of a gallium nitride PCB with double-sided surface mount technology. Figure 4a For the PCB surface layer in a gallium nitride double-sided surface mount solution, Figure 4b This is the first inner layer of the PCB in a gallium nitride double-sided surface mount solution. Figure 4c This is the second inner layer of the PCB in a gallium nitride double-sided surface mount solution. Figure 4d This is the bottom layer of the PCB in a gallium nitride double-sided surface mount solution; Figure 5a This is a type of gallium nitride switching circuit PCB available on the market. Figure 5b The test results in the 30~76MHz frequency band were obtained without using the solution of this invention. Figure 5c The test results are for the 30~76MHz frequency band using the scheme of this invention. Detailed Implementation

[0017] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0018] Example The present invention provides a layout structure for a gallium nitride switching circuit in a multilayer PCB board, comprising: a first gallium nitride device, a first switching controller, and an input capacitor; The first gallium nitride device and the first switch controller are arranged on the surface layer of a multilayer PCB board, and the output terminal of the first switch controller is connected to the gate pin of the first gallium nitride device through the gate connection copper foil on the surface layer. The input capacitor is arranged on the multilayer PCB board and close to the first gallium nitride device; The drain pin of the first gallium nitride device is connected through a drain connection copper layer on the surface, and the source pin of the first gallium nitride device is connected through a source connection copper layer on the surface. Multiple vias connecting to the inner layer of the multilayer PCB board are provided on the source connection copper layer and the drain connection copper layer. The multilayer PCB board also includes a first inner layer disposed adjacent to the surface layer. The first inner layer includes a copper foil that is electrically connected to the source pin of the first gallium nitride device through the via.

[0019] The first switch controller is arranged on the surface of the PCB, close to the first gallium nitride device.

[0020] The vias at the source pin and the drain pin of the first gallium nitride device are arranged adjacent to each other at their projected positions on the surface of the multilayer PCB board.

[0021] The input capacitor is arranged on the bottom layer of the multilayer PCB board; the positive terminal of the input capacitor is connected to the drain copper of the first gallium nitride device through an inner layer trace or via, and the negative terminal of the input capacitor is connected to the source copper of the first inner layer through an inner layer trace or via.

[0022] It also includes a second gallium nitride device and a second switch controller, the second gallium nitride device and the second switch controller being disposed on the surface layer of the multilayer PCB board; In this configuration, the source copper layer of the first gallium nitride device and the drain copper layer of the second gallium nitride device are directly connected on the surface layer.

[0023] The first switch controller is arranged close to the first gallium nitride device, the second switch controller is arranged close to the second gallium nitride device, and the first gallium nitride device and the second gallium nitride device are arranged adjacent to each other.

[0024] The multilayer PCB board has a four-layer structure, which consists of the following layers from top to bottom: surface layer, first inner layer, second inner layer and bottom layer. The gate connection copper foil of the first gallium nitride device and the second gallium nitride device is arranged on the surface layer; The first inner layer is provided with a first source plane copper foil that is electrically connected to the source electrode of the first gallium nitride device; The second inner layer is provided with the drain plane copper of the first gallium nitride device and the drain plane copper of the second gallium nitride device. The drain plane copper of the first gallium nitride device is connected to the positive terminal of the input capacitor, and the drain plane copper of the second gallium nitride device is connected to the source terminal of the first gallium nitride device.

[0025] The projection area of ​​the first source plane copper foil of the first inner layer, in the direction perpendicular to the surface of the multilayer PCB board, does not overlap with the projection of the high-power copper foil area where the drain of the first gallium nitride device is located in the surface layer.

[0026] The first inner layer is spaced between the second inner layer and the outer layer, such that the gate connection copper of the first gallium nitride device and the second gallium nitride device are separated from their respective drain plane copper by a vertical distance.

[0027] The input capacitor is arranged on the bottom layer, and on the projection surface of the bottom layer, the position of the input capacitor is adjacent to the projection position of the first gallium nitride device on the bottom layer.

[0028] like Figure 1The diagram shows a switching control circuit with a gallium nitride (GaN) gate drive circuit. The first loop is the GaN gate drive circuit, and the third loop is the high-frequency, high-power loop. The switch controller is placed close to the GaN to minimize the area of ​​the GaN gate drive circuit. The input capacitor is also placed close to the GaN, with its return path being the next copper layer. The distance between this next copper layer and the PCB surface is extremely thin in the stack-up design to further minimize the area of ​​the high-frequency, high-power loop and improve EMI performance. Furthermore, the GaN gate drive circuit is perpendicular to the high-frequency, high-power loop. This perpendicular design of the GaN gate drive circuit and the high-frequency, high-power loop reduces mutual interference.

[0029] Figures 2a-2d This is an example of the stacking distribution of a gallium nitride package; other packaging principles are similar, and the present invention includes, but is not limited to, this gallium nitride package.

[0030] like Figure 2a As shown, this is the surface layer of the PCB. Device A is gallium nitride (GaN), 1 is the drain pin of the GaN device, 2 is the gate pin of the GaN device, and 3 is the source pin of the GaN device. Figure 2b In the diagram, 1_c is the gallium nitride (GaN) drain connection copper layer. 1_v1 and 1_v2 are vias located near the GaN drain pin. The other vias on the 1_c copper layer are similar and will not be described in detail. These vias can connect to other layers to further improve current carrying capacity. 2_c is the GaN gate connection copper layer, designed as a wider copper layer to connect to the switch controller to reduce parasitic inductance of the gate trace. 3_c1 is the source pin connection copper layer, with multiple vias designed to connect to inner layers, reducing the parasitic inductance of the vias. 3_v1 and 3_v2 are vias located near the GaN gate pin. The other vias on the 3_c copper layer are similar and will not be described in detail. These vias can connect to other layers to further improve current carrying capacity. Figure 2c As shown, this illustrates the direction of high current on gallium nitride (GaN). By placing vias close to the source and drain of the GaN, the current directions on the source and drain are opposite, ultimately canceling out the magnetic fields and effectively reducing the parasitic inductance of the power loop. Simultaneously, vias such as 3_v1 at the source pin and 1_v1 at the drain pin are designed to be very close together to achieve opposite current directions and magnetic field cancellation. Figure 2d As the first inner layer of the PCB, it is designed to be close to the surface layer to reduce the gallium nitride gate drive circuit and high-current power circuit. In the example with the source connected to ground, the first inner layer of the PCB is arranged as copper 3_c2, which is electrically a gallium nitride source. The gallium nitride gate return current and high-power return current are all in this layer, so it is designed as a plane to greatly reduce the common source inductance.

[0031] Figure 3a and Figure 3bThis is another layout method for double-sided surface mount technology (SMT) of gallium nitride (GaN) PCBs.

[0032] like Figure 3a As shown, the first switch controller is the switch control circuit for the first gallium nitride (GaN), the second switch controller is the switch control circuit for the second GaN, the first loop is the gate drive circuit for the first GaN, and the second loop is the gate drive circuit for the second GaN. The first and second switch controllers, as well as the first and second GaN, are placed on the surface of the PCB. Similarly, the first switch controller is designed to be close to the first GaN, and the second switch controller is designed to be close to the second GaN. The first GaN is designed to be close to the second GaN, minimizing the size of the gate drive circuits for both GaN and second GaN. Figure 3b As shown, the input capacitor is placed on the bottom layer of the PCB, close to the location where the first gallium nitride (GaN) capacitor is projected onto the bottom layer of the PCB. The high-current power loop runs from the positive terminal of the bottom input capacitor through the first GaN and the second GaN, returning to the negative terminal of the input capacitor. The first and second GaN drive circuits are perpendicular to the high-current power loop, minimizing their mutual interference. Under this layout, a thinner PCB is preferred to further reduce the area of ​​the high-power current loop.

[0033] Figure 4a In the gallium nitride (GaN) double-sided surface mount solution shown in Figure 3, 11 represents the first GaN layer, and 12 represents the second GaN layer. 11s_c is the source copper layer of the first GaN layer, which is also connected to the drain of the second GaN layer. 11g_c is the gate copper layer of the first GaN layer, designed to be short and wide to connect to the first switch controller to reduce parasitic inductance of the traces. 12g_c is the gate copper layer of the second GaN layer, designed to be short and wide to connect to the second switch controller to reduce parasitic inductance of the traces. 12s_c is the source copper layer of the second GaN layer, connected to the inner layer via vias. Multiple vias are designed on the source copper layers of both the first and second GaN layers to connect to the inner layer, reducing the parasitic inductance of the vias.

[0034] Figure 4bFigure 3 shows the first inner layer of the PCB in the gallium nitride (GaN) double-sided surface mount solution, which is immediately adjacent to the surface layer. 11 represents the first GaN, 12 the second GaN, 13 the first switch controller, and 14 the second switch controller. 11s_c, the first GaN source copper layer, is the first GaN gate drive return path and is designed to be close to the surface layer 11g_c GaN gate copper layer, resulting in a smaller gate drive loop and reduced parasitic inductance. Simultaneously, 11s_c has no overlap with the surface high-power copper layer. This physically isolates the noisy high-frequency, high-current power loop from the small-signal gate drive loop, preventing the gate loop from being affected by switching noise. 12s_c is the second GaN source copper layer. The second GaN gate drive loop and the high-frequency, high-current power loop share a common path here; therefore, 12s_c is designed with a large copper area to reduce parasitic inductance of the common path.

[0035] Figure 4c In the gallium nitride (GaN) double-sided surface mount solution shown in Figure 3, the second inner layer of the PCB is adjacent to the first inner layer. 11d_c is the first GaN drain copper layer, which is also connected to the input capacitor. 12d_c is the second GaN drain copper layer, which is also connected to the first GaN source. 11d_c and 12d_c are designed on the second inner layer of the PCB to increase current carrying capacity. Meanwhile, the first and second GaN gate copper layers are located on the PCB surface, while the drain copper layer is placed on the second inner layer. This maximizes the distance between the gate and drain, reducing parasitic capacitance and helping to improve switching speed and EMI performance.

[0036] Figure 4d This is the bottom layer of the PCB in the gallium nitride (GaN) double-sided surface mount solution shown in Figure 3, directly attached to the second inner layer. 13 is the input capacitor, 11d_c is the GaN drain copper layer, also connected to the input capacitor. 12s_c is the GaN source copper layer, connected to the negative terminal of the input capacitor. Position 13 is designed as the location where the first GaN projection is on the bottom layer of the PCB to reduce high-power loops.

[0037] Figure 5a This is a commercially available gallium nitride (GaN) switch circuit PCB. There is overlap between the main power circuit 3 and the GaN gate drive circuit 1. The GaN switch controller is also placed far away. Ignoring interlayer distances and parasitic parameters, RE testing revealed exceedances in the 30MHz~76MHz frequency band. The test results are as follows... Figure 5b The PCB was modified according to the method of this invention. After optimizing the component placement, layer stack-up design, and copper traces, a subsequent RE test revealed a decrease in noise radiation of approximately 15 dB. This met the requirements in the 30MHz~76MHz frequency band and provided sufficient margin. The test results are as follows: Figure 5c .

[0038] In the description of this application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0039] Those skilled in the art will understand that, in addition to implementing the system, apparatus, and their modules provided by this invention in purely computer-readable program code, the same program can be implemented in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system, apparatus, and their modules provided by this invention can be considered a hardware component, and the modules included therein for implementing various programs can also be considered structures within the hardware component; alternatively, modules for implementing various functions can be considered both software programs implementing the method and structures within the hardware component.

[0040] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A layout structure for a gallium nitride switching circuit in a multilayer PCB board, characterized in that, include: A first gallium nitride device, a first switch controller, and an input capacitor; The first gallium nitride device and the first switch controller are arranged on the surface layer of a multilayer PCB board, and the output terminal of the first switch controller is connected to the gate pin of the first gallium nitride device through the gate connection copper foil on the surface layer. The input capacitor is arranged on the multilayer PCB board and close to the first gallium nitride device; The drain pin of the first gallium nitride device is connected through a drain connection copper layer on the surface, and the source pin of the first gallium nitride device is connected through a source connection copper layer on the surface. Multiple vias connecting to the inner layer of the multilayer PCB board are provided on the source connection copper layer and the drain connection copper layer. The multilayer PCB board also includes a first inner layer disposed adjacent to the surface layer. The first inner layer includes a copper foil that is electrically connected to the source pin of the first gallium nitride device through the via.

2. The layout structure of the gallium nitride switching circuit in the multilayer PCB board according to claim 1, characterized in that, The first switch controller is arranged on the surface of the PCB, close to the first gallium nitride device.

3. The layout structure of the gallium nitride switching circuit in the multilayer PCB board according to claim 1, characterized in that, The vias at the source pin and the drain pin of the first gallium nitride device are arranged adjacent to each other at their projected positions on the surface of the multilayer PCB board.

4. The layout structure of the gallium nitride switching circuit in the multilayer PCB board according to claim 1, characterized in that, The input capacitor is arranged on the bottom layer of the multilayer PCB board; the positive terminal of the input capacitor is connected to the drain copper of the first gallium nitride device through an inner layer trace or via, and the negative terminal of the input capacitor is connected to the source copper of the first inner layer through an inner layer trace or via.

5. The layout structure of the gallium nitride switching circuit in the multilayer PCB board according to claim 1, characterized in that, It also includes a second gallium nitride device and a second switch controller, the second gallium nitride device and the second switch controller being disposed on the surface layer of the multilayer PCB board; In this configuration, the source copper layer of the first gallium nitride device and the drain copper layer of the second gallium nitride device are directly connected on the surface layer.

6. The layout structure of the gallium nitride switching circuit in the multilayer PCB board according to claim 5, characterized in that, The first switch controller is arranged close to the first gallium nitride device, the second switch controller is arranged close to the second gallium nitride device, and the first gallium nitride device and the second gallium nitride device are arranged adjacent to each other.

7. The layout structure of the gallium nitride switching circuit in the multilayer PCB board according to claim 6, characterized in that, The multilayer PCB board has a four-layer structure, which consists of the following layers from top to bottom: surface layer, first inner layer, second inner layer and bottom layer. The gate connection copper foil of the first gallium nitride device and the second gallium nitride device is arranged on the surface layer; The first inner layer is provided with a first source plane copper foil that is electrically connected to the source electrode of the first gallium nitride device; The second inner layer is provided with the drain plane copper of the first gallium nitride device and the drain plane copper of the second gallium nitride device. The drain plane copper of the first gallium nitride device is connected to the positive terminal of the input capacitor, and the drain plane copper of the second gallium nitride device is connected to the source terminal of the first gallium nitride device.

8. The layout structure of the gallium nitride switching circuit in the multilayer PCB board according to claim 7, characterized in that, The projection area of ​​the first source plane copper foil of the first inner layer, in the direction perpendicular to the surface of the multilayer PCB board, does not overlap with the projection of the high-power copper foil area where the drain of the first gallium nitride device is located in the surface layer.

9. The layout structure of the gallium nitride switching circuit in the multilayer PCB board according to claim 7, characterized in that, The first inner layer is spaced between the second inner layer and the outer layer, such that the gate connection copper of the first gallium nitride device and the second gallium nitride device are separated from their respective drain plane copper by a vertical distance.

10. The layout structure of the gallium nitride switching circuit in the multilayer PCB board according to claim 7, characterized in that, The input capacitor is arranged on the bottom layer, and on the projection surface of the bottom layer, the position of the input capacitor is adjacent to the projection position of the first gallium nitride device on the bottom layer.

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