Three-level embedded module

Abstract

The invention provides a three-level embedded module, and relates to the technical field of power electronics, the three-level embedded module comprises a circuit board, the front surface of the circuit board is provided with signal pins and power terminals; and the plurality of chip units are embedded and integrated in the circuit board and are connected with the signal pins and the power terminal wires to form a three-level topological structure. The beneficial effects of the invention are that copper cladding in the PCB is adopted to replace tedious wiring and dispersed layout in a traditional scheme, the wiring path is shortened and optimized, stray and loop inductance are greatly reduced, and the circuit control precision and the whole machine efficiency are improved; the chip is embedded in the PCB, traditional shell packaging is omitted, the size of the whole machine is remarkably reduced, the PCB substrate has an insulation function, an insulation structure does not need to be additionally arranged, heat dissipation and safety regulation troubles are avoided, and the junction temperature of the chip is improved; the integrated design avoids uneven current caused by layout difference of discrete devices, the assembly process is simplified, compared with a traditional plastic shell module, the manufacturing cost is reduced, and reliability and economical efficiency are both considered.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a three-level embedded module. Background Technology

[0002] The application of photovoltaic-storage inverters places strict requirements on module efficiency, size, and reliability. Currently, there are two main solutions for photovoltaic-storage inverters: Solution 1 uses a module design with a plastic casing. The circuitry is integrated into the same module, which uses a high-temperature resistant plastic casing as a protective shell. Its advantages are high integration and ease of use; however, it also has significant disadvantages. Most inverters have different layout designs, resulting in complex internal wiring, which can lead to large stray inductance. The casing material also limits the chip junction temperature, and the price is relatively high. Solution 2 uses discrete components in series and parallel. Its advantages are convenient layout design and lower cost; however, its disadvantages include uneven current distribution among components in the same circuit due to layout differences when used in parallel. Furthermore, the dispersed and unconcentrated chips can lead to excessively large loop inductance, making voltage control more difficult and resulting in lower efficiency. Additionally, discrete components lack insulation, requiring inverter manufacturers to add insulation themselves, which significantly impacts heat dissipation and safety compliance. Summary of the Invention

[0003] To address the problems existing in the prior art, the present invention provides a three-level embedded module, comprising:

[0004] A circuit board, the front side of which is provided with signal pins and power terminals;

[0005] Multiple chip units are embedded and integrated inside the circuit board, and are connected to the signal pins and power terminals to form a three-level topology.

[0006] Preferably, the circuit board includes:

[0007] Signal trace layers, power trace layers, and chip layers are isolated from each other by insulating layers;

[0008] Each of the chip units is integrated in the chip layer, and the signal electrode of each chip unit is connected to the corresponding signal pin through the signal trace layer. The power electrode of each chip unit is connected to the corresponding power terminal through the power trace layer.

[0009] Preferably, the chip unit includes:

[0010] A metal base on which a power chip is soldered, the power chip including a MOS chip, or a combination of an IGBT chip and a diode chip.

[0011] Preferably, when the power chip is a MOS chip, the gate of the MOS chip is connected to the signal pin as a signal electrode, and the source and drain of the MOS chip are connected to the power terminal as power electrodes.

[0012] When the power chip is a combination of an IGBT chip and a diode chip, the gate of the IGBT chip is connected to the signal pin as the signal electrode, and the emitter and collector of the IGBT chip are connected to the power terminal as the power electrodes.

[0013] Preferably, the circuit board further includes a heat dissipation layer disposed at the bottom of the circuit board.

[0014] Preferably, the three-level topology is a T-type three-level topology, then the power terminals corresponding to every 4 chip units integrated in the circuit board are 3.

[0015] Preferably, a heat dissipation substrate is connected to the back of the circuit board.

[0016] Preferably, the metal base includes features that increase heat capacity.

[0017] Preferably, the number of signal pins is twice the number of chip units.

[0018] Preferably, nickel is plated at the solder joints of the signal pins and the power terminals to the circuit board.

[0019] The above technical solution has the following advantages or beneficial effects:

[0020] 1. The use of internal copper-clad connections on the PCB board replaces the cumbersome routing and scattered layout of discrete components in traditional plastic housing modules. The routing path is shorter and more optimized, which greatly reduces internal stray inductance and loop inductance, and improves circuit control accuracy and overall efficiency.

[0021] 2. The chip unit is directly embedded inside the circuit board, eliminating the bulky packaging volume of traditional plastic shells, significantly reducing the overall size of the device. At the same time, the PCB substrate also has insulation protection functions, eliminating the need for additional insulation structures, avoiding the heat dissipation and safety design problems in discrete device solutions, and improving the chip junction temperature characteristics.

[0022] 3. The integrated design avoids the problem of uneven current caused by layout differences in discrete components, simplifies the assembly process, reduces manufacturing costs compared to traditional plastic housing modules, and balances reliability and economy. Attached Figure Description

[0023] Figure 1 A schematic diagram of a three-level embedded module is shown in a preferred embodiment of the present invention.

[0024] Figure 2 This is a schematic diagram of the circuit board structure in a preferred embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram of the structure of a chip unit in a preferred embodiment of the present invention;

[0026] Figure 4 This is a schematic diagram of a T-type three-level topology in a preferred embodiment of the present invention. Detailed Implementation

[0027] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. The present invention is not limited to this embodiment; other embodiments that conform to the spirit of the present invention may also fall within the scope of the present invention.

[0028] In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, a three-level embedded module is provided, such as... Figure 1-3 As shown, it includes:

[0029] Circuit board 2, the front side of circuit board 2 is provided with signal pins 3 and power terminals 1;

[0030] Multiple chip units U are integrated inside the circuit board 2 and connected to the signal pins 3 and power terminals 1 to form a three-level topology.

[0031] Specifically, this embodiment provides a three-level embedded module, mainly used in photovoltaic-storage inverters. The module includes a circuit board 2 and multiple chip units U integrated within the circuit board 2. The front side of the circuit board 2 has signal pins 3 and power terminals 1. The internal chip units U are connected to these pins and terminals via traces, forming a three-level topology. This embodiment changes the traditional approach of encapsulating chips in plastic shells or using discrete components in series and parallel; instead, it employs PCB embedded technology to directly embed the chip units inside the circuit board.

[0032] Compared to the cumbersome and complex wiring inside traditional plastic housing modules, this embodiment utilizes copper-clad connections inside the circuit board to form the circuit, resulting in shorter and more optimized wiring paths, effectively reducing internal stray inductance.

[0033] Furthermore, by embedding the chip inside the circuit board, the bulky plastic casing is eliminated, which effectively reduces the overall size of the device compared to the plastic casing solution.

[0034] Moreover, compared to discrete device solutions, integrated design avoids the problem of uneven current caused by differences in layout design.

[0035] In a preferred embodiment of the present invention, the circuit board 2 includes:

[0036] The signal trace layer G, power trace layers E and C, and chip layer A are isolated from each other by insulating layer B;

[0037] Each chip unit U is integrated in chip layer A. The signal electrode of each chip unit U is connected to the corresponding signal pin through the signal trace layer, and the power electrode of the chip unit U is connected to the corresponding power terminal through the power trace layer.

[0038] Specifically, this embodiment further defines the internal hierarchical structure of the circuit board. For example... Figure 2 As shown, the circuit board is manufactured using a multilayer printed circuit board (PCB) process. The layers stacked from top to bottom along the Z-axis (vertical direction) are: signal trace layer (G layer), first power trace layer (E layer), device bonding layer (A layer), and second power trace layer (C layer). That is, the G layer is above the E layer, the E layer is above the A layer, and the C layer is below the A layer. Each layer is electrically isolated from the others by insulating dielectric layers (such as B1-B5 layers).

[0039] To enable communication between the internal power layer and the external interface, the E and C layers are electrically connected to the power terminals on the circuit board surface via vias that penetrate the G layer. Specifically, clearance holes or insulating holes are made at corresponding positions on the G layer, allowing the conductive vias connecting the E and C layers to pass through the plane containing the G layer without short-circuiting with the signal network of the G layer, thereby bringing the deep power loop out to the power terminals on the circuit board surface.

[0040] This embodiment employs a dedicated hierarchical design. Layer B (insulation layer) provides high- and low-voltage potential isolation; layer G (signal layer) is dedicated to transmitting gate control signals; and layers E and C (power layers) are responsible for power current transmission, clearly distinguishing between signal and power paths. The signal and power layers are arranged in layers, with an insulation gap maintained between layer G (top layer) and the underlying layer E (high-voltage power layer). Utilizing the PCB layer shielding effect, electromagnetic interference and vertical coupling interference from high-current and high-frequency switching actions in the power circuit to the gate drive signal are reduced, improving operational stability. The multi-layer insulation structure ensures reliable isolation between the high-voltage power circuit and the low-voltage signal circuit, eliminating the need for additional insulation measures and reducing application complexity.

[0041] Moreover, the G layer enables vertical power connections by opening through-holes, replacing the traditional routing method that goes around the edge. This fully utilizes the Z-axis space of the PCB, allowing for the integration of more complex topologies within a limited planar size. This improves module integration, significantly shortens the physical length of power loops, effectively reduces loop resistance and stray inductance, and directly improves module switching speed and operating efficiency.

[0042] In a preferred embodiment of the present invention, the chip unit U includes:

[0043] A metal base on which power chips are soldered. The power chips include MOS chips or a combination of IGBT chips and diode chips.

[0044] In a preferred embodiment of the present invention, the metal base includes features that increase heat capacity.

[0045] In a preferred embodiment of the present invention, when the power chip is a MOS chip, the gate of the MOS chip is connected to the signal pin as a signal electrode, and the source and drain of the MOS chip are connected to the power terminals as power electrodes.

[0046] When the power chip is a combination of an IGBT chip and a diode chip, the gate of the IGBT chip is connected to the signal pin as the signal electrode, and the emitter and collector of the IGBT chip are connected to the power terminals as the power electrodes.

[0047] Specifically, in this embodiment, each chip unit is located in the device bonding layer (layer A) inside the circuit board, and includes a metal base and a power chip soldered thereon. For example... Figure 3 As shown, the structure is illustrated by soldering an IGBT chip (U-3) and a diode (U-1) onto a metal base U-1.

[0048] Depending on the type of power chip (MOS chip or IGBT chip combined with diode), its electrodes are connected to the G, E, and C layers of the circuit board in the following ways:

[0049] Control gate connection (G layer): The gate on the surface of the power chip serves as the signal control gate, extending upwards and electrically connecting to the uppermost signal trace layer (G layer). This connection path passes through the E layer (which requires insulation clearance), directly introducing the drive signal into the chip to ensure high-speed transmission of the control signal.

[0050] Top surface power electrode connection (E layer): The source (for MOS) or emitter (for IGBT) on the surface of the power chip serves as the first power electrode, extending upwards and electrically connecting to the power trace layer (E layer) located above the chip. The E layer is responsible for collecting the current flowing out of each chip cell and directing it to external terminals.

[0051] Bottom-side power electrode connection (C layer): The drain (for MOS) or collector (for IGBT) on the bottom surface of the power chip serves as the second power electrode and is directly soldered to the metal base. This metal base not only acts as a heat sink but also serves as or connects to the power routing layer (C layer) located below the chip, thus forming a complete vertical current loop.

[0052] The chip electrodes are directly and vertically connected to the adjacent copper layers (E layer and C layer). Compared with the traditional wire bonding process, this greatly shortens the current transmission path and minimizes parasitic inductance, which is crucial for high-frequency switching photovoltaic-storage inverters.

[0053] The gate connection (G layer) and power circuit (E layer / C layer) are spatially vertically separated, and the E layer, as a large-area copper layer, plays an electrostatic shielding role between the G layer and the A layer (chip), effectively reducing Miller capacitance coupling interference of power switching action (dv / dt) to the gate signal, and electromagnetic interference (EMI) suppression to prevent false turn-on.

[0054] The collector (C) at the bottom of the chip directly utilizes a large metal base for electrical and thermal conductivity, which not only reduces the on-resistance (Rds_on) but also mitigates temperature fluctuations by leveraging the thermal capacity of the metal base.

[0055] In a preferred embodiment of the present invention, the circuit board 2 further includes a heat dissipation layer S disposed at the bottom of the circuit board.

[0056] Specifically, such as Figure 2 As shown, a heat dissipation layer (S layer) is provided on the bottom of the circuit board, and a heat dissipation substrate is connected to the back of the circuit board. The inner S layer is made of a high thermal conductivity material and is in close contact with the chip layer or power layer to quickly conduct heat downwards; the back of the circuit board is fully nickel-plated and soldered or bonded to the external heat dissipation substrate, and finally fixed to the external heat sink with bolts.

[0057] Compared to traditional plastic modules whose junction temperature cannot be too high due to limitations in casing material, the heat dissipation path (chip-metal base-S layer-heat dissipation substrate) in this embodiment has lower thermal resistance, allowing the chip to operate at a higher junction temperature, thereby improving the efficiency and power density of a single module.

[0058] Moreover, the embedded circuit board is directly integrated with the heat dissipation substrate, eliminating the need for additional thermally conductive insulating pads and improving heat conduction efficiency.

[0059] In a preferred embodiment of the present invention, the three-level topology is a T-type three-level topology, in which case there are 3 power terminals corresponding to every 4 chip units integrated on the circuit board. The T-type three-level topology is as follows: Figure 4 As shown, Figure 4 The diagram shows a chip unit U using a combination of IGBT and diode chips. The 1, 0, and -1 on the left side of the diagram represent positive, zero, and negative output levels, respectively, and are connected to a power terminal.

[0060] In a preferred embodiment of the present invention, the back of the circuit board 2 is connected to the heat dissipation substrate 4.

[0061] In a preferred embodiment of the present invention, the number of signal pins is twice the number of chip cells.

[0062] In a preferred embodiment of the present invention, nickel is plated at the solder joints between the signal pins and power terminals and the circuit board.

[0063] Specifically, this embodiment adopts a T-type three-level topology, and the number of terminals is configured according to the electrical requirements of the three-level topology; when four chip units are integrated, there are three power terminals (outputting positive level, zero level and negative level respectively) (e.g., 12 units correspond to 9 terminals).

[0064] Furthermore, the solder joints between the signal pins and power terminals and the circuit board employ a localized nickel plating process. This localized nickel plating improves the metallurgical bonding at the solder interface. The nickel plating layer effectively prevents copper oxidation and enhances solder wettability, ensuring the mechanical strength and electrical conductivity between the signal pins and power terminals and the circuit board, thus meeting the reliability requirements of long-term operation of the photovoltaic-storage inverter.

[0065] The number of signal pins is twice the number of chip units. The standardized terminal and pin layout allows clients to complete circuit connections simply by soldering and bolting, eliminating the need to deal with complex internal topology wiring and reducing the complexity of system integration.

[0066] The above are merely preferred embodiments of the present invention and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should recognize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present invention.

Claims

1. A three-level embedded module, characterized in that, include: A circuit board, the front side of which is provided with signal pins and power terminals; Multiple chip units are embedded and integrated inside the circuit board, and are connected to the signal pins and power terminals to form a three-level topology.

2. As described in claim 1, characterized in that, The circuit board includes: Signal trace layers, power trace layers, and chip layers are isolated from each other by insulating layers; Each of the chip units is integrated in the chip layer, and the signal electrode of each chip unit is connected to the corresponding signal pin through the signal trace layer. The power electrode of each chip unit is connected to the corresponding power terminal through the power trace layer.

3. The three-level embedded module according to claim 2, characterized in that, The chip unit includes: A metal base on which a power chip is soldered, the power chip including a MOS chip, or a combination of an IGBT chip and a diode chip.

4. The three-level embedded module according to claim 3, characterized in that, When the power chip is a MOS chip, the gate of the MOS chip is connected to the signal pin as a signal electrode, and the source and drain of the MOS chip are connected to the power terminal as power electrodes. When the power chip is a combination of an IGBT chip and a diode chip, the gate of the IGBT chip is connected to the signal pin as the signal electrode, and the emitter and collector of the IGBT chip are connected to the power terminal as the power electrodes.

5. The three-level embedded module according to claim 2, characterized in that, The circuit board also includes a heat dissipation layer disposed at the bottom of the circuit board.

6. The three-level embedded module according to claim 1, characterized in that, The three-level topology is a T-type three-level topology, so there are 3 power terminals corresponding to every 4 chip units integrated in the circuit board.

7. The three-level embedded module according to claim 1, characterized in that, The back of the circuit board is connected to a heat dissipation substrate.

8. The three-level embedded module according to claim 3, characterized in that, The metal base includes features to increase heat capacity.

9. The three-level embedded module according to claim 2, characterized in that, The number of signal pins is twice the number of chip units.

10. The three-level embedded module according to claim 1, characterized in that, Nickel is plated at the solder joints of the signal pins and the power terminals to the circuit board.

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