Semiconductor device

Abstract

Provided is a semiconductor device that can improve element performance and reliability. The semiconductor device includes: a gate structure disposed on an active pattern and including a gate electrode and a gate capping pattern disposed on the gate electrode; a source / drain pattern disposed on at least one side of the gate structure; a contact silicide film disposed on the source / drain pattern and defining a contact groove; a source / drain contact filling the contact groove and connected to the source / drain pattern; an etch stop film disposed on an upper surface of the gate cover pattern and an upper surface of the source / drain contact; and a first via pattern penetrating the etch stop film and connected to the source / drain contact and formed of a first metal, in which the source / drain contact includes a lower conductive contact pattern, a first contact metal pattern formed of a second metal, and a second contact metal pattern formed of a third metal.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] As a miniaturization technique for increasing the density of semiconductor devices, multi-gate transistors have been proposed. In a multi-gate transistor, a multi-channel active pattern (or silicon body) with a fin shape or nanowire shape is formed on a substrate, and a gate is formed on the surface of the multi-channel active pattern.

[0003] Because this multi-gate transistor utilizes a three-dimensional channel, it can be easily miniaturized. Furthermore, current control capability can be improved even without increasing the gate length of the multi-gate transistor. Additionally, the short-channel effect (SCE), where the channel potential is affected by the drain voltage, can be effectively suppressed.

[0004] On the other hand, as the spacing dimensions of semiconductor devices decrease, research is needed to ensure reduced capacitance and electrical stability between contacts in semiconductor devices. Summary of the Invention

[0005] Various aspects of this disclosure provide semiconductor devices that can improve component performance and reliability.

[0006] However, the scope of this disclosure is not limited to what is set forth herein. Those skilled in the art will gain a clearer understanding of the foregoing and other aspects of this disclosure by referring to the detailed description of the disclosure given below.

[0007] According to an aspect of this disclosure, a semiconductor device is provided, the semiconductor device comprising: a gate structure disposed on an active pattern and including a gate electrode and a gate cover pattern disposed on the gate electrode; a source / drain pattern disposed on at least one side of the gate structure; a contact silicide film disposed on the source / drain pattern and defining a contact groove; a source / drain contact filling the contact groove and connected to the source / drain pattern; an etch stop film disposed on an upper surface of the gate cover pattern and an upper surface of the source / drain contact; and a first via pattern penetrating the etch stop film, connected to the source / drain contact, and formed of a first metal. The source / drain contact includes: a lower conductive contact pattern, a first contact metal pattern formed of a second metal, and a second contact metal pattern formed of a third metal. The first contact metal pattern and the second contact metal pattern are disposed on the lower conductive contact pattern. The third metal is different from the first metal and the second metal. The second contact metal pattern is disposed between the first contact metal pattern and the first path pattern and is in contact with the first path pattern.

[0008] According to another aspect of this disclosure, a semiconductor device is provided, the semiconductor device comprising: a gate structure disposed on an active pattern and including a gate electrode and a gate overlay pattern disposed on the gate electrode; a source / drain pattern disposed on at least one side of the gate structure; a source / drain contact disposed on the source / drain pattern and connected to the source / drain pattern; and a molybdenum path pattern disposed on the source / drain contact and in contact with an upper surface of the source / drain contact. The source / drain contact comprises: a lower conductive contact pattern, a contact metal pattern formed of a first metal, and a tungsten contact pattern, the contact metal pattern being disposed between the tungsten contact pattern and the lower conductive contact pattern, and at least a portion of the upper surface of the source / drain contact being defined by the tungsten contact pattern.

[0009] According to another aspect of this disclosure, a semiconductor device is provided, the semiconductor device comprising: an active pattern including a lower pattern and a sheet pattern located on the lower pattern; a gate structure located on the active pattern and including a gate electrode and a gate cover pattern, the gate electrode surrounding the sheet pattern and the gate cover pattern disposed on the gate electrode; a source / drain pattern disposed on at least one side of the gate structure; a source / drain contact located on and connected to the source / drain pattern; an etch stop film disposed on an upper surface of the gate cover pattern and an upper surface of the source / drain contact; and a molybdenum path pattern penetrating the etch stop film and contacting the upper surface of the source / drain contact. The source / drain contact includes a lower conductive contact pattern, a molybdenum contact pattern, and a tungsten contact pattern, and at least a portion of the upper surface of the source / drain contact is defined by the tungsten contact pattern.

[0010] It should be noted that the effects of this disclosure are not limited to those described above, and other effects of this disclosure will become clear from the following description. Attached Figure Description

[0011] The above and other aspects and features of this disclosure will become clearer from the following detailed description of exemplary embodiments with reference to the accompanying drawings, in which: Figure 1 This is an example layout diagram used to illustrate a semiconductor device according to some embodiments.

[0012] Figure 2 It is along Figure 1 The cross-sectional view taken from AA.

[0013] Figure 3 It is along Figure 1 A cross-sectional view of BB.

[0014] Figure 4 It is along Figure 1 The cross-sectional view taken by CC.

[0015] Figure 5 It is a curve comparing the resistivity of the upper conductive film with the materials contained in the lower film.

[0016] Figure 6 and Figure 7 These are diagrams used to illustrate semiconductor devices according to some embodiments.

[0017] Figure 8 and Figure 9 These are diagrams used to illustrate semiconductor devices according to some embodiments.

[0018] Figure 10 and Figure 11 These are diagrams used to illustrate semiconductor devices according to some embodiments.

[0019] Figures 12 to 14 These are diagrams used to illustrate semiconductor devices according to some embodiments.

[0020] Figure 15 and Figure 16 These are diagrams used to illustrate semiconductor devices according to some embodiments.

[0021] Figure 17 These are diagrams used to illustrate semiconductor devices according to some embodiments.

[0022] Figures 18 to 21 These are diagrams used to illustrate semiconductor devices according to some embodiments.

[0023] Figures 22 to 24 These are diagrams used to illustrate semiconductor devices according to some embodiments.

[0024] Figures 25 to 31 This is an intermediate stage diagram illustrating a method for manufacturing a semiconductor device according to some embodiments.

[0025] Figures 32 to 35 This is an intermediate stage diagram illustrating a method for manufacturing a semiconductor device according to some embodiments.

[0026] Figures 36 to 40 This is an intermediate stage diagram illustrating a method for manufacturing a semiconductor device according to some embodiments. Detailed Implementation

[0027] It should be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, region, layer, or portion described below may be referred to as the second element, component, region, layer, or portion.

[0028] Although the accompanying drawings of semiconductor devices according to some embodiments illustrate fin transistors (FinFETs) including channel regions with fin-patterned shapes, transistors including nanowires or nanosheets, and MBCFETs... TM(Multi-channel field-effect transistor) is used as an example, but the embodiments are not limited thereto. Semiconductor devices according to some embodiments may of course include tunneling transistors (tunneling FETs) or three-dimensional (3D) transistors. Semiconductor devices according to some embodiments may of course include planar transistors. Furthermore, the technical ideas of this disclosure can be applied to transistors based on two-dimensional materials (2D material-based FETs) and their heterostructures.

[0029] In addition, the semiconductor device according to some embodiments may also include bipolar junction transistors, laterally diffused metal-oxide semiconductors (LDMOS), etc.

[0030] Reference Figures 1 to 5 Describes a semiconductor device according to some embodiments.

[0031] Figure 1 This is an example layout diagram used to illustrate a semiconductor device according to some embodiments. Figure 2 It is along Figure 1 The cross-sectional view taken from AA. Figure 3 It is along Figure 1 A cross-sectional view of BB. Figure 4 It is along Figure 1 The cross-sectional view taken by CC. Figure 5 It is a curve comparing the resistivity of the upper conductive film with the materials contained in the lower film.

[0032] For ease of explanation, Figure 1 The source / drain path 180, gate path pattern 185, and first wiring 207 are not shown. Furthermore, although a gate contact 175 is shown disposed on one of the plurality of first gate electrodes 120, this is for illustrative purposes only, and the embodiments are not limited thereto.

[0033] refer to Figures 1 to 5 According to some embodiments, a semiconductor device may include a first active pattern AP1, a second active pattern AP2, at least one first gate electrode 120, a first source / drain contact 170, a second source / drain contact 270, a gate contact 175, a source / drain path pattern 180, a gate path pattern 185, and wiring 207.

[0034] As an example, substrate 100 may be bulk silicon or silicon-on-insulator (SOI). Alternatively, substrate 100 may be a silicon substrate, or may include other materials, such as, but not limited to, silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. As another example, substrate 100 may be formed of an insulating material.

[0035] A first active pattern AP1 and a second active pattern AP2 can be disposed on the substrate 100. Both the first active pattern AP1 and the second active pattern AP2 can extend longitudinally along a first direction DR1. The first active pattern AP1 and the second active pattern AP2 can be disposed spaced apart from each other in a second direction DR2. For example, the first direction DR1 is the direction that intersects with the second direction DR2.

[0036] As an example, one of the first active pattern AP1 and the second active pattern AP2 can be a PMOS forming region, while the other can be an NMOS forming region. As another example, the first active pattern AP1 and the second active pattern AP2 can both be NMOS forming regions. As yet another example, the first active pattern AP1 and the second active pattern AP2 can both be PMOS forming regions.

[0037] As an example, the first active pattern AP1 and the second active pattern AP2 can be located in the logic area. As another example, the first active pattern AP1 and the second active pattern AP2 can be located in the SRAM area. As yet another example, the first active pattern AP1 and the second active pattern AP2 can be located in the I / O area.

[0038] The first active pattern AP1 and the second active pattern AP2 can be, for example, multi-channel active patterns. The first active pattern AP1 may include a first lower pattern BP1 and multiple first sheet patterns NS1. The second active pattern AP2 may include a second lower pattern BP2 and multiple second sheet patterns NS2.

[0039] Each of the first lower pattern BP1 and the second lower pattern BP2 can protrude from the substrate 100. Each of the first lower pattern BP1 and the second lower pattern BP2 can extend longitudinally along the first direction DR1.

[0040] The first lower pattern BP1 can be spaced apart from the second lower pattern BP2 in the second direction DR2. The first lower pattern BP1 and the second lower pattern BP2 can be separated by a fin-shaped groove FT extending in the first direction DR1.

[0041] Multiple first sheet patterns NS1 can be disposed on the upper surface of a first lower pattern BP1. The multiple first sheet patterns NS1 can be spaced apart from the first lower pattern BP1 on a third direction DR3. The third direction DR3 can be a direction intersecting with the first direction DR1 and the second direction DR2. For example, the third direction DR3 can be the thickness direction of the substrate 100. The first direction DR1 can be a direction intersecting with the second direction DR2.

[0042] Multiple second sheet patterns NS2 can be disposed on the upper surface of the second lower pattern BP2. The multiple second sheet patterns NS2 can be spaced apart from the second lower pattern BP2 on the third direction DR3.

[0043] Although it is shown that each of the three first sheet patterns NS1 and the three second sheet patterns NS2 is disposed on the third direction DR3, this is only for illustrative purposes and the embodiment is not limited thereto.

[0044] As an example, the first lower pattern BP1 and the second lower pattern BP2 can be formed by etching a portion of the substrate 100, and may include an epitaxial layer grown from the substrate 100. Each of the first lower pattern BP1 and the second lower pattern BP2 may include silicon or germanium as an elemental semiconductor material. Furthermore, the first lower pattern BP1 and the second lower pattern BP2 may include compound semiconductors, and may include, for example, group IV-IV compound semiconductors or group III-V compound semiconductors.

[0045] Group IV-IV compound semiconductors may include, for example, binary or ternary compounds comprising at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or compounds obtained by doping these elements with group IV elements.

[0046] III-V compound semiconductors can be, for example, at least one of binary, ternary, or quaternary compounds formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In), which are group III elements, with one of phosphorus (P), arsenic (As), and antimony (Sb), which are group V elements.

[0047] As another example, the first lower pattern BP1 and the second lower pattern BP2 can be formed by filling the spaces in which the pattern containing the semiconductor material has been removed with an insulating material. Both the first lower pattern BP1 and the second lower pattern BP2 may include an insulating material.

[0048] Both the first sheet pattern NS1 and the second sheet pattern NS2 can include silicon or germanium, group IV-IV compound semiconductors, or group III-V compound semiconductors as elemental semiconductor materials. When the first lower pattern BP1 includes a semiconductor material, the first sheet pattern NS1 can include the same material as the first lower pattern BP1, or it can include a different material than the first lower pattern BP1. Similarly, when the second lower pattern BP2 includes a semiconductor material, the second sheet pattern NS2 can include the same material as the second lower pattern BP2, or it can include a different material than the second lower pattern BP2.

[0049] In a semiconductor device according to some embodiments, the first lower pattern BP1 and the second lower pattern BP2 are silicon under-patterns including silicon, and the first sheet pattern NS1 and the second sheet pattern NS2 may be silicon sheet patterns including silicon.

[0050] For example, the width of the first sheet pattern NS1 in the second direction DR2 can be increased or decreased proportionally to the width of the first lower pattern BP1 in the second direction DR2. As an example, although it is shown that the width of the first sheet pattern NS1 stacked on the third direction DR3 is the same in the second direction DR2, this is only for illustrative purposes and the embodiment is not limited thereto. Unlike the example shown, the width of the first sheet pattern NS1 stacked on the third direction DR3 in the second direction DR2 can decrease as it moves away from the first lower pattern BP1.

[0051] A field insulating film 105 can be formed on the substrate 100. The field insulating film 105 can fill at least a portion of the fin trench FT.

[0052] The field insulating film 105 can be disposed on the sidewalls of the first lower pattern BP1 and the second lower pattern BP2. The field insulating film 105 is not disposed on the upper surface of the first lower pattern BP1 and the upper surface of the second lower pattern BP2.

[0053] As an example, the field insulating film 105 may completely cover the sidewalls of the first lower pattern BP1. Unlike the example shown, the field insulating film 105 may cover a portion of the sidewalls of the first lower pattern BP1 and / or a portion of the sidewalls of the second lower pattern BP2. In this case, taking the first lower pattern BP1 as an example, a portion of the first lower pattern BP1 may protrude beyond the upper surface of the field insulating film 105 on the third-direction DR3.

[0054] Each first sheet pattern NS1 and each second sheet pattern NS2 is disposed above the upper surface of the field insulating film 105. The field insulating film 105 may include, for example, an oxide film, a nitride film, an oxide oxynitride film, or a combination thereof. Although the field insulating film 105 is shown as a single-layer film, this is for illustrative purposes only, and the embodiments are not limited thereto.

[0055] At least one gate structure GS can be disposed on the substrate 100. For example, at least one gate structure GS can be disposed on the field insulating film 105. The gate structure GS can extend in the second direction DR2. Adjacent gate structures GS can be spaced apart from each other in the first direction DR1.

[0056] The gate structure GS can be disposed on the first active pattern AP1 and the second active pattern AP2. The gate structure GS can intersect with the first active pattern AP1 and the second active pattern AP2.

[0057] Although the gate structure GS is shown as spanning the first active pattern AP1 and the second active pattern AP2, this is for illustrative purposes only, and the embodiment is not limited thereto. That is, a portion of the gate structure GS may be divided into two parts and disposed on the first active pattern AP1 and the second active pattern AP2.

[0058] The gate structure GS may intersect with the first lower pattern BP1 and the second lower pattern BP2. The gate structure GS may surround the first sheet pattern NS1 and the second sheet pattern NS2.

[0059] The gate structure GS may include a first gate electrode 120, a first gate insulating film 130, a first gate spacer 140, and a gate cover pattern 145.

[0060] The gate structure GS may include an inner gate structure INT_GS disposed between adjacent first sheet patterns NS1 along the third direction DR3 and between a first lower pattern BP1 and the first sheet pattern NS1. The inner gate structure INT_GS may include a first gate electrode 120 and a first gate insulating film 130 disposed between adjacent first sheet patterns NS1 and between the first lower pattern BP1 and the first sheet pattern NS1. Although not shown, the inner gate structure INT_GS may be disposed between adjacent second sheet patterns NS2 along the third direction DR3 and between the second lower pattern BP2 and the second sheet pattern NS2.

[0061] The first gate electrode 120 may be disposed on the first lower pattern BP1 and the second lower pattern BP2. The first gate electrode 120 may intersect with the first lower pattern BP1 and the second lower pattern BP2. The first gate electrode 120 may surround the first sheet pattern NS1. The first gate electrode 120 may surround the second sheet pattern NS2.

[0062] The upper surface of the first gate electrode 120 may be a concave curved surface recessed toward the upper surface of the first active pattern AP1, but is not limited thereto. That is, unlike the example shown, the upper surface of the first gate electrode 120 may be a flat plane. For example, the upper surface of the first active pattern AP1 may be the upper surface of the first sheet pattern NS1 disposed at the uppermost part of the first sheet pattern NS1.

[0063] The first gate electrode 120 may include at least one of the following: metal, metal alloy, conductive metal nitride, metal silicide, doped semiconductor material, conductive metal carbonitride, conductive metal carbide, conductive metal oxide, or conductive metal oxynitride. The first gate electrode 120 may include at least one of the following: titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium tantalum nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), carbonitride... Tantalum (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof. Conductive metal oxides and conductive metal nitrides may be, but are not limited to, the oxidation forms of the above materials.

[0064] The first gate electrode 120 may be disposed on both sides of the first source / drain pattern 150, which will be described later. The gate structure GS may be disposed on both sides of the first source / drain pattern 150 in the first direction DR1.

[0065] As an example, the two first gate electrodes 120 disposed on both sides of the first source / drain pattern 150 can be normal gate electrodes used as gates of transistors. As another example, although the first gate electrode 120 disposed on one side of the first source / drain pattern 150 can be used as the gate of a transistor, the first gate electrode 120 disposed on the other side of the first source / drain pattern 150 can be a dummy gate electrode.

[0066] Although not shown, the first gate electrode 120 may be disposed on both sides of the second source / drain pattern 250, which will be described later. The gate structure GS may be disposed on both sides of the second source / drain pattern 250 in the first direction DR1.

[0067] The first gate insulating film 130 may extend along the upper surface of the field insulating film 105, the upper surface of the first lower pattern BP1, and the upper surface of the second lower pattern BP2. The first gate insulating film 130 may surround the first sheet pattern NS1. The first gate insulating film 130 may surround the second sheet pattern NS2. The first gate insulating film 130 may be disposed along the periphery of the first sheet pattern NS1 and the periphery of the second sheet pattern NS2. The first gate electrode 120 is disposed on the first gate insulating film 130. The first gate insulating film 130 may be disposed between the first gate electrode 120 and the first sheet pattern NS1, and between the first gate electrode 120 and the second sheet pattern NS2.

[0068] The first gate insulating film 130 may include silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material with a dielectric constant greater than that of silicon oxide. The high dielectric constant material may include, for example, one or more of boron nitride, hafnium oxide, hafnium oxide, aluminum hafnium oxide, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0069] Although the first gate insulating film 130 is shown as a single film, this is for illustrative purposes only, and the embodiments are not limited thereto. The first gate insulating film 130 may include multiple films. The first gate insulating film 130 may include an interfacial layer disposed between the first sheet pattern NS1 and the first gate electrode 120 and between the second sheet pattern NS2 and the first gate electrode 120, and a high dielectric constant insulating film.

[0070] The semiconductor device according to some embodiments may include an NC (negative capacitance) FET that uses a negative capacitor. For example, the first gate insulating film 130 may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0071] Ferroelectric films can have negative capacitance, while paraelectric films can have positive capacitance. For example, if two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance is smaller than the capacitance of each individual capacitor. On the other hand, if at least one of the capacitances of the two or more capacitors connected in series has a negative capacitance, the total capacitance can be greater than the absolute value of the capacitance of each individual capacitor while also being positive.

[0072] When a ferroelectric film with negative capacitance is connected in series with a paraelectric film with positive capacitance, the total capacitance of the two films connected in series can be increased. By utilizing the increased total capacitance, a transistor including the ferroelectric film can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0073] Ferroelectric material films can possess ferroelectric properties. Ferroelectric material films can include at least one of, for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, or lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide can be a material obtained by doping hafnium oxide with zirconium (Zr). As another example, hafnium zirconium oxide can also be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0074] Ferroelectric material films may also include dopants. For example, dopants may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), or tin (Sn). The types of dopants included in the ferroelectric material film may vary depending on the ferroelectric material contained in the film.

[0075] When the ferroelectric material film includes hafnium oxide, the dopant contained in the ferroelectric material film may include at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al) and yttrium (Y).

[0076] When the dopant is aluminum (Al), the ferroelectric film can include 3 at% to 8 at% (atomic percentage) aluminum. Here, the dopant ratio can be the ratio of aluminum to the sum of hafnium and aluminum.

[0077] When the dopant is silicon (Si), the ferroelectric film may include 2 at% to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric film may include 2 at% to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric film may include 1 at% to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric film may include 50 at% to 80 at% zirconium.

[0078] The paraelectric material film may possess paraelectric properties. The paraelectric material film may include at least one of, for example, silicon oxide or a metal oxide having a high dielectric constant. The metal oxide contained in the paraelectric material film may include, for example, but not limited to, at least one of hafnium oxide, zirconium oxide, or aluminum oxide.

[0079] Ferroelectric and paraelectric material films can contain the same material. Ferroelectric material films exhibit ferroelectric properties, but paraelectric material films may not. For example, when both ferroelectric and paraelectric material films include hafnium oxide, the crystal structure of the hafnium oxide in the ferroelectric material film differs from that in the paraelectric material film.

[0080] Ferroelectric material films can have a thickness that exhibits ferroelectric properties. The thickness of a ferroelectric material film can be, for example, but not limited to, 0.5 to 10 nm. Since the critical thickness for exhibiting ferroelectric properties can be different for each ferroelectric material, the thickness of the ferroelectric material film can vary depending on the ferroelectric material.

[0081] As an example, the first gate insulating film 130 may include a ferroelectric material film. As another example, the first gate insulating film 130 may include a plurality of ferroelectric material films spaced apart from each other. The first gate insulating film 130 may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are stacked alternately.

[0082] The first gate spacer 140 may be disposed on the sidewall of the first gate electrode 120. The first gate spacer 140 may extend in the second direction DR2.

[0083] For example, the first gate spacer 140 may not be disposed between the first sheet patterns NS1 adjacent to each other along the third direction DR3, nor between the first sheet pattern NS1 and the first lower pattern BP1. The first gate spacer 140 may consist only of the outer spacer.

[0084] The first gate spacer 140 may include, for example, silicon nitride, silicon oxynitride, silicon oxide, silicon carbonitride, boron silicon nitride, boron silicon oxynitride, silicon carbonitride, or combinations thereof.

[0085] Although not shown, as an example, along Figure 1 The cross-sectional view of the second active pattern AP2 in the image can be compared with... Figure 2 Similar. As another example, along Figure 1 The cross-sectional view of the second active pattern AP2 in the image can be compared with the one described later. Figure 17 resemblance.

[0086] A gate overlay pattern 145 may be disposed on the first gate electrode 120 and the first gate spacer 140. The upper surface 145US of the gate overlay pattern 145 may be coplanar with the upper surface of the first interlayer insulating film 190. Unlike the example shown, the gate overlay pattern 145 may be disposed between the first gate spacers 140.

[0087] The gate cover pattern 145 may include, for example, silicon nitride, silicon oxynitride, silicon oxide, silicon carbonitride, silicon carbonitride, or a combination thereof. The gate cover pattern 145 may include a material that has etch selectivity for the first interlayer insulating film 190.

[0088] A first source / drain pattern 150 is disposed on the substrate 100. The first source / drain pattern 150 may be disposed on a first lower pattern BP1. The first source / drain pattern 150 is in contact with a first sheet pattern NS1. For example, the first source / drain pattern 150 may be in contact with the first gate insulating film 130 of the inner gate structure INT_GS.

[0089] The first source / drain pattern 150 may be disposed between the gate structures GS. The first source / drain pattern 150 may be disposed on at least one side of the gate structure GS. The first source / drain pattern 150 may be disposed on the side of the first gate electrode 120. For example, the first source / drain pattern 150 may be disposed on both sides of the gate structure GS. Unlike the example shown, the first source / drain pattern 150 may be disposed on one side of the gate structure GS, and may not be disposed on the other side of the gate structure GS.

[0090] A second source / drain pattern 250 is disposed on the substrate 100. The second source / drain pattern 250 may be disposed on a second lower pattern BP2. Although not shown, the shape of the second source / drain pattern 250 disposed on the second lower pattern BP2 may be similar to Figure 2 The shape of the first source / drain pattern 150 is set in the middle.

[0091] As an example, the first source / drain pattern 150 may include multiple width-extended regions. Figure 2 In this process, the outer wall of the first source / drain pattern 150 may be wavy. In the width extension region, the width of the first source / drain pattern 150 along the first direction DR1 may increase and then decrease as it moves away from the first lower pattern BP1. The width extension region of the first source / drain pattern 150 may be defined between adjacent first sheet patterns NS1 along the third direction DR3. The width extension region of the first source / drain pattern 150 may be defined between the first lower pattern BP1 and the first sheet pattern NS1. In each width extension region of the first source / drain pattern 150, the point where the width of the first source / drain pattern 150 is greatest is located between the first sheet pattern NS1 and the first lower pattern BP1, or between adjacent first sheet patterns NS1 along the third direction DR3.

[0092] As another example, unlike the example shown, the first source / drain pattern 150 may not include multiple width extension regions.

[0093] The first source / drain pattern 150 can be included in the source / drain of a transistor that uses the first active pattern AP1 (e.g., the first patch pattern NS1) as the channel region. The second source / drain pattern 250 can be included in the source / drain of a transistor that uses the second patch pattern NS2 as the channel region.

[0094] Each of the first source / drain pattern 150 and the second source / drain pattern 250 may include an epitaxial pattern. The first source / drain pattern 150 and the second source / drain pattern 250 may include, for example, a semiconductor material.

[0095] The first source / drain pattern 150 and the second source / drain pattern 250 may include n-type or p-type impurities. The n-type impurities may include at least one of phosphorus (P), arsenic (As), antimony (Sb), or bismuth (Bi). The p-type impurities may include at least one of, for example, boron (B) or gallium (Ga).

[0096] From such as Figure 2 When viewed from a cross-sectional angle, the upper surface of the first source / drain pattern 150 is shown as being higher than the upper surface of the first active pattern AP1, but the embodiments are not limited to this.

[0097] The source / drain etch stop film 156 can be disposed on the upper surface of the field insulating film 105, the sidewall of the gate structure GS, the sidewall of the first source / drain pattern 150, and the sidewall of the second source / drain pattern 250. Although not shown, the source / drain etch stop film 156 can be disposed on the upper surface of the first source / drain pattern 150 and the upper surface of the second source / drain pattern 250.

[0098] The source / drain etch stop film 156 may comprise a material having etch selectivity relative to the first interlayer insulating film 190, which will be described later. The source / drain etch stop film 156 may comprise, for example, silicon nitride, silicon carbonitride, silicon boron nitride, silicon boron oxynitride, silicon carbonitride, or combinations thereof. Unlike the example shown, the source / drain etch stop film 156 may not be formed.

[0099] The first interlayer insulating film 190 can be formed on the field insulating film 105. The first interlayer insulating film 190 can be disposed on the first source / drain pattern 150 and the second source / drain pattern 250. The first interlayer insulating film 190 may not cover the upper surface 145US of the gate cover pattern 145.

[0100] The first interlayer insulating film 190 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric constant material. The low dielectric constant material may include, but is not limited to, tetraethyl orthosilicate (FTEOS), silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilylborate (TMSB), diacetoxydi-tert-butylsiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), TOSZ (Toran silazane), FSG (fluorinated silicate glass), polyimide nanofoams such as polypropylene oxide, CDO (carbon-doped silicon oxide), OSG (organosilicon glass), SiLK, amorphous fluorinated carbon, silica aerogel, silica dry gel, mesoporous silica, or combinations thereof.

[0101] The first source / drain contact 170 can be disposed on the first active pattern AP1. The first source / drain contact 170 can be disposed on the first source / drain pattern 150. The first source / drain contact 170 is connected to the first source / drain pattern 150 located on the first active pattern AP1.

[0102] The second source / drain contact 270 can be disposed on the second active pattern AP2. The second source / drain contact 270 can be disposed on the second source / drain pattern 250. The second source / drain contact 270 is connected to the second source / drain pattern 250 located on the second active pattern AP2.

[0103] Unlike the example shown, a portion of the first source / drain contact 170 can be directly connected to the second source / drain contact 270. That is, the connection source / drain contact that is simultaneously connected to the first source / drain pattern 150 and the second source / drain pattern 250 can span across the first active pattern AP1 and the second active pattern AP2.

[0104] Since the description of the second source / drain contact 270 is substantially the same as the description of the first source / drain contact 170, the first source / drain contact 170 will be used to provide the following description.

[0105] The first source / drain contact 170 may extend along the sidewall of the first gate electrode 120 in the third direction DR3. With the lowermost part of the first source / drain pattern 150 as a reference, the lowermost part of the first source / drain contact 170 is lower than the upper surface of the first gate electrode 120.

[0106] The first source / drain contact 170 may be disposed inside the first interlayer insulating film 190. The first source / drain contact 170 penetrates the source / drain etch stop film 156.

[0107] A first contact silicide film 155 may be disposed between the first source / drain contact 170 and the first source / drain pattern 150. The first contact silicide film 155 is disposed on the first source / drain pattern 150. The first contact silicide film 155 may define a contact groove 170R. The first source / drain contact 170 may fill the contact groove 170R.

[0108] The second contact silicide film 255 may be disposed between the second source / drain contact 270 and the second source / drain pattern 250. The description of the first contact silicide film 155 can be applied to the second contact silicide film 255. Both the first contact silicide film 155 and the second contact silicide film 255 may include, for example, a metal silicide material.

[0109] A contact liner 157 may be disposed on the first source / drain pattern 150. The contact liner 157 may be disposed between the first source / drain contact 170 and the first interlayer insulating film 190.

[0110] Contact pad 157 may extend along the sidewall of the first source / drain contact 170. Contact pad 157 may extend along the sidewall of the gate structure GS. Contact pad 157 may be disposed between the first source / drain contact 170 and the gate structure GS. Contact pad 157 may extend to, but is not limited to, the upper surface 145US of the gate cover pattern 145. Contact pad 157 is not formed along the bottom surface of the first source / drain contact 170. In a semiconductor according to some embodiments, for example, contact pad 157 may be disposed between the first source / drain contact 170 and the source / drain etch stop film 156.

[0111] Contact pad 157 may contact the first source / drain contact 170. Contact pad 157 may contact the sidewall of the first source / drain contact 170.

[0112] Contact pad 157 includes an insulating material. For example, contact pad 157 may be made of an insulating material. Contact pad 157 may include, for example, silicon oxycarbide, silicon nitride, silicon oxynitride, silicon carbonitride, boron silicon nitride, or boron silicon oxynitride.

[0113] As an example, contact pad 157 may comprise an insulating material containing carbon (C) and oxygen (O). Contact pad 157 may comprise, for example, silicon carbide. Alternatively, contact pad 157 may comprise silicon carbide doped with hydrogen (H).

[0114] Contact pad 157 may extend along the sidewall of the second source / drain contact 270. Source / drain etch stop film 156 and contact pad 157 may be included in source / drain etch pad 158.

[0115] The first source / drain contact 170 may include a lower conductive contact pattern 171, a first contact metal pattern 172, and a second contact metal pattern 173. The first contact metal pattern 172 and the second contact metal pattern 173 may be disposed on the lower conductive contact pattern 171. The first contact metal pattern 172 may be disposed between the lower conductive contact pattern 171 and the second contact metal pattern 173.

[0116] The lower conductive contact pattern 171 may contact the first contact silicide film 155. For example, the lower conductive contact pattern 171 may fill at least a portion of the contact groove 170R.

[0117] In a semiconductor device according to some embodiments, the lower conductive contact pattern 171 may be a single-material film structure. For example, the lower conductive contact pattern 171 may be formed from a single conductive material. In this case, the lower conductive contact pattern 171 may include impurities unintentionally introduced during the process of forming the lower conductive contact pattern 171.

[0118] For example, the lower conductive contact pattern 171 may be formed of a first metal. The lower conductive contact pattern 171 may be a conductive pattern formed of a first metal. The first metal may include, for example, but not limited to, one of titanium (Ti), tungsten (W), molybdenum (Mo), ruthenium (Ru), or cobalt (Co). As an example, the first metal may be tungsten.

[0119] The first contact metal pattern 172 can be a single-material film structure. The first contact metal pattern 172 can be formed of a second metal. The first contact metal pattern 172 can be a conductive pattern formed of a second metal. For example, the second metal can be different from the first metal included in the lower conductive contact pattern 171.

[0120] The first contact metal pattern 172 may include, for example, but not limited to, one of titanium (Ti), molybdenum (Mo), ruthenium (Ru), or cobalt (Co). As an example, the second metal may be molybdenum. The first contact metal pattern 172 may be a molybdenum contact pattern.

[0121] The first contact metal pattern 172 may include an upper surface 172US and a bottom surface 172BS opposite to each other on the third-direction DR3. The first contact metal pattern 172 may include a sidewall 172SW connecting the upper surface 172US and the bottom surface 172BS of the first contact metal pattern. The sidewall 172SW of the first contact metal pattern may extend on the third-direction DR3. The sidewall 172SW of the first contact metal pattern faces the first gate electrode 120. For example, in... Figure 2 In the cross-sectional view shown, the sidewall 172SW of the first contact metal pattern can face the first gate electrode 120 disposed on the upper surface of the first active pattern AP1.

[0122] The first contact metal pattern 172 can contact the lower conductive contact pattern 171. The bottom surface 172BS of the first contact metal pattern can contact the lower conductive contact pattern 171.

[0123] For example, the first contact metal pattern 172 may contact the source / drain etch pad 158. The first contact metal pattern 172 may contact the contact pad 157. The sidewall 172SW of the first contact metal pattern may contact the source / drain etch pad 158 (e.g., contact pad 157).

[0124] The second contact metal pattern 173 can be a single-material film structure. The second contact metal pattern 173 can be formed of a third metal. The third metal can be different from the second metal included in the first contact metal pattern 172. The second contact metal pattern 173 can be a conductive pattern formed of the third metal.

[0125] The second contact metal pattern 173 may include, for example, tungsten (W). The third metal may be tungsten. The second contact metal pattern 173 may be a tungsten contact pattern.

[0126] The second contact metal pattern 173 may contact the upper surface 172US of the first contact metal pattern. In a semiconductor device according to some embodiments, the second contact metal pattern 173 may contact the source / drain etch pad 158. The second contact metal pattern 173 may contact the contact pad 157.

[0127] The second contact metal pattern 173 may include at least a portion of the upper surface 170US of the first source / drain contact. At least a portion of the upper surface 170US of the first source / drain contact may be defined by the second contact metal pattern 173. In a semiconductor device according to some embodiments, the upper surface 170US of the first source / drain contact may be defined by the second contact metal pattern 173. The second contact metal pattern 173 may include the entire upper surface 170US of the first source / drain contact.

[0128] The gate contact 175 may be disposed inside the gate structure GS. The gate contact 175 may penetrate the gate cover pattern 145 and be connected to the first gate electrode 120.

[0129] The gate contact 175 can be positioned at the overlap with the gate structure GS. Although in Figure 1 The diagram shows that the gate contact 175 is disposed at a position that does not overlap with the first active pattern AP1 and the second active pattern AP2, but the embodiment is not limited thereto. The gate contact 175 may be disposed at a position that overlaps with at least one of the first active pattern AP1 and the second active pattern AP2.

[0130] Gate contact 175 may include a gate contact barrier film 176 and a gate contact fill film 177. The gate contact barrier film 176 may be disposed between the first gate electrode 120 and the gate contact fill film 177. For example, gate contact 175 may have a multi-material film structure comprising different materials from each other. Gate contact barrier film 176 may include at least one of, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boride (NiB), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), or rhodium (Rh). The gate contact filler 177 may include, for example, aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), or molybdenum (Mo).

[0131] The second interlayer insulating film 191 may be disposed on the first interlayer insulating film 190, the gate structure GS, the first source / drain contact 170, the second source / drain contact 270, and the gate contact 175. The second interlayer insulating film 191 may include at least one of, for example, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, and low dielectric constant materials.

[0132] A first etch stop film 195 may be disposed between a first interlayer insulating film 190 and a second interlayer insulating film 191. The first etch stop film 195 may extend along the upper surface 145µs of the gate overlay pattern, the upper surface of the first interlayer insulating film 190, the upper surface 170µs of the first source / drain contact, the upper surface of the second source / drain contact 270, and the upper surface 175µs of the gate contact. The first etch stop film 195 is disposed on the upper surface 145µs of the gate overlay pattern, the upper surface 170µs of the first source / drain contact, and the upper surface of the second source / drain contact 270.

[0133] The first etch stop film 195 may comprise a material having etch selectivity relative to the second interlayer insulating film 191. The first etch stop film 195 may comprise at least one of, for example, silicon nitride, silicon oxynitride, silicon oxycarbonitride, boron silicon nitride, boron silicon oxynitride, silicon oxycarbonitride, aluminum oxide, aluminum nitride, aluminum oxycarbonitride, and combinations thereof. Although the first etch stop film 195 is shown as a single film, the embodiments are not limited thereto. Unlike the illustrated example, the first etch stop film 195 may not be formed.

[0134] The wiring structure is disposed on the first source / drain contact 170, the second source / drain contact 270, and the gate contact 175. The wiring structure may include a source / drain path pattern 180, a gate path pattern 185, and wiring 207. The source / drain path pattern 180 and the gate path pattern 185 may be disposed inside the second interlayer insulating film 191.

[0135] The source / drain path pattern 180 can connect to the first source / drain contact 170 and the second source / drain contact 270. The source / drain path pattern 180 can penetrate the first etch stop film 195 and contact the first source / drain contact 170 and the second source / drain contact 270. The source / drain path pattern 180 can contact the upper surface 170US of the first source / drain contact.

[0136] The source / drain path pattern 180 can contact the second contact metal pattern 173. The second contact metal pattern 173 can be disposed between the source / drain path pattern 180 and the first contact metal pattern 172.

[0137] Gate path pattern 185 can be connected to gate contact 175. Gate path pattern 185 can penetrate the first etch stop film 195 and contact gate contact 175. Gate path pattern 185 can contact the upper surface 175US of the gate contact.

[0138] The first source / drain contact 170 can be disposed between the first source / drain pattern 150 and the source / drain path pattern 180. The first source / drain contact 170 can connect the first source / drain pattern 150 and the source / drain path pattern 180. The second source / drain contact 270 can be disposed between the second source / drain pattern 250 and the source / drain path pattern 180.

[0139] A gate contact 175 may be disposed between the first gate electrode 120 and the gate path pattern 185. The gate contact 175 may connect the first gate electrode 120 and the gate path pattern 185.

[0140] The source / drain path pattern 180 may have a single-material film structure. The source / drain path pattern 180 may include a metal capable of selective growth on a conductive material. The source / drain path pattern 180 may be formed of a fourth metal. The fourth metal may be different from the third metal included in the second contact metal pattern 173.

[0141] The source / drain path pattern 180 may include, but is not limited to, one of titanium (Ti), molybdenum (Mo), ruthenium (Ru), or cobalt (Co). As an example, the fourth metal may be molybdenum. The source / drain path pattern 180 may be a molybdenum path pattern.

[0142] The resistivity of a molybdenum (Mo) film can vary depending on the material present on its underside.

[0143] exist Figure 5 In the first experimental example (S1), molybdenum is deposited on a metal carbonitride film. For example, the metal carbonitride film in the first experimental example (S1) may include tungsten carbonitride. The second experimental example (S2) involves depositing molybdenum on a metal nitride film. For example, the metal nitride film in the second experimental example (S2) may include titanium nitride. The third experimental example (S3) involves depositing molybdenum on an insulating film. For example, the insulating film in the third experimental example (S3) may include silicon oxide. The fourth experimental example (S4) involves depositing molybdenum on a metal film. For example, the metal film in the fourth experimental example (S4) may include tungsten.

[0144] In the first to fourth experimental examples (S1, S2, S3, and S4), the resistivity of the molybdenum film can decrease as the thickness of the molybdenum film increases. Compared to the other experimental examples (S1, S2, and S3), the molybdenum film deposited on the tungsten film (fourth experimental example S4), despite its thinness, exhibits low resistivity. That is, when a thin molybdenum film is formed on a tungsten film, the molybdenum film can have low resistance despite its thinness. When the molybdenum film is formed on the tungsten film, it is not necessary to increase the thickness of the molybdenum film to reduce resistivity. Since the source / drain path pattern including the molybdenum film is formed on the source / drain contact including the tungsten film, the size of the semiconductor device in the vertical direction (e.g., the third direction DR3) can be reduced. Furthermore, the performance and reliability of the semiconductor device can be improved.

[0145] The gate path pattern 185 may include a gate path barrier film 186 and a gate path fill film 187. The gate path fill film 187 is disposed on the gate path barrier film 186.

[0146] The gate path blocking film 186 may include, for example, but not limited to, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boride (NiB), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), or rhodium (Rh).

[0147] The gate path filling film 187 may include, for example, but not limited to, one of aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn) or molybdenum (Mo).

[0148] The second etch stop film 196 may be disposed between the second interlayer insulating film 191 and the third interlayer insulating film 192. The second etch stop film 196 may extend along the upper surface of the second interlayer insulating film 191.

[0149] The second etch stop film 196 may include a material having etch selectivity relative to the third interlayer insulating film 192. The second etch stop film 196 may include at least one of, for example, silicon nitride, silicon oxynitride, silicon oxycarbonitride, boron silicon nitride, boron silicon oxynitride, silicon oxycarbonitride, aluminum oxide, aluminum nitride, aluminum oxycarbonitride, and combinations thereof. The second etch stop film 196 is shown as a single film, but the embodiments are not limited thereto. Unlike the example shown, the second etch stop film 196 may not be formed.

[0150] Wiring 207 can be disposed inside the third interlayer insulating film 192. Wiring 207 is connected to the source / drain path pattern 180. Wiring 207 is in contact with the source / drain path pattern 180. Wiring 207 is connected to the gate path pattern 185. Wiring 207 is in contact with the gate path pattern 185.

[0151] The wiring 207 may include a wiring barrier film 207A and a wiring filler film 207B. The wiring barrier film 207A may include at least one of the following: tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boride (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), or a two-dimensional material. The wiring filler film 207B may include at least one of the following: aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), or molybdenum (Mo).

[0152] Figure 6 and Figure 7 These are diagrams used to illustrate semiconductor devices according to some embodiments. Figure 8 and Figure 9 These are diagrams used to illustrate semiconductor devices according to some embodiments. Figure 10 and Figure 11 This is a diagram illustrating a semiconductor device according to some embodiments. For ease of explanation, the following description will focus on the use of... Figures 1 to 5 The differences in the content described.

[0153] refer to Figure 6 and Figure 7 In a semiconductor device according to some embodiments, a portion of the first contact metal pattern 172 may extend along the boundary between the second contact metal pattern 173 and the contact pad 157.

[0154] The first contact metal pattern 172 may cover the sidewall of the second contact metal pattern 173. The upper surface 172US of the first contact metal pattern may be bowl-shaped.

[0155] Since a portion of the first contact metal pattern 172 is located between the second contact metal pattern 173 and the contact pad 157, the second contact metal pattern 173 may not contact the contact pad 157.

[0156] The upper surface 170US of the first source / drain contact may be defined by a first contact metal pattern 172 and a second contact metal pattern 173. The second contact metal pattern 173 may define a portion of the upper surface 170US of the first source / drain contact.

[0157] refer to Figure 8 and Figure 9In a semiconductor device according to some embodiments, the first contact metal pattern 172 does not contact the source / drain etch pad 158.

[0158] The first contact metal pattern 172 does not contact the contact pad 157. The lower conductive contact pattern 171 may extend along the boundary between the first contact metal pattern 172 and the contact pad 157.

[0159] The lower conductive contact pattern 171 may extend along the contour of the contact groove 170R. The lower conductive contact pattern 171 may extend along the sidewall 172SW of the first contact metal pattern. The lower conductive contact pattern 171 may contact the sidewall 172SW of the first contact metal pattern. The first contact metal pattern 172 may include an interface that forms a boundary with the lower conductive contact pattern 171. In the portion where the first contact metal pattern 172 and the first source / drain pattern 150 overlap in the first direction DR1 and the second direction DR2, the interface of the first contact metal pattern 172 may be the bottom surface 172BS of the first contact metal pattern.

[0160] The lower conductive contact pattern 171 may extend along the boundary between the second contact metal pattern 173 and the contact pad 157. The second contact metal pattern 173 may contact the lower conductive contact pattern 171. Viewed from a cross-sectional perspective, the second contact metal pattern 173 may be triangular in shape, but the embodiment is not limited to this.

[0161] The lower conductive contact pattern 171 may include at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boride (NiB), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), or rhodium (Rh).

[0162] refer to Figure 10 and Figure 11 In a semiconductor device according to some embodiments, the lower conductive contact pattern 171 may include a first lower conductive contact pad 171A and a second lower conductive contact pad 171B sequentially formed on a first contact silicide film 155.

[0163] The second lower conductive contact pad 171B can be disposed between the first lower conductive contact pad 171A and the first contact metal pattern 172. The first lower conductive contact pad 171A can extend along the contour of the contact groove 170R. The first lower conductive contact pad 171A can contact the first contact silicide film 155. The first lower conductive contact pad 171A can contact the first contact metal pattern 172.

[0164] The second lower conductive contact pad 171B can contact the first lower conductive contact pad 171A. The second lower conductive contact pad 171B can contact the first contact metal pattern 172.

[0165] The first lower conductive contact pad 171A (e.g., lower conductive contact pattern 171) may include at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boride (NiB), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), or rhodium (Rh).

[0166] The second lower conductive contact pad 171B can be formed of a fifth metal. As an example, the fifth metal can be different from the second metal included in the first contact metal pattern 172.

[0167] As another example, the fifth metal may be the same as the second metal included in the first contact metal pattern 172. The method of forming the second lower conductive contact pad 171B may differ from the method of forming the first contact metal pattern 172. Even if the second lower conductive contact pad 171B and the first contact metal pattern 172 include the same metal, the boundary between the second lower conductive contact pad 171B and the first contact metal pattern 172 can be distinguished.

[0168] The fifth metal may include, for example, tungsten (W) or molybdenum (Mo).

[0169] The upper surface 172US of the first contact metal pattern may include a dent region 172US_DT recessed toward the first source / drain pattern 150.

[0170] Figures 12 to 14 These are diagrams used to illustrate semiconductor devices according to some embodiments. Figure 15 and Figure 16 These are diagrams used to illustrate semiconductor devices according to some embodiments. Figure 17 This is a diagram illustrating a semiconductor device according to some embodiments. For ease of explanation, the description and use will be primarily based on... Figures 1 to 5 The differences in the content described.

[0171] refer to Figure 12 In a semiconductor device according to some embodiments, the gate path pattern 185 may be a single-material film structure.

[0172] The gate path pattern 185 may include a metal that can be selectively grown on a conductive material. The gate path pattern 185 may include, but is not limited to, one of titanium (Ti), molybdenum (Mo), ruthenium (Ru), or cobalt (Co).

[0173] refer to Figure 13 In a semiconductor device according to some embodiments, the gate contact 175 may be a single-material film structure.

[0174] The gate contact 175 may include a metal capable of being selectively grown on a conductive material. The gate contact 175 may include, but is not limited to, one of titanium (Ti), molybdenum (Mo), ruthenium (Ru), or cobalt (Co).

[0175] exist Figure 12 and Figure 13 In contrast to the previous example, both the gate contact 175 and the gate path pattern 185 can be a single-material film structure.

[0176] refer to Figure 14 In a semiconductor device according to some embodiments, the gate contact 175 may penetrate the first etch stop film 195 and the gate cover pattern 145.

[0177] The gate contact 175 may be disposed within the gate cover pattern 145 and the second interlayer insulating film 191. The upper surface 175US of the gate contact is higher than the upper surface 145US of the gate cover pattern. A portion of the gate contact 175 protrudes beyond the upper surface 145US of the gate cover pattern.

[0178] Gate contact 175 can be used without a gate path pattern ( Figure 3 In the case of 185), it is connected to the wiring 207.

[0179] refer to Figure 15 and Figure 16 In semiconductor devices according to some embodiments, the source / drain etch pad 158 may not include a contact pad. Figure 2 (157).

[0180] The first contact metal pattern 172 may contact the source / drain etch stop film 156. For example, the sidewall 172SW of the first contact metal pattern may contact the source / drain etch stop film 156. When the source / drain etch stop film 156 is not formed, the sidewall 172SW of the first contact metal pattern may contact the gate structure GS.

[0181] The second contact metal pattern 173 can contact the gate cover pattern 145.

[0182] refer to Figure 17In a semiconductor device according to some embodiments, the gate structure GS may further include a plurality of inner spacers 140ISP disposed between first sheet patterns NS1 adjacent to each other on a third-direction DR3.

[0183] An inner spacer 140ISP is disposed between the inner gate structure INT_GS and the first source / drain pattern 150. Because of the inner spacer 140ISP, the inner gate structure INT_GS does not contact the first source / drain pattern 150.

[0184] The inner spacer 140ISP may include, for example, silicon nitride, silicon oxynitride, silicon oxide, silicon carbonitride, boron silicon nitride, boron silicon oxynitride, silicon carbonitride, or combinations thereof.

[0185] Figures 18 to 21 This is a diagram illustrating a semiconductor device according to some embodiments. For ease of explanation, the description and use will be primarily based on... Figures 1 to 5 The differences in the content explained.

[0186] For reference only. Figure 18 This is an example layout diagram used to illustrate a semiconductor device according to some embodiments. Figure 19 It is along Figure 18 The cross-sectional view taken from AA. Figure 20 and Figure 21 They are along Figure 18 A cross-sectional view of BB.

[0187] refer to Figures 18 to 21 In a semiconductor device according to some embodiments, each of the first active pattern AP1 and the second active pattern AP2 may be a fin-shaped pattern protruding above the upper surface of the field insulating film 105.

[0188] exist Figure 20 In this configuration, both the first active pattern AP1 and the second active pattern AP2 can be positioned within the active region defined by the deep trench DT. The deep trench DT can define the field region positioned between the active regions.

[0189] Although each of two first active patterns AP1 and two second active patterns AP2 is shown in the active region, the embodiment is not limited thereto. The number of first active patterns AP1 and second active patterns AP2 disposed in the active region can be one or more. The first active patterns AP1 and second active patterns AP2 disposed in the active region can be separated by fin-shaped grooves FT extending longitudinally in the first direction DR1, respectively.

[0190] Field insulating film 105 can fill deep trench DT.

[0191] exist Figure 21 In this context, a dummy protruding pattern DPF can be set in the field area that distinguishes the active region. No deep trenches are formed in the field area ( Figure 20 (DT). The upper surface of the dummy protruding pattern DPF is covered by a field insulating film 105.

[0192] Each of the first active pattern AP1 and the second active pattern AP2 may contain, for example, silicon or germanium as an elemental semiconductor material. Furthermore, the first active pattern AP1 and the second active pattern AP2 may contain compound semiconductors, and may contain, for example, group IV-IV compound semiconductors or group III-V compound semiconductors. As an example, the first active pattern AP1 and the second active pattern AP2 may contain the same material. As another example, the first active pattern AP1 may contain a different material than the second active pattern AP2.

[0193] When the first active pattern AP1 is disposed in the PMOS formation region and the second active pattern AP2 is disposed in the NMOS formation region, the first active pattern AP1 is a fin pattern including silicon and germanium, and the second active pattern AP2 may be a fin pattern including silicon, but the embodiments are not limited thereto.

[0194] Gate structure GS does not include internal gate structure ( Figure 2 (INT_GS).

[0195] Figures 22 to 24 These are illustrations used to depict semiconductor devices according to some embodiments. For reference, Figure 22 It is a plan view used to illustrate a semiconductor device according to some embodiments. Figure 23 It is along Figure 22 The cross-sectional view of lines DD and EE. Figure 24 It is along Figure 22 The cross-sectional view taken from the line FF.

[0196] refer to Figures 22 to 24 Logic cells LC can be disposed on substrate 100. Logic cells LC can refer to logic elements that perform specific functions (e.g., inverters, flip-flops, etc.). Logic cells LC may include vertical transistors (Vertical FETs) that constitute logic elements and wiring that connects the vertical transistors to each other.

[0197] The logic cell LC located on the substrate 100 may include a first active region RX1 and a second active region RX2. For example, the first active region RX1 may be a PMOSFET region, and the second active region RX2 may be an NMOSFET region. The first active region RX1 and the second active region RX2 may be defined by a trench TR formed in the upper part of the substrate 100. The first active region RX1 and the second active region RX2 may be spaced apart from each other in a second direction DR2.

[0198] A first lower epitaxial pattern SPO1 can be formed on a first active region RX1, and a second lower epitaxial pattern SPO2 can be formed on a second active region RX2. Viewed from a planar perspective, the first lower epitaxial pattern SPO1 can overlap with the first active region RX1, and the second lower epitaxial pattern SPO2 can overlap with the second active region RX2. The first lower epitaxial pattern SPO1 and the second lower epitaxial pattern SPO2 can be epitaxial patterns formed by a selective epitaxial growth process. The first lower epitaxial pattern SPO1 can be disposed in a first recessed region RS1 of the substrate 100, and the second lower epitaxial pattern SPO2 can be disposed in a second recessed region RS2 of the substrate 100.

[0199] A third active pattern AP3 can be disposed on the first active region RX1, and a fourth active pattern AP4 can be disposed on the second active region RX2. Each of the third active pattern AP3 and the fourth active pattern AP4 can have the form of a vertically projecting fin. Viewed from a planar perspective, each of the third active pattern AP3 and the fourth active pattern AP4 can have the form of a strip extending in the second direction DR2. The third active pattern AP3 can be arranged along the first direction DR1, and the fourth active pattern AP4 can be arranged along the first direction DR1.

[0200] Each third active pattern AP3 may include a first channel pattern CHP1 that protrudes vertically from the first lower epitaxial pattern SpO1 and a first upper epitaxial pattern DOP1 located on the first channel pattern CHP1. Each fourth active pattern AP4 may include a second channel pattern CHP2 that protrudes vertically from the second lower epitaxial pattern SpO2 and a second upper epitaxial pattern DOP2 located on the second channel pattern CHP2.

[0201] A device isolation film ST can be disposed on the substrate 100 to fill the trench TR. The device isolation film ST can cover the upper surface of the first lower epitaxial pattern SPO1 and the upper surface of the second lower epitaxial pattern SPO2. The third active pattern AP3 and the fourth active pattern AP4 can protrude vertically from the device isolation film ST.

[0202] Multiple second gate electrodes 320 extending parallel to each other in the second direction DR2 can be disposed on the element isolation film ST. The second gate electrodes 320 can be arranged along the first direction DR1. The second gate electrodes 320 can surround the first channel pattern CHP1 of the third active pattern AP3 and can surround the second channel pattern CHP2 of the fourth active pattern AP4. For example, the first channel pattern CHP1 of the third active pattern AP3 can have first sidewalls SW1 to fourth sidewalls SW4. The first sidewalls SW1 and second sidewalls SW2 can be opposite each other in the first direction DR1, and the third sidewalls SW3 and fourth sidewalls SW4 can be opposite each other in the second direction DR2. The second gate electrodes 320 can be disposed on the first sidewalls SW1 to fourth sidewalls SW4. In other words, the second gate electrodes 320 can surround the first sidewalls SW1 to fourth sidewalls SW4.

[0203] The second gate insulating film 330 may be located between the second gate electrode 320 and each of the first channel pattern CHP1 and the second channel pattern CHP2. The second gate insulating film 330 may cover the bottom surface of the second gate electrode 320 and the inner sidewall of the second gate electrode 320. For example, the second gate insulating film 330 may directly cover the first sidewall SW1 to the fourth sidewall SW4 of the third active pattern AP3.

[0204] The first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2 can protrude vertically above the second gate electrode 320. The upper surface of the second gate electrode 320 can be lower than the bottom surface of each of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. In other words, each of the third active pattern AP3 and the fourth active pattern AP4 can have a structure that protrudes vertically from the substrate 100 and penetrates the second gate electrode 320.

[0205] A semiconductor device according to some embodiments may include a vertical transistor in which charge carriers move along a third-direction DR3. For example, when a voltage is applied to the second gate electrode 320 to "on" the transistor, charge carriers can move from the lower epitaxial patterns SpO1, SpO2 through the channel patterns CHP1, CHP2 to the upper epitaxial patterns DOP1, DOP2. In a semiconductor device according to some embodiments, the second gate electrode 320 may completely surround the sidewalls SW1 to SW4 of the channel patterns CHP1, CHP2. The transistor according to this disclosure may be a three-dimensional field-effect transistor (e.g., a VFET) with a full-ring gate structure. Because the gate surrounds the channel, the semiconductor device according to some embodiments may have excellent electrical characteristics.

[0206] Spacers 340 covering the second gate electrode 320 and the third active pattern AP3 and the fourth active pattern AP4 can be disposed on the device isolation film ST. Spacers 340 may include silicon nitride or silicon oxynitride. Spacers 340 may include a lower spacer 340LS, an upper spacer 340US, and a second gate spacer 340GS located between the lower spacer 340LS and the upper spacer 340US.

[0207] The lower spacer 340LS can directly cover the upper surface of the device isolation film ST. The second gate electrode 320 can be spaced from the device isolation film ST on the third-direction DR3 by the lower spacer 340LS. The second gate spacer 340GS can cover the upper surface and outer sidewall of each second gate electrode 320. The upper spacer 340 can cover the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. However, the upper spacer 340US can not cover the upper surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2, and can expose the upper surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2.

[0208] A first lower interlayer insulating film 190BP can be disposed on spacer 340. The upper surface of the first lower interlayer insulating film 190BP can be substantially coplanar with the upper surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. A first upper interlayer insulating film 190UP, a first etch stop film 195, a second interlayer insulating film 191, a second etch stop film 196, and a third interlayer insulating film 192 can be sequentially stacked on the first lower interlayer insulating film 190BP. The first lower interlayer insulating film 190BP and the first upper interlayer insulating film 190UP can be included in the first interlayer insulating film 190. The first upper interlayer insulating film 190UP can cover the upper surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2.

[0209] At least one first vertical source / drain contact 370 may be provided, which penetrates the first upper interlayer insulating film 190UP and connects to the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. At least one second vertical source / drain contact 470 may be provided, which penetrates the first interlayer insulating film 190, the lower spacer 340LS, and the element isolation film ST, and connects to the first lower epitaxial pattern SPO1 and the second lower epitaxial pattern SPO2. A vertical gate contact 380 may be provided, which penetrates the first upper interlayer insulating film 190UP, the first lower interlayer insulating film 190BP, and the second gate spacer 340GS, and connects to the second gate electrode 320.

[0210] The first etch stop film 195, the second interlayer insulating film 191, and the second etch stop film 196 can be disposed between the first upper interlayer insulating film 190UP and the third interlayer insulating film 192.

[0211] The source / drain path pattern 180 and the gate path pattern 185 may be disposed within the first etch stop film 195 and the second interlayer insulating film 191. The wiring 207 may be disposed within the third interlayer insulating film 192 and the second etch stop film 196. Although the vertical gate contact 380, the gate path pattern 185, and the wiring 207 are shown as a single film, this is for illustrative purposes only, and the embodiment is not limited thereto.

[0212] The first vertical source / drain contact 370 may include a first vertical lower contact metal pattern 370A and a first vertical upper contact metal pattern 370B. The second vertical source / drain contact 470 may include a second vertical lower contact metal pattern 470A and a second vertical upper contact metal pattern 470B.

[0213] exist Figures 1 to 21 The content of the first contact metal pattern 172 described herein can be applied to each of the first vertical lower contact metal pattern 370A and the second vertical source / drain contact 470. The first vertical upper contact metal pattern 370B and the second vertical upper contact metal pattern 470B can be formed of tungsten. The first vertical upper contact metal pattern 370B and the second vertical upper contact metal pattern 470B can be tungsten contact patterns.

[0214] The first vertical source / drain contact 370 and the second vertical source / drain contact 470 are shown excluding the lower conductive contact pattern (e.g., Figure 2 (171), but the embodiments are not limited thereto.

[0215] Figures 25 to 31 This is an intermediate stage diagram illustrating a method for manufacturing a semiconductor device according to some embodiments.

[0216] refer to Figure 25 A first source / drain pattern 150 can be formed on the first active pattern AP1.

[0217] Source / drain etch stop film 156 and first interlayer insulating film 190 are sequentially formed on the first source / drain pattern 150.

[0218] After the first interlayer insulating film 190 is formed, the gate structure GS can be formed by a replacement metal gate (RMG) process. During the formation of the gate overlay pattern 145, a portion of the source / drain etch stop film 156 can be etched. Therefore, the gate overlay pattern 145 can be formed on the source / drain etch stop film 156, but the embodiments are not limited thereto.

[0219] refer to Figure 25 and Figure 26 Contact holes 170H can be formed in the first interlayer insulating film 190.

[0220] The contact hole 170H can expose the first source / drain pattern 150. During the formation of the contact hole 170H, a portion of the source / drain etch stop film 156 can be removed. The bottom surface of the contact hole 170H can be defined by the first source / drain pattern 150.

[0221] Unlike the example shown, the source / drain etch stop film 156 may not be removed when forming the contact hole 170H. In this case, the bottom surface of the contact hole 170H may be defined by the source / drain etch stop film 156.

[0222] refer to Figure 26 and Figure 27 Contact pads 157 can be formed along the sidewalls of contact hole 170H and the upper surface of gate cover pattern 145.

[0223] More specifically, a pre-contact liner film can be formed along the sidewalls and bottom surface of the contact hole 170H. The pre-contact liner film can also be formed along the upper surface of the gate overlay pattern 145 and the upper surface of the first source / drain pattern 150. For example, but not limited to, the pre-contact liner film can be formed using a chemical vapor deposition (CVD) method. The thickness of the pre-contact liner film can be non-uniform. For example, the thickness of the pre-contact liner film on the upper surface of the first source / drain pattern 150 can be less than the thickness of the pre-contact liner film on the upper surface of the gate overlay pattern 145, but the embodiments are not limited thereto.

[0224] The pre-contact pad film on the bottom surface of the contact hole 170H can be removed using directional etching. This forms the contact pad 157. When removing the pre-contact pad film on the bottom surface of the contact hole 170H, the pre-contact pad film on the upper surface of the gate cover pattern 145 may not be completely removed, but the embodiment is not limited thereto. When the pre-contact pad film on the upper surface of the gate cover pattern 145 is completely removed, the contact pad 157 is not formed on the upper surface of the gate cover pattern 145.

[0225] If the source / drain etch stop film 156 on the upper surface of the first source / drain pattern 150 is not removed before the pre-contact pad film is formed, the source / drain etch stop film 156 on the upper surface of the first source / drain pattern 150 can be removed during the formation of the contact pad 157.

[0226] Next, the contact pad 157 can be used as a mask to remove a portion of the first source / drain pattern 150.

[0227] refer to Figure 28 A first contact silicide film 155 can be formed on the first source / drain pattern 150.

[0228] A first contact silicide film 155 can be formed using a silicide process. The first contact silicide film 155 can define a contact groove 170R.

[0229] Next, a lower conductive contact pattern 171 can be formed on the first contact silicide film 155. The lower conductive contact pattern 171 can be formed in the contact hole 170H. The lower conductive contact pattern 171 can fill at least a portion of the contact groove 170R. More specifically, a pre-lower conductive contact film can be formed in the contact hole 170H. The pre-lower conductive contact film can fill the contact hole 170H. A portion of the pre-lower conductive contact film can be etched to form the lower conductive contact pattern 171.

[0230] refer to Figure 29 A first contact metal pattern 172 can be formed on the lower conductive contact pattern 171.

[0231] The first contact metal pattern 172 can be formed inside the contact hole 170H. For example, the first contact metal pattern 172 can be formed using, for example but not limited to, chemical vapor deposition (CVD) methods. The chemical vapor deposition method can include selective chemical vapor deposition methods.

[0232] refer to Figure 30 A pre-contact metal pattern 173P can be formed on the first contact metal pattern 172.

[0233] The pre-contact metal pattern 173P can fill the remaining portion of the contact hole 170H. The pre-contact metal pattern 173P can be formed on the upper surface of the gate overlay pattern 145. The pre-contact metal pattern 173P can be formed using, but is not limited to, chemical vapor deposition (CVD) or physical vapor deposition (PVD) methods.

[0234] Unlike the example shown, a seed metal pad may be formed along the upper surface of the first contact metal pattern 172, the upper surface of the gate overlay pattern 145, and the sidewall of the contact hole 170H before forming the pre-contact metal pattern 173P. For example, the seed metal pad may contain the metal included in the first contact metal pattern 172.

[0235] refer to Figure 30 and Figure 31 The pre-contact metal pattern 173P located on the upper surface of the gate cover pattern 145 can be removed to form the second contact metal pattern 173.

[0236] Thus, a first source / drain contact 170 can be formed. The upper surface 170US of the first source / drain contact can be coplanar with the upper surface 145US of the gate overlay pattern.

[0237] When forming the second contact metal pattern 173, a portion of the gate cover pattern 145 can also be removed. The thickness of the gate cover pattern 145 can be reduced.

[0238] Next, refer to Figure 2 and Figure 3 The source / drain path pattern 180 and wiring 207 can be formed. As an example, the gate contact 175 can be formed before the formation of the first etch stop film 195. As another example, the gate contact 175 can be formed after the formation of the first etch stop film 195 and the second interlayer insulating film 191.

[0239] Figures 32 to 35 This is an intermediate stage diagram illustrating a method for manufacturing a semiconductor device according to some embodiments. Figure 32 It can be in Figure 27 The subsequent manufacturing process.

[0240] refer to Figure 32 A first contact silicide film 155 can be formed on the first source / drain pattern 150.

[0241] Subsequently, a pre-conductive contact film 171P can be formed on the first contact silicide film 155. The pre-conductive contact film 171P can be formed along the contour of the contact groove 170R, the sidewall of the contact hole 170H, and the upper surface of the gate cover pattern 145.

[0242] refer to Figure 33 A first contact metal pattern 172 can be formed on the pre-conductive contact film 171P.

[0243] For example, the first contact metal pattern 172 can be formed using a deposition-etch-deposition method. When the first contact metal pattern 172 is formed of molybdenum (Mo), molybdenum pentachloride (MoCl5) can be used as a precursor. In the deposition-etch-deposition method, a portion of the first contact metal pattern 172 can be etched simultaneously with its formation. Using this method, the thickness of the first contact metal pattern 172 formed at the lower part of the contact hole 170H can be greater than the thickness of the first contact metal pattern 172 formed at the upper part of the contact hole 170H or on the upper surface of the gate cover pattern 145. By repeating the above process, the formation of the first contact metal pattern 172 on the upper surface of the gate cover pattern 145 can be prevented.

[0244] refer to Figure 34 A pre-contact metal pattern 173P can be formed on the first contact metal pattern 172.

[0245] The pre-contact metal pattern 173P can fill the remaining portion of the contact hole 170H. The pre-contact metal pattern 173P can be formed on the upper surface of the gate overlay pattern 145.

[0246] refer to Figure 34 and Figure 35 The pre-contact metal pattern 173P and the pre-lower conductive contact film 171P located on the upper surface of the gate cover pattern 145 are removed, thereby forming the lower conductive contact pattern 171 and the second contact metal pattern 173.

[0247] Figures 36 to 40 This is an intermediate stage diagram illustrating a method for manufacturing a semiconductor device according to some embodiments. Figure 36 It can be in Figure 27 The subsequent manufacturing process.

[0248] refer to Figure 36 A first contact silicide film 155 can be formed on the first source / drain pattern 150.

[0249] Next, a first pre-under conductive contact pad 171A_P can be formed on the first contact silicide film 155. The first pre-under conductive contact pad 171A_P can be formed along the contour of the contact groove 170R, the sidewall of the contact hole 170H, and the upper surface of the gate cover pattern 145.

[0250] The second pre-under conductive contact pad 171B_P can be formed on the first pre-under conductive contact pad 171A_P. The second pre-under conductive contact pad 171B_P can fill the contact hole 170H. The second pre-under conductive contact pad 171B_P can be formed on the upper surface of the gate overlay pattern 145. The second pre-under conductive contact pad 171B_P may include a pad gap 171B_PAG. The pad gap 171B_PAG can be formed during the formation of the second pre-under conductive contact pad 171B_P.

[0251] refer to Figure 36 and Figure 37 Anisotropic etching can be used to remove a portion of the first pre-under conductive contact pad 171A_P and a portion of the second pre-under conductive contact pad 171B_P.

[0252] Thus, a first lower conductive contact pad 171A and a second lower conductive contact pad 171B can be formed.

[0253] The lower conductive contact pattern 171, including the first lower conductive contact pad 171A and the second lower conductive contact pad 171B, can be formed inside the contact groove 170R.

[0254] refer to Figure 38A first contact metal pattern 172 can be formed on the first lower conductive contact pad 171A and the second lower conductive contact pad 171B.

[0255] The first contact metal pattern 172 can be formed, for example, using a selective chemical vapor deposition method.

[0256] refer to Figure 39 A pre-contact metal pattern 173P can be formed on the first contact metal pattern 172.

[0257] refer to Figure 39 and Figure 40 The pre-contact metal pattern 173P located on the upper surface of the gate cover pattern 145 can be removed to form the second contact metal pattern 173.

[0258] In summarizing the detailed description, those skilled in the art will understand that various changes and modifications can be made to the preferred embodiments without substantially departing from the principles of this disclosure. Therefore, the preferred embodiments disclosed herein are for general and descriptive purposes only and not for limiting purposes.

Claims

1. A semiconductor device, the semiconductor device comprising: A gate structure disposed on an active pattern and including a gate electrode and a gate cover pattern disposed on the gate electrode; Source / drain pattern, wherein the source / drain pattern is disposed on at least one side of the gate structure; A contact silicide film is disposed on the source / drain pattern and defines a contact groove; Source / drain contacts that fill the contact grooves and are connected to the source / drain pattern; An etch stop film is disposed on the upper surface of the gate cover pattern and the upper surface of the source / drain contact; as well as A first via pattern, which penetrates the etch stop film, connects to the source / drain contact, and is formed of a first metal. The source / drain contact includes: a lower conductive contact pattern, a first contact metal pattern formed of a second metal, and a second contact metal pattern formed of a third metal. The first contact metal pattern and the second contact metal pattern are disposed on the lower conductive contact pattern. The third metal is different from the first metal and the second metal, and The second contact metal pattern is disposed between the first contact metal pattern and the first passage pattern, and is in contact with the first passage pattern.

2. The semiconductor device according to claim 1, further comprising: Source / drain etch pads extend along the sidewalls of the gate structure. The first contact metal pattern is in contact with the source / drain etched pad.

3. The semiconductor device according to claim 2, in, The lower conductive contact pattern is formed of a fourth metal and is in contact with the contact silicide film.

4. The semiconductor device according to claim 2, in, The lower conductive contact pattern includes: a first lower conductive contact pad in contact with the contact silicide film, and a second lower conductive contact pad disposed between the first lower conductive contact pad and the first contact metal pattern. The second lower conductive contact pad is formed of a fifth metal and is in contact with the first contact metal pattern.

5. The semiconductor device according to claim 1, in, The first contact metal pattern includes a sidewall facing the gate electrode, and The lower conductive contact pattern extends along the contour of the contact groove and the sidewall of the first contact metal pattern.

6. The semiconductor device according to claim 1, in, Each of the first metal and the second metal is molybdenum.

7. The semiconductor device according to claim 6, in, The third metal is tungsten.

8. The semiconductor device according to claim 1, in, The second contact metal pattern includes at least a portion of the upper surface of the source / drain contact.

9. The semiconductor device according to claim 1, further comprising: A gate contact that penetrates the etch stop film and the gate cover pattern and is connected to the gate electrode.

10. The semiconductor device of claim 1, further comprising: A gate contact, wherein the gate contact is disposed within the gate cover pattern; as well as A second path pattern, which penetrates the etch stop film and connects to the gate contact.

11. The semiconductor device according to claim 1, in, The active pattern includes a lower pattern and a sheet-like pattern located on the lower pattern, and The gate electrode surrounds the sheet-like pattern.

12. A semiconductor device, the semiconductor device comprising: A gate structure disposed on an active pattern and including a gate electrode and a gate cover pattern disposed on the gate electrode; Source / drain pattern, wherein the source / drain pattern is disposed on at least one side of the gate structure; Source / drain contacts are disposed on the source / drain pattern and connected to the source / drain pattern; as well as A molybdenum path pattern is disposed on the source / drain contact and contacts the upper surface of the source / drain contact. The source / drain contact includes: a lower conductive contact pattern, a contact metal pattern formed of a first metal, and a tungsten contact pattern. The contact metal pattern is disposed between the tungsten contact pattern and the lower conductive contact pattern, and At least a portion of the upper surface of the source / drain contact is defined by the tungsten contact pattern.

13. The semiconductor device according to claim 12, in, The first metal is molybdenum.

14. The semiconductor device of claim 12, further comprising: Source / drain etch pads extend along the sidewalls of the gate structure. The contact metal pattern is in contact with the source / drain etched pad.

15. The semiconductor device of claim 14, further comprising: A contact silicide film is disposed between the source / drain contact and the source / drain pattern. The lower conductive contact pattern is formed of a second metal different from the first metal and is in contact with the contact silicide film.

16. The semiconductor device of claim 14, further comprising: A contact silicide film is disposed between the source / drain contact and the source / drain pattern. The lower conductive contact pattern includes: a first lower conductive contact pad in contact with the contact silicide film, and a second lower conductive contact pad disposed between the first lower conductive contact pad and the contact metal pattern. The second lower conductive contact pad is formed of a third metal and contacts the contact metal pattern. The third metal is either tungsten or molybdenum.

17. The semiconductor device of claim 12, further comprising: A contact silicide film is disposed between the source / drain contact and the source / drain pattern, and defines a contact groove. The contact metal pattern includes a sidewall facing the gate electrode. The lower conductive contact pattern extends along the contour of the contact groove and the sidewall of the contact metal pattern.

18. A semiconductor device, the semiconductor device comprising: An active pattern, the active pattern comprising a lower pattern and a sheet pattern located on the lower pattern; A gate structure located on the active pattern and including a gate electrode and a gate cover pattern, the gate electrode surrounding the sheet pattern and the gate cover pattern disposed on the gate electrode; Source / drain pattern, wherein the source / drain pattern is disposed on at least one side of the gate structure; Source / drain contacts are located on and connected to the source / drain pattern. An etch stop film is disposed on the upper surface of the gate cover pattern and the upper surface of the source / drain contact; as well as A molybdenum pathway pattern that penetrates the etch stop film and contacts the upper surface of the source / drain electrode. The source / drain contacts include: a lower conductive contact pattern, a molybdenum contact pattern, and a tungsten contact pattern. At least a portion of the upper surface of the source / drain contact is defined by the tungsten contact pattern.

19. The semiconductor device of claim 18, further comprising: Source / drain etch pads extend along the sidewalls of the gate structure. The molybdenum contact pattern is in contact with the source / drain etched pad.

20. The semiconductor device of claim 18, further comprising: A contact silicide film is disposed between the source / drain contact and the source / drain pattern. The lower conductive contact pattern is formed of tungsten and is in contact with the contact silicide film.

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