Method of inspecting display device and electronic device

Abstract

A method of inspecting a display device and an electronic device are provided. The method includes: supplying different voltages to gate electrodes of driving transistors of pixels for different frames; and measuring an amount of current flowing through the driving transistor while allowing a switching transistor of the pixel connected between the data line and a first electrode of the driving transistor to be turned on during a partial period of each frame, a diode transistor between the gate electrode of the pixel and the second electrode of the driving transistor is set to be in an off state.

Description

Methods for inspecting display devices and electronic devices

[0001] This application claims priority to Korean Patent Application No. 10-2024-0149690, filed on October 29, 2024, and all benefits derived therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure generally relates to display devices and methods for inspecting display devices, as well as electronic devices. Background Technology

[0003] With the development of information technology, display devices, as the connection medium between users and information, are becoming increasingly important. Consequently, display devices such as liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs) are being used more and more frequently.

[0004] The inspection process for checking whether pixels are abnormal is included in the manufacturing process of the display device. A method is desired that can reliably and accurately detect pixel abnormalities during the inspection process. Summary of the Invention

[0005] The embodiments provide a display device in which pixel abnormalities can be detected reliably and accurately, a method for inspecting the display device, and an electronic device.

[0006] According to an aspect of this disclosure, a method for inspecting a display device is provided, wherein the display device includes pixels, each of the pixels including: a first transistor including a gate electrode connected to a first node, a first electrode connected to a first power line via a second node, and a second electrode connected to a third node; a second transistor connected between a data line and a second node, the second transistor including a gate electrode connected to a first scan line; a third transistor connected between the first node and the third node, the third transistor including a gate electrode connected to a second scan line; a fourth transistor connected between the first node and the second power line, the fourth transistor including a gate electrode connected to the third scan line; a fifth transistor connected between the third node and the third power line, the fifth transistor including a gate electrode connected to the fourth scan line; and a sixth transistor connected between the second node and the fourth power line, the sixth transistor including a gate electrode connected to the fourth scan line, and the method includes: during a pixel inspection process, supplying a first voltage to the data line, the first power line, and the fourth power line; supplying a second voltage to the third power line; supplying a voltage reduced from the third voltage to the fourth voltage to the second power line; and supplying a gate cutoff voltage to the second scan line, such that the third transistor is turned off.

[0007] The first voltage can be 0 volts (V).

[0008] The second voltage can be a lower voltage than the first voltage.

[0009] The third voltage can be a higher voltage than the first voltage, and the fourth voltage can be a lower voltage than the second voltage.

[0010] The voltage supplied to the second power line can be reduced by a specific voltage for each frame.

[0011] Each of the pixels may further include: a seventh transistor connected between the first power line and the second node, the seventh transistor including a gate electrode connected to the emitter control line; and an eighth transistor connected between the third node and the fifth transistor, the eighth transistor including a gate electrode connected to the emitter control line.

[0012] The method may further include: during the inspection process, supplying an enabling first scan signal to a first scan line, causing a second transistor to be turned on at least once in a frame period; and supplying a gate turn-on voltage to a third scan line, causing a fourth transistor to be turned on.

[0013] The method may further include: supplying an enable transmit control signal to the transmit control line during a portion of the frame time period to overlap with the enable first scan signal in time, such that the seventh transistor and the eighth transistor are turned on; and supplying a disable transmit control signal to the transmit control line during the remaining portion of the frame time period, such that the seventh transistor and the eighth transistor are turned off.

[0014] The remaining time period can be 95% to 99% of the frame time period.

[0015] The method may further include: during the aforementioned partial time period, supplying an enabling fourth scan signal to the fourth scan line to turn on the sixth transistor; and during the aforementioned remaining time period, supplying a disabling fourth scan signal to the fourth scan line to turn off the sixth transistor.

[0016] A first voltage can be supplied to a first power line via a first resistor. A first voltage can be supplied to a fourth power line via a second resistor.

[0017] The first resistor and the second resistor can each have a resistance of 100 ohms. Up to 100 megaohms The resistance value.

[0018] According to another aspect of this disclosure, a method for inspecting a display device including pixels is provided, the method comprising: supplying different voltages to the gate electrode of a driving transistor of a pixel for different frames; and measuring the amount of current flowing through the driving transistor while a switching transistor of the pixel connected between a data line and a first electrode of the driving transistor is turned on during a portion of a time period of each frame, and setting a diode transistor of the pixel located between the gate electrode of the driving transistor and a second electrode of the driving transistor to a cut-off state.

[0019] The first voltage can be supplied to the first power supply line and the bias power supply line, which are electrically connected to the first electrode of the driving transistor.

[0020] The first voltage can then be supplied to the data line.

[0021] A first voltage can be supplied to a first power supply line via a first resistor. A first voltage can also be supplied to a bias power supply line via a second resistor.

[0022] The first resistor and the second resistor can each have their own characteristics. to The resistance value.

[0023] According to another aspect of this disclosure, a display device including pixel units is provided, the pixel units including pixels for displaying images and test pixels for not displaying images. The test pixels include: a first transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a storage capacitor connected between a first power line and the first node; a second transistor connected between a data line and the second node, the second transistor including a gate electrode connected to a first scan line; a third transistor connected between the first node and the third node, the third transistor including a gate electrode connected to a second scan line; a fourth transistor connected between the first node and the second power line, the fourth transistor including a gate electrode connected to the third scan line; a fifth transistor connected between the third node and the third power line, the fifth transistor including a gate electrode connected to the fourth scan line; a sixth transistor including a second electrode connected to the second node and a gate electrode connected to the fourth scan line; a seventh transistor including a second electrode connected to the second node and a gate electrode connected to an emission control line; and an eighth transistor connected between the third node and the fifth transistor, the eighth transistor including a gate electrode connected to the emission control line, and the first electrode of the seventh transistor is not electrically connected to the first power line.

[0024] The first electrode of the sixth transistor may not be electrically connected to a separate power supply line.

[0025] According to another aspect of this disclosure, an electronic device is provided, comprising a display panel including pixels for displaying images and test pixels for not displaying images. The test pixels include: a first transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a storage capacitor connected between a first power line and the first node; a second transistor connected between a data line and the second node, the second transistor including a gate electrode connected to a first scan line; a third transistor connected between the first node and the third node, the third transistor including a gate electrode connected to a second scan line; a fourth transistor connected between the first node and the second power line, the fourth transistor including a gate electrode connected to the third scan line; a fifth transistor connected between the third node and the third power line, the fifth transistor including a gate electrode connected to the fourth scan line; a sixth transistor including a second electrode connected to the second node and a gate electrode connected to the fourth scan line; a seventh transistor including a second electrode connected to the second node and a gate electrode connected to an emission control line; and an eighth transistor connected between the third node and the fifth transistor, the eighth transistor including a gate electrode connected to the emission control line, and the first electrode of the seventh transistor is not electrically connected to the first power line. Attached Figure Description

[0026] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, exemplary embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0027] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as "between" two elements, the element may be the only element between the two elements, or there may be one or more intervening elements. The same reference numerals always refer to the same elements.

[0028] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0029] Figure 2 is a diagram illustrating an embodiment of the scan driver and transmit driver shown in Figure 1.

[0030] Figure 3 is a diagram illustrating pixels according to an embodiment of the present disclosure.

[0031] Figure 4 is a waveform diagram illustrating an embodiment of a method for driving the pixels shown in Figure 3 during a display scan period.

[0032] Figure 5 is a waveform diagram illustrating an embodiment of a method for driving the pixel shown in Figure 3 during a self-scanning period.

[0033] Figures 6 and 7 are diagrams illustrating embodiments of signals supplied during valid and blank periods.

[0034] Figure 8 is a diagram illustrating an embodiment of the voltage supplied to the pixel during the pixel inspection process.

[0035] Figures 9A and 9B are diagrams showing the drive waveforms supplied to the pixels during the inspection process.

[0036] Figure 10 shows an example of the transmission control signal supplied during the inspection period.

[0037] Figure 11 is a graph showing the characteristic curve of the first transistor detected during the inspection process.

[0038] Figure 12 is a diagram illustrating an embodiment in which voltage is supplied to the pixel during the pixel inspection process.

[0039] Figure 13 is a graph showing the characteristic curve of the first transistor generated during the inspection process when the voltage is supplied via the resistor shown in Figure 12.

[0040] Figure 14 is a diagram showing test pixels according to an embodiment of the present disclosure.

[0041] Figure 15 is a diagram illustrating an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0042] In the following description, exemplary embodiments are described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily practice this disclosure. This disclosure may be implemented in various different forms and is not limited to the exemplary embodiments described herein.

[0043] Parts irrelevant to the description will be omitted to clearly describe this disclosure, and throughout the specification, the same or similar constituent elements will be indicated by the same reference numerals. Therefore, the same reference numerals may be used in different figures to identify the same or similar elements.

[0044] In the specification, the expression "equal" can mean "substantially equal." That is, it can mean equality to a degree that can be understood by a person skilled in the art. Other expressions may be in which "substantially" is omitted.

[0045] Some embodiments are described with respect to functional blocks, units, and / or modules and are illustrated in the accompanying drawings. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by logic circuitry, individual components, microprocessors, hardwired circuitry, memory elements, wire connections, and other electronic circuitry. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case of blocks, units, and / or modules implemented by microprocessors or other similar hardware, the blocks, units, and / or modules are programmed and controlled using software to perform the various functions discussed in this disclosure and may optionally be driven by firmware and / or software. Additionally, each block, each unit, and / or each module may be implemented by dedicated hardware, or by a combination of dedicated hardware for performing some functions of the block, unit, and / or module and a processor (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions of the block, unit, and / or module. In some embodiments, blocks, units, and / or modules may be physically separated into two or more separate blocks, two or more separate units, and / or two or more separate modules without departing from the scope of this disclosure. Furthermore, in some embodiments, blocks, units, and / or modules may be physically combined into more complex blocks, more complex units, and / or more complex modules without departing from the scope of this disclosure.

[0046] The term "connection" between two components can include both electrical and physical connections, but this disclosure is not necessarily limited to this. For example, the term "connection" used in circuit diagrams can mean an electrical connection, and the term "connection" used in cross-sectional and plan views can mean a physical connection. Similarly, it will be understood that when an element is referred to as being "connected to" another element, the element may be directly connected to the other element, or an intermediary element may exist between the element and the other element. Conversely, when an element is referred to as being "directly connected to" another element, there is no intermediary element.

[0047] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, the “first” element discussed below may also be referred to as the “second” element without departing from the teachings of this disclosure.

[0048] This disclosure is not limited to the embodiments disclosed below, and can be implemented in various forms. Each of the embodiments disclosed below can be embodied independently or in combination with at least one other embodiment.

[0049] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a,” “the,” and “at least one” do not indicate a limitation on quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. For example, “element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” should not be construed as limited to “a.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” or “containing” and / or “having” indicate the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0050] FIG1 is a diagram illustrating a display device according to an embodiment of the present disclosure. FIG2 is a diagram illustrating an embodiment of the scan driver and transmit driver shown in FIG1.

[0051] Referring to FIG1, a display device 100 according to an embodiment of the present disclosure may include a pixel unit 110 (or a display panel), a timing controller 120, a scan driver 130, a data driver 140, a transmit driver 150, and a power supply 160.

[0052] The display device 100 can display images at various image refresh rates (or drive frequencies or screen refresh rates) depending on the driving conditions. Image refresh rate refers to the frequency at which data signals are written to the driving transistor of pixel PX (i.e., the first transistor M1 in Figures 3, 8, 12, and 14). For example, image refresh rate can also be called screen scan rate or screen refresh rate, and can represent the number of times the displayed image is reproduced per second.

[0053] In an embodiment, the output frequency of the data driver 140 and / or the output frequency of the first scan driver 132, which outputs a first scan signal (or writes a scan signal) for a horizontal line (e.g., pixels PX connected to the same scan line can be classified as a single horizontal line (or pixel row)), can be determined in relation to the image refresh rate. For example, the image refresh rate used to drive moving images can be a frequency of approximately 60 Hz or higher (e.g., 120 Hz, 240 Hz, or 360 Hz, etc.).

[0054] For example, the display device 100 can display images corresponding to various image refresh rates from 1Hz to 360Hz. However, this is merely illustrative, and the display device 100 can also display images at image refresh rates of 360Hz or higher (e.g., 480Hz).

[0055] Pixel unit 110 may include pixels PX (n, m and o are natural numbers greater than 2) connected to first scan lines SL11, SL12, ... and SL1n, second scan lines SL21, SL22, ... and SL2n, third scan lines SL31, SL32, ... and SL3n, fourth scan lines SL41, SL42, ... and SL4n, data lines DL1, DL2, ... and DLm, transmit control lines EL1, EL2, ... and ELo, and power lines PL1, PL2, PL3, PL4 and PL5.

[0056] In the example, a pixel PXij located on the j-th vertical line (or pixel column) of the i-th horizontal line (or pixel row) (see Figure 3) can be connected to the i-th first scan line SL1i (see Figure 3), the i-th second scan line SL2i (see Figure 3), the i-th third scan line SL3i (see Figure 3), the i-th fourth scan line SL4i (see Figure 3), the k-th emission control line ELk (see Figure 3), and the j-th data line DLj (see Figure 3) (i is a natural number greater than 2 and less than n, j is a natural number greater than 2 and less than m, and k is a natural number greater than 2 and less than 0). Here, k can be a number equal to or less than i. In the example, if each of the emission control lines EL1 to ELo is connected to a pixel PX located on a single horizontal line, k and i can be the same number. In the example, if each of the emission control lines EL1 to ELo is connected to a pixel PX located on two or more horizontal lines, k can be a number less than i.

[0057] With the first scan signal enabled and supplied to the first scan lines SL11 to SL1n, pixels PX can be selected on a horizontal line basis. Pixels PX selected by enabling the first scan signal can be supplied with data signals from data lines (any one of data lines DL1 to DLm) connected to the selected pixel PX. Pixels PX supplied with data signals can generate light with brightness corresponding to the voltage of the data signal.

[0058] Scan driver 130 can receive scan drive signal SCS from timing controller 120. A clock signal for driving scan driver 130 and at least one scan start signal can be included in scan drive signal SCS. Scan driver 130 can generate enable first scan signal, enable second scan signal, enable third scan signal and enable fourth scan signal by shifting the scan start signal in correspondence with the clock signal.

[0059] Therefore, as shown in Figure 2, the scan driver 130 may include a first scan driver 132, a second scan driver 134, a third scan driver 136, and a fourth scan driver 138. Depending on the design, at least some of the scan drivers 132, 134, 136, and 138 may be integrated into a single drive circuit or a single module, etc.

[0060] The first scan driver 132 can receive a first scan start signal FLM1 and can generate an enable first scan signal by shifting the first scan start signal FLM1 in accordance with a clock signal. The first scan driver 132 can sequentially supply the enable first scan signal to the first scan lines SL11 to SL1n. In an embodiment, the first scan driver 132 can supply the enable first scan signal during the display scan period of a frame.

[0061] The second scan driver 134 can receive the second scan start signal FLM2 and can generate an enable second scan signal by shifting the second scan start signal FLM2 in accordance with a clock signal. The second scan driver 134 can sequentially supply the enable second scan signal to the second scan lines SL21 to SL2n. The second scan driver 134 can supply the enable second scan signal during the display scan period of a frame.

[0062] The third scan driver 136 can receive a third scan start signal FLM3 and can generate an enable third scan signal by shifting the third scan start signal FLM3 in accordance with a clock signal. The third scan driver 136 can sequentially supply the enable third scan signal to the third scan lines SL31 to SL3n. The third scan driver 136 can supply the enable third scan signal during the display scan period of a frame.

[0063] The fourth scan driver 138 can receive the fourth scan start signal FLM4 and can generate an enable fourth scan signal by shifting the fourth scan start signal FLM4 in accordance with a clock signal. The fourth scan driver 138 can sequentially supply the enable fourth scan signal to the fourth scan lines SL41 to SL4n.

[0064] In an embodiment, the fourth scan driver 138 may supply an enabling fourth scan signal during both the display scan period and the self-scan period of a frame. For example, the fourth scan driver 138 may perform one scan during the display scan period (i.e., supply at least one enabling fourth scan signal) and may perform at least one scan during the self-scan period depending on the image refresh rate. When the image refresh rate is reduced (i.e., when the frame length is increased), the number of times the operation of supplying the enabling fourth scan signal by the fourth scan driver 138 to each of the fourth scan lines SL41 to SL4n is repeated during the frame period may be increased.

[0065] The enable first scan signal, enable second scan signal, enable third scan signal, and enable fourth scan signal can be set to gate conduction voltages, so that the transistors included in the pixel PX can be turned on.

[0066] In the example, the enable first scan signal GW and enable fourth scan signal GB supplied to the P-type transistor shown in Figure 3 can be set to a logic low level. In the embodiment, the enable second scan signal GC and enable third scan signal GI supplied to the N-type transistor can be set to a logic high level.

[0067] Figure 2 shows that the first scan driver 132, the second scan driver 134, the third scan driver 136, and the fourth scan driver 138 are connected to the first scan line SL1, the second scan line SL2, the third scan line SL3, and the fourth scan line SL4, respectively. However, embodiments of this disclosure are not limited thereto. In another example, at least two of the first scan line SL1, the second scan line SL2, the third scan line SL3, and the fourth scan line SL4 (i.e., at least two of SL1, SL2, SL3, and SL4) can be driven by a single scan driver.

[0068] Data driver 140 can receive output data Dout and data drive signal DCS from timing controller 120. Data drive signal DCS may include sampling signals and / or timing signals for driving data driver 140. Data driver 140 can generate a data signal based on data drive signal DCS and output data Dout. In this example, data driver 140 can generate an analog data signal based on the grayscale of output data Dout. Data driver 140 can supply data signals in horizontal time intervals.

[0069] Transmit driver 150 can receive transmit drive signal ECS from timing controller 120. Transmit start signal and clock signal used to drive transmit driver 150 can be included in transmit drive signal ECS. Transmit driver 150 can generate disabled transmit control signal EM by shifting the transmit start signal in accordance with the clock signal (see Figure 3).

[0070] As shown in Figure 2, the transmit driver 150 can receive a transmit start signal EFLM and can generate a disabled transmit control signal EM by shifting the transmit start signal EFLM in accordance with a clock signal. The transmit driver 150 can sequentially supply the disabled transmit control signal EM to the transmit control lines EL1 to ELo. The disabled transmit control signal EM can be set to a gate cutoff voltage, such that the transistors included in the pixel PX can be turned off. In the example, the disabled transmit control signal EM supplied to the P-type transistor shown in Figure 3 can be set to a logic high level voltage.

[0071] In an embodiment, the transmit driver 150 can supply the disabled transmit control signal EM during both the display scan period and the self-scan period of a frame. For example, the transmit driver 150 can perform one scan during the display scan period and at least one scan during the self-scan period depending on the image refresh rate. When the image refresh rate is reduced (i.e., when the frame length is longer), the number of times the operation of supplying the disabled transmit control signal EM to each of the transmit control lines EL1 to ELo by the transmit driver 150 during the frame period can be increased.

[0072] The timing controller 120 can receive input data Din and timing control signal TCS from the host system via an interface. In this example, the timing controller 120 can receive input data Din and timing control signal TCS from at least one of the graphics processing unit (GPU), central processing unit (CPU), and application processor (AP) included in the host system. Various signals, including clock signals, can be included in the timing control signal TCS.

[0073] The timing controller 120 can generate a scan drive signal SCS, a data drive signal DCS, and a transmit drive signal ECS based on the timing control signal TCS. The scan drive signal SCS, the data drive signal DCS, and the transmit drive signal ECS can be supplied to the scan driver 130, the data driver 140, and the transmit driver 150, respectively.

[0074] The timing controller 120 can rearrange the input data Din to suit the specifications of the display device 100. Furthermore, the timing controller 120 can generate output data Dout by correcting the input data Din, and can supply the output data Dout to the data driver 140. In an embodiment, the timing controller 120 can correct the input data Din in correspondence with optical measurement results measured during the manufacturing process.

[0075] Power supply 160 can generate various power supplies for driving display device 100. In this example, power supply 160 can generate a first driving power supply VDD, a second driving power supply VSS, a first initialization power supply Vint1, a second initialization power supply Vint2, and a bias power supply Vbias.

[0076] The first driving power supply VDD can be a power supply that supplies driving current to pixel PX. The second driving power supply VSS can be a power supply that receives driving current from pixel PX. During the period when pixel PX is set to be in the emission state, the first driving power supply VDD can be set to a voltage higher than that of the second driving power supply VSS.

[0077] The first initialization power supply Vint1 can be a power supply used to initialize the gate electrode of the driving transistor (i.e., the first transistor M1 in Figures 3, 8, 12, and 14) included in each pixel PX. The first initialization power supply Vint1 can be set to a voltage lower than the voltage of the data signal. The second initialization power supply Vint2 can be a power supply used to initialize the first electrode (or anode electrode) of the light-emitting element LD (see Figure 3) included in each pixel PX. The second initialization power supply Vint2 can be set to the voltage at which the light-emitting element LD is turned off. The bias power supply Vbias can be a power supply used to apply a conduction bias voltage to the driving transistor (i.e., the first transistor M1 in Figures 3, 8, 12, and 14) included in each pixel PX.

[0078] The first driving power supply VDD generated by power supply 160 can be supplied to the first power line PL1, the second driving power supply VSS generated by power supply 160 can be supplied to the fifth power line PL5, the first initialization power supply Vint1 generated by power supply 160 can be supplied to the second power line PL2, the second initialization power supply Vint2 generated by power supply 160 can be supplied to the third power line PL3, and the bias power supply Vbias generated by power supply 160 can be supplied to the fourth power line PL4. The first power line PL1, the second power line PL2, the third power line PL3, the fourth power line PL4, and the fifth power line PL5 can be connected together to each pixel PX, but the embodiments of this disclosure are not limited thereto.

[0079] In one embodiment, the first power line PL1 can be configured with multiple power lines, and these multiple power lines can be connected to different pixels PX. In another embodiment, the second power line PL2 can be configured with multiple power lines, and these multiple power lines can be connected to different pixels PX. In another embodiment, the third power line PL3 can be configured with multiple power lines, and these multiple power lines can be connected to different pixels PX. In another embodiment, the fourth power line PL4 can be configured with multiple power lines, and these multiple power lines can be connected to different pixels PX. In another embodiment, the fifth power line PL5 can be configured with multiple power lines, and these multiple power lines can be connected to different pixels PX. For example, in an embodiment of this disclosure, each pixel PX can be connected to any one of the multiple power lines constituting the first power line PL1, any one of the multiple power lines constituting the second power line PL2, any one of the multiple power lines constituting the third power line PL3, any one of the multiple power lines constituting the fourth power line PL4, and any one of the multiple power lines constituting the fifth power line PL5.

[0080] In embodiments of this disclosure, the display device 100 may include a flat panel display device, a curved display device in which a portion of the display unit 110 is bent, a flexible display device in which a portion of the display unit 110 is folded or bent, and a retractable display device in which a portion of the display unit 110 is expanded / contracted.

[0081] In embodiments of this disclosure, the display device 100 is a device for displaying moving or still images and may be included in portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs). In embodiments of this disclosure, the display device 100 may be included in electronic devices such as televisions, laptop computers, monitors, billboards, and Internet of Things (IoT) devices.

[0082] Figure 3 is a diagram illustrating pixels according to an embodiment of the present disclosure. In Figure 3, pixels located on the i-th horizontal line and the j-th vertical line will be shown.

[0083] Referring to FIG3, according to embodiments of the present disclosure, pixel PXij can be connected to corresponding signal lines SL1i, SL2i, SL3, SL4i, ELk, and DLj. For example, pixel PXij can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th third scan line SL3i, the i-th fourth scan line SL4i, the k-th transmit control line ELk, and the j-th data line DLj. In embodiments, pixel PXij can be further connected to the first power line PL1, the second power line PL2, the third power line PL3, the fourth power line PL4, and the fifth power line PL5.

[0084] According to embodiments of the present disclosure, a pixel PXij may include a light-emitting element LD and a pixel circuit for controlling the amount of current supplied to the light-emitting element LD.

[0085] The light-emitting element (LD) can be connected between the first power line PL1 and the fifth power line PL5. In the example, the first electrode (or anode electrode) of the LD can be electrically connected to the first power line PL1 via the eighth transistor M8, the third node N3, the first transistor M1, the second node N2, and the seventh transistor M7, and the second electrode (or cathode electrode) of the LD can be electrically connected to the fifth power line PL5. The LD can generate light with a brightness corresponding to the amount of current supplied from the first power line PL1 to the fifth power line PL5 via the pixel circuit.

[0086] The light-emitting element LD can be selected as an organic light-emitting diode. Alternatively, the light-emitting element LD can be selected as an inorganic light-emitting diode such as a micro light-emitting diode (LED) or a quantum dot light-emitting diode. Furthermore, the light-emitting element LD can be a device composed of a combination of organic and inorganic materials. Figure 3 shows a pixel PXij comprising a single light-emitting element LD. However, in another embodiment, the pixel PXij can comprise multiple light-emitting elements LD, and these multiple light-emitting elements LD can be connected in series, in parallel, or in a series / parallel connection.

[0087] The pixel circuit may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a storage capacitor Cst.

[0088] The first electrode of the first transistor M1 (or driving transistor) can be connected to the first power supply line PL1 via the second node N2, and the second electrode of the first transistor M1 can be connected to the first electrode of the light-emitting element LD via the third node N3. Additionally, the gate electrode of the first transistor M1 can be connected to the first node N1. The first transistor M1 can control the amount of current supplied from the first driving power supply VDD to the second driving power supply VSS via the light-emitting element LD, corresponding to the voltage at the first node N1.

[0089] The second transistor M2 (or switching transistor) can be connected between the j-th data line DLj and the second node N2. Additionally, the gate electrode of the second transistor M2 can be electrically connected to the i-th first scan line SL1i. When the first scan signal GW is supplied to the i-th first scan line SL1i, the second transistor M2 can be turned on to electrically connect the j-th data line DLj and the second node N2 to each other.

[0090] A third transistor M3 (or a diode transistor) can be connected between the first node N1 and the third node N3. Additionally, the gate electrode of the third transistor M3 can be electrically connected to the i-th second scan line SL2i. When the second scan signal GC is supplied to the i-th second scan line SL2i, the third transistor M3 can be turned on to electrically connect the first node N1 and the third node N3 to each other. When the third transistor M3 is turned on, the first transistor M1 can be connected by a diode.

[0091] The first electrode of the fourth transistor M4 can be connected to the first node N1, and the second electrode of the fourth transistor M4 can be electrically connected to the second power supply line PL2. Additionally, the gate electrode of the fourth transistor M4 can be electrically connected to the i-th third scan line SL3i. When the third scan signal GI is enabled and supplied to the i-th third scan line SL3i, the fourth transistor M4 can be turned on to supply the voltage of the first initialization power supply Vint1 to the first node N1.

[0092] The first electrode of the fifth transistor M5 can be connected to the first electrode of the light-emitting element LD, and the second electrode of the fifth transistor M5 can be electrically connected to the third power supply line PL3. Additionally, the gate electrode of the fifth transistor M5 can be electrically connected to the i-th fourth scan line SL4i. When the fourth scan signal GB is enabled and supplied to the i-th fourth scan line SL4i, the fifth transistor M5 can be turned on to supply the voltage of the second initialization power supply Vint2 to the first electrode of the light-emitting element LD.

[0093] When the voltage of the second initialization power supply Vint2 is supplied to the first electrode of the light-emitting element LD, the parasitic capacitor of the light-emitting element LD can be discharged. Since the residual voltage charged in the parasitic capacitor of the light-emitting element LD is discharged (or removed), accidental micro-emissions can be prevented. Therefore, the black level performance of pixel PXij can be improved.

[0094] The first electrode of the sixth transistor M6 can be electrically connected to the fourth power supply line PL4 (or the bias power supply line), and the second electrode of the sixth transistor M6 can be connected to the second node N2. Additionally, the gate electrode of the sixth transistor M6 can be electrically connected to the i-th fourth scan line SL4i. When the fourth scan signal GB is supplied to the i-th fourth scan line SL4i, the sixth transistor M6 can be turned on to electrically connect the fourth power supply line PL4 and the second node N2 to each other.

[0095] The first electrode of the seventh transistor M7 can be electrically connected to the first power supply line PL1, and the second electrode of the seventh transistor M7 can be connected to the second node N2. Additionally, the gate electrode of the seventh transistor M7 can be electrically connected to the k-th transmit control line ELk. When the disable transmit control signal EM is supplied to the k-th transmit control line ELk, the seventh transistor M7 can be turned off, and when the enable transmit control signal EM is supplied to the k-th transmit control line ELk, the seventh transistor M7 can be turned on.

[0096] The eighth transistor M8 can be connected between the third node N3 and the first electrode of the light-emitting element LD. Additionally, the gate electrode of the eighth transistor M8 can be electrically connected to the k-th emission control line ELk. When the disabling emission control signal EM is supplied to the k-th emission control line ELk, the eighth transistor M8 can be turned off, and when the enabling emission control signal EM is supplied to the k-th emission control line ELk, the eighth transistor M8 can be turned on.

[0097] A storage capacitor Cst can be connected between the first power line PL1 and the first node N1. The storage capacitor Cst can store the voltage applied to the first node N1.

[0098] In this embodiment, the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 can be implemented using polysilicon semiconductor transistors. For example, the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 can comprise a polysilicon semiconductor layer formed as an active layer (channel) using a low-temperature polysilicon (LTPS) process. Alternatively, the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 can be implemented using P-type transistors (e.g., PMOS transistors). Accordingly, the gate turn-on voltage of the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 can have a logic low level. Because polysilicon semiconductor transistors have the advantage of high response speed, they can be used in switching elements requiring fast switching.

[0099] In this embodiment, the third transistor M3 and the fourth transistor M4 can be implemented using oxide semiconductor transistors. For example, the third transistor M3 and the fourth transistor M4 can be implemented using N-type oxide semiconductor transistors (e.g., NMOS transistors), and can include an oxide semiconductor layer as an active layer. Accordingly, the gate turn-on voltage of the third transistor M3 and the fourth transistor M4 can have a logic high level.

[0100] Oxide-semiconductor transistors (OSTs) can be fabricated using low-temperature processes and can exhibit lower charge mobility than polysilicon (PSTs). For example, OSTs have excellent cutoff current characteristics. Therefore, when the third transistor M3 and the fourth transistor M4 are implemented using OSTs, current leakage from the first node N1 driven at low frequencies can be minimized, and consequently, display quality can be improved.

[0101] Figure 4 is a waveform diagram illustrating an embodiment of a method for driving the pixels shown in Figure 3 during a display scan period. The display scan period DSP can be included in the valid time period of a frame.

[0102] Referring to Figures 3 and 4, the scanning period DSP can include a first period P1, a second period P2, a third period P3, and a fourth period P4. The first period P1, the second period P2, and the third period P3 can be set as non-transmission periods, and the fourth period P4 can be set as a transmission period.

[0103] During the first time period P1 to the third time period P3, the disabled emission control signal EM can be supplied to the k-th emission control line ELk. When the disabled emission control signal EM is supplied to the k-th emission control line ELk, the seventh transistor M7 and the eighth transistor M8 can be turned off. When the seventh transistor M7 and the eighth transistor M8 are turned off, the electrical connection between the first power line PL1 and the light-emitting element LD can be disconnected, and correspondingly, the light-emitting element LD can be set to a non-emitting state.

[0104] During the first time period P1, the enabling third scan signal GI can be supplied to the i-th third scan line SL3i. With the enabling third scan signal GI supplied to the i-th third scan line SL3i, the fourth transistor M4 can be turned on. With the fourth transistor M4 turned on, the voltage of the first initialization power supply Vint1 of the second power supply line PL2 can be supplied to the first node N1.

[0105] During the second time period P2, the enabling signal GC for the second scan line SL2i can be supplied, and correspondingly, the third transistor M3 can be turned on. With the third transistor M3 turned on, the first transistor M1 can be connected via a diode.

[0106] During the write period P_W, which overlaps with the second period P2, the first scan signal GW can be supplied to the i-th first scan line SL1i. With the first scan signal GW supplied to the i-th first scan line SL1i, the second transistor M2 can be turned on. With the second transistor M2 turned on, the data signal from the j-th data line DLj can be supplied to the second node N2. The first transistor M1, connected by a diode, is held in place by the turned-on third transistor M3, and therefore, the first node N1 can have a voltage obtained by compensating for the threshold voltage of the first transistor M1 in the data signal.

[0107] During the third time period P3, the enabling signal GB can be supplied to the i-th fourth scan line SL4i. With the enabling signal GB supplied to the i-th fourth scan line SL4i, the fifth transistor M5 and the sixth transistor M6 can be turned on. With the fifth transistor M5 turned on, the voltage of the second initialization power supply Vint2 can be supplied to the first electrode of the light-emitting element LD, and accordingly, the light-emitting element LD can be initialized. With the sixth transistor M6 turned on, the voltage of the bias power supply Vbias can be supplied to the second node N2. With the voltage of the bias power supply Vbias supplied to the second node N2, the first transistor M1 can be set to the on-bias state.

[0108] In the fourth time period P4, the enable transmit control signal EM (or a low-level transmit control signal) can be supplied to the k-th transmit control line ELk, causing the seventh transistor M7 and the eighth transistor M8 to be turned on. With the seventh transistor M7 and the eighth transistor M8 turned on, a current flow path can be formed from the first power line PL1 through the seventh transistor M7, the first transistor M1, the eighth transistor M8, and the light-emitting element LD to the fifth power line PL5. Depending on the operation of the first transistor M1, a drive current corresponding to the voltage of the first node N1 can flow through the light-emitting element LD, and the light-emitting element LD can emit light with a brightness corresponding to this drive current.

[0109] Figure 5 is a waveform diagram illustrating an embodiment of a method for driving the pixel shown in Figure 3 during a self-scanning period. The self-scanning period (SSP) is a period in which light is emitted while maintaining the voltage of the previously supplied data signal, and can also be a period in which the image is re-displayed without changing any frames. In an embodiment, a frame may include a display scan period (DSP) and at least one self-scanning period (SSP). At least one self-scanning period (SSP) may be consecutively set after the display scan period (DSP). The self-scanning period (SSP) may be included in the blank periods of the frame.

[0110] When compared to the display scan period DSP, threshold voltage compensation operations and data writing operations can be omitted in the self-scan period SSP, and the emission operation and the operation of applying bias voltage to the first transistor M1 (and the operation of initializing the light-emitting element LD) can be performed in the self-scan period SSP. The self-scan period SSP can be set to have a length equal to or similar to that of the display scan period DSP. The self-scan period SSP may include a first period P1', a second period P2', a third period P3', and a fourth period P4'.

[0111] Referring to Figures 3 and 5, during the first time period P1' to the third time period P3', the disabled emission control signal EM can be supplied to the k-th emission control line ELk. When the disabled emission control signal EM is supplied to the k-th emission control line ELk, the seventh transistor M7 and the eighth transistor M8 can be turned off, and correspondingly, the light-emitting element LD can be set to a non-emitting state.

[0112] During the first time period P1' to the third time period P3', the enabling first scan signal GW, the enabling second scan signal GC, and the enabling third scan signal GI may not be supplied (or the disabling scan signals GW, GC, and GI may be supplied). Accordingly, during the first time period P1' to the third time period P3', the second transistor M2, the third transistor M3, and the fourth transistor M4 may be set to the off state.

[0113] During the third time period P3', the enabling signal GB can be supplied to the i-th fourth scan line SL4i. With the enabling signal GB supplied to the i-th fourth scan line SL4i, the fifth transistor M5 and the sixth transistor M6 can be turned on.

[0114] With the fifth transistor M5 turned on, the voltage of the second initialization power supply Vint2 can be supplied to the first electrode of the light-emitting element LD, and the light-emitting element LD can be initialized accordingly. With the sixth transistor M6 turned on, the voltage of the bias power supply Vbias can be supplied to the second node N2. With the voltage of the bias power supply Vbias supplied to the second node N2, the first transistor M1 can be set to the on-bias state.

[0115] Because a frame includes a display scanning period (DSP) and a self-scanning period (SSP), the display device 100 described above according to embodiments of this disclosure can be driven at various driving frequencies (various frame rates).

[0116] Figures 6 and 7 are diagrams illustrating embodiments of signals supplied during active and passive time periods. The scan signals GW, GC, GI, and GB shown in Figures 6 and 7 indicate whether scan signals GW, GC, GI, and GB are supplied during the display scan period DSP and the self-scanning period SSP. For ease of description, the second scan signal GC and the third scan signal GI are shown as a single signal.

[0117] Referring to Figure 6, the display scan period DSP and the self-scan period SSP can be included in Frame 1. In the display scan period DSP, the enable transmit control signal EM, the enable first scan signal GW, the enable second scan signal GC, the enable third scan signal GI, and the enable fourth scan signal GB can be supplied.

[0118] During the self-scanning period (SSP), the enable transmit control signal EM and the enable fourth scan signal GB can be supplied. For example, the enable transmit control signal EM and the enable fourth scan signal GB can be supplied in both the display scan period (DSP) and the self-scanning period (SSP), and other enable scan signals GW, GC, and GI can be supplied only in the display scan period (DSP).

[0119] In some embodiments, as the driving frequency of the display device 100 becomes lower (e.g., low-frequency driving), as shown in FIG7, the number of self-scanning periods SSP included in Frame 1 can be increased, and correspondingly, the number of times the enable transmit control signal EM and the enable fourth scan signal GB are supplied in Frame 1 can be increased.

[0120] Figure 8 is a diagram illustrating an embodiment of the voltage supplied to the pixel during the pixel inspection process. Figures 9A and 9B are diagrams illustrating the driving waveforms supplied to the pixel during the inspection process. The inspection process can be performed during the manufacturing process of the display device 100. In the example, after the transistors M1 to M8 included in each of the pixels PX are formed, (before the light-emitting element has been formed) the transistors M1 to M8 can undergo the inspection process.

[0121] During the inspection, the characteristics of the first transistor M1 (e.g., voltage-current characteristics) can be detected, and whether the pixel PX is abnormal can be detected using the detected characteristics of the first transistor M1.

[0122] Referring to Figure 8, during the inspection process, a first voltage can be supplied to the j-th data line DLj (or data lines DL1 to DLm), the first power line PL1, and the fourth power line PL4. The first voltage can be set to 0V. During the inspection process, a second voltage can be supplied to the third power line PL3, and a voltage reduced from the third voltage to the fourth voltage can be supplied to the second power line PL2.

[0123] The second voltage can be set to a voltage lower than the first voltage (e.g., -5.1V). The third voltage can be set to a voltage higher than the first voltage (e.g., 3V). The fourth voltage can be set to a voltage lower than the second voltage (e.g., -8V).

[0124] Referring to Figure 9A, the enabling first scan signal GW can be supplied to the i-th first scan line SL1i during the inspection process. Additionally, the enabling fourth scan signal GB can be supplied to the i-th fourth scan line SL4i, and the enabling transmit control signal EM can be supplied to the k-th transmit control line ELk, such that the enabling fourth scan signal GB and the enabling transmit control signal EM overlap with the enabling first scan signal GW in time. The enabling fourth scan signal GB and the enabling transmit control signal EM can be supplied during a portion of the frame time period.

[0125] Additionally, during the remaining period of the frame time, the disabled fourth scan signal GB can be supplied to the i-th fourth scan line SL4i, and the disabled transmission control signal EM can be supplied to the k-th transmission control line ELk. The remaining period can be more than 95% of the frame time (e.g., 95% to 99% of the frame time).

[0126] During the inspection process, the disabled second scan signal GC (i.e., the gate cutoff voltage (e.g., -8V)) can be supplied to the i-th second scan line SL2i. When the disabled second scan signal GC is supplied to the i-th second scan line SL2i, the third transistor M3 can be set to the cutoff state during the inspection process.

[0127] During the inspection process, the enabling third scan signal GI (i.e., the gate on-voltage (e.g., 8V)) can be supplied to the i-th third scan line SL3i. With the enabling third scan signal GI supplied to the i-th third scan line SL3i, the fourth transistor M4 can be set to the on state during the inspection process.

[0128] Referring to Figure 9B, the voltage supplied to the second power line PL2 during the inspection process can be reduced by a specific voltage for each frame. In the example, the voltage supplied to the second power line PL2 can be reduced by 0.2V each time the frame changes. The voltage of the second power line PL2 can be gradually reduced from 3V to -8V.

[0129] The operation process will be described. During the first frame period, the first node N1 can be set to 3V, and the second transistor M2 can be turned on when the first scan signal GW is supplied to enable it. Current can flow from the j-th data line DLj through the second transistor M2, the first transistor M1, the eighth transistor M8, and the fifth transistor M5 to the third power line PL3.

[0130] During the second frame period, the first node N1 can be set to 2.8V, and the second transistor M2 can be turned on when the first scan signal GW is supplied to enable it. Current can flow from the j-th data line DLj through the second transistor M2, the first transistor M1, the eighth transistor M8, and the fifth transistor M5 to the third power line PL3.

[0131] During the third frame period, the first node N1 can be set to 2.6V, and the second transistor M2 can be turned on when the first scan signal GW is supplied to enable it. Current can flow from the j-th data line DLj through the second transistor M2, the first transistor M1, the eighth transistor M8, and the fifth transistor M5 to the third power line PL3.

[0132] During the 55th frame period, the first node N1 can be set to -8V, and the second transistor M2 can be turned on when the first scan signal GW is supplied to enable it. Current can flow from the j-th data line DLj through the second transistor M2, the first transistor M1, the eighth transistor M8, and the fifth transistor M5 to the third power line PL3. In the example, the second transistor M2 can be turned on at least once during the inspection process within a frame period.

[0133] The characteristic curve of the first transistor M1 can be obtained using the voltage (i.e., 3V to -8V) supplied to the gate electrode of the first transistor M1 during the inspection process and the current measured in the j-th data line DLj. Furthermore, whether a pixel PX is abnormal can be determined using the characteristic curve of the first transistor M1. For example, during the inspection process, the characteristic curve of the first transistor M1 included in each of the pixels PX can be detected, and whether a pixel PX is abnormal can be determined using the detected characteristic curve.

[0134] When the third transistor M3 is turned on during the inspection process, the first node N1 and the third node N3 can be electrically connected to each other. When current is supplied from the first node N1 to the third node N3, or when current is supplied from the third node N3 to the first node N1, the characteristics of the first transistor M1 may not be reliably and accurately detected. To prevent this, in embodiments of this disclosure, the third transistor M3 can be set to the off state by supplying a gate cutoff voltage to the i-th second scan line SL2i during the inspection process.

[0135] During the inspection, due to the IR drop of the first power line PL1 and the fourth power line PL4, the current from the j-th data line DLj may be supplied to the first power line PL1 and / or the fourth power line PL4, or the current from the first power line PL1 and / or the fourth power line PL4 may be supplied to the second node N2. The characteristics of the first transistor M1 may not be able to be detected stably and accurately.

[0136] In embodiments of this disclosure, to minimize the influence of the first power line PL1 and the fourth power line PL4, the disabled fourth scan signal GB can be supplied to the i-th fourth scan line SL4i and the disabled transmit control signal EM can be supplied to the k-th transmit control line ELk for approximately 95% of the frame period. Therefore, the time during which the first power line PL1 and the fourth power line PL4 are electrically connected to the second node N2 during the frame period can be minimized, and correspondingly, the characteristics of the first transistor M1 can be detected more stably and accurately.

[0137] Figure 10 illustrates an example of the transmit control signals supplied during the inspection period. In Figure 10, the numbers enclosed in parentheses in M1(1), M1(2), M1(3), ..., M1(n) can refer to the horizontal lines on which the first transistor M1 is formed. In Figure 10, the numbers enclosed in parentheses in parentheses in EM(1), EM(2), EM(3), ..., EM(n) can refer to the horizontal lines on which the transmit control signals are supplied. In Figure 10, it is assumed that there are n transmit control lines. In Figure 10, for ease of description, the first data line D1 is shown, and it is shown that the first data line D1 is directly connected to the first transistors M1(1), M1(2), M1(3), ..., and M1(n).

[0138] Referring to Figure 10, during the inspection period, the transmission control signals can be supplied sequentially.

[0139] When the enable transmit control signal EM(1) is supplied to the first horizontal line, the current flowing through the first transistor M1(1) located on the first horizontal line can be detected. In the example, the current flowing through the first transistor M1(1) can be detected by a testing device electrically connected to the first data line D1.

[0140] When the enable transmit control signal EM(2) is supplied to the second horizontal line, the current flowing through the first transistor M1(2) located on the second horizontal line can be detected. In the example, the current flowing through the first transistor M1(2) can be detected by a testing device electrically connected to the first data line D1.

[0141] When the enable transmit control signal EM(3) is supplied to the third horizontal line, the current flowing through the first transistor M1(3) located on the third horizontal line can be detected. In the example, the current flowing through the first transistor M1(3) can be detected by a testing device electrically connected to the first data line D1.

[0142] When the enable transmit control signal EM(n) is supplied to the nth horizontal line, the current flowing through the first transistor M1(n) located on the nth horizontal line can be detected. In the example, the current flowing through the first transistor M1(n) can be detected by a testing device electrically connected to the first data line D1.

[0143] By using the above method, whether a pixel PX is abnormal can be detected during the inspection process.

[0144] Figure 11 is a graph showing the characteristic curves of the first transistor detected during the inspection process. In Figure 11, the ideal characteristics can refer to the ideal characteristic curves of the first transistor M1 obtained by taking into account the IR drops of the first power line PL1 and the fourth power line PL4. In Figure 11, the true characteristics can refer to the true characteristic curves of the first transistor M1 obtained by taking into account the IR drops of the first power line PL1 and the fourth power line PL4.

[0145] Referring to Figure 11, the voltage of the second power line PL2 can be gradually reduced from 3V to -8V, and correspondingly, the amount of current of the first transistor M1 included in each of the pixels PX can be set differently.

[0146] In the example, the amount of current flowing through the first transistor M1 can increase as the voltage approaches a fourth voltage (i.e., -8V) from a third voltage (i.e., 3V). During inspection, the amount of current flowing through the first transistor M1 can be measured using an inspection device connected to data lines DL1 to DLm, corresponding to the voltage supplied to the second power line PL2, and a characteristic curve of the first transistor M1 can be generated corresponding to the measured amount of current. Furthermore, whether each pixel PX is abnormal can be determined using the characteristic curve of the first transistor M1.

[0147] Figure 11 shows the ideal characteristic curve and the actual characteristic curve of the first transistor M1. When the voltage supplied to the second power line PL2 is relatively high (e.g., above approximately -2.5V), the characteristics of the first transistor M1 may not be detected stably and accurately due to the IR drop of the first power line PL1 and the fourth power line PL4. During inspection, whether pixel PX is abnormal can be determined by considering such characteristics.

[0148] Figure 12 is a diagram illustrating an embodiment in which voltage is supplied to the pixel during the pixel inspection process.

[0149] Referring to Figure 12, during the inspection process, the first test power supply unit 200 can supply a first voltage to the first power line PL1 via the first resistor R1. With the seventh transistor M7 turned on, the amount of current supplied from the second node N2 to the first power line PL1 and / or from the first power line PL1 to the second node N2 can be minimized, and correspondingly, the characteristics of the first transistor M1 can be detected stably and accurately. The first resistor R1 can have… to The resistance value.

[0150] During the inspection, the second test power supply unit 202 can supply the first voltage to the fourth power line PL4 via the second resistor R2. With the sixth transistor M6 turned on, the amount of current supplied from the second node N2 to the fourth power line PL4 and / or from the fourth power line PL4 to the second node N2 can be minimized, and correspondingly, the characteristics of the first transistor M1 can be stably and accurately detected. The second resistor R2 can have… to The resistance value.

[0151] Figure 12 shows that the first test power supply unit 200 and the second test power supply unit 202 are separate components. However, the embodiments of this disclosure are not limited thereto. In another example, the first test power supply unit 200 and the second test power supply unit 202 may be integrated into a single power supply unit.

[0152] Figure 13 is a graph showing the characteristic curve of the first transistor generated during the inspection process when the voltage is supplied via the resistor shown in Figure 12.

[0153] Referring to Figure 13, the voltage of the second power line PL2 can be gradually reduced from 3V to -8V, and correspondingly, the amount of current of the first transistor M1 included in each of the pixels PX can be set differently.

[0154] During the inspection process, the current of the first transistor M1 can be measured using an inspection device connected to data lines DL1 to DLm, corresponding to the voltage supplied to the second power line PL2, and a characteristic curve of the first transistor M1 can be generated corresponding to the measured current. Furthermore, whether each pixel PX is abnormal can be determined using the characteristic curve of the first transistor M1.

[0155] When the first voltage is supplied to the first power line PL1 and the fourth power line PL4 via the first resistor R1 and the second resistor R2, the amount of current supplied from the first power line PL1 and the fourth power line PL4 to the second node N2 and / or the amount of current supplied from the second node N2 to the first power line PL1 and the fourth power line PL4 can be minimized. As shown in Figure 13, the characteristics of the first transistor M1 can be detected stably and accurately.

[0156] Figure 14 is a diagram showing test pixels according to an embodiment of the present disclosure.

[0157] Referring to FIG14, the display device 100 according to an embodiment of the present disclosure may include a test pixel TPX. The test pixel TPX may be included in the pixel unit 110 and may be a pixel that does not display an image.

[0158] In the example, the test pixel TPX can be a pixel used to detect the characteristics of the first transistor M1. The basic configuration of the test pixel PX can be substantially the same as the configuration of the pixel PXij described in Figure 3. Therefore, the same or similar components will be indicated by the same reference numerals, and detailed descriptions will be omitted.

[0159] The first power line PL1 included in the test pixel TPX can be electrically disconnected from the seventh transistor M7. In the example, the first power line PL1 can be cut off, thus not electrically connected to the seventh transistor M7.

[0160] The fourth power line PL4 included in the test pixel TPX can be electrically disconnected from the sixth transistor M6. In the example, the fourth power line PL4 can be cut off, thus not electrically connected to the sixth transistor M6.

[0161] Therefore, when the second node N2 is electrically disconnected from the first power line PL1 and the fourth power line PL4, the characteristics of the first transistor M1 can be detected more stably and accurately. For example, if it is desired to detect the characteristics of the first transistor M1 stably and accurately during the inspection process, a test pixel TPX can be formed in the pixel unit 110. In another embodiment, the light-emitting element LD may not be included in the test pixel TPX.

[0162] Figure 15 is a diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0163] Referring to FIG15, the electronic device 1000 according to an embodiment of the present disclosure can output various information through the display module 1140. When the processor 1110 executes an application stored in the memory 1120, the display module 1140 can provide application information to the user through the display panel 1141.

[0164] Processor 1110 can acquire external input via input module 1130 or sensor module 1161, and can execute an application corresponding to the external input. For example, if the user selects a camera icon (or camera application icon) displayed on display panel 1141, processor 1110 can acquire user input via input sensor 1161-2 and activate camera module 1171. Processor 1110 can then transmit image data corresponding to the captured image obtained by camera module 1171 to display module 1140. Display module 1140 can display the image corresponding to the captured image via display panel 1141.

[0165] In another example, when personal information authentication is performed in display module 1140, fingerprint sensor 1161-1 can acquire input fingerprint information as input data. Processor 1110 can compare the input data acquired by fingerprint sensor 1161-1 with authentication data stored in memory 1120, and can execute an application based on the comparison result. Display module 1140 can display information executed according to the logic of the application through display panel 1141. Fingerprint sensor 1161-1 can be positioned to acquire fingerprint information over the entire area of ​​display panel 1141.

[0166] In another example, when a music stream icon is selected to be displayed on display module 1140, processor 1110 can acquire user input via input sensor 1161-2 and activate the music stream application stored in memory 1120. When a music playback command is entered into the music stream application, processor 1110 can activate sound output module 1163, thereby providing the user with sound information consistent with the music playback command.

[0167] The operation of the electronic device 1000 has been briefly described above. The components of the electronic device 1000 will be described in detail below. Some of the components of the electronic device 1000, which will be described later, can be integrated to be provided as a single component, and a single component can be provided as two or more separate components.

[0168] Electronic device 1000 can communicate with external electronic device 2000 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). In an embodiment, electronic device 1000 may include a processor 1110, a memory 1120, an input module 1130, a display module 1140, a power module 1150, an internal module 1160, and an external module 1170. In an embodiment, at least one of the above-mentioned components may be omitted, or one or more other components may be added. In an embodiment, some of the above-mentioned components (e.g., sensor module 1161, antenna module 1162, and / or sound output module 1163) may be integrated into another component (e.g., display module 1140).

[0169] Processor 1110 can control at least one other component (e.g., hardware or software component) of electronic device 1000 connected to processor 1110 by executing software, and can perform various data processing or calculations. In an embodiment, as at least part of data processing or calculation, processor 1110 can store commands or data received from another component (e.g., input module 1130, sensor module 1161, or communication module 1173) in volatile memory 1121, can process commands or data stored in volatile memory 1121, and can store result data in non-volatile memory 1122.

[0170] Processor 1110 may include a main processor 1111 and an auxiliary processor 1112. Main processor 1111 may include a central processing unit (CPU) 1111-1. Main processor 1111 may further include at least one of a graphics processing unit (GPU) 1111-2, a communication processor (CP), and an image signal processor (ISP). Main processor 1111 may further include a neural processing unit (NPU) 1111-3. NPU 1111-3 is a processor specifically designed for processing artificial intelligence (AI) models, and the AI ​​models can be generated through machine learning. The AI ​​model may include multiple layers of artificial neural networks. The artificial neural network may be one or a combination of two or more of the following: deep neural network (DNN), convolutional neural network (CNN), recurrent neural network (RNN), restricted Boltzmann machine (RBM), deep belief network (DBN), bidirectional recurrent deep neural network (BRDNN), and deep Q-network, but embodiments are not necessarily limited thereto. In addition to the hardware architecture, the AI ​​model may additionally or alternatively include software architecture. At least two of the aforementioned processing units and processors may be implemented as an integrated component (e.g., a single chip), or the aforementioned processing units and processors may be implemented as independent components (e.g., multiple chips).

[0171] The auxiliary processor 1112 may include a controller 1112-1. The controller 1112-1 may include an interface conversion circuit and a timing control circuit. In the example, the auxiliary processor 1112 may include the timing controller 120 shown in FIG. 1. At least some functions (or components) of the timing controller 120 may be included in the controller 1112-1, the data conversion circuit 1112-2, the gamma correction circuit 1112-3, the rendering circuit 1112-4, and the touch control circuit 1112-5, etc.

[0172] The controller 1112-1 can receive image signals from the main processor 1111 and convert the image signal data format into a format suitable for the interface specification with the display module 1140, thereby outputting image data. The controller 1112-1 can output various control signals for driving the display module 1140.

[0173] The auxiliary processor 1112 may further include a data conversion circuit 1112-2, a gamma correction circuit 1112-3, a rendering circuit 1112-4, and a touch control circuit 1112-5, etc. The data conversion circuit 1112-2 can receive image data from the controller 1112-1 and can compensate the image data so that the image is displayed at the desired brightness according to the characteristics of the electronic device 1000 or the user's settings, or can convert the image data for purposes such as reducing power consumption or compensating for image retention.

[0174] The gamma correction circuit 1112-3 can convert image data or gamma reference voltage, etc., so that the image displayed in the electronic device 1000 has the desired gamma characteristics. The rendering circuit 1112-4 can receive image data from the controller 1112-1 and can render the image data by taking into account the pixel arrangement of the display panel 1141 applied to the electronic device 1000.

[0175] The touch control circuit 1112-5 can supply touch signals to the input sensor 1161-2, and can be supplied with sensing signals corresponding to the touch signals from the input sensor 1161-2.

[0176] At least one of the data conversion circuit 1112-2, gamma correction circuit 1112-3, rendering circuit 1112-4, and touch control circuit 1112-5 can be integrated into another component (e.g., the main processor 1111 or the controller 1112-1). At least one of the data conversion circuit 1112-2, gamma correction circuit 1112-3, and rendering circuit 1112-4 can be integrated into the source driver 1143, which will be described later.

[0177] The memory 1120 may store various data used by at least one component of the electronic device 1000 (e.g., processor 1110 or sensor module 1161), as well as input or output data regarding commands related to these various data. Furthermore, various setting data corresponding to user settings may be stored in the memory 1120. The memory 1120 may include at least one of volatile memory 1121 and non-volatile memory 1122.

[0178] The input module 1130 can receive commands or data from an external source of the electronic device 1000 (e.g., a user or external electronic device 2000) to be used in components of the electronic device 1000 (e.g., processor 1110, sensor module 1161, or voice output module 1163).

[0179] Input module 1130 may include a first input module 1131 for inputting commands or data from a user and a second input module 1132 for inputting commands or data from an external electronic device 2000. The first input module 1131 may include a microphone, mouse, keyboard, buttons (e.g., keypads), or pen (e.g., a passive or active pen). The second input module 1132 may support a specified protocol enabling the electronic device 1000 to connect to the external electronic device 2000 via wired or wireless communication. The second input module 1132 may include a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, an SD card interface, or an audio interface. The second input module 1132 may include a connector (e.g., an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector)) that allows the electronic device 1000 to be physically connected to the external electronic device 2000.

[0180] Display module 1140 can visually provide information to a user. Display module 1140 may include a display panel 1141, a gate driver 1142, a source driver 1143, and a voltage generation circuit 1144. Display module 1140 may further include a window, housing, and bracket for protecting the display panel 1141. Display module 1140 may include at least some components of the display device 100 shown in FIG. 1.

[0181] The display panel 1141 (or display) may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel, and the type of display panel 1141 is not particularly limited. The display panel 1141 may be a rigid type or a flexible type in which the display panel 1141 can be rolled up or folded. The display module 1140 may further include a support, bracket, or heat dissipation component for supporting the display panel 1141. The display panel 1141 may include the pixel unit 110 shown in FIG. 1.

[0182] Display panel 1141 may include the pixel PX shown in FIG. 1. Additionally, display panel 1141 may include the test pixel TPX shown in FIG. 14. Whether the pixel PX included in display panel 1141 is abnormal can be determined while undergoing the inspection process described with reference to FIGS. 8 to 12.

[0183] Gate driver 1142 is a driver chip and can be mounted in display panel 1141. Alternatively, gate driver 1142 can be integrated into display panel 1141. For example, gate driver 1142 may include an amorphous silicon TFT gate (ASG) driver circuit, a low-temperature polycrystalline silicon (LTPS) TFT gate driver circuit, or an oxide semiconductor TFT gate (OSG) driver circuit embedded in display panel 1141. Gate driver 1142 can receive control signals from controller 1112-1 and can output scan signals to display panel 1141 in response to the control signals. Gate driver 1142 may include scan driver 130 as shown in FIG. 1.

[0184] The display module 1140 may further include a transmitter driver. The transmitter driver may correspond to the transmitter driver 150 shown in FIG. 1. The transmitter driver may output a transmitter control signal to the display panel 1141 in response to a control signal received from the controller 1112-1. The transmitter driver may be formed separately from the gate driver 1142, or it may be integrated into the gate driver 1142.

[0185] The source driver 1143 can receive control signals from the controller 1112-1 and can convert image data into analog voltages (e.g., data voltages) in response to the control signals and then output the data voltages to the display panel 1141. The source driver 1143 may include the data driver 140 shown in FIG1.

[0186] The source driver 1143 can be integrated into another component (e.g., controller 1112-1). The functions of the interface conversion circuitry and timing control circuitry of the controller 1112-1 described above can be integrated into the source driver 1143. The voltage generation circuit 1144 can output various voltages for driving the display panel 1141. The voltage generation circuit 1144 may include the power supply 160 shown in FIG. 1.

[0187] In an embodiment, the source driver 1143 can convert the data corresponding to red (R), green (G) and blue (B) included in the image data received from the processor 1110 into red data signals (or data voltages), green data signals and blue data signals, and can provide the red data signals, green data signals and blue data signals to a plurality of pixel columns included in the display panel 1141 during a horizontal time period.

[0188] Power module 1150 can supply power to at least one component of electronic device 1000. Power module 1150 may include a battery for charging with a power supply voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. Power module 1150 may include a power management integrated circuit (PMIC). The PMIC can supply an optimized power supply voltage to each of the modules described above and later. Power module 1150 may include a wireless power transmission / reception component electrically connected to the battery. The wireless power transmission / reception component may include a plurality of coil-shaped antenna radiators. At least some components of power module 1150 and voltage generation circuit 1144 may be provided as integrated into a single component. Voltage generation circuit 1144 may be included in power module 1150.

[0189] The electronic device 1000 may further include an internal module 1160 and an external module 1170. The internal module 1160 may include a sensor module 1161, an antenna module 1162, and a sound output module 1163. The external module 1170 may include a camera module 1171, an optical module 1172, and a communication module 1173.

[0190] The sensor module 1161 can sense input caused by the user's body or by a pen in the first input module 1131, and can generate an electrical signal or data value corresponding to the input. The sensor module 1161 may include at least one of a fingerprint sensor 1161-1, an input sensor 1161-2, and a digitizer 1161-3.

[0191] The fingerprint sensor 1161-1 can generate data values ​​corresponding to the user's fingerprint.

[0192] Input sensor 1161-2 can generate data values ​​corresponding to the coordinate information of input caused by the user's body or input caused by a pen. Input sensor 1161-2 can generate the amount of capacitance change caused by the input as a data value. Input sensor 1161-2 can sense input caused by a passive pen, or can send data to / receive data from an active pen.

[0193] Input sensor 1161-2 can measure biometric signals related to biometric information such as pressure, moisture, or body fat. For example, if a user remains stationary for a specific period of time while a part of the user's body is in contact with the sensor layer or sensing panel, input sensor 1161-2 can sense biometric signals based on changes in the electric field caused by that body part to output the information desired by the user to display module 1140.

[0194] The digitizer 1161-3 can generate data values ​​corresponding to the coordinate information of the input caused by the pen. The digitizer 1161-3 can also generate the electromagnetic change caused by the input as a data value. The digitizer 1161-3 can sense the input caused by a passive pen, or it can send data to / receive data from an active pen.

[0195] At least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 can be implemented as a sensor layer formed on the display panel 1141 through a continuous process. At least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 can be located on the upper side of the display panel 1141, and / or any one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 (e.g., the digitizer 1161-3) can be located on the lower side of the display panel 1141.

[0196] At least two of the fingerprint sensor 1161-1, input sensor 1161-2, and digitizer 1161-3 can be formed into a single sensing panel using the same process. When at least two of the fingerprint sensor 1161-1, input sensor 1161-2, and digitizer 1161-3 are integrated into a single sensing panel, the sensing panel can be located between the display panel 1141 and the window located above the display panel 1141. According to an embodiment, the sensing panel can be located on the window, and the position of the sensing panel is not particularly limited.

[0197] At least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 can be integrated into the display panel 1141. That is, at least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 can be formed simultaneously by a process for forming elements (e.g., light-emitting elements and transistors) included in the display panel 1141.

[0198] Furthermore, sensor module 1161 can generate electrical signals or data values ​​corresponding to the internal or external states of electronic device 1000. Sensor module 1161 may further include, for example, a gesture sensor, gyroscope sensor, atmospheric pressure sensor, magnetic sensor, accelerometer, grip sensor, proximity sensor, color sensor, infrared (IR) sensor, biometric sensor, temperature sensor, humidity sensor, or illuminance sensor.

[0199] Antenna module 1162 may include one or more antennas for transmitting or receiving signals or power to or from an external source. According to an embodiment, communication module 1173 may transmit or receive signals to or from external electronic device 2000 via an antenna suitable for a communication scheme. The antenna pattern of antenna module 1162 may be integrated into a component of display module 1140 (e.g., display panel 1141) or input sensors 1161-2, etc.

[0200] The sound output module 1163 is a device for outputting sound signals to the outside of the electronic device 1000, and may include, for example, a speaker for general purposes such as multimedia playback or transcription playback, and a receiver for call reception only. The receiver may be integrally formed with the speaker or may be formed separately from the speaker. The sound output pattern of the sound output module 1163 may be integrated into the display module 1140.

[0201] Camera module 1171 can capture still images and moving images. Camera module 1171 may include one or more lenses, image sensors, or image signal processors. Camera module 1171 may further include an infrared camera capable of measuring the presence of a user, the user's position, or the user's line of sight.

[0202] The optical module 1172 can provide light. The optical module 1172 may include a light-emitting diode or a xenon lamp. The optical module 1172 may operate in conjunction with the camera module 1171 or may operate independently of the camera module 1171.

[0203] Communication module 1173 can establish a wired or wireless communication channel between electronic device 1000 and external electronic device 2000, and can support communication through the established communication channel. Communication module 1173 may include any one or all of wireless communication modules (e.g., cellular communication modules, short-range wireless communication modules, or Global Navigation Satellite System (GNSS) communication modules) and wired communication modules (e.g., local area network (LAN) communication modules or power line communication (PLC) modules). Communication module 1173 can communicate via short-range communication networks (e.g., Bluetooth). ® The communication module 2000 communicates with external electronic devices via a wireless fidelity (WiFi Direct) or infrared data association (IrDA) standard, or a long-range communication network (e.g., cellular network, internet, or computer network (e.g., LAN or WAN)). These various communication modules can be implemented on a single chip or as separate chips.

[0204] The input module 1130, sensor module 1161, and camera module 1171 can work in conjunction with the processor 1110 to control the operation of the display module 1140.

[0205] The processor 1110 can output commands or data to the display module 1140, the sound output module 1163, the camera module 1171, or the optical module 1172 based on the input data received from the input module 1130. For example, the processor 1110 can generate image data corresponding to input data applied via a mouse or active pen, and can output the image data to the display module 1140. Alternatively, the processor 1110 can generate command data corresponding to the input data and can output the command data to the camera module 1171 or the optical module 1172. In the absence of input data received from the input module 1130, the processor 1110 can change the operating mode of the electronic device 1000 to a low-power mode or a sleep mode, thereby reducing the power consumed in the electronic device 1000.

[0206] Processor 1110 can output commands or data to display module 1140, sound output module 1163, camera module 1171, or optical module 1172 based on sensing data received from sensor module 1161. For example, processor 1110 can compare authentication data applied by fingerprint sensor 1161-1 with authentication data stored in memory 1120, and then execute an application based on the comparison result. Processor 1110 can execute commands or output corresponding image data to display module 1140 based on sensing data sensed by input sensor 1161-2 or digitizer 1161-3. When a temperature sensor is included in sensor module 1161, processor 1110 can receive temperature data about the measured temperature from sensor module 1161, and can further perform brightness correction on image data based on the temperature data.

[0207] Processor 1110 can receive measurement data from camera module 1171 regarding the presence of a user, the user's position, or the user's gaze. Processor 1110 can further perform brightness correction on image data based on the measurement data. For example, processor 1110, which determines the presence of a user based on input from camera module 1171, can output image data whose brightness has been corrected via data conversion circuit 1112-2 or gamma correction circuit 1112-3 to display module 1140.

[0208] At least some of the aforementioned components can be connected to each other via peripheral communication schemes (e.g., bus, general purpose input / output (GPIO), serial peripheral interface (SPI), mobile industrial processor interface (MIPI), or ultrapath interconnect (UPI) link) and can exchange signals (e.g., commands or data) therebetween. Processor 1110 can communicate with display module 1140 via a specified interface and can use any of the aforementioned communication schemes. However, this disclosure is not limited to the aforementioned communication schemes.

[0209] In the display device and method for inspecting the display device according to embodiments of the present disclosure, as well as in the electronic device, the diode transistor included in the pixel (i.e., the third transistor M3 in FIG3, 8, 12 and 14) is set to a cut-off state during the inspection process, and accordingly, the characteristics of the driving transistor (i.e., the first transistor M1 in FIG3, 8, 12 and 14) can be detected stably and accurately.

[0210] Furthermore, in the display device and method for inspecting the display device and electronic device according to embodiments of the present disclosure, during the inspection process, voltage is supplied to the power line via a resistor, so that the characteristics of the driving transistor can be detected while minimizing the influence of the power line.

[0211] Furthermore, in the display device and the method for inspecting the display device according to embodiments of the present disclosure, as well as the electronic device, test pixels are formed, and the test pixels and some power lines are electrically disconnected from each other, so that the characteristics of the driving transistors can be detected stably and accurately.

[0212] Example embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only and is not intended to be limiting. In some instances, as will be apparent to those skilled in the art at the time of filing this application, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Accordingly, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as set forth in the claims.

Claims

1. A method for inspecting a display device, wherein, The display device includes pixels, each of the pixels including: a first transistor including a gate electrode connected to a first node, a first electrode connected to a first power line via a second node, and a second electrode connected to a third node; a second transistor connected between a data line and the second node, the second transistor including a gate electrode connected to a first scan line; a third transistor connected between the first node and the third node, the third transistor including a gate electrode connected to a second scan line; a fourth transistor connected between the first node and the second power line, the fourth transistor including a gate electrode connected to the third scan line; a fifth transistor connected between the third node and the third power line, the fifth transistor including a gate electrode connected to the fourth scan line; and a sixth transistor connected between the second node and the fourth power line, the sixth transistor including a gate electrode connected to the fourth scan line, and wherein the method includes: during an inspection process, supplying a first voltage to the data line, the first power line, and the fourth power line; supplying a second voltage to the third power line; supplying a voltage reduced from the third voltage to the fourth voltage to the second power line; and supplying a gate cutoff voltage to the second scan line, such that the third transistor is turned off.

2. The method according to claim 1, wherein, The first voltage is 0V.

3. The method according to claim 1, wherein, The second voltage is a voltage lower than the first voltage.

4. The method according to claim 1, wherein, The third voltage is a voltage higher than the first voltage, and the fourth voltage is a voltage lower than the second voltage.

5. The method according to claim 1, wherein, The voltage supplied to the second power line is reduced by a specific voltage for each frame.

6. The method according to claim 1, wherein, Each of the pixels further includes: a seventh transistor connected between the first power line and the second node, the seventh transistor including a gate electrode connected to the emitt control line; and an eighth transistor connected between the third node and the fifth transistor, the eighth transistor including a gate electrode connected to the emitt control line.

7. The method of claim 6, further comprising: During the inspection process: an enabling first scan signal is supplied to the first scan line, causing the second transistor to be turned on at least once in a frame period; and a gate turn-on voltage is supplied to the third scan line, causing the fourth transistor to be turned on.

8. The method of claim 7, further comprising: During a portion of the frame time period, an enable transmit control signal is supplied to the transmit control line to overlap with the enable first scan signal in time, thereby turning on the seventh transistor and the eighth transistor; During the remaining time period of the frame period, a disabled transmit control signal is supplied to the transmit control line, causing the seventh transistor and the eighth transistor to be turned off.

9. The method according to claim 8, wherein, The remaining time period is 95% to 99% of the frame time period.

10. The method of claim 8, further comprising: During the specified time period, a fourth scan signal is supplied to the fourth scan line, causing the sixth transistor to be turned on; During the remaining time period, a disabled fourth scan signal is supplied to the fourth scan line, causing the sixth transistor to be turned off.

11. The method according to any one of claims 1 to 10, wherein, The first voltage is supplied to the first power line via a first resistor, and wherein the first voltage is supplied to the fourth power line via a second resistor.

12. The method according to claim 11, wherein, The first resistor and the second resistor each have to The resistance value.

13. A method for inspecting a display device comprising pixels, the method comprising: For different frames, different voltages are supplied to the gate electrode of the driving transistor of the pixel; And while allowing the switching transistor of the pixel connected between the data line and the first electrode of the driving transistor to be turned on during a portion of each frame, the amount of current flowing through the driving transistor is measured, wherein the diode transistor of the pixel located between the gate electrode of the driving transistor and the second electrode of the driving transistor is set to be in the off state.

14. The method according to claim 13, wherein, A first voltage is supplied to a first power supply line and a bias power supply line that are electrically connected to the first electrode of the driving transistor.

15. The method according to claim 14, wherein, The first voltage is further supplied to the data line.

16. The method of claim 14, wherein, The first voltage is supplied to the first power line via a first resistor, and wherein the first voltage is supplied to the bias power line via a second resistor.

17. The method according to claim 16, wherein, The first resistor and the second resistor each have to The resistance value.

18. An electronic device comprising: A display panel includes pixels for displaying images and test pixels for not displaying the images. The test pixels include: a first transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a storage capacitor connected between a first power line and the first node; a second transistor connected between a data line and the second node, the second transistor including a gate electrode connected to a first scan line; a third transistor connected between the first node and the third node, the third transistor including a gate electrode connected to a second scan line; a fourth transistor connected between the first node and the second power line, the fourth transistor including a gate electrode connected to the third scan line; a fifth transistor connected between the third node and the third power line, the fifth transistor including a gate electrode connected to the fourth scan line; a sixth transistor including a second electrode connected to the second node and a gate electrode connected to the fourth scan line; a seventh transistor including a second electrode connected to the second node and a gate electrode connected to an emission control line; and an eighth transistor connected between the third node and the fifth transistor, the eighth transistor including a gate electrode connected to the emission control line, wherein the first electrode of the seventh transistor is not electrically connected to the first power line.

19. The electronic device according to claim 18, wherein, The first electrode of the sixth transistor is not electrically connected to a separate power supply line.

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