Secondary circuit fault detection method, device, equipment, medium and program product
By equipping the secondary circuit nodes of substations with lower-level computer modules, power parameters and connectivity status data are automatically acquired, a connectivity matrix is constructed, and fault areas and equipment are identified. This solves the problem of low efficiency in traditional detection methods and enables rapid and accurate fault detection and location.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUIZHOU POWER SUPPLY BUREAU OF GUANGDONG POWER GRID CO LTD
- Filing Date
- 2026-01-09
- Publication Date
- 2026-05-01
AI Technical Summary
Traditional secondary circuit fault detection relies on manual inspection and basic electrical testing, which is inefficient and cannot achieve real-time monitoring and rapid response, leading to the escalation of faults.
Lower-level modules are equipped at multiple secondary circuit nodes in the substation. By sending fault detection commands, power parameters and connectivity data are obtained, a connectivity matrix is constructed, power parameter differences and communication paths are analyzed, and suspected fault areas and equipment are identified.
It enables rapid and accurate detection and location of secondary circuit faults, reduces manual intervention time, improves detection efficiency and accuracy, and reduces the impact of faults on the power system.
Smart Images
Figure CN121955816A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electrical fault detection technology, and in particular to a method, apparatus, equipment, medium and program product for secondary circuit fault detection. Background Technology
[0002] After a substation is newly built or undergoes major repairs, secondary circuit fault detection must be carried out. The purpose of this detection is to ensure the reliability and safety of the secondary circuits, as well as to improve the operating efficiency of the entire power system.
[0003] Traditional secondary circuit fault detection relies primarily on manual inspection and basic electrical testing instruments. Manual inspection and testing are time-consuming and labor-intensive, especially in large substations, resulting in low efficiency. The long detection cycle also prevents real-time monitoring and rapid response to faults, potentially leading to the escalation of existing faults. Summary of the Invention
[0004] This application provides a method, apparatus, equipment, medium, and program product for secondary circuit fault detection, which aims to improve the efficiency and accuracy of secondary circuit fault detection and reduce the impact of faults on power system operation.
[0005] In a first aspect, embodiments of this application provide a secondary circuit fault detection method, wherein multiple secondary circuit nodes in a substation are respectively equipped with a lower-level machine module, the lower-level machine module being used to collect power parameters of the corresponding secondary circuit nodes, the method comprising:
[0006] A secondary circuit fault detection command is sent to the target lower-level machine module. The secondary circuit fault detection command indicates the target secondary circuit node and the sampled power parameters. The target secondary circuit node is the secondary circuit node that performs secondary circuit fault detection. The target lower-level machine module is the lower-level machine module equipped at the target secondary circuit node.
[0007] The system acquires detection data returned by the target lower-level machine module in response to the secondary circuit fault detection command, and acquires connectivity status data between the target lower-level machine module and other target lower-level machine modules. The detection data includes power parameters collected at the target secondary circuit node, and the connectivity status data is used to determine the current connectivity status between the target lower-level machine module and other target lower-level machine modules.
[0008] Based on the detection data and the connectivity status data, a secondary circuit fault detection result is generated for the secondary circuit fault detection command. The secondary circuit fault detection result includes the identified suspected fault areas and the suspected faulty electrical equipment within the suspected fault areas.
[0009] In one possible implementation, generating a secondary circuit fault detection result based on the detection data and the connectivity status data in response to the secondary circuit fault detection command includes:
[0010] A connectivity matrix is constructed based on the connectivity status data returned by each target lower-level machine module. Each element in the connectivity matrix represents the connectivity status between any two lower-level machine modules.
[0011] For any target secondary circuit node, the power parameters extracted from the detection data and collected at the target secondary circuit node are compared with the power parameters collected at the target secondary circuit node under normal conditions to obtain the comparison result.
[0012] Based on the comparison results and the connectivity matrix, suspected fault regions are identified.
[0013] Identify suspected faulty electrical equipment from the suspected fault area to generate secondary circuit fault detection results in response to the secondary circuit fault detection command.
[0014] In one possible implementation, determining the suspected fault region based on the comparison result and the connectivity matrix includes:
[0015] Based on the comparison results, an abnormal target lower-level machine module was identified;
[0016] Based on the connectivity matrix analysis, the communication paths between the abnormal target lower-level machine module and other target lower-level machine modules are analyzed to identify suspected fault areas.
[0017] In one possible implementation, the lower-level machine module that identifies abnormal targets based on the comparison results includes:
[0018] If the difference between the power parameters collected at the target secondary circuit node extracted from the detection data and the power parameters collected at the target secondary circuit node under normal conditions is greater than a preset difference threshold, then the target lower-level machine module equipped at the target secondary circuit node is identified as the abnormal target lower-level machine module.
[0019] In one possible implementation, after analyzing the communication paths between the abnormal target lower-level machine module and other target lower-level machine modules based on the connectivity matrix to identify suspected fault areas, the method further includes:
[0020] The suspected fault areas are sorted to generate a fault handling plan, which includes the order in which fault handling personnel will inspect each of the suspected fault areas.
[0021] In one possible implementation, identifying the suspected faulty electrical equipment from the suspected fault area includes:
[0022] The electrical equipment within the suspected fault area is divided into two sets, and the unmanageable combinations are identified from the two sets based on the improved particle swarm optimization algorithm to obtain the suspected faulty electrical equipment.
[0023] Secondly, embodiments of this application provide a secondary circuit fault detection device, wherein multiple secondary circuit nodes in a substation are respectively equipped with a lower-level machine module, the lower-level machine module being used to collect power parameters of the corresponding secondary circuit nodes, and the device comprising:
[0024] The sending module is used to send a secondary circuit fault detection command to the target lower-level machine module. The secondary circuit fault detection command indicates the target secondary circuit node and the sampled power parameters. The target secondary circuit node is the secondary circuit node that performs secondary circuit fault detection. The target lower-level machine module is the lower-level machine module equipped at the target secondary circuit node.
[0025] The acquisition module is used to acquire detection data returned by the target lower-level machine module in response to the secondary circuit fault detection command, and to acquire the connectivity status data between the target lower-level machine module and other target lower-level machine modules. The detection data includes the power parameters collected by the target secondary circuit node, and the connectivity status data is used to determine the current connectivity status between the target lower-level machine module and other target lower-level machine modules.
[0026] The generation module is used to generate a secondary circuit fault detection result for the secondary circuit fault detection command based on the detection data and the connectivity status data. The secondary circuit fault detection result includes the identified suspected fault areas and the suspected faulty electrical equipment within the suspected fault areas.
[0027] In one possible implementation, the generation module is specifically used for:
[0028] A connectivity matrix is constructed based on the connectivity status data returned by each target lower-level machine module. Each element in the connectivity matrix represents the connectivity status between any two lower-level machine modules.
[0029] For any target secondary circuit node, the power parameters extracted from the detection data and collected at the target secondary circuit node are compared with the power parameters collected at the target secondary circuit node under normal conditions to obtain the comparison result.
[0030] Based on the comparison results and the connectivity matrix, suspected fault regions are identified.
[0031] Identify suspected faulty electrical equipment from the suspected fault area to generate secondary circuit fault detection results in response to the secondary circuit fault detection command.
[0032] In one possible implementation, the generation module is specifically used for:
[0033] Based on the comparison results, an abnormal target lower-level machine module was identified;
[0034] Based on the connectivity matrix analysis, the communication paths between the abnormal target lower-level machine module and other target lower-level machine modules are analyzed to identify suspected fault areas.
[0035] In one possible implementation, the generation module is specifically used for:
[0036] If the difference between the power parameters collected at the target secondary circuit node extracted from the detection data and the power parameters collected at the target secondary circuit node under normal conditions is greater than a preset difference threshold, then the target lower-level machine module equipped at the target secondary circuit node is identified as the abnormal target lower-level machine module.
[0037] In one possible implementation, the secondary circuit fault detection device is further used for:
[0038] The suspected fault areas are sorted to generate a fault handling plan, which includes the order in which fault handling personnel will inspect each of the suspected fault areas.
[0039] In one possible implementation, the generation module is specifically used for:
[0040] The electrical equipment within the suspected fault area is divided into two sets, and the unmanageable combinations are identified from the two sets based on the improved particle swarm optimization algorithm to obtain the suspected faulty electrical equipment.
[0041] Thirdly, embodiments of this application provide a secondary circuit fault detection device, including: a memory and a processor;
[0042] The memory stores computer-executed instructions;
[0043] The processor executes computer execution instructions stored in the memory, causing the processor to perform the first aspect and / or various possible implementations of the first aspect as described above.
[0044] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the first aspect and / or various possible implementations of the first aspect.
[0045] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the first aspect and / or various possible implementations of the first aspect.
[0046] The secondary circuit fault detection method, apparatus, equipment, medium, and program products provided in this application embodiment are as follows: Multiple secondary circuit nodes in a substation are equipped with lower-level machine modules. These lower-level machine modules are used to collect the power parameters of the corresponding secondary circuit nodes. By sending a secondary circuit fault detection command to a target lower-level machine module, the detection data returned by the target lower-level machine module in response to the fault detection command and its connectivity status data with other target lower-level machine modules can be obtained. The process of sending the fault detection command and obtaining the detection data is automated, reducing manual intervention time and enabling rapid fault response. Combined with connectivity status data, the communication status between lower-level machine modules can be analyzed to help locate the fault propagation path and the scope of impact. This method, through real-time collection and analysis of power parameters and connectivity status data, achieves rapid and accurate detection and location of secondary circuit faults, thereby improving the efficiency and accuracy of secondary circuit fault detection and reducing the impact of faults on power system operation. Attached Figure Description
[0047] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0048] Figure 1 A schematic diagram of a scenario for the secondary circuit fault detection method provided in this application;
[0049] Figure 2 Flowchart of the secondary circuit fault detection method provided in this application Figure 1 ;
[0050] Figure 3 Flowchart of the secondary circuit fault detection method provided in this application Figure 2 ;
[0051] Figure 4 A schematic diagram of the secondary circuit fault detection device provided in this application;
[0052] Figure 5 This is a structural schematic diagram of the secondary circuit fault detection device provided in this application.
[0053] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation
[0054] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0055] During the construction or major overhaul of substations, secondary circuit fault detection is a crucial step in ensuring the safe and reliable operation of the power system. Secondary circuits are an important component of the power system, responsible for transmitting control and protection signals; their reliability directly affects the stability and security of the entire power system.
[0056] Traditional methods for detecting secondary circuit faults mainly rely on manual inspection and basic electrical testing instruments. This method has several significant limitations:
[0057] Manual inspection requires a large number of technicians to check each secondary circuit node one by one, which consumes a lot of human resources.
[0058] In large substations, there are numerous secondary circuit nodes, and manual inspection requires a significant amount of time and has a long inspection cycle.
[0059] Traditional methods rely on periodic manual inspections and cannot provide real-time monitoring data.
[0060] Due to the lack of real-time data support, fault location mainly relies on experience and limited test data, making it difficult to accurately pinpoint the fault location.
[0061] The secondary circuit fault detection method provided in this application equips multiple secondary circuit nodes in a substation with slave modules. These slave modules collect the power parameters of their respective secondary circuit nodes. By sending a secondary circuit fault detection command to a target slave module, the method obtains the detection data returned by the target slave module in response to that command, as well as its connectivity data with other target slave modules. This automated process of sending the fault detection command and acquiring the detection data reduces manual intervention time and enables rapid fault response. Combined with connectivity data, the communication status between slave modules can be analyzed, helping to locate the fault propagation path and its impact range. This method, through real-time collection and analysis of power parameters and connectivity data, achieves rapid and accurate detection and location of secondary circuit faults, solving the technical problems of low efficiency and low detection accuracy in traditional detection methods.
[0062] Figure 1This is a schematic diagram of a scenario for the secondary circuit fault detection method provided in this application, such as... Figure 1 As shown, the host computer module 101 is communicatively connected to multiple slave computer modules 102. The multiple slave computer modules 102 are deployed at multiple secondary circuit nodes in the substation to simultaneously collect the power parameters of multiple secondary circuit nodes. After the host computer module 101 obtains the detection data and connectivity data returned by the multiple slave computer modules 102, it analyzes and processes these data to automatically generate secondary circuit fault detection results.
[0063] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.
[0064] Figure 2 Flowchart of the secondary circuit fault detection method provided in this application Figure 1 ,like Figure 2 As shown, multiple secondary circuit nodes in the substation are each equipped with a lower-level machine module. The lower-level machine module is used to collect the power parameters of the corresponding secondary circuit nodes. The method includes:
[0065] S201. Send the secondary circuit fault detection command to the target lower-level machine module. The secondary circuit fault detection command indicates the target secondary circuit node and the sampled power parameters. The target secondary circuit node is the secondary circuit node for which secondary circuit fault detection is performed, and the target lower-level machine module is the lower-level machine module equipped at the target secondary circuit node.
[0066] The sampled power parameters may include at least one of voltage and current.
[0067] The secondary circuit fault detection instruction explicitly specifies the target secondary circuit node, i.e., the specific node to be detected for faults. The instruction also includes the electrical parameters to be sampled, such as voltage and current. These parameters are crucial indicators for identifying electrical faults. The target slave module is a device installed on the target secondary circuit node, responsible for executing instructions and collecting data.
[0068] S202. Obtain the detection data returned by the target lower-level module for the secondary circuit fault detection command, and obtain the connectivity status data between the target lower-level module and other target lower-level modules. The detection data includes the power parameters collected by the target secondary circuit node, and the connectivity status data is used to determine the current connectivity status between the target lower-level module and other target lower-level modules.
[0069] In this embodiment, detection data and connectivity data can be obtained from the target lower-level machine module. Detection data includes electrical parameters, such as voltage and current values, collected from the target secondary circuit nodes. Connectivity data reflects the communication status between the target lower-level machine module and other target lower-level machine modules. This helps to understand the connection status between modules and the stability of data transmission.
[0070] S203. Based on the detection data and connectivity status data, generate secondary circuit fault detection results for the secondary circuit fault detection command. The secondary circuit fault detection results include the identified suspected fault areas and the suspected faulty electrical equipment within the suspected fault areas.
[0071] Analyzing detection and connectivity data identifies abnormal power parameters and communication interruptions. It also identifies potential faulty areas, i.e., communication paths where faults may exist. Further identification of potentially faulty electrical equipment helps pinpoint the specific fault location.
[0072] The secondary circuit fault detection method provided in this application equips multiple secondary circuit nodes in a substation with a lower-level machine module. This lower-level machine module collects the power parameters of the corresponding secondary circuit node. By sending a secondary circuit fault detection command to a target lower-level machine module, the method obtains the detection data returned by the target lower-level machine module in response to the fault detection command, as well as its connectivity data with other target lower-level machine modules. The process of sending the fault detection command and obtaining the detection data is automated, reducing manual intervention time and enabling rapid fault response. Combined with the connectivity data, the communication status between lower-level machine modules can be analyzed, helping to locate the fault propagation path and its impact range. This method, through real-time collection and analysis of power parameters and connectivity data, achieves rapid and accurate detection and location of secondary circuit faults, thereby improving the efficiency and accuracy of secondary circuit fault detection and reducing the impact of faults on power system operation.
[0073] Figure 3 Flowchart of the secondary circuit fault detection method provided in this application Figure 2 ,like Figure 3 As shown, in this embodiment... Figure 2 Based on the embodiments, the secondary circuit fault detection method is described in detail. Multiple secondary circuit nodes in the substation are each equipped with a lower-level machine module, which is used to collect the power parameters of the corresponding secondary circuit nodes. The method includes:
[0074] S301. Send the secondary circuit fault detection command to the target lower-level machine module. The secondary circuit fault detection command indicates the target secondary circuit node and the sampled power parameters. The target secondary circuit node is the secondary circuit node for which secondary circuit fault detection is performed, and the target lower-level machine module is the lower-level machine module equipped at the target secondary circuit node.
[0075] Specifically, a secondary circuit fault detection system can be deployed on the host computer module. After the user clicks the "Start Detection" button, the system begins executing a preset test procedure and sends secondary circuit fault detection commands to the slave computer module. The slave computer module samples the voltage and current signals at the corresponding secondary circuit nodes, and can further acquire the amplitude, frequency, and phase of the voltage and current signals. The secondary circuit fault detection system provides multiple functional modules, allowing users to set the secondary circuit nodes to be detected and to set specific sampling power parameters. The secondary circuit fault detection system has a time synchronization function, which can be achieved by clicking the "Online Time Synchronization" button to synchronize the time between the host computer module and the slave computer module.
[0076] The testing process can be as follows:
[0077] 1. First, confirm the status of the lower-level module to ensure that communication between the upper-level module and the lower-level module is successfully established. When communication is successful, the connection status will be displayed as "online".
[0078] 2. Next, click the "Online Time Synchronization" button. At this time, the host computer module will synchronize its time with the slave computer module via the RS-485 communication protocol.
[0079] 3. After time synchronization is complete, click the "Start Detection" button to enter the detection state. Once the detection is complete, the test status will be updated to "Test Complete".
[0080] 4. After the test is completed, click the "Test Results" button to view the secondary circuit fault detection results.
[0081] S302. Obtain the detection data returned by the target lower-level module for the secondary circuit fault detection command, and obtain the connectivity status data between the target lower-level module and other target lower-level modules. The detection data includes the power parameters collected by the target secondary circuit node, and the connectivity status data is used to determine the current connectivity status between the target lower-level module and other target lower-level modules.
[0082] S303. Construct a connectivity matrix based on the connectivity status data returned by each target lower-level machine module. Each element in the connectivity matrix represents the connectivity status between any two lower-level machine modules.
[0083] By constructing a connectivity matrix, the communication relationships between various target lower-level machine modules can be easily analyzed. A connectivity matrix provides an effective way to analyze the communication network between lower-level machine modules. A connectivity matrix can be represented as follows:
[0084]
[0085] Where a ij This indicates the connectivity status between lower-level module i and lower-level module j; a ij =1 indicates that data transmission can be completed from lower-level module i to lower-level module j; a ij =0 indicates that data transmission from lower-level module i to lower-level module j cannot be completed; n is the number of lower-level modules involved in the current secondary circuit fault detection.
[0086] S304. For any target secondary circuit node, the power parameters extracted from the detection data and collected at the target secondary circuit node are compared with the power parameters collected at the target secondary circuit node under normal conditions to obtain the comparison result.
[0087] The current and voltage parameters of the secondary circuit node currently acquired are compared item by item with the reference parameters of the node under normal conditions. If the comparison results show that the current or voltage has deviated significantly, it may indicate that the node is faulty.
[0088] S305. Based on the comparison results and connectivity matrix, determine the suspected fault areas.
[0089] In one possible implementation, the suspected fault region is determined based on the comparison results and the connectivity matrix, which may specifically include:
[0090] Based on the comparison results, the abnormal target lower-level machine module was identified;
[0091] Based on connectivity matrix analysis, the communication paths between the abnormal target lower-level machine module and other target lower-level machine modules are analyzed to identify suspected fault areas.
[0092] By comparing the currently collected power parameters with the baseline parameters under normal conditions, target lower-level machine modules with significant parameter shifts are identified from multiple target lower-level machine modules. These modules are marked as abnormal target lower-level machine modules.
[0093] Connectivity matrix analysis is used to analyze the communication paths between the abnormal target lower-level machine module and other target lower-level machine modules. By analyzing these communication paths, the connection relationships between the abnormal target lower-level machine module and other target lower-level machine modules can be determined, thereby identifying potential fault areas.
[0094] In one possible implementation, identifying the abnormal target lower-level machine module based on the comparison results may specifically include:
[0095] If the difference between the power parameters collected at the target secondary circuit node extracted from the detection data and the power parameters collected at the target secondary circuit node under normal conditions is greater than a preset difference threshold, then the target lower-level machine module equipped at the target secondary circuit node will be identified as an abnormal target lower-level machine module.
[0096] The process of identifying abnormal target lower-level machine modules can be described as follows:
[0097]
[0098] Where i is the node number (i=1,…,n); These are the power parameters collected under normal conditions at the i-th node; This represents the power parameters currently collected at the i-th node; The preset difference threshold; This is the difference between the power parameters collected at the current node i and the power parameters collected at the node under normal conditions.
[0099] In one possible implementation, after analyzing the communication paths between the abnormal target lower-level machine module and other target lower-level machine modules based on the connectivity matrix to identify the suspected fault area, the secondary loop fault detection method of this application may further include:
[0100] The suspected fault areas are sorted and a fault handling plan is generated. The fault handling plan includes the order in which the fault handling personnel will inspect each suspected fault area.
[0101] For each suspected faulty area, the Skyline Query algorithm is applied for ranking. The Skyline Query algorithm is a multidimensional data analysis technique used to identify the "optimal" data points from a dataset that are not dominated by other data across all dimensions. In fault detection, this can be used to assess the severity, scope of impact, and difficulty of repair for each suspected faulty area. Based on the ranking results of the Skyline Query algorithm, a fault handling plan is generated. This plan prioritizes suspected faulty areas that exhibit higher priority across multiple dimensions, thereby optimizing resource allocation and repair sequence.
[0102] S306. Identify suspected faulty electrical equipment from the suspected fault area to generate secondary circuit fault detection results for the secondary circuit fault detection command. The secondary circuit fault detection results include the identified suspected fault area and the suspected faulty electrical equipment within the suspected fault area.
[0103] After identifying suspected fault areas, further analysis is conducted to identify specific suspected faulty electrical devices. Specifically, components within the fault area can be grouped into a suspected faulty component set. Within each suspected fault area, all relevant components can be included in this set. These components may include transformers, circuit breakers, relays, sensors, etc. Further analysis is performed on each component in the suspected faulty component set. This may involve examining the operating status of each component, historical fault records, real-time monitoring data, etc., to identify the most likely faulty component. Through analysis, the specific electrical devices most likely to cause the problem within the suspected faulty component set can be identified. These devices are marked as suspected faulty electrical devices.
[0104] In one possible implementation, identifying suspected faulty electrical equipment from the suspected fault area may specifically include:
[0105] The electrical equipment in the suspected fault area is divided into two sets, and the unmanageable combinations are identified from the two sets based on the improved particle swarm optimization algorithm to obtain the suspected faulty electrical equipment.
[0106] In this implementation, all electrical equipment within the suspected fault area can be divided into two sets. Within these sets, unmanageable combinations are identified. Unmanageable combinations are those where no other combination is significantly superior across multiple dimensions. This method is similar to a skyline query, aiming to identify equipment combinations that excel in certain key performance indicators. An improved particle swarm optimization (PSO) algorithm can be used to accelerate the solution process for massive numbers of combinations. PSO is a swarm intelligence-based optimization algorithm suitable for finding optimal solutions in complex search spaces.
[0107] The secondary circuit fault detection method provided in this application equips multiple secondary circuit nodes in a substation with a lower-level machine module. This lower-level machine module collects the power parameters of the corresponding secondary circuit node. By sending a secondary circuit fault detection command to a target lower-level machine module, the method obtains the detection data returned by the target lower-level machine module in response to the fault detection command, as well as its connectivity data with other target lower-level machine modules. The process of sending the fault detection command and obtaining the detection data is automated, reducing manual intervention time and enabling rapid fault response. Combined with the connectivity data, the communication status between lower-level machine modules can be analyzed, helping to locate the fault propagation path and its impact range. This method, through real-time collection and analysis of power parameters and connectivity data, achieves rapid and accurate detection and location of secondary circuit faults, thereby improving the efficiency and accuracy of secondary circuit fault detection and reducing the impact of faults on power system operation.
[0108] Figure 4This is a schematic diagram of the secondary circuit fault detection device provided in this application, as shown below. Figure 4 As shown, multiple secondary circuit nodes in the substation are each equipped with a lower-level machine module. The lower-level machine module is used to collect the power parameters of the corresponding secondary circuit nodes. The secondary circuit fault detection device 40 provided in this embodiment includes:
[0109] The sending module 401 is used to send the secondary circuit fault detection command to the target lower-level machine module. The secondary circuit fault detection command indicates the target secondary circuit node and the sampled power parameters. The target secondary circuit node is the secondary circuit node that performs secondary circuit fault detection, and the target lower-level machine module is the lower-level machine module equipped at the target secondary circuit node.
[0110] The acquisition module 402 is used to acquire the detection data returned by the target lower-level module for the secondary circuit fault detection command, and to acquire the connectivity status data between the target lower-level module and other target lower-level modules. The detection data includes the power parameters collected by the target secondary circuit node, and the connectivity status data is used to determine the current connectivity status between the target lower-level module and other target lower-level modules.
[0111] The generation module 403 is used to generate secondary circuit fault detection results based on detection data and connectivity status data for secondary circuit fault detection commands. The secondary circuit fault detection results include the identified suspected fault areas and the suspected faulty electrical equipment within the suspected fault areas.
[0112] In one possible implementation, the generation module is specifically used for:
[0113] A connectivity matrix is constructed based on the connectivity status data returned by each target lower-level machine module. Each element in the connectivity matrix represents the connectivity status between any two lower-level machine modules.
[0114] For any target secondary circuit node, the power parameters extracted from the detection data and collected at the target secondary circuit node are compared with the power parameters collected at the target secondary circuit node under normal conditions to obtain the comparison results.
[0115] Based on the comparison results and connectivity matrix, suspected fault regions were identified;
[0116] Identify suspected faulty electrical equipment from the suspected fault area to generate secondary circuit fault detection results for secondary circuit fault detection commands.
[0117] In one possible implementation, the generation module is specifically used for:
[0118] Based on the comparison results, the abnormal target lower-level machine module was identified;
[0119] Based on connectivity matrix analysis, the communication paths between the abnormal target lower-level machine module and other target lower-level machine modules are analyzed to identify suspected fault areas.
[0120] In one possible implementation, the generation module is specifically used for:
[0121] If the difference between the power parameters collected at the target secondary circuit node extracted from the detection data and the power parameters collected at the target secondary circuit node under normal conditions is greater than a preset difference threshold, then the target lower-level machine module equipped at the target secondary circuit node will be identified as an abnormal target lower-level machine module.
[0122] In one possible implementation, the secondary circuit fault detection device is further used for:
[0123] The suspected fault areas are sorted and a fault handling plan is generated. The fault handling plan includes the order in which the fault handling personnel will inspect each suspected fault area.
[0124] In one possible implementation, the generation module is specifically used for:
[0125] The electrical equipment in the suspected fault area is divided into two sets, and the unmanageable combinations are identified from the two sets based on the improved particle swarm optimization algorithm to obtain the suspected faulty electrical equipment.
[0126] The secondary circuit fault detection device provided in this embodiment can execute the method provided in the above method embodiment. Its implementation principle and technical effect are similar, and will not be described in detail here.
[0127] Figure 5 This is a structural schematic diagram of the secondary circuit fault detection device provided in this application. Figure 5 As shown, the secondary circuit fault detection device 50 provided in this embodiment includes at least one processor 501 and a memory 502. Optionally, the device 50 further includes a communication component 503. The processor 501, memory 502, and communication component 503 are connected via a bus.
[0128] In a specific implementation, at least one processor 501 executes computer execution instructions stored in memory 502, causing at least one processor 501 to perform the above-described method.
[0129] The specific implementation process of processor 501 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.
[0130] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.
[0131] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.
[0132] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.
[0133] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.
[0134] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.
[0135] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.
[0136] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.
[0137] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.
[0138] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0139] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0140] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0141] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.
[0142] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.
Claims
1. A method for detecting faults in a secondary circuit, characterized in that, The substation is equipped with multiple secondary circuit nodes, each equipped with a lower-level machine module. These lower-level machine modules are used to collect the power parameters of the corresponding secondary circuit nodes. The method includes: A secondary circuit fault detection command is sent to the target lower-level machine module. The secondary circuit fault detection command indicates the target secondary circuit node and the sampled power parameters. The target secondary circuit node is the secondary circuit node that performs secondary circuit fault detection. The target lower-level machine module is the lower-level machine module equipped at the target secondary circuit node. The system acquires detection data returned by the target lower-level machine module in response to the secondary circuit fault detection command, and acquires connectivity status data between the target lower-level machine module and other target lower-level machine modules. The detection data includes power parameters collected at the target secondary circuit node, and the connectivity status data is used to determine the current connectivity status between the target lower-level machine module and other target lower-level machine modules. Based on the detection data and the connectivity status data, a secondary circuit fault detection result is generated for the secondary circuit fault detection command. The secondary circuit fault detection result includes the identified suspected fault areas and the suspected faulty electrical equipment within the suspected fault areas.
2. The method according to claim 1, characterized in that, The step of generating a secondary circuit fault detection result based on the detection data and the connectivity status data in response to the secondary circuit fault detection command includes: A connectivity matrix is constructed based on the connectivity status data returned by each target lower-level machine module. Each element in the connectivity matrix represents the connectivity status between any two lower-level machine modules. For any target secondary circuit node, the power parameters extracted from the detection data and collected at the target secondary circuit node are compared with the power parameters collected at the target secondary circuit node under normal conditions to obtain the comparison result. Based on the comparison results and the connectivity matrix, suspected fault regions are identified. Identify suspected faulty electrical equipment from the suspected fault area to generate secondary circuit fault detection results in response to the secondary circuit fault detection command.
3. The method according to claim 2, characterized in that, The step of determining suspected fault regions based on the comparison results and the connectivity matrix includes: Based on the comparison results, an abnormal target lower-level machine module was identified; Based on the connectivity matrix analysis, the communication paths between the abnormal target lower-level machine module and other target lower-level machine modules are analyzed to identify suspected fault areas.
4. The method according to claim 3, characterized in that, The lower-level machine module that identifies abnormal targets based on the comparison results includes: If the difference between the power parameters collected at the target secondary circuit node extracted from the detection data and the power parameters collected at the target secondary circuit node under normal conditions is greater than a preset difference threshold, then the target lower-level machine module equipped at the target secondary circuit node is identified as the abnormal target lower-level machine module.
5. The method according to claim 3, characterized in that, After analyzing the communication paths between the abnormal target lower-level machine module and other target lower-level machine modules based on the connectivity matrix and identifying the suspected fault area, the method further includes: The suspected fault areas are sorted to generate a fault handling plan, which includes the order in which fault handling personnel will inspect each of the suspected fault areas.
6. The method according to claim 2, characterized in that, The step of identifying suspected faulty electrical equipment from the suspected fault area includes: The electrical equipment within the suspected fault area is divided into two sets, and the unmanageable combinations are identified from the two sets based on the improved particle swarm optimization algorithm to obtain the suspected faulty electrical equipment.
7. A secondary circuit fault detection device, characterized in that, The substation is equipped with multiple secondary circuit nodes, each equipped with a lower-level machine module. These lower-level machine modules are used to collect the power parameters of the corresponding secondary circuit nodes. The device includes: The sending module is used to send a secondary circuit fault detection command to the target lower-level machine module. The secondary circuit fault detection command indicates the target secondary circuit node and the sampled power parameters. The target secondary circuit node is the secondary circuit node that performs secondary circuit fault detection. The target lower-level machine module is the lower-level machine module equipped at the target secondary circuit node. The acquisition module is used to acquire detection data returned by the target lower-level machine module in response to the secondary circuit fault detection command, and to acquire the connectivity status data between the target lower-level machine module and other target lower-level machine modules. The detection data includes the power parameters collected by the target secondary circuit node, and the connectivity status data is used to determine the current connectivity status between the target lower-level machine module and other target lower-level machine modules. The generation module is used to generate a secondary circuit fault detection result for the secondary circuit fault detection command based on the detection data and the connectivity status data. The secondary circuit fault detection result includes the identified suspected fault areas and the suspected faulty electrical equipment within the suspected fault areas.
8. A secondary circuit fault detection device, characterized in that, include: Memory, processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory, causing the processor to perform the method as described in any one of claims 1-6.
9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1-6.
10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the method described in any one of claims 1-6.