Interface detection method, device, circuit, equipment, medium and product

Abstract

The invention provides an interface detection method, device, circuit and equipment, a medium and a product, and relates to the technical field of interfaces. The method comprises the following steps: acquiring state information of a target interface of the electronic equipment; based on the state information, determining whether a cable is inserted into the target interface; if it is determined that the cable is inserted, whether the target interface establishes a communication protocol conforming to a universal serial bus power transmission protocol with a protocol control chip or not is determined, and the current communication protocol state of the target interface is obtained; and if the communication protocol state represents that the to-be-charged external equipment exists, adjusting a grounding path of the target interface according to the communication protocol state. According to the invention, heat dissipation optimization during high-power charging is realized, and meanwhile, a cable detection function is reserved.

Description

Technical Field

[0001] This application relates to the field of interface technology, and in particular to an interface testing method, apparatus, circuit, device, medium and product. Background Technology

[0002] With the widespread adoption of USB Type-C (USB C) interfaces, their applications are becoming increasingly diverse, making them a standard feature in devices such as laptops, monitors, and power banks. USB C supports high-speed data transfer and high-power charging, and is commonly used in devices like monitors to simultaneously provide power and data transfer. However, in high-power charging scenarios, power management and heat dissipation of the USB C interface and related cables become crucial considerations to ensure stable and reliable device operation. To more effectively manage power consumption and heat dissipation, accurately identifying the connection status of the USB C cable and optimizing charging strategies accordingly is essential.

[0003] Currently, the common method for detecting USB-C female connector cables involves modifying one of the four ground pins specified in the USB protocol, reusing it as a detection pin. Specifically, this involves disconnecting the direct connection between this ground (GND) pin and the motherboard ground pin, and connecting it to a general-purpose input / output (GPIO) pin of the microcontroller unit (MCU) via a pull-up resistor. When the USB-C cable is inserted into the female connector, the cable's internal ground pin connects to this modified pin on the female connector, pulling the voltage of the detection pin low. The MCU can then determine whether the cable is inserted by monitoring this voltage change. However, this method results in a significant increase in heat generation. Summary of the Invention

[0004] This application provides interface detection methods, apparatus, circuits, devices, media, and products to optimize heat dissipation during high-power charging while retaining cable detection functionality.

[0005] Firstly, this application provides an interface detection method, including:

[0006] Obtain the status information of the target interface of the electronic device;

[0007] Based on the status information, determine whether a cable is inserted into the target interface;

[0008] If a cable insertion is confirmed, determine whether the target interface has established a communication protocol that conforms to the Universal Serial Bus Power Transmission Protocol with the protocol control chip, and obtain the current communication protocol status of the target interface. The communication protocol status is used to characterize whether there is an external device to be charged.

[0009] If the communication protocol status indicates the presence of an external device to be charged, adjust the grounding path of the target interface according to the communication protocol status.

[0010] In one possible implementation, adjusting the grounding path of the target interface according to the communication protocol state includes:

[0011] Based on the communication protocol state, generate control signals corresponding to the communication protocol state;

[0012] Adjust the grounding path of the target interface based on the control signal.

[0013] In one possible implementation, adjusting the grounding path of the target interface based on a control signal includes:

[0014] Based on the control signal, the conduction state of the control logic switch is adjusted to adjust the grounding path of the target interface.

[0015] In one possible implementation, the logic switch is an NMOS transistor, and the conduction state of the logic switch is controlled based on a control signal to adjust the ground path of the target interface, including:

[0016] When the control signal is high, the gate voltage of the NMOS transistor is higher than the source voltage, and the current path between the drain and source of the NMOS transistor is turned on so that the target interface is connected to the ground pin of the motherboard circuit.

[0017] When the control signal is low, the gate voltage of the NMOS transistor is lower than the source voltage, cutting off the current path between the drain and source so that the target interface is connected to the microcontroller unit (MCU) through a pull-up resistor.

[0018] In one possible implementation, the communication protocol state is determined in the following way:

[0019] The protocol control chip is used to identify the master / slave roles of electronic devices and negotiate the charging protocol to obtain the communication protocol status. The protocol control chip is at least one of the following: a microcontroller unit that integrates a Universal Serial Bus Power Transfer Protocol stack, a power transfer protocol controller, or other integrated circuits used to negotiate and process the Universal Serial Bus protocol and the power transfer protocol.

[0020] In one possible implementation, before acquiring the status information of the target interface of the electronic device, the method further includes:

[0021] Select one of the multiple ground pins of the electronic device as the cable detection pin of the target interface, and configure the remaining pins of the multiple ground pins as grounding functions.

[0022] Secondly, this application provides an interface detection device, comprising:

[0023] The acquisition module is used to acquire the status information of the target interface of the electronic device.

[0024] The determination module is used to determine whether a cable is inserted into the target interface based on the status information; and if it is determined that a cable is inserted, it determines whether the target interface has established a communication protocol that conforms to the Universal Serial Bus Power Transmission Protocol with the protocol control chip, and obtains the current communication protocol status of the target interface, wherein the communication protocol status is used to characterize whether there is an external device to be charged.

[0025] The adjustment module is used to adjust the grounding path of the target interface according to the communication protocol status if the communication protocol status indicates the presence of an external device to be charged.

[0026] In one possible implementation, the adjustment module is specifically used for:

[0027] Based on the communication protocol state, generate control signals corresponding to the communication protocol state;

[0028] Adjust the grounding path of the target interface based on the control signal.

[0029] In one possible implementation, the adjustment module is specifically used for:

[0030] Based on the control signal, the conduction state of the control logic switch is adjusted to adjust the grounding path of the target interface.

[0031] In one possible implementation, the logic switch is an NMOS transistor, and the adjustment module is specifically used for:

[0032] When the control signal is high, the gate voltage of the NMOS transistor is higher than the source voltage, and the current path between the drain and the source is turned on so that the target interface is connected to the ground pin of the motherboard circuit.

[0033] When the control signal is low, the gate voltage of the NMOS transistor is lower than the source voltage, cutting off the current path between the drain and source so that the target interface is connected to the microcontroller unit (MCU) through a pull-up resistor.

[0034] In one possible implementation, the communication protocol state is determined in the following way:

[0035] The protocol control chip is used to identify the master / slave roles of electronic devices and negotiate the charging protocol to obtain the communication protocol status. The protocol control chip is at least one of the following: a microcontroller unit that integrates a Universal Serial Bus Power Transfer Protocol stack, a power transfer protocol controller, or other integrated circuits used to negotiate and process the Universal Serial Bus protocol and the power transfer protocol.

[0036] In one possible implementation, a processing module is also included, which is specifically used for:

[0037] Select one of the multiple ground pins of the electronic device as the cable detection pin of the target interface, and configure the remaining pins of the multiple ground pins as grounding functions.

[0038] Thirdly, this application provides a switching circuit applied to an electronic device as described in the first aspect and / or various possible embodiments of the first aspect. The electronic device includes a target interface, and the switching circuit includes: a protocol control chip, a logic switch, motherboard circuitry, pull-up resistors, pull-down resistors, and an MCU; wherein,

[0039] The logic switch includes a control terminal, a first conducting terminal, and a second conducting terminal. The control terminal is connected to the protocol control chip, the first conducting terminal is connected to the cable detection pin of the target interface, and the second conducting terminal is connected to the ground pin of the motherboard circuit. The control terminal is connected to the first end of a pull-down resistor, which is also connected to the general-purpose input / output (GPIO) port of the protocol control chip. The second end of the pull-down resistor is grounded. The cable detection pin of the target interface is connected to the MCU through a pull-up resistor.

[0040] Protocol control chip, used to control the conduction state of logic switches;

[0041] When the conduction state characterization logic switch is in the conduction state, the first conduction terminal is connected to the second conduction terminal;

[0042] When the logic switch representing the conduction state is in the off state, the first conduction terminal and the second conduction terminal are cut off.

[0043] Fourthly, this application provides an electronic device, including: a memory and a processor;

[0044] The memory stores the instructions that the computer executes;

[0045] The processor executes computer execution instructions stored in memory, causing the processor to perform the first aspect and / or various possible implementations of the first aspect as described above.

[0046] Fifthly, this application provides a computer-readable storage medium storing computer-executable instructions, which, when executed, are used to implement the first aspect and / or various possible embodiments of the first aspect.

[0047] In a sixth aspect, this application provides a computer program product, including a computer program that, when executed, implements the first aspect and / or various possible implementations of the first aspect.

[0048] This application provides an interface detection method, apparatus, circuit, device, medium, and product, relating to the field of interface technology. The method includes acquiring the status information of a target interface of an electronic device; determining, based on the status information, whether a cable is inserted into the target interface; if a cable is inserted, determining whether the target interface has established a communication protocol conforming to the Universal Serial Bus Power Transfer Protocol (USB Power Transfer Protocol) with the protocol control chip, obtaining the current communication protocol status of the target interface, wherein the communication protocol status is used to indicate whether an external device to be charged exists; if the communication protocol status indicates the presence of an external device to be charged, adjusting the grounding path of the target interface according to the communication protocol status. This application determines whether a cable is inserted into the target interface by real-time monitoring of the target interface's status information; and after determining that a cable is inserted, further determining whether the target interface has established a communication protocol conforming to USB Power Transfer Protocol (USB Power Transfer Protocol) with the protocol control chip, and obtaining the current communication protocol status of the target interface based on the determination result. The communication protocol status is used to determine whether there is a current charging demand, i.e., whether there is an external device to be charged; when the communication protocol status indicates the presence of an external device to be charged, adjusting the grounding path of the target interface according to the communication protocol status. This method of jointly judging through status information and communication protocol status can prevent grounding path switching errors due to misjudgment, ensuring accurate matching between cable detection function and charging demand. In summary, the above method directly resolves the conflict between grounding path redundancy and cable detection function. By dynamically adjusting the grounding path, heat dissipation optimization is achieved during high-power charging, while retaining the cable detection function. Attached Figure Description

[0049] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0050] Figure 1 A schematic diagram showing the layout of the four grounding pins provided in an embodiment of this application;

[0051] Figure 2 A schematic diagram of the pin layout of a USB-C cable male connector provided in an embodiment of this application;

[0052] Figure 3 A flowchart illustrating the interface detection method provided in this application embodiment;

[0053] Figure 4 This is a schematic diagram of a USB C cable detection function circuit configuration provided in an embodiment of this application;

[0054] Figure 5 A schematic diagram of the switching circuit provided in an embodiment of this application;

[0055] Figure 6This is a schematic diagram of the interface detection device provided in the embodiments of this application;

[0056] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0057] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0058] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0059] In existing technical solutions, a common method for detecting USB-C female connector cables is to use one of the four ground pins (A1, A2, B1, B12) specified in the USB protocol as the cable detection pin. The specific implementation is as follows: First, select a ground pin (e.g., A1) and disconnect it from the motherboard's ground. Then, instead of using this selected pin as a traditional ground terminal, connect it to the MCU's GPIO port via a series pull-up resistor. The layout of the four ground pins is shown in [reference needed]. Figure 1 , Figure 1 This is a schematic diagram showing the layout of the four grounding pins provided in an embodiment of this application.

[0060] When a USB-C male cable is plugged into a USB-C female connector, the cable's internal ground is electrically connected to the female connector's ground. See the pin layout diagram of the USB-C male connector for details. Figure 2 , Figure 2 This is a schematic diagram of the pin layout of a USB C cable male connector provided in an embodiment of this application.

[0061] Because the ground wire of a USB-C cable is internally continuous, the ground pin, which is originally used for cable detection, will have its voltage pulled down to 0V through the cable's ground connection. At this time, the voltage at the GPIO port connected to this pin will change from high to low. The MCU can detect this voltage change to determine that the USB-C cable has been successfully inserted.

[0062] In summary, the USB protocol specifies four ground pins in the design of the USB-C interface to ensure good connection and signal integrity. However, in the above scheme, one of the ground pins is configured as a cable detection function pin.

[0063] This design would use a pin that was originally intended for grounding connection for cable detection, thus occupying a grounding pin that was originally intended for connecting cables.

[0064] With the widespread adoption of USB-C interfaces and the continuous improvement of charging power, the drawbacks of using a ground pin for cable detection have become increasingly apparent. This is because, in a cable, the primary function of the ground pin is to form a complete current loop together with the positive power supply (VBUS). Current flows from VBUS into the load, performs its work, and then needs to flow back to the power supply through the ground pin to complete the loop. Therefore, the ground pin needs to carry a current equal to the load current. The heat generated is essentially Joule heat due to the resistance of the current flowing through the ground path, as expressed by the formula: Q=I 2 Rt.

[0065] Furthermore, in a USB-C female connector, if one of the ground pins is used for cable detection, then of the four ground pins originally designed to carry current, only three (and the connected cable ground pin) can actually share the load current. According to the parallel resistance formula, if n identical resistors are connected in parallel, then the total resistance = single resistance / n. Assuming that the sum of the internal resistances of each ground pin on the USB-C female connector and the connected cable ground pins is the same, then the total internal resistance is R. total =R single / 3, at this point the total heating power is P=I 2 R single / 3. In contrast, the total power generated by the configuration of four ground pins is P=I 2 R single / 4. Therefore, it can be concluded that the total heat generation of ground pin 3 is more severe than that of ground pin 4.

[0066] Therefore, configuring one of the four ground pins specified by the USB protocol in the USB-C female connector as a cable detection pin will lead to overheating issues. This design flaw has been confirmed in practice. For example, some display ODM manufacturers have encountered this type of overheating problem caused by improper GND pin configuration when designing devices that support 140W charging.

[0067] To address the aforementioned issues, this application dynamically adjusts the grounding path configuration of the target interface. While retaining the cable detection function, it dynamically switches the redundancy of the grounding path according to the communication protocol status. This maintains the detection function when charging is not required and restores the complete grounding path of the four grounding pins when charging is needed, thereby reducing interface heat generation.

[0068] This application applies to electronic devices requiring high-power charging (e.g., 140W and above) and dynamic identification of cable connection status, such as monitors, laptops, and power banks. In these devices, the USB-C interface must simultaneously meet the requirements of cable insertion detection, device charging status identification, and high-power current return.

[0069] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0070] Figure 3 This is a flowchart illustrating the interface detection method provided in the embodiments of this application, as shown below. Figure 3 As shown, the method includes:

[0071] S301. Obtain the status information of the target interface of the electronic device.

[0072] This step is the data source for the entire interface testing process. The target interface refers to the physical port that needs to be tested for plugging and unplugging, such as a USB-C female connector. The status information encompasses raw data reflecting the current physical or electrical characteristics of the interface. By performing real-time status monitoring of the target interface, such as level sampling or current monitoring, basic parameters can be obtained, thus providing an objective basis for subsequent logical judgments.

[0073] Furthermore, before acquiring the status information of the target interface of the electronic device, the process includes: selecting one of the multiple ground pins of the electronic device as the cable detection pin of the target interface, configuring the target interface for cable detection, and configuring the remaining ground pins for grounding. This means that before detecting the status information of the target interface, one ground pin is selected as the cable detection pin of the target interface based on the charging requirements, and the remaining ground pins are configured for grounding. For example, when there is an external charging requirement, GND1 is selected as the cable detection pin, and GND2, GND3, and GND4 are all configured for grounding. By dynamically allocating the ground pin functions, it is ensured that all ground pins participate in the current loop at any time, avoiding the increase in internal resistance and heat generation caused by fixed occupation of a certain pin, thus improving the compatibility and adaptability of the interface and optimizing resource utilization.

[0074] S302. Based on the status information, determine whether a cable is inserted into the target interface.

[0075] After determining the status information, the logic needs to be transitioned to cable connection determination. Step S102 implements this logical transformation from physical signals to cable connection determination. Specifically, this involves threshold comparison or logical analysis of the status information. For example, when the cable detection pin level of the target interface changes from high to low and stabilizes within a preset range, it can be determined that a cable is inserted into the target interface. Furthermore, the status information may also include voltage change information and current change information. This embodiment does not limit the status information; it is merely an example.

[0076] This step achieves higher system stability by providing multiple connection status detection methods. For example, voltage change detection is suitable for low-noise environments, while current change detection is suitable for high-noise environments. The two methods are redundant to avoid misjudgment of cable insertion status due to the failure of a single detection method.

[0077] This design significantly improves the reliability of the interface under complex electromagnetic interference or hardware aging scenarios, ensuring the accuracy of charging protocol negotiation and grounding path switching.

[0078] Figure 4 This is a schematic diagram of a USB-C cable detection function circuit configuration provided in an embodiment of this application. Figure 4 As shown, B12 is used as the cable detection pin of the target interface, and B12 is connected to the MCU port through a series pull-up resistor.

[0079] S303. If it is determined that a cable is inserted, determine whether the target interface has established a communication protocol that conforms to the Universal Serial Bus Power Transmission Protocol with the protocol control chip, and obtain the communication protocol status of the target interface. The communication protocol status is used to characterize whether there is an external device to be charged.

[0080] After confirming the existence of a physical connection, this embodiment of the application does not blindly initiate the charging logic, but further probes whether there are any external devices to be charged. The determination of external devices to be charged is based on the current communication protocol status of the target interface.

[0081] For example, the communication protocol state is determined by the following method: the electronic device is identified as master / slave and the charging protocol is negotiated through a protocol control chip to obtain the communication protocol state. The protocol control chip is at least one of a microcontroller unit that integrates a Universal Serial Bus Power Transfer Protocol stack, a power transfer protocol controller, or other integrated circuits used for negotiating and processing the Universal Serial Bus protocol and the power transfer protocol.

[0082] In this example, it can be seen that this embodiment of the application utilizes a protocol control chip (such as a PD IC) to communicate deeply with the configuration channel (such as the CC pin) in the USB-C cable. One end of the USB-C cable is used to connect to the protocol control chip, and the other end is used to connect to the external device to be charged. The PD IC performs a bidirectional signal handshake with the access device according to the USB PD protocol specification, performing master-slave role identification to determine whether the device is currently acting as a power supply or a power receiver. Subsequently, both parties negotiate the charging protocol through the CC pin, exchanging the voltage and current parameter levels they support. When this protocol interaction based on the CC pin is successfully completed, and both parties reach a consensus on the power allocation scheme, it can be determined that a legitimate USB device has been inserted, and that USB device can be identified as the external device to be charged.

[0083] This application embodiment, through the protocol handshake of the protocol control chip, can eliminate false accesses that only have physical connections but no data or power interaction requirements, thereby providing an accurate basis for subsequent targeted heat reduction operations.

[0084] S304. If the communication protocol status indicates the presence of an external device to be charged, adjust the grounding path of the target interface according to the communication protocol status.

[0085] Based on the communication protocol status, the grounding path of the target interface is adjusted. Traditional detection methods result in a loop formed by the remaining three grounding pins and the charging current traces when a large charging current flows through the interface. In fact, current flowing through any resistive conductor generates heat, which can be calculated using Joule's law, expressed as Q=I²Rt. Therefore, the equivalent resistance of the loop generates heat, and the equivalent resistance of the loop formed by three grounding pins is greater than that of the loop formed by four grounding pins. This embodiment dynamically adjusts the grounding path of the target interface based on the communication protocol status. Upon confirming entry into the charging protocol state, it proactively adds a loop to the restored grounding pins, cutting off the power consumption path that generates additional heat.

[0086] This embodiment monitors the target interface's status information in real time and determines whether a cable is inserted based on this information. After confirming a cable insertion, it further determines whether the target interface has established a communication protocol conforming to the Universal Serial Bus Power Transmission Protocol (USB-PTP) with the protocol control chip. The current communication protocol status of the target interface is obtained based on this determination, and this status is used to determine whether there is a charging requirement, i.e., whether an external device to be charged is present. When the communication protocol status indicates the presence of an external device to be charged, the grounding path of the target interface is adjusted accordingly. This method, using both status information and communication protocol status for joint judgment, prevents incorrect grounding path switching due to misjudgment, ensuring accurate matching between cable detection and charging requirements. In summary, this approach directly resolves the conflict between grounding path redundancy and cable detection functionality. By dynamically adjusting the grounding path, heat dissipation optimization during high-power charging is achieved, while retaining the cable detection function.

[0087] Based on the above embodiments, adjusting the grounding path of the target interface according to the communication protocol state includes: generating a control signal corresponding to the communication protocol state based on the communication protocol state; and adjusting the grounding path of the target interface based on the control signal.

[0088] In this embodiment, it can be understood that the control signal is determined according to the communication protocol state. For example, a high-level control signal is generated when an external device to be charged is detected, and a low-level control signal is generated when no external device to be charged is detected. The generated control signal will be used to adjust the grounding path of the target interface. Furthermore, there are various specific implementation methods for adjusting the grounding path of the target interface using the generated control signal.

[0089] In one implementation, adjusting the grounding path of the target interface based on a control signal includes: controlling the on / off state of a logic switch based on the control signal to adjust the grounding path of the target interface.

[0090] In this implementation, the control signal is used to control the on or off state of the logic switch. A logic switch, such as an NMOS transistor, is an electronic switching device that is turned on or off by the high or low level state of a control signal.

[0091] By controlling the on or off states of the logic switches, the grounding path can be dynamically switched, ensuring that the redundant grounding path is restored when charging is needed and the detection function is maintained when charging is not needed, thus significantly reducing the heat generation problem of the target interface.

[0092] Furthermore, by controlling the on or off state of the logic switch, the grounding path can be quickly adjusted, avoiding delays caused by mechanical switches or complex circuits.

[0093] Taking an NMOS transistor as an example, this section explains how to adjust the ground path. Specifically, when the logic switch is an NMOS transistor, the conduction state of the logic switch is controlled based on a control signal to adjust the ground path of the target interface. This includes: when the control signal is high, the gate voltage of the NMOS transistor is controlled to be higher than the source voltage, thus conducting the current path between the drain and source to connect the target interface to the ground pin of the motherboard; when the control signal is low, the gate voltage of the NMOS transistor is controlled to be lower than the source voltage, thus cutting off the current path between the drain and source to connect the target interface to the microcontroller unit (MCU) through a pull-up resistor. Here, the gate voltage refers to the control terminal voltage of the NMOS transistor, which determines the on or off state of the NMOS transistor.

[0094] In this example, when the protocol control chip outputs a high-level control signal, the gate voltage of the NMOS transistor is boosted to a level higher than the source voltage, turning the NMOS transistor on. This connects the current path between the target interface and the motherboard ground pin, thus increasing the grounding loop. For example, when one of the multiple ground pins of the electronic device is selected as the cable detection pin of the target interface and the NMOS transistor is on, the current path between the cable detection pin and the motherboard ground pin is connected, and the cable detection pin is switched to grounding function. When the protocol control chip outputs a low-level control signal, the gate voltage of the NMOS transistor is pulled down to a level lower than the source voltage, turning the NMOS transistor off. The target interface is then connected to the MCU via a pull-up resistor. For example, when one of the multiple ground pins of the electronic device is selected as the cable detection pin of the target interface and the NMOS transistor is off, the cable detection pin is connected to the MCU via a pull-up resistor, thus maintaining the cable detection function of the cable detection pin.

[0095] Furthermore, it can be understood that the target interface provides a reference high voltage to the microcontroller when no cable (such as a type-C cable) is connected through a parallel pull-up resistor, in order to identify whether a cable is inserted that causes the line reference voltage to be pulled low.

[0096] This application embodiment achieves low power consumption and high response characteristics of the logic switch by controlling the gate voltage of the NMOS transistor. The NMOS transistor should be selected with low on-resistance to effectively reduce the internal resistance of the current loop and minimize heat generation. Simultaneously, its fast switching characteristics improve the real-time performance of interface function switching. In other words, the selection of the NMOS transistor is based on the on-state current of its source and drain. Specifically, NMOS transistors with higher current carrying capacity and lower on-resistance exhibit better performance in the on-state and are more suitable for this application embodiment.

[0097] Furthermore, this application embodiment also provides a switching circuit applied to the electronic devices described in the above embodiments. The electronic device includes a target interface, and the switching circuit includes: a protocol control chip, a logic switch, a motherboard circuit, a pull-up resistor, a pull-down resistor, and an MCU. The logic switch includes a control terminal, a first conducting terminal, and a second conducting terminal. The control terminal is connected to the protocol control chip, the first conducting terminal is connected to the cable detection pin of the target interface, the second conducting terminal is connected to the ground pin of the motherboard circuit, the control terminal is connected to the first end of the pull-down resistor, the first end is connected to the general-purpose input / output port of the protocol control chip, and the second end of the pull-down resistor is grounded. The cable detection pin of the target interface is connected to the MCU through the pull-up resistor. The protocol control chip is used to control the conduction state of the logic switch. When the conduction state indicates that the logic switch is conducting, the first conducting terminal and the second conducting terminal are connected; when the conduction state indicates that the logic switch is cut off, the first conducting terminal and the second conducting terminal are cut off.

[0098] Figure 5 This is a schematic diagram of a switching circuit provided in an embodiment of this application. Figure 5 This is a schematic diagram of a switching circuit using an NMOS transistor as the logic switch and the cable detection pin B12 of the target interface as an example. Figure 5 As shown, the first conducting terminal D of the NMOS transistor is connected to B12, the second conducting terminal S of the NMOS transistor is connected to the ground pin of the motherboard circuit, the control terminal G of the NMOS transistor is connected to the first terminal of the pull-down resistor, and the first terminal is also connected to the general purpose input / output port (PD_GPIO) pin of the protocol control chip. The second terminal of the pull-down resistor is grounded. The pull-up resistor is connected to a voltage of 5V or 3.3V (VCC) to provide a reference high voltage to the MCU GPIO for detecting whether the voltage of this line is pulled to 0V by the ground pin of the connected cable.

[0099] The following combination Figure 5 The interface detection circuit shown is explained in detail, illustrating the application of this method and its implementation process for dynamic function switching. This method achieves dynamic function switching through the following process:

[0100] Cable insertion detection: The MCU monitors the voltage of B12 in the USB-C female connector in real time via GPIO. When a cable is inserted, the voltage of B12 is pulled down to a low level, and the MCU triggers a cable insertion event.

[0101] Communication status determination: The protocol control chip communicates with the cable via the CC pin to determine whether the cable is connected to the load device. If communication is successful (e.g., a charging request is detected), the PD IC generates a high-level control signal. The control protocol chip can be an MCU, a PD IC, or other integrated circuits that integrate USB and PD protocol communication functions.

[0102] Grounding path adjustment: A high-level signal drives the NMOS transistor to conduct, connecting B12 to the motherboard ground, forming a complete current loop; if communication fails (e.g., no device charging requirement is detected), the NMOS transistor remains off, and B12 is connected to the MCU through a pull-up resistor to maintain the cable detection (cable_DET) function. It should be noted that when communication fails, this embodiment will not perform a charging action, i.e., Vbus is not provided.

[0103] Dynamic switching: When the cable is unplugged, the MCU re-detects the B12 voltage, the PD IC resets the communication state, the NMOS transistor returns to the default off state, and B12 is used again for cable detection function switching.

[0104] In summary, this embodiment achieves a dynamic balance between cable insertion detection and current loop optimization by dynamically adjusting the electrical function of the ground pin in the USB-C interface. Specifically, by utilizing the coordinated control of a protocol control chip (such as a PD IC) and logic switches (such as NMOS transistors), after detecting cable insertion, the function of the target interface is dynamically switched according to whether the cable is connected to a load device: when the cable is not connected to a load, the target interface maintains the cable detection function; when the cable is connected to a load device, the logic switch restores the target interface to part of a complete current loop, thereby reducing interface heat generation.

[0105] In other words, the above concept solves the heat generation problem caused by the fixed occupation of the grounding pin in the prior art by introducing a function switching mechanism, while retaining the cable detection capability.

[0106] Furthermore, the detection circuit provided in this application embodiment has advantages such as simple structure, intuitive indication, and strong versatility. Through the reasonable application of this circuit, the need for additional heat dissipation components can be effectively reduced, thereby optimizing hardware costs and ensuring a fast system response speed.

[0107] Figure 6 This is a schematic diagram of the interface detection device provided in the embodiments of this application, as shown below. Figure 6 As shown, the interface detection device provided in this embodiment includes:

[0108] The acquisition module 601 is used to acquire the status information of the target interface of the electronic device;

[0109] The determination module 602 is used to determine, based on the status information, whether a cable is inserted into the target interface; and, if it is determined that a cable is inserted, whether the target interface has established a communication protocol conforming to the Universal Serial Bus Power Transmission Protocol with the protocol control chip, and obtain the current communication protocol status of the target interface, wherein the communication protocol status is used to characterize whether there is an external device to be charged.

[0110] The adjustment module 603 is used to adjust the grounding path of the target interface according to the communication protocol status if the communication protocol status indicates that there is an external device to be charged.

[0111] In one possible implementation, the adjustment module 603 is specifically used for:

[0112] Based on the communication protocol state, generate control signals corresponding to the communication protocol state;

[0113] Adjust the grounding path of the target interface based on the control signal.

[0114] In one possible implementation, the adjustment module 603 is specifically used for:

[0115] Based on the control signal, the conduction state of the control logic switch is adjusted to adjust the grounding path of the target interface.

[0116] In one possible implementation, the logic switch is an NMOS transistor, and the adjustment module 603 is specifically used for:

[0117] When the control signal is high, the gate voltage of the NMOS transistor is higher than the source voltage, and the current path between the drain and the source is turned on so that the target interface is connected to the ground pin of the motherboard circuit.

[0118] When the control signal is low, the gate voltage of the NMOS transistor is lower than the source voltage, cutting off the current path between the drain and source so that the target interface is connected to the microcontroller unit (MCU) through a pull-up resistor.

[0119] In one possible implementation, the communication protocol state is determined in the following way:

[0120] The protocol control chip is used to identify the master / slave roles of electronic devices and negotiate the charging protocol to obtain the communication protocol status. The protocol control chip is at least one of the following: a microcontroller unit that integrates a Universal Serial Bus Power Transfer Protocol stack, a power transfer protocol controller, or other integrated circuits used to negotiate and process the Universal Serial Bus protocol and the power transfer protocol.

[0121] In one possible implementation, a processing module (not shown) is also included, which is specifically used for:

[0122] Select one of the multiple ground pins of the electronic device as the cable detection pin of the target interface, and configure the remaining pins of the multiple ground pins as grounding functions.

[0123] The interface detection device provided in this embodiment can execute the method provided in the above method embodiment. Its implementation principle and technical effect are similar, and will not be described in detail here.

[0124] It should be noted that the division of the various modules in the above device is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, these modules can be implemented entirely in software via processing element calls; they can be fully implemented in hardware; or some modules can be implemented by processing element calls to software, while others are implemented in hardware. For example, a processing module can be a separate processing element, or it can be integrated into an integrated circuit within the above device. Alternatively, it can be stored as program code in the device's memory, and its functions can be called and executed by a processing element. The implementation of other modules is similar. Moreover, these modules can be fully or partially integrated together, or they can be implemented independently. The processing element here can be an integrated circuit with signal processing capabilities. During implementation, each step of the above method or each of the above modules can be completed through integrated logic circuits in the hardware of the processor element or through software instructions.

[0125] For example, these modules can be one or more integrated circuits configured to implement the above methods, such as one or more Application Specific Integrated Circuits (ASICs), one or more Digital Signal Processors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs). As another example, when a module is implemented by calling program code through a processing element, that processing element can be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. Furthermore, these modules can be integrated together to implement a System-On-a-Chip (SOC).

[0126] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 7 As shown, the electronic device 700 provided in this application embodiment may include: a processor 701, and a memory 702 communicatively connected to the processor, wherein:

[0127] The memory stores the instructions that the computer executes;

[0128] The processor executes computer execution instructions stored in memory to implement the method described in the foregoing method embodiments.

[0129] It should be understood that processor 701 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the application can be directly manifested as execution by a hardware processor, or execution by a combination of hardware and software modules within the processor. Memory 702 may include high-speed random access memory (RAM), and may also include non-volatile memory (NVM), such as at least one disk storage device, or a USB flash drive, external hard drive, read-only memory, disk, or optical disc, etc.

[0130] Optionally, the electronic device 700 may also include a communication interface 703. In specific implementations, if the communication interface 703, memory 702, and processor 701 are implemented independently, they can be interconnected via a bus to complete communication. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc., but this does not imply that there is only one bus or one type of bus.

[0131] Optionally, in a specific implementation, if the communication interface 703, memory 702, and processor 701 are integrated on a single integrated circuit, then the communication interface 703, memory 702, and processor 701 can communicate through an internal interface.

[0132] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed, are used to implement the methods described in any of the foregoing embodiments.

[0133] It is understood that the computer-readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Read Only Memory (PROM), Read Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0134] An exemplary computer-readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the computer-readable storage medium. Of course, the computer-readable storage medium can also be a component of the processor. The processor and the computer-readable storage medium can reside in an ASIC. Alternatively, the processor and the computer-readable storage medium can exist as discrete components in an electronic device.

[0135] The integrated modules implemented as software functional modules described above can be stored in a computer-readable storage medium. These software functional modules, stored in a computer-readable storage medium, include several instructions to cause an electronic device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods described in the various embodiments of this application.

[0136] This application also provides a computer program product, including a computer program that, when executed, implements the method described in any of the foregoing embodiments.

[0137] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this application.

[0138] It should be further noted that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0139] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments have been described. However, as long as these combinations of technical features do not contradict each other, they should be considered within the scope of this specification.

[0140] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0141] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. An interface detection method, characterized in that, include: Obtain the status information of the target interface of the electronic device; Based on the status information, determine whether a cable is inserted into the target interface; If a cable insertion is confirmed, determine whether the target interface has established a communication protocol that conforms to the Universal Serial Bus Power Transmission Protocol with the protocol control chip, and obtain the current communication protocol status of the target interface. The communication protocol status is used to characterize whether there is an external device to be charged. If the communication protocol status indicates the presence of an external device to be charged, the grounding path of the target interface is adjusted according to the communication protocol status.

2. The method according to claim 1, characterized in that, Adjusting the grounding path of the target interface according to the communication protocol status includes: Based on the communication protocol state, a control signal corresponding to the communication protocol state is generated; Based on the control signal, adjust the grounding path of the target interface.

3. The method according to claim 2, characterized in that, Adjusting the grounding path of the target interface based on the control signal includes: Based on the control signal, the conduction state of the control logic switch is adjusted to adjust the grounding path of the target interface.

4. The method according to claim 3, characterized in that, The logic switch is an NMOS transistor. The control of the logic switch's conduction state based on the control signal to adjust the grounding path of the target interface includes: When the control signal is high, the gate voltage of the NMOS transistor is higher than the source voltage, and the current path between the drain and the source of the NMOS transistor is turned on, so that the target interface is connected to the ground pin of the motherboard circuit. When the control signal is low, the gate voltage of the NMOS transistor is lower than the source voltage, cutting off the current path between the drain and the source, so that the target interface is connected to the microcontroller unit (MCU) through a pull-up resistor.

5. The method according to any one of claims 1 to 4, characterized in that, The communication protocol status is determined in the following way: The protocol control chip is used to identify the master / slave roles and negotiate the charging protocol for the electronic device to obtain the communication protocol status. The protocol control chip is at least one of a microcontroller unit that integrates a Universal Serial Bus Power Transfer Protocol stack, a power transfer protocol controller, or other integrated circuits used for negotiating and processing the Universal Serial Bus protocol and the power transfer protocol.

6. The method according to any one of claims 1 to 4, characterized in that, Before acquiring the status information of the target interface of the electronic device, the method further includes: Select one of the multiple ground pins of the electronic device as the cable detection pin of the target interface, and configure the remaining pins of the multiple ground pins to ground function.

7. An interface testing device, characterized in that, include: The acquisition module is used to acquire the status information of the target interface of the electronic device. The determination module is used to determine, based on the status information, whether a cable is inserted into the target interface; In addition, if it is determined that a cable is inserted, it is determined whether the target interface has established a communication protocol that conforms to the Universal Serial Bus Power Transmission Protocol with the protocol control chip, and the current communication protocol status of the target interface is obtained, wherein the communication protocol status is used to characterize whether there is an external device to be charged; An adjustment module is used to adjust the grounding path of the target interface according to the communication protocol status if the communication protocol status indicates the presence of an external device to be charged.

8. A switching circuit applied to an electronic device in the method of any one of claims 1-6, the electronic device comprising a target interface, characterized in that, The switching circuit includes: a protocol control chip, logic switches, motherboard circuitry, pull-up resistors, pull-down resistors, and a microcontroller unit (MCU); wherein... The logic switch includes a control terminal, a first conducting terminal, and a second conducting terminal. The control terminal is connected to the protocol control chip. The first conducting terminal is connected to the cable detection pin of the target interface. The second conducting terminal is connected to the ground pin of the motherboard circuit. The control terminal is connected to the first end of the pull-down resistor, which is connected to the general-purpose input / output port of the protocol control chip. The second end of the pull-down resistor is grounded. The cable detection pin of the target interface is connected to the MCU through the pull-up resistor. The protocol control chip is used to control the conduction state of the logic switch; When the conduction state indicates that the logic switch is on, the first conduction terminal is connected to the second conduction terminal. When the conduction state indicates that the logic switch is off, the first conduction terminal and the second conduction terminal are cut off.

9. An electronic device, characterized in that, include: Memory, processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory, causing the processor to perform the method as described in any one of claims 1-6.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed, are used to implement the method as described in any one of claims 1-6.

11. A computer program product, characterized in that, Includes a computer program, which, when executed, implements the method according to any one of claims 1-6.

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