Method and device for determining layout of printed circuit board, electronic equipment and program product

Abstract

The invention relates to a method and device for determining the layout of a printed circuit board, electronic equipment and a program product. The method includes acquiring parameters of the PCB. The method further includes determining a plurality of candidate layouts of the PCB and a respective plurality of magnetic field energies for the plurality of candidate layouts based on the parameters. The method further includes selecting a target layout from the plurality of candidate layouts based on the plurality of magnetic field energies. In this manner, the degree of parasitic inductance is calculated by using a calculation of magnetic field energy without performing a simulated run of finite element analysis, such that the computational complexity is greatly reduced, thereby saving time and computational resources.

Description

Technical Field

[0001] This disclosure relates to the field of circuits, and more specifically to methods, apparatus, electronic devices, and computer program products for determining the layout of printed circuit boards. Background Technology

[0002] A printed circuit board (PCB) is a circuit board composed of a substrate, insulating material, and copper foil. The circuit board is then manufactured into a circuit through printing and etching processes. PCBs are important electronic components, serving both as the carrier of internal electronic components and providing the circuit connections between them. On a PCB, all electronic components required for circuit operation, such as capacitors, resistors, inductors, and IC chips, are connected as a whole.

[0003] The circuitry on a PCB used to connect electronic components is called a trace, which can be considered equivalent to an inductance whose inductive reactance depends on the length and width of the trace. This inductance is known as parasitic inductance. As the length of the PCB trace increases, the resulting inductance also increases, especially noticeable on double-sided substrates. Summary of the Invention

[0004] The embodiments of this disclosure propose a scheme for determining the stack-up layout of a PCB based on magnetic field energy.

[0005] In a first aspect of this disclosure, a method for determining the layout of a printed circuit board (PCB) is provided. The method includes acquiring parameters of the PCB. The method further includes determining, based on the parameters, a plurality of candidate layouts of the PCB and corresponding plurality of magnetic field energies for the plurality of candidate layouts. The method also includes determining a target layout from the plurality of candidate layouts based on the magnitudes of the plurality of magnetic field energies.

[0006] In a second aspect of this disclosure, an electronic device is provided. It includes: at least one processor; and a memory coupled to the at least one processor and having instructions stored thereon, which, when executed by the at least one processor, cause the electronic device to perform a method according to the first aspect of this disclosure.

[0007] In a second aspect of this disclosure, an apparatus for determining the layout of a printed circuit board (PCB) is provided, comprising a parameter acquisition module configured to acquire parameters of the PCB; a magnetic field energy determination module configured to determine, based on the parameters, a plurality of candidate layouts of the PCB and a plurality of magnetic field energies corresponding to the plurality of candidate layouts; and a target layout determination module configured to select a target layout from the plurality of candidate layouts based on the plurality of magnetic field energies.

[0008] In a third aspect of this disclosure, an electronic device is provided. It includes: at least one processor; and a memory coupled to the at least one processor and having instructions stored thereon, the instructions causing the electronic device to perform a method according to a first aspect of this disclosure when executed by the at least one processor.

[0009] In a fourth aspect of this disclosure, a computer program product is provided. The computer program product includes computer-executable instructions, wherein the computer-executable instructions are executed by a processor to implement the method provided according to a first aspect of this disclosure.

[0010] In a fifth aspect of this disclosure, a computer-readable storage medium is provided. The computer-readable storage medium stores computer-executable instructions, which are executed by a processor to implement the method provided according to a first aspect of this disclosure.

[0011] It should be understood that the description in the Summary of the Invention section is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0012] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein:

[0013] Figure 1 A schematic diagram of an example environment in which several embodiments of the present disclosure may be implemented is shown;

[0014] Figure 2 A flowchart illustrating an example method for determining the layout of a PCB according to some embodiments of the present disclosure is shown;

[0015] Figure 3 A schematic diagram of an example method for determining magnetic field energy according to some embodiments of the present disclosure is shown;

[0016] Figures 4A-4D A schematic diagram illustrating an example process for determining magnetic field energy according to some embodiments of the present disclosure is shown;

[0017] Figure 5 A block diagram of an example apparatus for determining the layout of a printed circuit board (PCB) according to some embodiments of the present disclosure is shown; and

[0018] Figure 6 A block diagram of a device that can implement several embodiments of the present disclosure is shown. Detailed Implementation

[0019] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0020] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0021] It should be understood that when a component is referred to as "connected" or "coupled" to another component, it may be directly connected or coupled to the other component or there may be intermediate components. Conversely, when a component is referred to as "directly connected" or "directly coupled" to another component, there are no intermediate components. Other terms used to describe the relationship between components should be interpreted in a similar manner (e.g., "between" and "directly between," "adjacent" and "directly adjacent," etc.).

[0022] As discussed above, every trace in a power system PCB carries a certain amount of parasitic inductance. However, parasitic inductance refers to inductance that is not intentionally designed in, but rather generated by other components. When current changes occur in the commutation circuit, the induced voltage across the parasitic inductance can damage components. Therefore, special measures are usually required to minimize the parasitic inductance of critical commutation circuits, and also to reduce the impact of parasitic responses on signals.

[0023] In related technologies, the current directions in the conductors of different layers of a PCB are set to opposite directions. This staggered structure reduces the magnetic field energy in the loop, thereby reducing parasitic inductance in the PCB. However, PCBs typically consist of many layers, each of which can have conductors with different current directions. Therefore, when designing a PCB, the layer stack-up layout can include various options depending on the layer configuration. In this case, it is necessary to select the layer stack-up layout with the lowest parasitic inductance.

[0024] Typically, after determining the PCB stack-up configuration parameters for the design goals, such as the total number of layers and the number of conductors with unidirectional current, PCB experts will select several feasible layouts based on their experience. Then, based on the layout chosen through finite element analysis, they will select the stack-up layout with the lowest parasitic inductance. However, this approach does not consider all layout options and consumes a significant amount of time during finite element analysis. Furthermore, PCB manufacturing processes vary greatly in practical applications. Therefore, a high-precision, low-time-consuming design flow is needed to find the optimized PCB layout with the lowest parasitic inductance.

[0025] In view of this, embodiments of the present disclosure provide a scheme for calculating the approximate magnetic field energy of all feasible layout schemes of a PCB based on a simplified model. In the scheme of the present disclosure, after obtaining the target parameters of the PCB design, feasible layouts of the PCB are determined. Then, the magnetic field energy of the corresponding layout designed according to the target parameters is calculated. Finally, the layout with the minimum magnetic field energy is selected from all feasible layouts to obtain the layout with the minimum parasitic inductance.

[0026] According to embodiments of this disclosure, the computational complexity is significantly reduced by calculating the degree of parasitic inductance using the calculation of magnetic field energy, without requiring a simulation run of finite element analysis, thereby saving time and computational resources. This also greatly reduces computation time, making it possible to traverse all feasible layouts. The resulting feasible layouts replace only a few candidate layouts predetermined based on expert experience, thus avoiding the omission of preferred solutions that might not have been considered based on expert experience.

[0027] The following will combine Figures 1 to 5 The present disclosure will now describe in detail the scheme and principles of the embodiments. Figure 1 A schematic diagram of an example environment 100 in which various embodiments of this disclosure may be implemented is shown. For example... Figure 1 As shown, environment 100 includes computing device 102. Computing device 102 can be, for example, any electronic device capable of providing computing resources. A user can utilize computing device 102 for PCB-aided design. The user can, for example, input design parameters 104 of the target PCB to be designed into computing device 102, such as the total number of PCB layers and the corresponding number of conductor layers with different current directions. Upon receiving the user-input design parameters 104 of the target PCB, computing device 102 can execute a method for determining PCB layout according to embodiments of this disclosure.

[0028] like Figure 1 As shown, the total number of layers L of the target PCB input by the user TThe value is 6. In interleaved circuits, the current direction of the conductors in a conductor layer can typically have one of two opposing directions. Here, the user-inputted number of the first conductor layer, L, with the first current direction is... v The answer is 3. Therefore, the number of layers of the second conductor with a current direction opposite to the first direction is L. T -L v =3. In addition, the user also entered the wire width W. F The thickness of each conductor layer is 1 mm, T. C The thickness T is 1 mm and the dielectric layer located between the conductor layers. D It is 1mm. It should be understood that... Figure 1 The data in the illustrated embodiments are merely exemplary; the conductor width and the thickness of each layer can be other values, and the thickness of the conductor layer can also differ from the thickness of the dielectric layer. This disclosure is not intended to impose any limitations in this regard.

[0029] Next, the computing device 102 determines multiple candidate layouts of the PCB based on the output design parameters 104 of the target PCB, and determines the magnetic field energy corresponding to each candidate layout based on the design parameters 104. Finally, the computing device 102 can select the target layout from the candidate layouts based on the magnitude of the magnetic field energy of each determined candidate layout. Figure 1 In the illustrated embodiment, the target PCB 106, as calculated by the computing device 102, includes a circuit board stack 110 constructed based on a target layout and electronic devices 120 disposed on the circuit board stack 110.

[0030] exist Figure 1 In the illustrated embodiment, the circuit board stack 110 includes: a conductive layer 111-1, a dielectric layer 112-1, a conductive layer 111-2, a dielectric layer 112-2, a conductive layer 111-3, a dielectric layer 112-3, a conductive layer 111-4, a dielectric layer 112-4, a conductive layer 111-5, a dielectric layer 112-5, and a conductive layer 111-6 located between the top and bottom layers. All conductive layers in the circuit board stack 110 have the same thickness T. C And all dielectric layers have the same thickness T. D Electronic device 120 includes a first electronic component 121 disposed in the top layer of conductive layers 111-1, and a second electronic component 122 and a third electronic component 123 disposed in the bottom layers. For example... Figure 1As shown, the current direction of the wires in wire layers 111-1, 111-4, and 111-5 is a first direction from the second electronic component 122 to the third electronic component 123, and the current direction of the wires in wire layers 111-2, 111-3, and 111-6 is a second direction from the third electronic component 123 to the second electronic component 122.

[0031] Figure 2 A flowchart of an example method 200 for determining a PCB layout according to some embodiments of the present disclosure is shown. For discussion purposes, it will be combined with... Figure 1 To describe method 200. Method 200 can, for example, be described by... Figure 1 The computing device 102 shown is used to perform the operation.

[0032] like Figure 2 As shown, at position 202, method 200 includes obtaining parameters of the PCB. For example, in Figure 1 In the illustrated embodiment, the computing device 102 can receive design parameters 104 of the target PCB input by the user. In some embodiments, the computing device 102 may display a parameter input interface to guide the user to input the design parameters required for the calculation via the parameter input interface. For example, the parameter input interface may include an input field for the total number of layers of the target PCB, an input field for the number of first conductor layers having a first current direction, an input field for the width of the conductors, an input field for the thickness of each conductor layer, and an input field for the thickness of the dielectric layer located between the conductor layers. It should be understood that the input parameters are any parameters that can be used to calculate the magnetic field energy.

[0033] At position 204, method 200 includes determining multiple candidate layouts of the PCB based on parameters and determining corresponding multiple magnetic field energies for the multiple candidate layouts. For example, in Figure 1 In the illustrated embodiment, the computing device 102 can determine multiple candidate layouts of the PCB based on the total number of layers of the target PCB and the number of first conductive layers with a first current direction. Here, each layout includes a certain number of first conductive layers and the same number of second conductive layers with currents opposite to those in the first conductive layers. Furthermore, the layout also includes dielectric layers between the conductive layers. For example, the computing device 102 can determine, based on user-input design parameters 104, that the first number of first conductive layers with a first current direction is 3, and thus determine that the second number of second conductive layers with a second current direction is also 3, thereby determining that the total number of conductive layers in the PCB is 6. Then, the computing device 102 can determine multiple combinations of 3 first conductive layers with a total of 6 layers. For example, this can be achieved through combination formula C. 3Using a calculation of 6, a total of 20 combinations can be obtained. Finally, the computing device 102 can determine the layout corresponding to each combination and identify all layouts as candidate layouts. Here, each layout includes not only the corresponding combination of conductor layers but also the dielectric layer between the conductor layers.

[0034] In some embodiments, the obtained combinations may include mutually symmetrical combinations. The layouts corresponding to symmetrical combinations can have the same magnetic field energy. Therefore, without additional design requirements, duplicate candidate layouts can be removed. For example, computing device 102 can determine multiple conductor layer sequences corresponding to multiple candidate layouts. That is, a first conductor layer with a first current direction and a second conductor layer with a second current direction are organized into conductor layer sequences according to the order of layers in the candidate layout, for example, from the top layer to the bottom layer. Based on multiple candidate layouts, multiple corresponding conductor layer sequences are obtained.

[0035] Optionally, the computing device 102 can determine multiple reverse sequences of multiple conductor layer sequences arranged in reverse order. That is, it sequentially swaps the first and last elements of the conductor layer sequence, swaps the second and second-to-last elements, and so on, until all elements are replaced. Figure 1 In the illustrated embodiment, the computing device 102, for example, determines a corresponding conductor layer sequence comprising six elements based on a candidate layout. When determining the reverse sequence, the computing device 102 can sequentially swap the first element with the sixth element, the second element with the fifth element, and the third element with the sixth element in the conductor layer sequence. Subsequently, the computing device 102 can determine that the first reverse sequence among the plurality of reverse sequences is the same as the first conductor layer sequence among the plurality of conductor layer sequences.

[0036] Optionally, the computing device 102 can remove the candidate layout corresponding to the first reverse sequence or the candidate layout corresponding to the first wire layer sequence from the multiple candidate layouts to obtain a plurality of deduplicated candidate layouts. For example, the multiple candidate layouts typically include half of the total number of duplicate layouts, and after determining the corresponding multiple pairs of candidate layouts, any one of the candidate layouts in each pair can be removed.

[0037] For example in Figure 1 In the illustrated embodiment, the computing device 102 can also determine the magnetic field energy of each of the multiple candidate layouts based on the width of the conductor, the thickness of each conductor layer, and the thickness of the dielectric layer between the conductor layers to obtain the corresponding multiple magnetic field energies.

[0038] In some embodiments, the magnetic field energy can be calculated, for example, using suitable physical laws. Suitable physical laws may include, for example, Ampere's circuital law and Biot-Savart's law for calculating magnetic flux density. Furthermore, candidate PCB layouts can be modeled to obtain computational models corresponding to the selected physical laws. After obtaining the model, complex physical representations can be empirically approximated to relatively simpler ones, enabling calculations to be performed based on the input design parameters. After calculating the magnetic flux density, the magnetic field energy can be calculated based on the magnetic flux density. Then, reference will be made to... Figure 3 This section will detail the methods used to calculate magnetic field energy.

[0039] At position 206, method 200 includes selecting a target layout from multiple candidate layouts based on multiple magnetic field energies. For example, in Figure 1 In the illustrated embodiment, the computing device 102 can select a candidate layout with a magnetic field energy less than a predetermined threshold from a plurality of candidate layouts as the target layout. In some embodiments, the computing device 102 can select a candidate layout with the minimum magnetic field energy from a plurality of candidate layouts as the target layout.

[0040] according to Figure 2 The illustrated embodiment determines all candidate layouts based on the input design parameters. Then, for each candidate layout, the magnetic field energy of the corresponding physical model is calculated according to physical laws. Finally, the target layout is selected based on the magnetic field energy of each candidate layout to obtain an optimized PCB layout. In this embodiment, instead of constructing corresponding PCB models based on candidate layouts and simulating the magnetic field energy of the PCB model through finite element analysis, calculations are performed solely using applicable physical laws. This significantly reduces computation time and computational resource consumption, thereby improving overall design speed.

[0041] Figure 3 A schematic diagram of an example method 300 for determining magnetic field energy according to some embodiments of the present disclosure is shown. For discussion purposes, it will be combined with... Figure 1 To describe method 300. Method 300, for example, can be described by... Figure 1 The computational device 102 shown is used to perform this operation. Furthermore, method 300 can, for example, correspond to step 204 of method 200. Since the calculation is performed in the same way for each candidate layout, method 300 can be applied to all candidate layouts. For the sake of brevity and without loss of generality, the process of calculating the magnetic field energy of only one candidate layout is described here.

[0042] like Figure 3 As shown, at point 302, computing device 102 obtains the width W of the conductor in the conductor layer from the design parameters input by the user. FThat is, 1 mm. At 304, the computing device 102 selects the outermost conductive layer among multiple conductive layers as the reference conductive layer. The outermost conductive layer can be the top conductive layer 111-1 or the bottom conductive layer 111-6. Here, the computing device 102 selects the bottom conductive layer 111-6 as the reference conductive layer. At 306, the computing device 102 determines the layer layout between the conductive layer and the reference conductive layer. For example, if the conductive layer currently being calculated is conductive layer 111-3, the layer layout between conductive layer 111-3 and the bottom conductive layer 111-6, which serves as the reference conductive layer, is determined. Here, the layer layout includes the dielectric layer 112-3, conductive layer 111-4, dielectric layer 112-4, conductive layer 111-5, dielectric layer 112-5, and conductive layer 111-6 arranged sequentially.

[0043] Subsequently, at 308, the computing device 102, based on the determined layer layout, determines a three-layer conductive layer and a three-layer dielectric layer between the conductive layer 111-3 and the reference conductive layer 111-6. The computing device 102 obtains the first thickness of the conductive layer and the second thickness of the dielectric layer set by the user. Here, the thickness T of each conductive layer is... C The thickness is 1 mm and the thickness T of each dielectric layer. D The value is 1mm. At 310, the number of conductor layers 3 and the thickness of conductor layers 1mm, as well as the number of dielectric layers 3 and the thickness of dielectric layers 1mm, are calculated in device 102. The distance between the currently calculated conductor layer 111-3 and the reference conductor layer 111-6 is determined to be 3x1+3x1=6mm.

[0044] At 312, the computing device 102 determines the direction of the current in the conductor layer 111-3 indicated by the current candidate layout 110, i.e., the second direction. At 314, the computing device 102 obtains the magnitude of the current in the conductor layer. At 316, the computing device 102 determines the current value of the current in the conductor of conductor layer 113-1 based on the direction and the current magnitude. Here, since the current magnitude is the same in each layer but the direction is opposite, a preset current can be used for calculation. Here, the current value with the first direction can be +I, while the current value with the second direction can be -I.

[0045] At point 318, computing device 102 determines the magnetic flux density of each conductor layer in the candidate layout based on width, current, and distance to obtain multiple magnetic flux densities. In some embodiments, the magnetic flux density of a layer can be calculated, for example, by a function based on Biot-Savart's law:

[0046]

[0047] Among them B i(z) represents the magnetic field strength generated by the i-th conductive layer at a distance z from the reference conductive layer, where μ0 is the vacuum conductivity, and I i It represents the current value in the i-th conductor layer, w represents the conductor width, and z i This represents the distance between the i-th conductor layer and the reference conductor layer.

[0048] At 320, the computing device 102 determines the total magnetic flux density of the candidate layout based on the magnetic flux density of each conductor layer, i.e., the sum of the magnetic flux densities of all conductor layers. At 322, the computing device 102 determines a unit energy representation of the total magnetic flux density relative to the distance to the reference conductor layer. The unit energy representation is, for example:

[0049]

[0050] Where dE represents the unit energy of the magnetic field generated by the PCB at a distance z from the reference conductor layer.

[0051] At position 324, computing device 102 determines the magnetic field energy of a candidate layout based on distance and unit energy representation. Here, computing device 102 can calculate the integral of the unit energy representation over distance using the following formula:

[0052]

[0053] Where E represents the magnetic field energy of the PCB under this candidate layout.

[0054] according to Figure 3 The illustrated embodiment simplifies the corresponding model by applying Biot-Savart's law and performs calculations with the same predetermined current magnitude. This allows for a simplified calculation of the magnetic field energy generated by the current in each conductive layer of a PCB while maintaining sufficient accuracy. Consequently, computation time is significantly reduced, making it possible to traverse all feasible candidate layouts.

[0055] This concludes the introduction of a general scheme for determining the layout of a PCB board. The following section will refer to... Figures 4A-4D This document describes an example process for determining the magnetic field energy for a PCB of a half-bridge circuit according to some embodiments of the present disclosure. Figure 4A A schematic diagram of an example process 400A for determining magnetic field energy according to some embodiments of the present disclosure is shown. Process 400A may, for example, be performed by... Figure 1 The computing device 102 in the middle is used to execute.

[0056] like Figure 4A As shown, process 400A includes the user inputting design parameters for the target PCB into the computing device 102. The design parameters include the total number of layers of the target PCB. Figure 4AThe parameter input interface shown includes a total number of conductor layers input field 402. Here, the user enters 4 in the input field. After receiving the user's input "4", the parameter input interface automatically displays the layer thickness input field 404. The layer thickness input field 404 includes the number of conductor layers L. C 1. Dielectric layer L D 1. Conductor layer L C 2. Dielectric layer L D 2. Conductor layer L C 3. Dielectric layer L D 3. Conductor layer L C 4. Accordingly, the user inputs the corresponding design thickness, i.e., conductor layer L. C 1 has a thickness T C 1. Dielectric layer L D 1 has a thickness T D 1. Conductor layer L C 2 has a thickness T C 2. Dielectric layer L D 2 has a thickness T D 2. Conductor layer L C 3 has a thickness T C 3. Dielectric layer L D 3 has a thickness T D 3. Conductor layer L C 4 has a thickness T C 4. The parameter input interface also displays the wire width field 406. Here, the user enters the wire width as 2mm.

[0057] In a half-bridge circuit, the current in the intermediate wire between two switching devices is opposite in direction to the current in the bus wire connecting the switching devices via capacitors; the number of intermediate wires is a key parameter. Here, the parameter input interface displays the number of intermediate wires 407 between the switching devices as 2. At this time, the computing device 102 can determine multiple candidate layouts of the PCB based on the total number of layers of the target PCB (4) and the number of layers of the intermediate wires. The computing device 102 determines multiple combinations 408 of the 2 intermediate wire layers under a total of 4 layers. The multiple combinations 408 include combinations 410-1, 410-2, 410-3, 410-4, 410-5, and 410-6. Here, the conductor layer sequence corresponding to combination 410-1 is [BBVV], where B represents the conductor layer of the bus wire and V represents the conductor layer of the intermediate wire. The conductor layer sequence corresponding to combination 410-2 is [BV BV]. The conductor layer sequence corresponding to combination 410-3 is [BVVB]. The conductor layer sequence corresponding to combination 410-4 is [VBVB]. The conductor layer sequence corresponding to combination 410-5 is [VV BB]. The conductor layer sequence corresponding to combination 410-6 is [VBBV].

[0058] At this point, the computing device 102 can deduplicate the obtained multiple combinations. In some embodiments, the computing device can determine multiple conductor layer sequences corresponding to multiple candidate layouts. Then, the computing device can determine multiple reverse sequences of the multiple conductor layer sequences arranged in reverse order. The computing device can determine that one or more reverse sequences are identical to one or more conductor layer sequences. Finally, the computing device can remove a candidate layout corresponding to a reverse sequence or a candidate layout corresponding to a conductor layer sequence from the multiple candidate layouts to obtain a deduplicated set of multiple candidate layouts.

[0059] exist Figure 4A In the illustrated embodiment, computing device 102 deduplicates combination 408. Computing device 102 determines that the reverse sequence [BV BV] of the conductor layer sequence [VBVB] of combination 410-4 is the same as the conductor layer sequence corresponding to combination 410-2. The reverse sequence [BBVV] of the conductor layer sequence [VVBB] of combination 410-5 is the same as the conductor layer sequence corresponding to combination 410-1. The reverse sequence of the conductor layer sequence [VBBV] of combination 410-6 is still [VBBV]. Here, due to the symmetry of the conductor layers, combination 410-6 is equivalent to combination 410-3. Thus, after removing one of the two identical or equivalent combinations, multiple candidate combinations 412 are obtained after deduplication. The multiple candidate combinations 412 include combination 410-1, combination 410-2, and combination 410-3. Computing device 102 determines the corresponding candidate layout based on combination 410-1, combination 410-2, and combination 410-3. The following will be combined with... Figures 4B to 4D To describe the identified candidate layouts.

[0060] Figure 4B Showing has corresponding Figure 4A A schematic diagram of the PCB 400B for the candidate layout of combination 410-1. (See diagram below.) Figure 4B As shown, PCB 400B includes: conductive layer 440-1, dielectric layer 442-1, conductive layer 440-2, dielectric layer 442-2, conductive layer 440-3, dielectric layer 442-3, and conductive layer 440-4, located between the top and bottom layers. All conductive layers in PCB 400B have the same thickness T. C And all dielectric layers have the same thickness T. D The electronic device includes an isolation capacitor 431 disposed in the top conductor layer 440-1, and a first switching device 432 at a high potential and a second switching device 433 at a low potential located in the bottom conductor layer 440-4. For example... Figure 4BAs shown, the wires in wire layers 440-1 and 440-2 are bus wires, and their current direction is a first direction from the first switching device 432 to the second switching device 433. The wires in wire layers 440-3 and 440-4 are intermediate wires, and their current direction is a second direction from the second switching device 433 to the first switching device 432.

[0061] Figure 4C Showing has corresponding Figure 4A A schematic diagram of the PCB 400C with candidate layouts for combination 410-2. (See diagram below.) Figure 4C As shown, the conductors in conductor layers 440-1 and 440-3 of PCB 400C are bus conductors, and their current direction is a first direction from the first switching device 432 to the second switching device 433. The conductors in conductor layers 440-2 and 440-4 are intermediate conductors, and their current direction is a second direction from the second switching device 433 to the first switching device 432.

[0062] Figure 4D Showing has corresponding Figure 4A A schematic diagram of PCB 400D showing the candidate layout of combination 410-3. (See diagram below.) Figure 4D As shown, the conductors in conductor layers 440-2 and 440-3 of PCB 400D are bus conductors, and their current direction is a first direction from the first switching device 432 to the second switching device 433. The conductors in conductor layers 440-1 and 440-4 are intermediate conductors, and their current direction is a second direction from the second switching device 433 to the first switching device 432.

[0063] return Figure 4A After determining the candidate layouts, the parameters of the candidate layouts, including parameter 414-1 corresponding to the candidate layout of combination 410-1, parameter 414-2 corresponding to the candidate layout of combination 410-2, and parameter 414-3 corresponding to the candidate layout of combination 410-3, are input into the magnetic field energy calculation module 416. In the magnetic field energy calculation module 416, the magnetic field energy corresponding to the candidate layout of combination 410-1 is calculated based on parameter 414-1 and according to... Figure 3 The method shown for determining the magnetic field energy is used to determine it. Similarly, the magnetic field energy corresponding to the candidate layout of combination 410-2 is based on parameter 414-2 and according to... Figure 3 The method for determining the magnetic field energy shown is used to determine the magnetic field energy, and the magnetic field energy corresponding to the candidate layout of combination 410-3 is based on parameter 414-3 and according to Figure 3 The method shown is used to determine the energy of the magnetic field.

[0064] After determining the magnetic field energy of each candidate layout, the determined magnetic field energy corresponding to the three candidate layouts is input into comparator 418. After comparison in comparator 418, the candidate layout with the smallest magnetic field energy is determined as the target layout 420.

[0065] Figure 5 A block diagram of an example apparatus 500 for determining the layout of a printed circuit board (PCB) according to some embodiments of the present disclosure is shown. Figure 5 As shown, the device 500 includes a parameter acquisition module 502 configured to acquire parameters of the PCB. The device 500 also includes a magnetic field energy determination module 504 configured to determine multiple candidate layouts of the PCB and corresponding multiple magnetic field energies of the multiple candidate layouts based on the parameters. The device 500 further includes a target layout determination module 506 configured to select a target layout from the multiple candidate layouts based on the multiple magnetic field energies.

[0066] In some embodiments, the magnetic field energy determination module includes: a first magnetic induction intensity determination unit configured to determine the magnetic induction intensity of each of the multiple conductive layers of each candidate layout to obtain multiple magnetic induction intensities; a total magnetic induction intensity determination unit configured to determine the total magnetic induction intensity of each candidate layout based on the multiple magnetic induction intensities of the multiple conductive layers; and a first magnetic field energy determination unit configured to determine the magnetic field energy of each candidate layout based on the total magnetic induction intensity.

[0067] In some embodiments, the first magnetic flux density determination unit includes: a width acquisition unit configured to acquire the width of a conductor in a conductor layer; a first distance determination unit configured to determine the distance between the conductor and a reference conductor layer; a current determination unit configured to determine the current in the conductor; and a second magnetic flux density determination unit configured to determine the magnetic flux density based on the width, current, and distance.

[0068] In some embodiments, the first distance determination unit includes: a reference conductor layer determination unit configured to select the outermost conductor layer among a plurality of conductor layers as a reference conductor layer; a layer layout determination unit configured to determine the layer layout between the conductor layer where the conductor is located and the reference conductor layer; and a second distance determination unit configured to determine the distance between the conductor and the reference conductor layer based on the layer layout.

[0069] In some embodiments, the second distance determination unit includes: a layer number determination unit configured to determine, based on layer layout, that there are a first number of conductor layers and a second number of dielectric layers between the conductor layer and the reference conductor layer; a thickness acquisition unit configured to acquire a first thickness of the conductor layer and a second thickness of the dielectric layer; and a third distance determination unit configured to determine the distance based on the first number and the first thickness, as well as the second number and the second thickness.

[0070] In some embodiments, the current determination unit includes: a direction determination unit configured to determine the direction of the current in the conductor layer where the conductor indicated by each candidate layout is located; a magnitude determination unit configured to obtain the magnitude of the current in the conductor layer; and a current value determination unit configured to determine the current value of the current in the conductor based on the direction and the current magnitude.

[0071] In some embodiments, the current magnitude is predetermined, and the current magnitude is the same for each conductor layer.

[0072] In some embodiments, each candidate layout includes a conductor layer having a current in a first direction and a conductor layer having a current in a second direction, the first current being in the opposite direction to the second current.

[0073] In some embodiments, the first magnetic field energy determination unit includes: an energy representation determination unit configured to determine a unit energy representation of the total magnetic flux density relative to the distance to the reference conductor layer; and a second magnetic field energy determination unit configured to determine the magnetic field energy of each candidate layout based on the distance and the unit energy representation.

[0074] In some embodiments, the magnetic field energy determination module 504 includes: a layer determination unit configured to determine a first number of first conductor layers having a first direction of current direction; a total number of layers acquisition unit configured to determine the total number of PCB layers according to parameters; a combination determination unit configured to determine multiple combination methods of the first conductor layers with the first number of layers under the total number of layers; and a candidate layout determination unit configured to determine the layouts corresponding to the multiple combination methods as multiple candidate layouts.

[0075] In some embodiments, the apparatus further includes: a conductor layer sequence determination unit configured to determine a plurality of conductor layer sequences corresponding to a plurality of candidate layouts; a reverse sequence determination unit configured to determine a plurality of reverse sequences of the plurality of conductor layer sequences arranged in reverse order; a sequence pair determination unit configured to determine that a first reverse sequence among the plurality of reverse sequences is the same as a first conductor layer sequence among the plurality of conductor layer sequences; and a layout deduplication unit configured to remove a candidate layout corresponding to the first reverse sequence or a candidate layout corresponding to the first conductor layer sequence from the plurality of candidate layouts to obtain a plurality of deduplicated candidate layouts.

[0076] Figure 6 A schematic block diagram of an example device 600 that can be used to implement embodiments of the present disclosure is shown. The example device 600 may be, for example,... Figure 1The computing device 102 is shown in the figure. The device 600 includes a computing unit 601, which can perform various appropriate actions and processes according to computer program instructions stored in read-only memory (ROM) 602 or loaded from storage unit 608 into random access memory (RAM) 603. The RAM 603 may also store various programs and data required for the operation of the device 600. The computing unit 601, ROM 602, and RAM 603 are interconnected via bus 604. An input / output (I / O) interface 605 is also connected to bus 604.

[0077] Figure 6 A schematic block diagram of an example device 600 that can be used to implement embodiments of the present disclosure is shown. As shown, device 600 includes a processor 601 that can perform various appropriate actions and processes based on computer program instructions loaded into random access memory (RAM) 603 according to computer program instructions stored in read-only memory (ROM) 602. Various programs and data required for the operation of device 600 may also be stored in RAM 603. The processor 601, ROM 602, and RAM 603 are interconnected via bus 604. Input / output (I / O) interface 605 is also connected to bus 604.

[0078] The various processes and procedures described above, such as methods 200 and 300, can be executed by processor 601. For example, in some embodiments, methods 200 and 300 may be implemented as computer software programs tangibly contained in a machine-readable medium. In some embodiments, part or all of the computer program may be loaded and / or installed on device 600 via ROM 602. When the computer program is loaded into RAM 603 and executed by processor 601, one or more actions of methods 200 and 300 described above may be performed.

[0079] This disclosure can be a method, apparatus, system, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for performing various aspects of this disclosure.

[0080] A computer-readable storage medium can be a tangible device capable of holding and storing instructions for use by an instruction execution device. A computer-readable storage medium can be, for example—but not limited to—an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), and any suitable combination thereof. The computer-readable storage medium as used herein is not to be construed as a transient signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0081] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0082] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0083] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0084] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processing unit of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0085] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0086] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0087] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, and are not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technical improvements to the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method (200) for determining the layout of a printed circuit board (PCB), comprising: Obtain the parameters of the PCB described in (202); Based on the parameters, (204) multiple candidate layouts of the PCB and the corresponding multiple magnetic field energies of the multiple candidate layouts are determined; as well as Based on the multiple magnetic field energies, a target layout (206) is selected from the multiple candidate layouts.

2. The method (200) according to claim 1, wherein determining the corresponding plurality of magnetic field energies of the plurality of candidate layouts comprises: For each of the plurality of candidate layouts: The magnetic flux density of each of the multiple conductive layers in each candidate layout is determined to obtain multiple magnetic flux densities; The total magnetic flux density of each candidate layout is determined based on the multiple magnetic flux densities of the multiple conductor layers. as well as Based on the total magnetic induction intensity, the magnetic field energy of each candidate layout is determined.

3. The method (200) of claim 2, wherein determining the magnetic flux density of each of the conductor layers comprises: Obtain the width of the conductors in the conductor layer; Determine the distance between the conductor and the reference conductor layer; Determine the current in the conductor; as well as The magnetic induction intensity is determined based on the width, the current, and the distance.

4. The method (200) according to claim 3, wherein determining the distance of the conductor from the reference conductor layer comprises: The outermost conductor layer among the plurality of conductor layers is selected as the reference conductor layer; Determine the layer layout between the conductor layer containing the conductor and the reference conductor layer; as well as Based on the layer layout, the distance between the conductor and the reference conductor layer is determined.

5. The method (200) according to claim 4, wherein determining the distance of the conductor from the reference conductor layer comprises: Based on the layer layout, it is determined that there is a first number of conductor layers and a second number of dielectric layers between the conductor and the reference conductor layer; Obtain the first thickness of the conductive layer and the second thickness of the dielectric layer; as well as The distance is determined based on the first number and the first thickness, and the second number and the second thickness.

6. The method (200) of claim 3, wherein determining the current in the conductor comprises: Determine the direction of the current in the conductor layer where the conductor indicated by each candidate layout is located; as well as Obtain the magnitude of the current in the conductor layer.

7. The method (200) according to claim 6, wherein the current magnitude is predetermined and the current magnitude of each of the conductor layers is the same.

8. The method of claim 6, wherein each candidate layout includes a conductor layer having current in a first direction and a conductor layer having current in a second direction, the first direction being opposite to the second direction.

9. The method (200) of claim 2, wherein determining the magnetic field energy of each candidate layout based on the total magnetic flux density comprises: Determine the total magnetic flux density as a unit energy representation relative to the reference conductor layer; as well as The magnetic field energy of each candidate layout is determined based on the distance and the unit energy representation.

10. The method (200) of claim 1, wherein determining the plurality of candidate layouts of the PCB comprises: Based on the parameters, determine the first number of the first conductor layer having a first current direction; Based on the first number of layers, the total number of conductor layers in the PCB is determined. The total number of layers also includes a second number of conductor layers with a second current direction, the first direction being opposite to the second direction. Determine multiple combinations of the first conductor layer of the first layer number under the total number of layers; as well as The layouts corresponding to the multiple combination methods are determined as the multiple candidate layouts.

11. The method (200) according to claim 10, further comprising: Determine multiple conductor layer sequences corresponding to the multiple candidate layouts; Determine multiple reverse sequences of the multiple conductor layer sequences arranged in reverse order; It is determined that one of the plurality of reverse sequences is identical to one of the plurality of wire layer sequences; as well as Remove the candidate layout corresponding to the reverse sequence or the candidate layout corresponding to the conductor layer sequence from the plurality of candidate layouts to obtain the plurality of candidate layouts after deduplication.

12. An apparatus (500) for determining the layout of a printed circuit board (PCB), comprising: The parameter acquisition module (502) is configured to acquire the parameters of the PCB; The magnetic field energy determination module (504) is configured to determine multiple candidate layouts of the PCB and corresponding multiple magnetic field energies of the multiple candidate layouts based on the parameters. as well as The target layout determination module (506) is configured to select a target layout from the plurality of candidate layouts based on the plurality of magnetic field energies.

13. An electronic device, comprising: At least one processor; as well as A memory coupled to the at least one processor and having instructions stored thereon, which, when executed by the at least one processor, cause the electronic device to perform the method according to any one of claims 1-11.

14. A computer program product comprising computer-executable instructions, wherein the computer-executable instructions are executed by a processor to implement the method according to any one of claims 1 to 11.

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