Neural network adversarial training method, device and equipment and analog computing circuit

Abstract

The invention provides a neural network adversarial training method, device and equipment and an analog calculation circuit. The neural network comprises a weight model and a deployment model. The method comprises the following steps: acquiring a voltage drop coefficient of each RRAM unit in each resistance state; training a weight model based on the first weight, the first deployment position and the voltage drop coefficient of each RRAM unit in each resistance state, and obtaining a second weight output by the weight model; inputting the second weight and the voltage drop coefficient of each RRAM unit in each resistance value state into a deployment model to obtain a second deployment position; and taking the second weight as a new first weight, taking the second deployment position as a new first deployment position, repeatedly executing the training step until an iteration stopping condition is met, stopping training, and obtaining a trained second deployment position and a trained second weight. According to the method, the hardware design of the circuit does not need to be adjusted, and the implementation difficulty of reducing the voltage drop influence is reduced.

Description

Technical Field

[0001] This application relates to the field of neural network training technology, and in particular to a neural network adversarial training method, apparatus, device, and analog computing circuit. Background Technology

[0002] Resistive Random Access Memory (RRAM) analog computing circuits can perform multiplication and addition operations directly in the storage cells. Compared with traditional computing architectures based on the separation of storage and computation, it reduces data movement, thereby reducing energy consumption and latency.

[0003] Internal Resistance Drop (IR Drop) is the voltage drop caused by the resistance of wires in an analog computing circuit. Analog computing circuits perform calculations based on the relationship between voltage, resistance, and current in the Restricted RAM (RRAM). Because IR Drop affects the voltage in various regions of the analog computing circuit, it impacts the accuracy of the calculations. In methods that train neural networks using RRAM, IR Drop affects the accuracy of calculations during the training process.

[0004] In existing methods, the resistance of the wires is reduced by adjusting the circuit, such as increasing the width of the wires or decreasing the length of the wires, thereby reducing the impact of voltage drop. However, reducing the impact of voltage drop by adjusting the circuit increases the complexity of the circuit design and makes it more difficult to implement. Summary of the Invention

[0005] This application provides a neural network adversarial training method, apparatus, device, and analog computing circuit to solve the problem that reducing the impact of voltage drop by adjusting the circuit increases the complexity of circuit design and makes implementation difficult.

[0006] In a first aspect, this application provides a neural network adversarial training method, wherein the neural network includes a weight model and a deployment model, and the method includes:

[0007] With each RRAM cell in the RRAM array having a different resistance value, a read voltage is applied to each RRAM cell to obtain the voltage drop coefficient of each RRAM cell under each resistance value state;

[0008] The weight model is trained based on the first weight, the first deployment position, and the voltage drop coefficient of each RRAM unit under each resistance state to obtain the second weight output by the weight model; the second weight and the voltage drop coefficient of each RRAM unit under each resistance state are input into the deployment model to obtain the second deployment position; wherein, the second deployment position is the deployment position that maximizes the voltage drop coefficient corresponding to the resistance state of each RRAM unit; the second weight is used as the new first weight, and the second deployment position is used as the new first deployment position, and this step is repeated until the iteration stopping condition is met, then the training is stopped, and the trained second deployment position and trained second weight are obtained.

[0009] Optionally, the step of inputting the second weight and the voltage drop coefficient of each RRAM cell under each resistance state into the deployment model to obtain the second deployment location includes:

[0010] The second weight and the voltage drop coefficient of each RRAM cell under each resistance state are input into the deployment neural network or fitting model to obtain the second deployment position.

[0011] Optionally, the second weight and the voltage drop coefficient of each RRAM cell under each resistance state are input into the fitting model to obtain the second deployment location, including:

[0012] The second weight and the voltage drop coefficient of each RRAM cell under each resistance state are input into the fitting model. The fitting model is based on an optimization algorithm, with the goal of maximizing the sum of the voltage drop coefficients of each RRAM cell in the RRAM array. In each iteration of the optimization algorithm, the sum of the voltage drop coefficients of each RRAM cell in the RRAM array is determined according to the deployment position of each RRAM cell in the RRAM array, and the second deployment position that maximizes the sum of the voltage drop coefficients is obtained.

[0013] Optionally, the method further includes:

[0014] The voltage drop coefficient of each RRAM cell under each resistance value state is stored in the voltage drop coefficient table;

[0015] The training of the weight model based on the first weight, the first deployment location, and the voltage drop coefficient of each RRAM cell corresponding to the first weight includes:

[0016] The first weight, the first deployment location, and the voltage drop coefficient table are input into the weight model. The weight model determines the resistance state of each RRAM cell based on the first weight and the first deployment location. Based on the resistance state of each RRAM cell, the voltage drop coefficient corresponding to the resistance state of each RRAM cell is looked up from the voltage drop coefficient table. The weight model is trained based on the first weight and the voltage drop coefficient corresponding to the resistance state of each RRAM cell.

[0017] The step of inputting the second weight and the voltage drop coefficient of each RRAM cell under each resistance state into the deployment model to obtain the second deployment location includes:

[0018] The second weight and the voltage drop coefficient table are input into the deployment model. The deployment model determines the resistance state of each RRAM cell and, based on the resistance state of each RRAM cell, looks up the voltage drop coefficient corresponding to the resistance state of each RRAM cell in the voltage drop coefficient table to obtain the second deployment position that maximizes the voltage drop coefficient corresponding to the resistance state of each RRAM cell in the RRAM array.

[0019] Optionally, the step of applying a read voltage to each RRAM cell in the RRAM array when each RRAM cell is in a different resistance state, and obtaining the voltage drop coefficient of each RRAM cell in each resistance state, includes:

[0020] When each RRAM cell in the RRAM array is in a high-resistance state, a first read voltage is applied to each RRAM cell to obtain a first voltage drop coefficient for each RRAM cell; and when each RRAM cell in the RRAM array is in a low-resistance state, a second read voltage is applied to each RRAM cell to obtain a second voltage drop coefficient for each RRAM cell.

[0021] The weight model is trained based on the first weight, the first deployment location, and the voltage drop coefficient of each RRAM cell under various resistance states to obtain the second weight output by the weight model, including:

[0022] The weight model is trained based on the first weight, the first deployment location, and the first and second voltage drop coefficients of each RRAM unit to obtain the second weight output by the weight model;

[0023] The step of inputting the second weight and the voltage drop coefficient of each RRAM cell under each resistance state into the deployment model to obtain the second deployment location includes:

[0024] The second weight and the first or second voltage drop coefficient of each RRAM cell are input into the deployment model. The deployment model determines the first voltage drop coefficient corresponding to the resistance state of each RRAM cell by determining that the resistance state of each RRAM cell is high resistance, or determines that the resistance state of each RRAM cell is low resistance, and obtains the second voltage drop coefficient corresponding to the resistance state of each RRAM cell. This yields a second deployment location that maximizes the voltage drop coefficient corresponding to the resistance state of each RRAM cell.

[0025] Optionally, the step of applying a first read voltage to each RRAM cell when each RRAM cell in the RRAM array is in a high-impedance state to obtain a first voltage drop coefficient for each RRAM cell, and applying a second read voltage to each RRAM cell when each RRAM cell in the RRAM array is in a low-impedance state to obtain a second voltage drop coefficient for each RRAM cell, includes:

[0026] When each RRAM cell is in a high-impedance state, the first read voltage is applied to each RRAM cell in the RRAM array to obtain the first output current of the RRAM array. The ratio of the first read voltage to the first resistance value of each RRAM cell in the high-impedance state is determined as the first desired current, and the ratio of the first output current to the first desired current is determined as the first voltage drop coefficient.

[0027] When each RRAM cell is in a low-resistance state, the second read voltage is applied to each RRAM cell in the RRAM array to obtain the second output current of the RRAM array. The ratio of the second read voltage to the second resistance value of each RRAM cell in the low-resistance state is determined as the second desired current, and the ratio of the second output current to the second desired current is determined as the second voltage drop coefficient.

[0028] Optionally, the method further includes:

[0029] For each bit of the second weight, each of the one or more RRAM cells is set to the resistance state corresponding to the bit, such that the one or more RRAM cells characterize each bit.

[0030] In a second aspect, this application provides an analog computing circuit, comprising: an RRAM array; wherein each RRAM cell in the RRAM array is provided with a trained second weight obtained by the method described in the first aspect above, and the trained second weight is deployed according to the trained second deployment position.

[0031] Thirdly, this application provides a neural network adversarial training device, wherein the neural network includes a weight model and a deployment model, comprising:

[0032] The acquisition module is used to apply a read voltage to each RRAM cell in the RRAM array when each RRAM cell is in a different resistance state, and to acquire the voltage drop coefficient of each RRAM cell in each resistance state.

[0033] The training module is used to train the weight model based on the first weight, the first deployment position, and the voltage drop coefficient of each RRAM unit under each resistance state, to obtain the second weight output by the weight model; input the second weight and the voltage drop coefficient of each RRAM unit under each resistance state into the deployment model to obtain the second deployment position; wherein, the second deployment position is the deployment position that maximizes the voltage drop coefficient corresponding to the resistance state of each RRAM unit; use the second weight as the new first weight, and use the second deployment position as the new first deployment position, repeat this step until the iteration stopping condition is met, then stop training, and obtain the trained second deployment position and trained second weight.

[0034] Fourthly, this application provides an electronic device, including: a processor, and a memory communicatively connected to the processor;

[0035] The memory stores computer-executed instructions;

[0036] The processor executes computer execution instructions stored in the memory to implement the method described in the first aspect above and various possible designs of the first aspect.

[0037] Fifthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the methods described in the first aspect and various possible designs of the first aspect.

[0038] Sixthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the method described in the first aspect above and various possible designs of the first aspect.

[0039] The neural network adversarial training method, apparatus, device, and analog computing circuit provided in this application include a neural network comprising a weight model and a deployment model. The method applies a read voltage to each RRAM cell in an RRAM array with different resistance values, obtaining the voltage drop coefficient of each RRAM cell under each resistance value. Based on a first weight, a first deployment position, and the voltage drop coefficient of each RRAM cell under each resistance value, the weight model is trained to obtain a second weight output by the weight model. The second weight and the voltage drop coefficient of each RRAM cell under each resistance value are input into the deployment model to obtain a second deployment position. The second weight is used as the new first weight, and the second deployment position is used as the new first deployment position. Training is repeated until an iteration stopping condition is met, at which point training stops, resulting in the trained second deployment position and trained second weight. This method adds the voltage drop coefficient of the RRAM cells to the neural network adversarial training to reduce the impact of the RRAM cell voltage drop on the neural network training. Compared to related RRAM-based neural network adversarial training methods, this method does not require adjustments to the circuit hardware design, reducing the difficulty of reducing the impact of voltage drop. Attached Figure Description

[0040] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0041] Figure 1 A flowchart illustrating a neural network adversarial training method provided in this application embodiment. Figure 1 ;

[0042] Figure 2 This is a schematic diagram of the structure of a neural network model provided in an embodiment of this application;

[0043] Figure 3 A flowchart illustrating a neural network adversarial training method provided in this application embodiment. Figure 2 ;

[0044] Figure 4 This is a schematic diagram of the structure of an RRAM array provided in an embodiment of this application;

[0045] Figure 5 A schematic diagram of the deployment positions of each RRAM cell in an RRAM array provided in this application. Figure 1 ;

[0046] Figure 6 A schematic diagram of the deployment positions of each RRAM cell in an RRAM array provided in this application. Figure 2 ;

[0047] Figure 7This is a schematic diagram of the structure of a plurality of RRAM arrays provided in an embodiment of this application;

[0048] Figure 8 A flowchart illustrating a neural network adversarial training method provided in this application embodiment. Figure 3 ;

[0049] Figure 9 This is a schematic diagram of the structure of a neural network adversarial training device provided in an embodiment of this application;

[0050] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0051] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0052] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0053] Analog computing circuits can perform multiply-accumulate operations directly in the storage unit. By training neural networks based on RRAM, compared with traditional computing architectures that separate storage and computation, data movement is reduced, thereby improving training speed.

[0054] Voltage drop is the decrease in voltage caused by the resistance of wires in a circuit, and it affects the voltage in various regions of the RRAM circuit. In methods of training neural networks based on RRAM, weights are mapped to multiple RRAM cells. The magnitude of the voltage applied to the RRAM cells is affected by voltage drop, which may lead to inaccurate weight calculations and thus affect the inference ability of the neural network.

[0055] Existing methods reduce the resistance of wires by adjusting the circuit, such as increasing the wire width or decreasing the wire length, thereby reducing the impact of voltage drop. However, adjusting the circuit increases the complexity of the circuit design and makes implementation difficult.

[0056] In view of this, this application proposes a neural network adversarial training method. The neural network includes a weight model and a deployment model. Under different resistance states for each RRAM cell in the RRAM array, a read voltage is applied to each RRAM cell to obtain the voltage drop coefficient of each RRAM cell under each resistance state. The weight model is trained based on a first weight, a first deployment position, and the voltage drop coefficient of each RRAM cell under each resistance state to obtain a second weight. The second weight and the voltage drop coefficient of each RRAM cell under each resistance state are input into the deployment model to obtain a second deployment position. The second weight is used as the new first weight, and the second deployment position is used as the new first deployment position. This training is repeated until the iteration stopping condition is met, at which point training stops, resulting in the trained second deployment position and trained second weight. This method adds the voltage drop coefficient of the RRAM cells to the neural network adversarial training to reduce the impact of the RRAM cell voltage drop on the neural network training. Compared to related RRAM-based neural network adversarial training methods, this method does not require adjustments to the circuit hardware design, reducing the difficulty of reducing the impact of voltage drop.

[0057] It should be understood that the neural network adversarial training method of this application embodiment can be used in any training scenario of an RRAM-based neural network. The execution subject of this application embodiment can be any control unit for neural network adversarial training, or a system or device equipped with such control unit. The following description takes a control unit for neural network adversarial training as the execution subject as an example.

[0058] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0059] Figure 1 A flowchart illustrating a neural network adversarial training method provided in this application embodiment. Figure 1 Neural networks include weight models and deployment models. For example... Figure 1 As shown, the neural network adversarial training method may include, for example, the following steps:

[0060] S101. Apply a read voltage to each RRAM cell in the RRAM array when each RRAM cell has a different resistance value, and obtain the voltage drop coefficient of each RRAM cell under each resistance value state.

[0061] An RRAM array is a matrix structure composed of multiple RRAM cells, which serve as storage and processing units in analog computing circuits.

[0062] The resistance state of an RRAM cell can be different, determined by the resistance state of the RRAM within the cell. Data storage can be achieved by applying a large voltage to the RRAM cell to change its resistance state. For example, if the RRAM cell has three resistance states, a high resistance state can be represented as logic 0, an intermediate resistance state between high and low resistance can be represented as logic 1 / 2, and a low resistance state can be represented as logic 1.

[0063] In an RRAM array, a read voltage can be applied to each RRAM cell individually, with each cell in its respective resistance state, to obtain the actual output current of the RRAM array. Due to the voltage drop, this actual output current is less than the desired output current, which can be obtained by comparing the read voltage with the resistance value of the RRAM cell in each resistance state.

[0064] Furthermore, to obtain the voltage drop coefficient of each RRAM cell under various resistance states, one possible approach is to apply a read voltage to the RRAM cell while it is in any resistance state, and use the ratio of the actual output current to the desired output current as the voltage drop coefficient of the RRAM cell under that resistance state. Another possible approach is to multiply the actual output current by the resistance value of the RRAM cell in that resistance state to obtain the actual voltage value, and then use the ratio of the actual voltage value to the read voltage as the voltage drop coefficient of the RRAM cell under that resistance state.

[0065] S102. The weight model is trained based on the first weight, the first deployment location, and the voltage drop coefficient of each RRAM cell under each resistance state, and the second weight output by the weight model is obtained.

[0066] The weight model can be any neural network model, such as a convolutional neural network or a fully connected neural network.

[0067] The first weight is the weight output by the weight model in the previous round of training of the neural network. In the first round of training of the neural network, the first weight can be a weight obtained randomly.

[0068] The first deployment position is the deployment position where the model output is deployed in the previous round of training. In the first round of training of the neural network, the first deployment position can be a randomly obtained deployment position.

[0069] The first weight, the first deployment location, and the voltage drop coefficient of each RRAM cell under various resistance states are input into the weight model to train the weight model and obtain the second weight output by the weight model. During the weight model training process, the input data includes a training set, which can be a training set for the scenario in which the analog computing circuit is applied. The training set can include input parameters and labels.

[0070] Figure 2 This is a schematic diagram of the structure of a neural network model provided in an embodiment of this application, such as... Figure 2 As shown, taking a convolutional neural network as the weight model as an example, in the weight model processing, the first weight and the input parameters in the training set are first weighted and summed, and then added to the bias parameters in the weight model. A nonlinear transformation is then performed through an activation function to obtain the output parameters. In the weighted summation, the resistance state of each RRAM cell corresponding to the first deployment position is determined, and the voltage drop coefficient corresponding to the resistance state of each RRAM cell is used as the error coefficient. This error coefficient is added to the calculation; that is, the product of the first weight and the error coefficient is used as the weight in the weighted summation calculation during the current iteration of the weight model.

[0071] S103. Input the second weight and the voltage drop coefficient of each RRAM cell under each resistance state into the deployment model to obtain the second deployment position.

[0072] The second deployment position is the deployment position that maximizes the voltage drop coefficient corresponding to the resistance state of each RRAM cell.

[0073] The deployment model can be any deployment neural network or fitting model.

[0074] The second weight and the voltage drop coefficient of each RRAM cell under various resistance states are input into the deployment model. The deployment model can deploy the RRAM cells in the RRAM array according to the second weight, determine the resistance state of each RRAM cell under the current condition, obtain the voltage drop coefficient corresponding to the resistance state of each RRAM cell, and add the voltage drop coefficients corresponding to the resistance states of each RRAM cell to obtain the sum of the voltage drop coefficients of all RRAM cells in the RRAM array. Under the constraints of telecommunications parameters, by adjusting the deployment positions of each RRAM cell in the RRAM array, a second deployment position that maximizes the sum of the voltage drop coefficients is obtained. The telecommunications parameters include, for example, the maximum voltage of the RRAM array, the maximum current of the RRAM array, the maximum current of each RRAM cell, and the maximum current of each RRAM cell.

[0075] Taking a deployment model that uses a neural network as an example, the neural network can, based on the second weights and the voltage drop coefficient of each RRAM cell under various resistance states, obtain the second deployment position that maximizes the voltage drop coefficient corresponding to the resistance state of each RRAM cell, under the constraints of telecommunications parameters. Taking a deployment model that uses a fitting model as an example, the fitting model can, based on fitting methods, obtain the second deployment position that maximizes the voltage drop coefficient corresponding to the resistance state of each RRAM cell, under the constraints of telecommunications parameters.

[0076] S104. Take the second weight as the new first weight and take the second deployment position as the new first deployment position.

[0077] Repeat steps S102 to S104 until the iteration stopping condition is met, then stop training and obtain the second deployment position and the second weight after training is completed.

[0078] The iteration stopping condition can be any preset condition that can be satisfied during the iteration process of the neural network. For example, the iteration stopping condition can be determined based on the number of iterations; for instance, training stops when the number of iterations of the neural network reaches a preset number. Alternatively, the iteration stopping condition can be determined based on the loss function of the neural network; for instance, training stops when the loss function of the neural network is less than or equal to a preset threshold.

[0079] The neural network adversarial training method of this application includes a weight model and a deployment model. Under different resistance states of each RRAM cell in the RRAM array, a read voltage is applied to each RRAM cell to obtain the voltage drop coefficient of each RRAM cell under each resistance state. The weight model is trained based on a first weight, a first deployment position, and the voltage drop coefficient of each RRAM cell under each resistance state to obtain a second weight. The second weight and the voltage drop coefficient of each RRAM cell under each resistance state are input into the deployment model to obtain a second deployment position. The second weight is used as the new first weight, and the second deployment position is used as the new first deployment position. Training is repeated until the iteration stopping condition is met, at which point training stops, resulting in the trained second deployment position and trained second weight. This method adds the voltage drop coefficient of the RRAM cells to the neural network adversarial training to reduce the impact of the RRAM cell voltage drop on the neural network training. Compared with related RRAM-based neural network adversarial training methods, it does not require adjustments to the circuit hardware design, reducing the difficulty of reducing the impact of voltage drop.

[0080] The following example illustrates the situation with two resistance states for each RRAM cell.

[0081] Figure 3 A flowchart illustrating a neural network adversarial training method provided in this application embodiment. Figure 2 When the resistance value of each RRAM cell has two states, such as... Figure 3 As shown, the neural network adversarial training method specifically includes the following steps:

[0082] S301. When each RRAM cell in the RRAM array is in a high-impedance state, apply a first read voltage to each RRAM cell to obtain the first voltage drop coefficient of each RRAM cell.

[0083] When each RRAM cell has two resistance states, one possible implementation is that each RRAM cell has either a high resistance state or a low resistance state. For example, a high resistance state is typically represented by logic 0, and a low resistance state is typically represented by logic 1.

[0084] The first read voltage is the voltage used to read the stored data of the RRAM cell when the resistance of the RRAM cell is in a high-resistance state. The first read voltage is a small voltage, such as 0.5V. It should be understood that the first read voltage does not change the resistance state of the RRAM cell.

[0085] The first voltage drop factor is used to characterize the effect of voltage drop on the output current of the RRAM array when the RRAM is in a high-resistance state.

[0086] In an RRAM array, a first read voltage can be applied to each RRAM cell individually while it is in a high-impedance state, and the actual output current of the RRAM array can be obtained. Due to the voltage drop, the actual output current is less than the desired output current, which can be obtained by the ratio of the first read voltage to the resistance of the RRAM cell in the high-impedance state.

[0087] Furthermore, to obtain the first voltage drop coefficient for each RRAM cell in a high-impedance state, one possible approach is to use the ratio of the actual output current to the desired output current as the first voltage drop coefficient. Another possible approach is to multiply the actual output current by the resistance of the RRAM cell in a high-impedance state to obtain the actual voltage value, and then use the ratio of the actual voltage value to the first read voltage as the first voltage drop coefficient.

[0088] S302. With each RRAM cell in the RRAM array in a low-resistance state, apply a second read voltage to each RRAM cell to obtain the second voltage drop coefficient of each RRAM cell.

[0089] The second read voltage is the voltage used to read the stored data from the RRAM cell when its resistance is low. The second read voltage is a small voltage, such as 0.5V, and it does not change the resistance state of the RRAM cell. The first read voltage and the second read voltage can be equal or unequal.

[0090] The second voltage drop factor is used to characterize the effect of voltage drop on the output current of the RRAM array when the RRAM is in a low-resistance state.

[0091] In an RRAM array, a second read voltage can be applied to each RRAM cell individually while each RRAM cell is in a low-resistance state, and the actual output current of the RRAM array can be obtained. Due to the voltage drop, the actual output current is less than the desired output current, which can be obtained based on the ratio of the second read voltage to the resistance of the RRAM cell in the low-resistance state.

[0092] Furthermore, to obtain the second voltage drop coefficient for each RRAM cell in its low-impedance state, one possible approach is to use the ratio of the actual output current to the desired output current as the second voltage drop coefficient. Another possible approach is to multiply the actual output current by the resistance of the RRAM cell in its low-impedance state to obtain the actual voltage value, and then use the ratio of this actual voltage value to the second read voltage as the second voltage drop coefficient.

[0093] S303. The weight model is trained based on the first weight, the first deployment location, and the first and second voltage drop coefficients of each RRAM unit to obtain the second weight output by the weight model.

[0094] The weight model is trained based on a first weight, a first deployment location, and a first and a second voltage drop coefficient for each RRAM cell. During training, the weight model includes determining the resistance state of each RRAM cell based on the first weight and the first deployment location. If the resistance state of each RRAM cell is high, the first voltage drop coefficient corresponding to that resistance state is determined; conversely, if the resistance state of each RRAM cell is low, the second voltage drop coefficient corresponding to that resistance state is determined. The weight model is trained using the first weight and the determined first or second voltage drop coefficient corresponding to the resistance state of each RRAM cell to obtain the second weight output by the weight model.

[0095] S304. Input the second weight and the first or second voltage drop coefficient of each RRAM cell into the deployment model to obtain the second deployment location.

[0096] The second deployment location is the deployment location of the RRAM cells in the RRAM array when the impact of voltage drop is minimized.

[0097] The second weight and the first or second voltage drop coefficient of each RRAM cell are input into the deployment model. The deployment model determines the first voltage drop coefficient corresponding to the resistance state of each RRAM cell by determining that the resistance state of each RRAM cell is high resistance state, or determines that the resistance state of each RRAM cell is low resistance state, and obtains the second voltage drop coefficient corresponding to the resistance state of each RRAM cell. The second deployment position is obtained that maximizes the voltage drop coefficient corresponding to the resistance state of each RRAM cell.

[0098] The deployment model is based on the second weight and the deployment location of the RRAM cells in the RRAM array to obtain the voltage drop coefficient corresponding to the resistance state of each RRAM cell. Under the current deployment location of each RRAM cell, whether it is in a high-resistance state or a low-resistance state, the voltage drop coefficient of each RRAM cell is determined one by one. If the RRAM cell is in a high-resistance state, its first voltage drop coefficient is added to the voltage drop coefficient sum; if the RRAM cell is in a low-resistance state, its second voltage drop coefficient is added to the voltage drop coefficient sum. This process is repeated for each RRAM cell in the RRAM array to determine the voltage drop coefficient sum of all RRAM cells in the RRAM array under the current deployment location. The deployment locations of the RRAM cells are then adjusted, and under the constraints of telecommunications parameters, a second deployment location that maximizes the voltage drop coefficient sum is determined.

[0099] After determining the deployment location of the RRAM cells in the RRAM array, the sum of the voltage drop coefficients of each RRAM cell in the RRAM array is determined based on the first or second voltage drop coefficient of each RRAM cell. If the RRAM cell is in a high-resistance state, the first voltage drop coefficient of that RRAM is added to the sum of the voltage drop coefficients; if the RRAM cell is in a low-resistance state, the second voltage drop coefficient of that RRAM is added to the sum of the voltage drop coefficients. This process is repeated for each RRAM cell in the RRAM array to determine the sum of the voltage drop coefficients of each RRAM cell in the RRAM array at the current weight deployment location.

[0100] Adjusting the deployment locations of RRAM units, under the constraints of telecommunications parameters, to determine the second deployment location that maximizes the sum of voltage drop coefficients, can be achieved by adjusting the deployment model according to the columns of the RRAM units in the RRAM array, i.e., shuffling the column order of the RRAM units in the RRAM array. Each time the deployment locations of the RRAM units are adjusted, the sum of the voltage drop coefficients of all RRAM units in the RRAM array under the current deployment location is determined. Under the constraints of telecommunications parameters, the sum of the voltage drop coefficients of all RRAM units in the RRAM array under each deployment location is compared, and the deployment location that maximizes the sum of the voltage drop coefficients is determined as the second deployment location.

[0101] In this context, the second weight corresponds to an RRAM cell. Optionally, for each bit of the second weight, each of the one or more RRAM cells can be set to a high-impedance state or a low-impedance state, so that the one or more RRAM cells represent each bit of the second weight. For example, if one RRAM cell represents each bit, then if the bit of the second weight is 1, the RRAM cell corresponding to that second weight is set to a low-impedance state; if the bit of the second weight is 0, then the RRAM cell is set to a high-impedance state. Similarly, if two RRAM cells represent each bit, then if the bit of the second weight is 1, then the first RRAM cell corresponding to that second weight is set to a low-impedance state, and the second RRAM cell is set to a high-impedance state; if the bit of the second weight is 0, then the first RRAM cell is set to a high-impedance state, and the second RRAM cell is set to a low-impedance state.

[0102] S305, take the second weight as the new first weight, and take the second deployment position as the new first deployment position.

[0103] Repeat steps S303 to S305 until the iteration stopping condition is met, then stop training and obtain the second deployment position and the second weight after training is completed.

[0104] The following example illustrates the specific implementation of the neural network adversarial training method proposed in this application, in which the second weight and the voltage drop coefficient of each RRAM unit under various resistance states are input into the fitting model to obtain the second deployment position.

[0105] Figure 4 This is a schematic diagram of an RRAM array provided in an embodiment of this application. Figure 4As shown, the RRAM array includes multiple RRAM cells, a word line decoder (WL decoder), and a bit line decoder (BL decoder). The RRAM array includes word lines (WL), bit lines (BL), and source lines (SL).

[0106] Each RRAM cell consists of an RRAM and a Metal-Oxide-Semiconductor Field-Effect Transistor (MOS). The WL Decoder selects the RRAM cell containing a specific WL, and the BL Decoder selects the RRAM cell containing a specific BL. The source line is used to output the current of the RRAM array. When the WL Decoder selects the RRAM cell containing a specific WL, the MOS on that WL causes the BL and SL of the RRAM cell containing the MOS to conduct.

[0107] Figure 5 A schematic diagram of the deployment positions of each RRAM cell in an RRAM array provided in this application. Figure 1 If so Figure 4 Taking the RRAM array shown as an example, if each row of the RRAM array includes 8 RRAM cells, and the weights are quantized to 8 bits, then each row of RRAM cells can correspond to one weight, and the RRAM array can correspond to m weights. The deployment positions of the RRAM cells in the RRAM array can be adjusted. For example, according to the bit order of the weights, the highest bit of the weight can be assigned to the RRAM cell in the first column, and the lowest bit of the weight can be assigned to the RRAM cell in the 8th column, such as... Figure 5 As shown, This represents the j-th position of the i-th weight in the neural network, arranged from least significant to most significant. If it is 0, then Figure 4 The resistance state of the RRAM cell at the corresponding position in the RRAM array shown is switched to a high-impedance state. Specifically, the RRAM cell in the i-th row and j-th column can be selected using WL Decoder and BL Decoder, and a specific write voltage can be applied to set the RRAM cell to a high-impedance state. If If it is 1, then... Figure 4 The resistance state of the RRAM cell at the corresponding position in the RRAM array shown is switched to a low resistance state.

[0108] Figure 6 A schematic diagram of the deployment positions of each RRAM cell in an RRAM array provided in this application. Figure 2 For example, the deployment positions of each RRAM cell in the RRAM array can also be adjusted column by column. Figure 5 The positions of the bits in column 2 and column 8 are swapped, as follows: Figure 6 As shown, correspond Figure 4 The RRAM cell in the 8th column of the RRAM array shown. correspond Figure 4 The RRAM cell in the second column of the RRAM array shown. For example, if If it is 0, then Figure 4 The RRAM cell in the i-th row and 8-th column of the RRAM array shown is set to a high-impedance state.

[0109] As illustrated in the above embodiment, the deployment positions of each RRAM cell in the RRAM array are adjusted column by column. Each RRAM cell is in a high-resistance or low-resistance state. At the current deployment position, the sum of the voltage drop coefficients of all RRAM cells in the RRAM array is determined based on the voltage drop coefficient of each RRAM cell under each resistance state. Taking the resistance state of the RRAM cell as including high-resistance or low-resistance states as an example, for instance, if the RRAM cell is in a high-resistance state, the first voltage drop coefficient of that RRAM cell is used as its voltage drop coefficient; if the RRAM cell is in a low-resistance state, the second voltage drop coefficient of that RRAM cell is used as its voltage drop coefficient. The voltage drop coefficients of each RRAM cell are added together to determine the sum of the voltage drop coefficients at the current weighted deployment position.

[0110] According to the above method, the deployment positions of each RRAM cell in the RRAM array are adjusted column by column to obtain the sum of voltage drop coefficients at any deployment position. Based on the second weight and the deployment positions of each RRAM cell in the RRAM array, the deployment position of each RRAM cell in the RRAM array with the largest sum of voltage drop coefficients is selected as the second deployment position.

[0111] One possible approach is to input the second weight and the voltage drop coefficient of each RRAM cell under various resistance states into the fitting model. The fitting model is based on an optimization algorithm, with the optimization objective being to maximize the sum of the voltage drop coefficients of each RRAM cell in the RRAM array. In each iteration of the optimization algorithm, the sum of the voltage drop coefficients of each RRAM cell in the RRAM array is determined according to the deployment position of each RRAM cell in the RRAM array, thus obtaining the second deployment position that maximizes the sum of the voltage drop coefficients.

[0112] An optimization algorithm is a method that aims to achieve the optimal goal under certain constraints. Examples include genetic algorithms and Bayesian optimization algorithms.

[0113] Based on optimization algorithms in related technologies, with the maximum voltage drop coefficient as the optimization objective and telecommunications parameters as constraints for the optimization algorithm, a second deployment location that maximizes the voltage drop coefficient can be obtained. These telecommunications parameter conditions include, for example, the voltage of the analog computing circuit being less than or equal to the maximum voltage of the analog computing circuit, and / or the current of the analog computing circuit being less than or equal to the maximum current of the analog computing circuit.

[0114] For example, taking the genetic algorithm as an example, the RRAM array is first encoded by columns. The order of the columns can be used as the encoding value. In this way, for example, the nth column is encoded as n. The column codes are arranged in any order as the initial deployment position. In each iteration of the optimization algorithm, the genetic algorithm adjusts the arrangement of the column codes, that is, adjusts the deployment position of each RRAM cell in the RRAM array, and determines the voltage drop coefficient corresponding to the deployment position of each RRAM cell in the RRAM array, until the optimal solution with the largest voltage drop coefficient is output, and the second deployment position with the largest voltage drop coefficient is found.

[0115] The neural network adversarial training method of this application determines a second deployment position that maximizes the voltage drop coefficient by adjusting the deployment position of each RRAM cell in the RRAM array. When the voltage drop coefficient is maximized, data transmission efficiency is higher, and the reliability of RRAM-based computation is also higher.

[0116] Optionally, in the neural network adversarial training method of this application, the voltage drop coefficient of each RRAM cell under each resistance state can also be stored in a voltage drop coefficient table.

[0117] In this method, after obtaining the voltage drop coefficient of each RRAM cell under various resistance conditions, the voltage drop coefficient of each RRAM cell under various resistance conditions is stored in a voltage drop coefficient table. The voltage drop coefficient table may include a description of the location of each RRAM cell in the RRAM array and the voltage drop coefficient under various resistance conditions.

[0118] In the implementation based on the voltage drop factor table, the weight model is trained accordingly based on the first weight, the first deployment location, and the voltage drop factor of each RRAM cell corresponding to the first weight. The first weight, the first deployment location, and the voltage drop factor table can be input into the weight model. The weight model determines the resistance state of each RRAM cell based on the first weight and the first deployment location. Based on the resistance state of each RRAM cell, the voltage drop factor corresponding to the resistance state of each RRAM cell is looked up from the voltage drop factor table. The weight model is trained based on the first weight and the voltage drop factor corresponding to the resistance state of each RRAM cell.

[0119] In the implementation based on the voltage drop factor table, the second weight and the voltage drop factor of each RRAM cell under each resistance state are input into the deployment model to obtain the second deployment position. The second weight and the voltage drop factor table can be input into the deployment model. The deployment model determines the resistance state of each RRAM cell and, based on the resistance state of each RRAM cell, looks up the voltage drop factor corresponding to the resistance state of each RRAM cell in the voltage drop factor table to obtain the second deployment position that maximizes the voltage drop factor corresponding to the resistance state of each RRAM cell in the RRAM array.

[0120] Taking the resistance state of an RRAM cell as an example, which includes a high-resistance state or a low-resistance state, the corresponding first voltage drop factor or second voltage drop factor is looked up from the voltage drop factor table according to whether each RRAM cell is in a high-resistance state or a low-resistance state, and the sum of the voltage drop factors of each RRAM cell in the RRAM array is determined. Specifically, looking up the corresponding first voltage drop factor or second voltage drop factor from the voltage drop factor table, for example, taking a weighted bit as 1 and deployed in a corresponding RRAM cell (i.e., the RRAM cell is in a low-resistance state), the data stored in that RRAM cell is found in the voltage drop factor table according to its location, and its second voltage drop factor is obtained.

[0121] The following example illustrates the specific implementation steps of the neural network adversarial training method of this application, where multiple weights correspond to multiple RRAM arrays, and the resistance state of each RRAM cell in the multiple RRAM arrays includes a high-resistance state or a low-resistance state. Figure 7 This is a schematic diagram of the structure of a plurality of RRAM arrays provided in an embodiment of this application. Figure 7 As shown, multiple weights in a neural network can be deployed in multiple RRAM arrays.

[0122] Figure 8 A flowchart illustrating a neural network adversarial training method provided in this application embodiment. Figure 3 .like Figure 8 As shown, the specific steps include:

[0123] S801. Apply a first read voltage to each RRAM cell in the RRAM array when each RRAM cell is in a high-impedance state, and obtain the first voltage drop coefficient of each RRAM cell.

[0124] One possible approach is to apply a first read voltage to each RRAM cell in the RRAM array when each RRAM cell is in a high-impedance state, obtain the first output current of the RRAM array, determine the ratio of the first read voltage to the first resistance value of each RRAM in the high-impedance state as the first desired current, and determine the ratio of the first output current to the first desired current as the first voltage drop factor.

[0125] The first resistance value is the resistance of each RRAM in its high-resistance state. Figure 7 Taking the RRAM cell in the first row and first column of the RRAM array shown as an example, the RRAM cell in the first column is selected by WL Decoder and the first read voltage is output to BL of the first row by BL Decoder to obtain the first output current of the RRAM array, that is, to obtain the output current of the SL terminal of the RRAM array. Since the first output current is the current output by the RRAM cell under the influence of voltage drop, the first output current is less than the first expected current.

[0126] S802. Apply a second read voltage to each RRAM cell in the RRAM array when each RRAM cell is in a low-resistance state, and obtain the second voltage drop coefficient of each RRAM cell.

[0127] One possible approach is to apply a second read voltage to each RRAM cell in the RRAM array when each RRAM cell is in a low-resistance state, obtain a second output current of the RRAM array, determine the ratio of the second read voltage to the second resistance value of each RRAM in the low-resistance state as a second desired current, and determine the ratio of the second output current to the second desired current as a second voltage drop factor.

[0128] The second resistance value is the resistance of each RRAM in its low-resistance state. Figure 7 Taking the RRAM cell in the first row and first column of the RRAM array shown as an example, the RRAM cell in the first column is selected by WL Decoder, and the second read voltage is output to BL of the first row by BL Decoder to obtain the second output current of the RRAM array, that is, to obtain the output current of the SL terminal of the RRAM array. Since the second output current is the current output by the RRAM cell under the influence of voltage drop, the second output current is less than the second expected current.

[0129] S803. Store the first voltage drop factor and the second voltage drop factor of each RRAM cell in the voltage drop factor table.

[0130] A voltage drop factor table may include, for example, the number of array rows, the number of array columns, the number of cell rows, the number of cell columns, a first voltage drop factor, and a second voltage drop factor. The number of array rows and columns indicates the location of the RRAM array; for example, when the number of array rows is 1 and the number of array columns is 1, it can indicate, as shown below. Figure 7In the matrix composed of RRAM arrays, the RRAM array in the first row and first column is represented. The number of cell rows and columns indicates the position of the RRAM cell in the RRAM array. For example, when the number of cell rows is 2 and the number of cell columns is 1, it can indicate the RRAM cell in the second row and first column of the RRAM array. The first voltage drop factor is the first voltage drop factor of the RRAM cell in the high-impedance state, determined by the number of array rows, array columns, cell rows, and cell columns. The second voltage drop factor is the second voltage drop factor of the RRAM cell in the high-impedance state, determined by the number of array rows, array columns, cell rows, and cell columns.

[0131] Optionally, when multiple RRAM arrays are integrated on the same hardware, the location of the RRAM cell can be determined based on the row and column of the location. The voltage drop factor table may include, for example, the number of cell rows, the number of cell columns, a first voltage drop factor, and a second voltage drop factor.

[0132] It should be understood that the above is only an example of the structure of the voltage drop factor table. The voltage drop factor table can also be implemented with other structures. The voltage drop factor table can store and query the first voltage drop factor and the second voltage drop factor of each RRAM cell.

[0133] S804. Input the first weight, the first deployment location, and the pressure drop coefficient table into the weight model to obtain the second weight output by the weight model.

[0134] The first weight, the first deployment location, and the voltage drop coefficient table are input into the weight model. The weight model determines the resistance state of each RRAM cell based on the first weight and the first deployment location. Based on the resistance state of each RRAM cell, the voltage drop coefficient corresponding to the resistance state of each RRAM cell is looked up from the voltage drop coefficient table. That is, if the resistance state of each RRAM cell is high, the first voltage drop coefficient corresponding to the resistance state of each RRAM cell is looked up from the voltage drop coefficient table; or, if the resistance state of each RRAM cell is low, the second voltage drop coefficient corresponding to the resistance state of each RRAM cell is looked up from the voltage drop coefficient table. The weight model is trained based on the first weight and the voltage drop coefficient corresponding to the resistance state of each RRAM cell.

[0135] S805. Input the second weight and pressure drop coefficient table into the deployment model to obtain the second deployment location.

[0136] The second weight and voltage drop coefficient table are input into the deployment model. The deployment model determines the resistance state of each RRAM cell and, based on the resistance state of each RRAM cell, looks up the voltage drop coefficient corresponding to the resistance state of each RRAM cell in the voltage drop coefficient table. That is, if the resistance state of each RRAM cell is high resistance, the first voltage drop coefficient corresponding to the resistance state of each RRAM cell is looked up in the voltage drop coefficient table. Alternatively, if the resistance state of each RRAM cell is low resistance, the second deployment position that maximizes the voltage drop coefficient corresponding to the resistance state of each RRAM cell in the RRAM array is obtained.

[0137] S806, take the second weight as the new first weight, and take the second deployment position as the new first deployment position.

[0138] Repeat steps S804 to S806 until the iteration stopping condition is met, then stop training and obtain the second deployment position and the second weight after training is completed.

[0139] The neural network adversarial training method of this application includes a weight model and a deployment model. Under different resistance states of each RRAM cell in the RRAM array, a read voltage is applied to each RRAM cell to obtain the voltage drop coefficient of each RRAM cell under each resistance state. The weight model is trained based on a first weight, a first deployment position, and the voltage drop coefficient of each RRAM cell under each resistance state to obtain a second weight. The second weight and the voltage drop coefficient of each RRAM cell under each resistance state are input into the deployment model to obtain a second deployment position. The second weight is used as the new first weight, and the second deployment position is used as the new first deployment position. Training is repeated until the iteration stopping condition is met, at which point training stops, resulting in the trained second deployment position and trained second weight. This method adds the voltage drop coefficient of the RRAM cells to the neural network adversarial training to reduce the impact of the RRAM cell voltage drop on the neural network training. Compared with related RRAM-based neural network adversarial training methods, it does not require adjustments to the circuit hardware design, reducing the difficulty of reducing the impact of voltage drop.

[0140] This application also proposes an analog computing circuit, which includes an RRAM array. Each RRAM cell in the RRAM array is equipped with a trained second weight obtained by the above-mentioned neural network adversarial training method, and the trained second weight is deployed according to the trained second deployment position.

[0141] The analog computing circuit implemented based on the second weights and the second deployment positions trained using the neural network adversarial training method can realize the calculation function of the weight model. Because the error introduced by the voltage drop of the RRAM cell is added to the neural network adversarial training during the training process, the impact of the voltage drop on the neural network adversarial training is reduced. The analog computing circuit implemented based on the second weights and the second deployment positions trained reduces the impact of the voltage drop of each RRAM cell in the RRAM array.

[0142] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this application.

[0143] It should be further noted that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0144] The above describes the method embodiments of this application. The apparatus provided in the embodiments of this application will be described below.

[0145] Figure 9 This is a schematic diagram of the structure of a neural network adversarial training device provided in an embodiment of this application. Figure 9 As shown, the neural network adversarial training device 900 may include, for example, an acquisition module 901 and a training module 902. Optionally, it may also include a storage module.

[0146] The acquisition module 901 is used to apply a read voltage to each RRAM cell when each RRAM cell in the RRAM array is in a different resistance state, and to acquire the voltage drop coefficient of each RRAM cell in each resistance state.

[0147] Training module 902 is used to train the weight model based on the first weight, the first deployment position, and the voltage drop coefficient of each RRAM unit under each resistance state, and obtain the second weight output by the weight model; input the second weight and the voltage drop coefficient of each RRAM unit under each resistance state into the deployment model to obtain the second deployment position; wherein, the second deployment position is the deployment position that maximizes the voltage drop coefficient corresponding to the resistance state of each RRAM unit; use the second weight as the new first weight, and use the second deployment position as the new first deployment position, and repeat this step until the iteration stopping condition is met, then stop training, and obtain the trained second deployment position and trained second weight.

[0148] One possible implementation is that the acquisition module 901 is specifically used to input the second weight and the voltage drop coefficient of each RRAM cell under each resistance state into the deployment neural network or fitting model to obtain the second deployment position.

[0149] For example, the acquisition module 901 is specifically used to input the second weight and the voltage drop coefficient of each RRAM cell under each resistance state into the fitting model. The fitting model is based on an optimization algorithm, with the goal of maximizing the sum of the voltage drop coefficients of each RRAM cell in the RRAM array. In each iteration of the optimization algorithm, the sum of the voltage drop coefficients of each RRAM cell in the RRAM array is determined according to the deployment position of each RRAM cell in the RRAM array, and the second deployment position that maximizes the sum of the voltage drop coefficients is obtained.

[0150] One possible implementation is that the storage module is specifically used to store the voltage drop coefficient of each RRAM cell under each resistance state in a voltage drop coefficient table.

[0151] Accordingly, the acquisition module 901 is specifically used to input the first weight, the first deployment location, and the voltage drop coefficient table into the weight model; determine the resistance state of each RRAM cell based on the first weight and the first deployment location through the weight model; and look up the voltage drop coefficient corresponding to the resistance state of each RRAM cell from the voltage drop coefficient table based on the resistance state of each RRAM cell; and train the weight model based on the first weight and the voltage drop coefficient corresponding to the resistance state of each RRAM cell.

[0152] Accordingly, the training module 902 is specifically used to input the second weight and voltage drop coefficient table into the deployment model. The deployment model determines the resistance state of each RRAM cell, and based on the resistance state of each RRAM cell, looks up the voltage drop coefficient corresponding to the resistance state of each RRAM cell from the voltage drop coefficient table to obtain the second deployment position that maximizes the voltage drop coefficient corresponding to the resistance state of each RRAM cell in the RRAM array.

[0153] In one possible implementation, the acquisition module 901 is specifically used to: apply a first read voltage to each RRAM cell when each RRAM cell in the RRAM array is in a high-resistance state, and acquire a first voltage drop coefficient of each RRAM cell; and apply a second read voltage to each RRAM cell when each RRAM cell in the RRAM array is in a low-resistance state, and acquire a second voltage drop coefficient of each RRAM cell.

[0154] Accordingly, the training module 902 is specifically used to train the weight model based on the first weight, the first deployment location, and the first and second voltage drop coefficients of each RRAM unit, to obtain the second weight output by the weight model; input the second weight and the first or second voltage drop coefficient of each RRAM unit into the deployment model, and the deployment model obtains the first voltage drop coefficient corresponding to the resistance state of each RRAM unit by determining that the resistance state of each RRAM unit is a high resistance state, or by determining that the resistance state of each RRAM unit is a low resistance state, to obtain the second voltage drop coefficient corresponding to the resistance state of each RRAM unit, and obtain the second deployment location that maximizes the voltage drop coefficient corresponding to the resistance state of each RRAM unit.

[0155] For example, the acquisition module 901 is specifically configured to: apply a first read voltage to each RRAM cell in the RRAM array when each RRAM cell is in a high-resistance state, acquire the first output current of the RRAM array, and determine the ratio of the first read voltage to the first resistance value of each RRAM in the high-resistance state as a first desired current, and determine the ratio of the first output current to the first desired current as a first voltage drop factor; and apply a second read voltage to each RRAM cell in the RRAM array when each RRAM cell is in a low-resistance state, acquire the second output current of the RRAM array, and determine the ratio of the second read voltage to the second resistance value of each RRAM in the low-resistance state as a second desired current, and determine the ratio of the second output current to the second desired current as a second voltage drop factor.

[0156] One possible implementation is that the training module 902 is specifically used to set each RRAM cell in one or more RRAM cells to the corresponding resistance state for each bit of the second weight, so that the one or more RRAM cells represent each bit.

[0157] The apparatus provided in this application embodiment can execute the above method embodiment, and its implementation principle and technical effect are similar, so it will not be described again here.

[0158] It should be understood that the above-described device embodiments are merely illustrative, and the device of this application can also be implemented in other ways. For example, the division of units / modules in the above embodiments is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units, modules, or components may be combined, or integrated into another system, or some features may be ignored or not executed.

[0159] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 10 As shown, the electronic device may include at least one processor 1001 and a memory 1002.

[0160] The memory 1002 is used to store programs. Specifically, the program may include program code, which includes computer operation instructions.

[0161] Memory 1002 may include high-speed RAM memory, and may also include non-volatile memory.

[0162] The processor 1001 is used to execute computer execution instructions stored in the memory 1002 to implement the method of the foregoing method embodiments. The processor 1001 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application.

[0163] Optionally, the electronic device may also include a communication interface 1003. In specific implementations, if the communication interface 1003, the memory 1002, and the processor 1001 are implemented independently, the communication interface 1003, the memory 1002, and the processor 1001 can be interconnected via a bus to complete communication between them.

[0164] Optionally, in a specific implementation, if the communication interface 1003, memory 1002 and processor 1001 are integrated on a single chip, then the communication interface 1003, memory 1002 and processor 1001 can communicate through an internal interface.

[0165] This application also provides a computer-readable storage medium, which may include various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), and a random access memory (RAM). Specifically, the computer-readable storage medium stores program instructions, which are used to implement the actions of the above-described method implementation.

[0166] This application also provides a program product including executable instructions stored in a readable storage medium. At least one processor of an electronic device can read the executable instructions from the readable storage medium, and the at least one processor executes the executable instructions to cause the electronic device to perform the actions described in the method embodiments.

[0167] Furthermore, unless otherwise specified, the functional units / modules in the various embodiments of this application can be integrated into one unit / module, or each unit / module can exist physically separately, or two or more units / modules can be integrated together. The integrated units / modules described above can be implemented in hardware or as software program modules.

[0168] When an integrated unit / module is implemented in hardware, the hardware can be digital circuits, analog circuits, etc. The physical implementation of the hardware structure includes, but is not limited to, transistors. Unless otherwise specified, the processor can be any suitable hardware processor, such as a CPU, GPU, FPGA, DSP, and ASIC, etc. Unless otherwise specified, the storage unit can be any suitable storage medium, such as Resistive Random Access Memory (RRAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Enhanced Dynamic Random Access Memory (EDRAM), High-Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), etc.

[0169] If the integrated unit / module is implemented as a software program module and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), and portable hard drives.

[0170] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0171] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM and RAM.

Claims

1. A neural network adversarial training method, characterized in that, The neural network includes a weight model and a deployment model, and the method includes: With each RRAM cell in the RRAM array having a different resistance value, a read voltage is applied to each RRAM cell to obtain the voltage drop coefficient of each RRAM cell under each resistance value state; The weight model is trained based on the first weight, the first deployment position, and the voltage drop coefficient of each RRAM unit under each resistance state to obtain the second weight output by the weight model; the second weight and the voltage drop coefficient of each RRAM unit under each resistance state are input into the deployment model to obtain the second deployment position; wherein, the second deployment position is the deployment position that maximizes the voltage drop coefficient corresponding to the resistance state of each RRAM unit; the second weight is used as the new first weight, and the second deployment position is used as the new first deployment position, and this step is repeated until the iteration stopping condition is met, then the training is stopped, and the trained second deployment position and trained second weight are obtained.

2. The method according to claim 1, characterized in that, The step of inputting the second weight and the voltage drop coefficient of each RRAM cell under each resistance state into the deployment model to obtain the second deployment location includes: The second weight and the voltage drop coefficient of each RRAM cell under each resistance state are input into the deployment neural network or fitting model to obtain the second deployment position.

3. The method according to claim 2, characterized in that, The second weight and the voltage drop coefficient of each RRAM cell under each resistance state are input into the fitting model to obtain the second deployment location, including: The second weight and the voltage drop coefficient of each RRAM cell under each resistance state are input into the fitting model. The fitting model is based on an optimization algorithm, with the goal of maximizing the sum of the voltage drop coefficients of each RRAM cell in the RRAM array. In each iteration of the optimization algorithm, the sum of the voltage drop coefficients of each RRAM cell in the RRAM array is determined according to the deployment position of each RRAM cell in the RRAM array, and the second deployment position that maximizes the sum of the voltage drop coefficients is obtained.

4. The method according to claim 1, characterized in that, Also includes: The voltage drop coefficient of each RRAM cell under each resistance value state is stored in the voltage drop coefficient table; The training of the weight model based on the first weight, the first deployment location, and the voltage drop coefficient of each RRAM cell corresponding to the first weight includes: The first weight, the first deployment location, and the voltage drop coefficient table are input into the weight model. The weight model determines the resistance state of each RRAM cell based on the first weight and the first deployment location. Based on the resistance state of each RRAM cell, the voltage drop coefficient corresponding to the resistance state of each RRAM cell is looked up from the voltage drop coefficient table. The weight model is trained based on the first weight and the voltage drop coefficient corresponding to the resistance state of each RRAM cell. The step of inputting the second weight and the voltage drop coefficient of each RRAM cell under each resistance state into the deployment model to obtain the second deployment location includes: The second weight and the voltage drop coefficient table are input into the deployment model. The deployment model determines the resistance state of each RRAM cell and, based on the resistance state of each RRAM cell, looks up the voltage drop coefficient corresponding to the resistance state of each RRAM cell in the voltage drop coefficient table to obtain the second deployment position that maximizes the voltage drop coefficient corresponding to the resistance state of each RRAM cell in the RRAM array.

5. The method according to claim 1, characterized in that, The step of applying a read voltage to each RRAM cell in the RRAM array, given that each RRAM cell is in a different resistance state, and obtaining the voltage drop coefficient of each RRAM cell in each resistance state, includes: When each RRAM cell in the RRAM array is in a high-resistance state, a first read voltage is applied to each RRAM cell to obtain a first voltage drop coefficient for each RRAM cell; and when each RRAM cell in the RRAM array is in a low-resistance state, a second read voltage is applied to each RRAM cell to obtain a second voltage drop coefficient for each RRAM cell. The weight model is trained based on the first weight, the first deployment location, and the voltage drop coefficient of each RRAM cell under various resistance states to obtain the second weight output by the weight model, including: The weight model is trained based on the first weight, the first deployment location, and the first and second voltage drop coefficients of each RRAM unit to obtain the second weight output by the weight model; The step of inputting the second weight and the voltage drop coefficient of each RRAM cell under each resistance state into the deployment model to obtain the second deployment location includes: The second weight and the first or second voltage drop coefficient of each RRAM cell are input into the deployment model. The deployment model determines the first voltage drop coefficient corresponding to the resistance state of each RRAM cell by determining that the resistance state of each RRAM cell is high resistance, or determines that the resistance state of each RRAM cell is low resistance, and obtains the second voltage drop coefficient corresponding to the resistance state of each RRAM cell. This yields a second deployment location that maximizes the voltage drop coefficient corresponding to the resistance state of each RRAM cell.

6. The method according to claim 5, characterized in that, The steps of applying a first read voltage to each RRAM cell in the RRAM array when each RRAM cell is in a high-resistance state to obtain a first voltage drop coefficient for each RRAM cell, and applying a second read voltage to each RRAM cell in the RRAM array when each RRAM cell is in a low-resistance state to obtain a second voltage drop coefficient for each RRAM cell, include: When each RRAM cell is in a high-impedance state, the first read voltage is applied to each RRAM cell in the RRAM array to obtain the first output current of the RRAM array. The ratio of the first read voltage to the first resistance value of each RRAM cell in the high-impedance state is determined as the first desired current, and the ratio of the first output current to the first desired current is determined as the first voltage drop coefficient. When each RRAM cell is in a low-resistance state, the second read voltage is applied to each RRAM cell in the RRAM array to obtain the second output current of the RRAM array. The ratio of the second read voltage to the second resistance value of each RRAM cell in the low-resistance state is determined as the second desired current, and the ratio of the second output current to the second desired current is determined as the second voltage drop coefficient.

7. The method according to any one of claims 1-6, characterized in that, Also includes: For each bit of the second weight, each of the one or more RRAM cells is set to the resistance state corresponding to the bit, so that the one or more RRAM cells characterize each bit.

8. An analog computing circuit, characterized in that, include: RRAM array; Each RRAM cell in the RRAM array is equipped with a trained second weight obtained by the method described in any one of claims 1-7, and the trained second weight is deployed according to the trained second deployment position.

9. A neural network adversarial training device, characterized in that, The neural network includes a weight model and a deployment model, including: The acquisition module is used to apply a read voltage to each RRAM cell in the RRAM array when each RRAM cell is in a different resistance state, and to acquire the voltage drop coefficient of each RRAM cell in each resistance state. The training module is used to train the weight model based on the first weight, the first deployment position, and the voltage drop coefficient of each RRAM unit under each resistance state, to obtain the second weight output by the weight model; input the second weight and the voltage drop coefficient of each RRAM unit under each resistance state into the deployment model to obtain the second deployment position; wherein, the second deployment position is the deployment position that maximizes the voltage drop coefficient corresponding to the resistance state of each RRAM unit; use the second weight as the new first weight, and use the second deployment position as the new first deployment position, repeat this step until the iteration stopping condition is met, then stop training, and obtain the trained second deployment position and trained second weight.

10. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1-6.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1-6.

12. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method of any one of claims 1-6.

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