Graphics processor, cache data sharing method, equipment, medium and program product

Abstract

The invention discloses a graphics processor, a cache data sharing method, equipment, a medium and a program product, and relates to the technical field of processors, first-level caches in one-to-one correspondence with computing cores are arranged, and pairwise communication links between the first-level caches and a central label buffer area are constructed through an interconnection interface unit; in cooperation with a global label table recording label information of all first-level cache data blocks, when a first-level cache receives a data reading request of a connected computing core and a target data block is not stored locally, other first-level caches where the target data block is located can be positioned through a central label buffer area; direct data transmission between first-level caches is achieved through the interconnection interface unit without relying on second-level cache transfer, the access pressure of the second-level caches is reduced, the bandwidth bottleneck problem is solved, the data transmission path is shortened, the data access delay is reduced, complex design brought by a traditional cache consistency protocol is avoided, the cache resource utilization rate is increased, and the data transmission efficiency is improved. And the overall operation performance of the graphics processor is optimized.

Description

Technical Field

[0001] This invention relates to the field of processor and data processing technology, and in particular to a graphics processor, a cache data sharing method, device, medium and program product. Background Technology

[0002] In the design of modern processors, such as graphics processors and central processing units, the general-purpose computing core is the main carrier for undertaking various computing tasks. The cache hierarchy, by setting up multiple levels of cache inside the processor, temporarily stores the data frequently used by the computing core in the cache that is closer to the core and has a faster access speed, thereby reducing the frequency of the core directly accessing low-speed storage.

[0003] Currently, the cache hierarchy of multi-core general-purpose computing cores typically equips each computing core with an independent dedicated level 1 cache. If cores need to share data, they must use a level 2 cache as an intermediary.

[0004] However, since all requests that miss in the L1 cache need to be processed through the L2 cache, the concurrent access volume that the L2 cache needs to handle increases sharply with the increase in the number of computing cores, easily leading to bandwidth bottlenecks in the L2 cache. When the miss rate of a single L1 cache increases, the original single data needs to be split into multiple copies for transmission, which consumes more clock cycles and increases the load on the data return bus, easily leading to bandwidth bottlenecks in the L1 cache. Even if the target data already exists in the L1 cache of other cores, data transmission still needs to be relayed through the L2 cache, resulting in a waste of L2 cache bandwidth resources and reducing cache resource utilization. Some technical solutions use traditional cache consistency protocols to achieve L1 cache sharing, but these solutions require adding complex state synchronization and message interaction mechanisms between various L1 caches, and still rely on the L2 cache as a consistency arbitration node, which cannot meet the needs of high real-time computing scenarios and increases data access latency. Summary of the Invention

[0005] This invention provides a graphics processor, a cache data sharing method, a device, a medium, and a program product to solve the problems of low cache resource utilization, high data access latency, and easy bandwidth bottlenecks when sharing cache data.

[0006] According to one aspect of the present invention, a graphics processor is provided, including multiple computing cores, multiple level 1 caches equal in number to the number of computing cores, interconnect interface units, and a central tag buffer; each level 1 cache is connected to each computing core in a one-to-one correspondence, and each level 1 cache and the central tag buffer establish a pairwise communication link through the interconnect interface units; the central tag buffer includes a global tag table, which records tag information of data blocks stored in each level 1 cache, wherein: Each level-1 cache is used to, upon receiving a read data request for a target data block from the connected computing core, if it is determined that the target data block is not stored locally, query the central tag buffer via the interconnect interface unit to see if there is another level-1 cache storing the target data block; and, upon receiving a target data block from another level-1 cache via the interconnect interface unit, feed the target data block back to the connected computing core. The central tag buffer is used to, upon receiving a query request for a target data block from a first-level cache, instruct other first-level caches to send the target data block to the first-level cache that requested the target data block if the global tag table determines that the target data block is stored in another first-level cache.

[0007] According to another aspect of the present invention, a cached data sharing method is provided, executed by a graphics processor as described in any embodiment of the present invention, the method comprising: After receiving a read data request for the target data block from the connected computing core, the first target level cache, if it is determined that the target data block is not stored locally, requests the central tag buffer to query whether there is another level cache storing the target data block via the interconnection interface unit. Upon receiving a query request for a target data block from the first target first-level cache via the central tag buffer, if the target data block is determined to be stored in the second target first-level cache based on the global tag table, the second target first-level cache is instructed to send the target data block to the first target first-level cache. After receiving an instruction from the central tag buffer to send the target data block to the first target first-level cache, the second target first-level cache sends the target data block to the first target first-level cache via the interconnect interface unit if the target data block is successfully obtained locally. When the first target level 1 cache receives the target data block sent by the second target level 1 cache via the interconnect interface unit, it feeds back the target data block to the connected computing core.

[0008] According to another aspect of the present invention, a cached data sharing device is provided, configured in a graphics processor as described in any embodiment of the present invention, the device comprising: The read request module is used to, upon receiving a read data request for a target data block from the connected computing core via the first target level cache, if it determines that the target data block is not stored locally, request the central tag buffer via the interconnect interface unit to query whether there is another level cache storing the target data block. The instruction sending module is used to, upon receiving a query request for a target data block sent by the first target first-level cache via the central tag buffer, instruct the second target first-level cache to send the target data block to the first target first-level cache if it is determined from the global tag table that the target data block is stored in the second target first-level cache. The data transmission module is used to send the target data block to the first target first-level cache via the interconnection interface unit after receiving an instruction from the central tag buffer to send the target data block to the first target first-level cache. If the target data block is successfully obtained locally, the module will send the target data block to the first target first-level cache via the second target first-level cache. The data feedback module is used to feed back the target data block to the connected computing core when it receives the target data block sent by the second target first-level cache through the interconnect interface unit via the first target first-level cache.

[0009] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: a graphics processor as described in any embodiment of the present invention.

[0010] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the cached data sharing method according to any embodiment of the present invention.

[0011] According to another aspect of the present invention, a computer program product is also provided, including a computer program that, when executed by a processor, implements the steps of the method as described in any embodiment of the present invention.

[0012] The graphics processor of this invention sets up a L1 cache corresponding one-to-one with the computing core, and constructs a pairwise communication link between each L1 cache and the central tag buffer through an interconnect interface unit. Combined with a global tag table that records the tag information of all L1 cache data blocks, when a L1 cache receives a read data request from a connected computing core and does not locally store the target data block, it can locate the other L1 cache containing the target data block through the central tag buffer. Direct data transmission between L1 caches is then achieved via the interconnect interface unit, eliminating the need for L2 cache relay. This reduces the access pressure on both L1 and L2 caches, solves the bandwidth bottleneck problem, shortens the data transmission path, reduces data access latency, avoids the complex design of traditional cache coherence protocols, improves cache resource utilization, optimizes the overall operating performance of the graphics processor, and meets the needs of high real-time computing scenarios.

[0013] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of a graphics processor according to Embodiment 1 of the present invention; Figure 2 This is a flowchart of a cached data sharing method provided in Embodiment 2 of the present invention; Figure 3 This is a flowchart of another cached data sharing method provided in Embodiment 3 of the present invention; Figure 4 This is a schematic diagram illustrating a graphics processor cache data sharing method applicable to an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of a cached data sharing device according to Embodiment 4 of the present invention; Figure 6 This is a schematic diagram of the structure of an electronic device that implements the cached data sharing method of this invention. Detailed Implementation

[0016] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0017] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0018] Example 1 Figure 1 This is a schematic diagram of a graphics processor according to Embodiment 1 of the present invention. This embodiment is applicable to situations where cached data is read. Figure 1 As shown, the graphics processor includes: The system includes multiple computing cores, such as computing core 1, 110, computing core 2, 120, computing core 3, 130, ..., and computing core N, 140; multiple L1 caches equal to the number of computing cores, such as L1 cache 1, 150, L1 cache 2, 160, L1 cache 3, 170, ..., and L1 cache N, 180; an interconnect interface unit 190; and a central tag buffer 1100. Each L1 cache is connected to each computing core in a one-to-one correspondence. Each L1 cache and the central tag buffer 1100 establish a pairwise communication link through the interconnect interface unit 190. The central tag buffer 1100 includes a global tag table 1110, which records the tag information of the data blocks stored in each L1 cache. It is understandable that... Figure 1 The number of computing cores mentioned is merely an example; in reality, the graphics processor can have two or more computing cores. This embodiment does not limit the number of computing cores described above. Wherein: Each level-1 cache is used to, upon receiving a read data request for a target data block from the connected computing core, if it is determined that the target data block is not stored locally, query the central tag buffer 1100 via the interconnect interface unit 190 to see if there is another level-1 cache storing the target data block; and, upon receiving a target data block sent by another level-1 cache via the interconnect interface unit 190, feed the target data block back to the connected computing core. The central tag buffer 1100 is used to, upon receiving a query request for a target data block sent by the first-level cache, instruct the other first-level cache to send the target data block to the first-level cache that requested the target data block if it is determined from the global tag table 1110 that the target data block is stored in another first-level cache.

[0019] In this embodiment of the invention, the computing core can be specifically understood as: multiple independent core units (such as...) within the graphics processing unit that carry out specific computing tasks. Figure 1 The computing cores (1 to N) are the main entities initiating data read requests, capable of processing different tasks in parallel, with a quantity N≥2 (to adapt to multi-core expansion needs). The first-level cache can be specifically understood as: a high-speed cache component corresponding one-to-one with each computing core (such as...). Figure 1 The L1 cache (from L1 to L1 cache N) is characterized by being close to the computing core and having low access latency. It can be represented as L1 cache and is used to temporarily store frequently used core data. It only handles read requests and includes a local tag table and a data storage area.

[0020] The interconnect interface unit 190 can be understood as a communication hub connecting all level-one caches and the central tag buffer 1100. It can be implemented via NoC (Network on Chip), crossbar switches, or bus interconnects, and is used to transmit messages such as query requests, data blocks, and synchronization notifications, establishing direct communication links between components. The central tag buffer can be understood as a component that stores global tag information, used to quickly locate the level-one cache containing the target data, avoiding blind access to the level-two cache. It can be located between the interconnect interface unit and the level-two cache.

[0021] The global tag table can be understood as a table in the central tag buffer 1100 that records the data storage location. Each entry can contain the high-order address bits of the data block (tag information) and N level-one cache flag bits (each bit corresponds to one level-one cache), supporting fast retrieval and real-time updates. The target data block can be understood as a specific data fragment that the computing core needs to obtain when initiating a read request; it is the object of the data sharing process.

[0022] Correspondingly, each computing core establishes a fixed connection with only one dedicated L1 cache. This L1 cache provides data caching and access services solely to the corresponding core, ensuring dedicated and efficient data access. Through the interconnect interface unit, messages and data can be directly transmitted between any two L1 caches, as well as between the L1 cache and the central tag buffer, without the need for other intermediary components.

[0023] Specifically, the graphics processor is compatible with GPU (Graphics Processing Unit) digital systems, containing an equal number of computing cores and multiple L1 caches. Each computing core establishes a one-to-one dedicated connection with only one L1 cache. It is also equipped with an interconnect interface unit and a central tag buffer. All L1 caches and the central tag buffer establish direct communication links between each other through the interconnect interface unit, without relying on L2 caches for relay.

[0024] The global tag table 1110 inside the central tag buffer 1100 records the tag information of all data blocks stored in each L1 cache in real time. For example, it records the tag information of the data blocks stored in each L1 cache in real time in the format of a table with the high-order bits of the data address and N L1 cache identifier bits, ensuring the accuracy of data location. Among them, the high-order bits of the data address serve as a unique tag for the data block, used to identify the address characteristics of the target data block, ensuring that the corresponding storage record can be quickly matched during data retrieval. In the N L1 cache identifier bits, N is consistent with the number of L1 caches of the graphics processor, and each bit corresponds to one L1 cache. If a bit is 1, it means that the target data block corresponding to the current tag (high-order bits of the data address) is stored in the L1 cache corresponding to that bit; if it is 0, it means that it is not stored. The global tag table 1110 records relevant information of all data blocks stored in the first-level cache in real time using this format. This allows the central tag buffer 1100 to quickly locate the storage record of the target data block by retrieving the high-order bits of the data address when receiving a query request from the first-level cache. Then, it can intuitively confirm all first-level caches storing the data block using N-bit flag bits, ensuring that accurate query results are returned within one clock cycle. Furthermore, it can promptly update the flag bit status of the corresponding table entry when a data block is added or deleted from the first-level cache, ensuring the real-time performance and accuracy of data location.

[0025] When a computing core needs to read a target data block, it sends a read data request to the corresponding L1 cache. After receiving the request, the L1 cache first checks whether the target data block is stored locally. For example, it checks whether the target data block is stored by checking the local tag table of the L1 cache (not shown in the figure). If it misses, it means that it is not stored locally. Then, it sends a query request containing the tag information of the target data block to the central tag buffer 1100 through the interconnect interface unit 190 to ask other L1 caches whether the target data block is stored.

[0026] After receiving a query request, the central tag buffer 1100 searches the global tag table 1110. If it is determined from the tag information that the target data block is stored in another first-level cache, it sends an instruction to the first-level cache that stores the target data block, requesting it to send the target data block to the first-level cache that initiated the query request.

[0027] After receiving the instruction, the first-level cache storing the target data block queries the local tag table to confirm the data is valid, packages the data block into a data packet, and sends it directly to the first-level cache that initiated the query through the dedicated data channel of the interconnect interface unit 190. If the first-level cache does not find the data locally (e.g., because the local data storage area is full, the least recently used old data block is evicted by the LRU (Least Recently Used) algorithm), it can also send a miss response through the interconnect interface unit 190, and the central tag buffer 1100 will retrieve the data again or trigger the second-level cache to intervene.

[0028] After receiving the target data block sent by other first-level caches via the interconnect interface unit 190, the first-level cache that initiated the query request stores it in its local data storage area (if the storage area is full, old data is evicted using a replacement strategy such as LRU), and generates a global tag update instruction, which is sent to the central tag buffer 1100 to update the corresponding data item in the global tag table 1110. The target data block is then fed back to the corresponding computing core, completing data sharing.

[0029] Furthermore, based on the above embodiments, the graphics processor may also include: a secondary cache (not shown in the figure), which is communicatively connected to each primary cache and the central tag buffer 1100; The central tag buffer 1100 is also used to request the second-level cache to send the target data block to the first-level cache that requested the target data block when it is determined that none of the first-level caches have stored the target data block. The second-level cache is used to retrieve the target data block and send it to the first-level cache that requested the target data block after receiving a data retrieval request for the target data block from the central tag buffer 1100.

[0030] In this embodiment of the invention, the second-level cache can be specifically understood as: a storage component below the first-level cache, typically with a much larger capacity and higher access latency than the first-level cache. It is used to handle requests that miss in the first-level cache or to store data not covered by the first-level cache. It serves as a fallback storage layer for data access, adapting to more high-load computing scenarios, and can be represented as an L2 cache. The second-level cache establishes data and message transmission links with each first-level cache and the central tag buffer 1100 through the interconnect interface unit 190, supporting interactions such as request sending, data feedback, and state synchronization.

[0031] Specifically, the graphics processor can be additionally configured with a secondary cache, which establishes communication connections with all primary caches and the central tag buffer 1100 through the interconnect interface unit 190, forming a complete cache hierarchy.

[0032] In the data access process, after the central tag buffer 1100 receives a query request from the first-level cache, it searches the global tag table 1110 to confirm the storage status of the target data block, or after receiving the miss response from all candidate first-level caches, it determines that none of the first-level caches store the target data block. In this case, data transmission between first-level caches is no longer triggered. The central tag buffer 1100 generates an acquisition request containing the target data block tag information and the identifier of the requesting first-level cache, and sends it to the second-level cache through the interconnection interface unit 190.

[0033] After receiving a request, the second-level cache queries its local tag table. If a match is found, the target data block is read directly from its own data storage area. If a match is not found, a data request is sent to the main memory. After receiving the data returned by the main memory, the target data block is sent to the first-level cache that initiated the query request through the dedicated data channel of the interconnect interface unit 190. The first-level cache then feeds back the data to the corresponding computing core to complete the data access.

[0034] By designing the communication connections between the graphics processor's secondary cache, each primary cache, and the central tag buffer 1100, and combining the logic that the central tag buffer 1100 initiates a data request to the secondary cache when none of the primary caches have stored the target data block, and the secondary cache receives the request, retrieves the data, and sends it to the requesting primary cache, the unified scheduling of the central tag buffer 1100 avoids bandwidth waste and conflicts caused by the primary caches initiating requests to the secondary cache out of order. This ensures that the secondary cache only intervenes when the primary cache level cannot meet the data demand, rationally allocating the service resources of the secondary cache and alleviating the bandwidth bottleneck caused by the secondary cache handling all primary cache misses in traditional solutions. Furthermore, by using the secondary cache as the bottom-line of data access, the integrity of data access is ensured, preventing request failures due to no data in the primary cache. At the same time, data is directly transmitted from the secondary cache to the corresponding primary cache, reducing unnecessary transit links. While ensuring data reachability, this indirectly reduces the overall data access latency and further improves the stability and efficiency of graphics processor data sharing.

[0035] Optionally, based on the above embodiments, each first-level cache stores a local tag table; each first-level cache is specifically used to determine whether the target data block is stored locally by querying the local tag table after receiving a read data request for the target data block sent by the connected computing core.

[0036] Specifically, each level 1 cache maintains its own local tag table, which can be implemented using a tag plus a validity bit to record the address identifier and validity status of the data block in the current level 1 cache.

[0037] Each level 1 cache is directly connected to the corresponding computing core. After receiving a read data request for the target data block sent by the connected computing core, it will parse the request address, split out the tag, index and offset fields, locate the corresponding group through the index, match the tag in the request with the tag in the local tag table, and check the validity bit to determine whether a valid target data block is stored locally.

[0038] By maintaining an independent local tag table for each first-level cache, read data requests from the computing core can be prioritized for local queries. This allows for rapid determination of whether a target data block is in the local cache, fully leveraging the low-latency characteristics of the first-level cache, reducing unnecessary global queries and cross-component communication, and improving data access response speed. Distributing local judgment logic across various first-level caches reduces the processing pressure on the central tag buffer, improving the parallel processing capability and overall efficiency of the entire caching system. Furthermore, the one-to-one correspondence between the local tag table and the first-level cache facilitates maintenance and expansion, and provides a reliable preliminary judgment basis for subsequent global tag queries, further ensuring the accuracy of cache data location and system stability.

[0039] Optionally, based on the above embodiments, each first-level cache is only used to respond to read data requests from each computing core or central tag buffer; the second-level cache is used to respond to read data requests from each computing core or central tag buffer, as well as write data requests from each computing core or central tag buffer.

[0040] Specifically, each Level 1 cache operates in read-only mode, handling and responding only to local read data requests initiated by connected computing cores and inter-level read data requests forwarded by the central tag buffer 1100. All write data requests bypass the Level 1 cache directly, avoiding complex cache consistency protocols. The Level 2 cache, as a unified read / write processing unit, responds to read data requests initiated by the central tag buffer 1100 when a Level 1 cache miss occurs, and also receives and processes write data requests directly sent by all computing cores. It can also respond to data write-back requests initiated by the central tag buffer 1100. That is, when data in the Level 1 cache is modified or needs to be evicted, and the central tag buffer determines that the data is valid dirty data, the central tag buffer will initiate a data write-back request to the Level 2 cache. Upon receiving this request, the Level 2 cache will read the corresponding data from the Level 1 cache and write it to its own storage area or further write it to main memory to complete data persistence and consistency maintenance.

[0041] By dividing the functions of the first-level cache into one that only responds to read data requests and the second-level cache that handles both read and write requests, the first-level cache is free from handling write operations and related cache consistency maintenance. This simplifies the hardware structure and control logic, reduces design complexity and implementation costs, avoids data synchronization and consistency issues caused by write operations, and improves system stability and read / write parallel efficiency. At the same time, centralizing all write requests for processing by the second-level cache facilitates data consistency management and cache update control, reduces global synchronization overhead, and allows the first-level cache to focus on read services, enabling more efficient local queries and data sharing between caches. This further reduces data access latency, alleviates the read access pressure on the second-level cache, relieves bandwidth bottlenecks, and improves the performance and resource utilization of the entire multi-core processor cache system.

[0042] Optionally, based on the above embodiments, each level-1 cache and central tag buffer 1100 is provided with an interconnection interface; wherein, each level-1 cache and central tag buffer 1100 is connected to the interconnection interface unit 190 through its respective interconnection interface to establish a pairwise communication link through the interconnection interface unit.

[0043] In this embodiment of the invention, the interconnection interface can be specifically understood as: a dedicated interface component set on the first-level cache and the central tag buffer, used to realize protocol docking, signal conversion and data interaction with the interconnection interface unit 190, serving as the medium for the component to access the communication network, and supporting the sending and receiving of messages such as query requests, data transmission and synchronization notifications.

[0044] Specifically, each Level 1 cache and central tag buffer 1100 has a built-in dedicated interconnect interface (the interface type can be flexibly adapted according to the type of interconnect interface unit, such as NoC adapter interface or bus adapter interface, etc.). Each component establishes a stable physical connection and logical communication link with the interconnect interface unit 190 through its own interconnect interface, ensuring protocol compatibility and reliable signal transmission. In this network, the interconnect interface unit 190 can build a global communication network covering all Level 1 caches and central tag buffers 1100, enabling independent pairwise communication links to be formed between any two Level 1 caches and between any Level 1 cache and the central tag buffer 1100, and link transmission does not require secondary cache relay.

[0045] When a Level 1 cache needs to send a query request to the central tag buffer 1100 or send data to other Level 1 caches, the relevant message will be transmitted to the interconnection interface unit 190 through the interconnection interface of the Level 1 cache, and then forwarded by the interconnection interface unit 190 to the interconnection interface of the target component. At the same time, the synchronization notification and tag update messages generated during the data transmission process can also be efficiently transmitted through this communication link.

[0046] In addition, the interconnection interfaces set on the first-level cache and the central tag buffer 1100, besides meeting the communication needs of basic data forwarding and query request sending and receiving, can also split large-capacity data blocks into multiple small fragments for sequential transmission, avoiding excessive interconnection bandwidth consumption in a single transmission and adapting to the transmission needs of different bandwidth scenarios; priority levels can be set for different types of messages (such as emergency data query requests, ordinary data transmission, and tag update notifications), and the interconnection interface unit will prioritize the transmission of high-priority messages to ensure the real-time access to critical data; data packets can be verified during data transmission (such as verifying data integrity through checksums), promptly detecting data errors caused by interference or other factors during transmission, and correcting errors through retransmission and other mechanisms to ensure the accuracy of data transmission.

[0047] Each L1 cache and the central tag buffer 1100 connects to the interconnect interface unit 190 via their configured interconnect interfaces, thus establishing a pairwise communication link design. This design makes the interconnect interface a standardized medium for each component to interface with the interconnect interface unit 190, ensuring the compatibility of the communication protocol between the L1 cache and the central tag buffer 1100, and the stability of signal transmission between L1 caches, avoiding compatibility issues that may arise from direct connections. On the other hand, the establishment of pairwise communication links allows the L1 cache to directly transmit query requests, data blocks, and synchronization notifications to other L1 caches or the central tag buffer 1100 without relying on the L2 cache for relay, shortening the data transmission path. This reduces the bandwidth consumption pressure on the L2 cache and lowers the latency caused by multiple relays. The modular interface design allows the interconnect interface unit 190 to flexibly adapt to various implementation forms such as NoC and bus interconnect, and facilitates the subsequent expansion of more L1 caches or functional components, improving the compatibility and scalability of the architecture. Through communication layer optimization, a foundation is laid for the efficiency and stability of data sharing in the graphics processor.

[0048] The graphics processor of this invention sets up a L1 cache corresponding one-to-one with the computing core, and constructs a pairwise communication link between each L1 cache and the central tag buffer through an interconnect interface unit. Combined with a global tag table that records the tag information of all L1 cache data blocks, when a L1 cache receives a read data request from a connected computing core and does not locally store the target data block, it can locate the other L1 cache containing the target data block through the central tag buffer. Direct data transmission between L1 caches is then achieved via the interconnect interface unit, eliminating the need for L2 cache relay. This reduces the access pressure on both L1 and L2 caches, solves the bandwidth bottleneck problem, shortens the data transmission path, reduces data access latency, avoids the complex design of traditional cache coherence protocols, improves cache resource utilization, optimizes the overall operating performance of the graphics processor, and meets the needs of high real-time computing scenarios.

[0049] Example 2 Figure 2 This is a flowchart of a cached data sharing method provided in Embodiment 2 of the present invention. This embodiment is applicable to reading cached data. The method can be executed by a cached data sharing device, which can be implemented in hardware and / or software, and is generally configured in a graphics processor. Figure 2 As shown, the method includes: S210. After receiving a read data request for the target data block sent by the connected computing core through the first target level cache, if it is determined that the target data block is not stored locally, the interconnection interface unit requests the central tag buffer to query whether there is another level cache storing the target data block.

[0050] In this embodiment of the invention, the first target level-one cache can be specifically understood as: a level-one cache that corresponds one-to-one with the computing core that initiates the data read request, is the initiator of the data query, and is used to receive core requests, query local data, initiate global queries, and finally return data.

[0051] S220. After receiving a query request for a target data block sent by the first target first-level cache through the central tag buffer, if it is determined from the global tag table that the target data block is stored in the second target first-level cache, then instruct the second target first-level cache to send the target data block to the first target first-level cache.

[0052] In this embodiment of the invention, the second target first-level cache can be specifically understood as: the first-level cache recorded in the global tag table that stores the target data block, which is the data provider and is used to send data to the first target first-level cache after receiving the central tag buffer instruction.

[0053] Specifically, after the computing core initiates a read request for the target data block, the request is sent to the corresponding first target level 1 cache. Upon receiving the request, the first target level 1 cache parses the data address, queries its locally stored tag table (the table entry format can be the high-order bits of the data address and 1 significant bit), and determines whether the target data block is stored. If no matching valid tag record is found (i.e., the target data block is not stored locally), it generates a query request containing the target data block tag information and its own identifier, and sends it to the interconnect interface unit through its configured interconnect interface. The interconnect interface unit then forwards it to the central tag buffer to inquire whether other level 1 caches store the target data block.

[0054] After receiving a query request, the central tag buffer searches the global tag table (entries may contain the high-order bits of the data address and N bits of the first-level cache identifier). It matches the corresponding storage record by the tag information of the target data block. If it is determined that the target data block is stored in a certain second target first-level cache (corresponding to an identifier bit of 1), it generates an indication message containing the target data block information and the first target first-level cache identifier. This message is sent to the second target first-level cache via the interconnection interface unit, requesting it to transfer the target data block to the first target first-level cache.

[0055] Optionally, based on the above embodiments, the global tag table may include multiple data items, each data item including tag information matching the set data block, and identification information storing all first-level caches of the set data block; Accordingly, based on the above embodiments, through the central tag buffer, upon receiving a query request for a target data block sent by the first target first-level cache, if it is determined according to the global tag table that the target data block is stored in the second target first-level cache, then the second target first-level cache is instructed to send the target data block to the first target first-level cache. Specifically, this may include: If, through the central tag buffer, it is determined that there is a target data item in the global tag table that matches the target tag information of the target data block, then all target level-one caches storing the target data block are retrieved from the target data item. The central tag buffer instructs the second target first-level cache, which contains the target data block, to send the target data block to the first target first-level cache.

[0056] In this embodiment of the invention, the designated data block can be specifically understood as: any data block whose stored information has been recorded in the global tag table, which is an object that may be queried and transmitted in the data sharing process, and is a different expression of the same concept as the target data block (the target data block is the designated data block currently being queried). The tag information can be specifically understood as: address features (such as the high bits of the data address) used to uniquely identify the data block, which is the identity identifier of the data block in the caching system, ensuring that the corresponding data item can be matched during the query.

[0057] Specifically, the global tag table of the central tag buffer manages the storage information of all L1 caches through multiple independent data items. Each data item corresponds to a set data block. The table entry includes the tag information of the data block (such as tag information in the form of the high bits of the data address) and the identification information corresponding to the number of L1 caches (which can be in the form of N-bit identifier bits or number list, etc.), identifying all L1 caches that store the set data block.

[0058] In the data query process, after the first target level cache fails to find the target data block locally and sends a query request through the interconnection interface unit, the central tag buffer receives the request and parses the tag information of the target data block. It then searches the global tag table to determine whether there is a target data item that matches the tag information of the target data block. If a matching target data item is found, it retrieves all target level caches (i.e., all level caches corresponding to the identification information) that store the target data block. Through preset rules (such as sending a verification request to all target level caches or filtering based on recent access records), it confirms that the second target level cache actually stores a valid target data block, thus avoiding transmission failures caused by data being replaced by LRU.

[0059] The central tag buffer sends an indication message containing target data block information and the identifier of the first target first-level cache to the second target first-level cache. After being transmitted through the interconnection interface unit, the second target first-level cache is triggered to directly send the target data block to the first target first-level cache.

[0060] By using a global tag table to manage multiple data items, each data item integrates the tag information of the set data block with the identification information of all first-level caches storing that data block. This, combined with the retrieval and direction indication logic of the central tag buffer after receiving query requests, allows the central tag buffer to quickly match target data items and lock all possible first-level caches storing the target data block through the associated storage of tag information and first-level cache identifiers. This avoids the inefficiency of blind retrieval or reliance on second-level cache relay in traditional solutions, improving data location efficiency. Instructions are sent only to the second target first-level cache that actually stores the target data block, selecting from all target first-level caches. This avoids sending invalid requests to first-level caches that do not actually store data, reducing bandwidth consumption and communication conflicts in interconnect interface units. Furthermore, direct data transmission between first-level caches replaces second-level cache relay, reducing data access latency and alleviating the query and transmission pressure on the second-level cache, thus alleviating its bandwidth bottleneck and further improving the overall data sharing efficiency and cache resource utilization of the graphics processor.

[0061] Furthermore, based on the above embodiments, each data item in the global tag table may also include the first-level cache that most recently read the specified data block in all first-level caches storing the specified data block; Accordingly, based on the above embodiments, by using the central tag buffer to instruct the second target first-level cache, which stores the target data block in all target first-level caches, to send the target data block to the first target first-level cache, specifically, this may include: Using the central tag buffer, the most recently read target data block in all target first-level caches is obtained from the target data items and used as the current second target first-level cache. A set of alternative second target first-level caches is constructed based on the remaining target first-level caches. Using the central tag buffer, a first-level cache inter-read request is constructed based on the first target first-level cache, target tag information, and the second target first-level cache set, and then the first-level cache inter-read request is sent to the current second target first-level cache; Upon receiving a read request between first-level caches, if it is determined that the target data block in the local storage matches the target tag information, the target data block is sent to the first target first-level cache. If it is determined that the target data block is not stored locally using the current second target first-level cache, then one of the candidate second target first-level caches is sequentially obtained from the candidate second target first-level cache set as the new current second target first-level cache. After that, the first-level cache inter-caching read request is sent to the new current second target first-level cache, so as to relay the instruction to the second target first-level cache in the candidate second target first-level cache set that stores the target data block to send the target data block to the first target first-level cache.

[0062] In this embodiment of the invention, the current second target first-level cache can be specifically understood as: the first-level cache that the central tag buffer preferentially selects from all target first-level caches as the first data provider, and is the primary candidate for data transmission. The second target first-level cache set can be specifically understood as: a set of first-level caches that store target data blocks, excluding the current second target first-level cache, used to provide relay candidates when the current second target first-level cache is not hit, ensuring the continuity of data transmission.

[0063] A read request between level 1 caches can be understood as follows: A central tag buffer constructs an instruction containing the identifier of the first target level 1 cache, the target data block tag information, and the candidate set information. This instruction is used to notify the target level 1 cache to send data and provides a basis for possible relay transmission. A relay instruction can be understood as follows: When the current second target level 1 cache misses, the central tag buffer or the current level 1 cache triggers a read request to the next level 1 cache in the candidate set, ensuring that data retrieval is not interrupted.

[0064] Specifically, each data item in the global tag table of the central tag buffer, in addition to recording the tag information of the set data block and storing all the first-level cache identifier information of the data block, also records the first-level cache that most recently read the set data block (which can be achieved through timestamp recording or access counters and other methods).

[0065] Based on this, after the central tag buffer retrieves the target data item and obtains all target first-level caches, it will prioritize selecting the most recently read first-level cache as the current second target first-level cache (the cache data has a higher probability of not being replaced by LRU, which can improve the success rate of the first transmission). At the same time, the remaining target first-level caches will be sorted according to preset rules (such as access frequency, or communication distance with the first target first-level cache, etc.) to build a set of candidate second target first-level caches.

[0066] The central tag buffer constructs an inter-level cache read request based on the first target level-one cache, target tag information, and the second target level-one cache set. For example, it constructs an inter-level cache read request that includes the first target level-one cache identifier, target data block tag information, and a candidate set list, and sends it to the current second target level-one cache through the interconnection interface unit.

[0067] After receiving a request through its own interconnection interface, the current second target first-level cache queries its local tag table to confirm whether the target data block is stored. If a match is found, the data block is packaged and sent directly to the first target first-level cache through the interconnection interface unit. If a match is not found, there is no need for the central tag buffer to intervene repeatedly. The current second target first-level cache can directly select the next first-level cache from the candidate set as the new current second target first-level cache and resend the read request. The query continues in a relay manner until a valid second target first-level cache storing the target data block is found and the data transmission is completed.

[0068] Each data item in the global tag table additionally records the L1 cache that most recently read the data block from all L1 caches of the specified data block. This, combined with the central tag buffer's logic of prioritizing the selection of this L1 cache as the current second target L1 cache, constructing a candidate set, and instructing data transmission via a relay mechanism, improves the success rate of the first data transmission. Since the target data block in the most recently read L1 cache has a lower probability of being replaced by LRU, it reduces latency caused by invalid communication and request retransmissions. It also avoids bandwidth occupation and conflicts in the interconnect interface units caused by blindly sending requests to all target L1 caches. The design of the candidate second target L1 cache set and relay mechanism ensures that even if the current second target L1 cache does not store the target data block, it can switch to other candidate L1 caches to continue trying, avoiding query interruption due to the failure of a single L1 cache data, thus guaranteeing the continuity and reliability of data sharing. Without relying on L2 cache relay, it reduces the access pressure on L2 cache to alleviate its bandwidth bottleneck, and improves the efficiency and stability of graphics processor data sharing by shortening the data transmission path and reducing invalid interactions, adapting to the high real-time computing needs of different digital systems.

[0069] Furthermore, based on the above embodiments, by instructing the second target first-level cache, which stores the target data block, in the central tag buffer to send the target data block to the first target first-level cache, the method may further include: If, through the current second target level 1 cache, it is determined that the target data block is not stored locally, and there is currently no target level 1 cache that can serve as the new current second target level 1 cache, a miss response is returned to the central label buffer to inform that none of the target level 1 caches in the central label buffer store the target data block.

[0070] In this embodiment of the invention, a miss response can be specifically understood as: when the current second target first-level cache confirms that the target data block is not stored after a local query and there are no other alternative first-level caches to take over, the feedback message sent to the central tag buffer to inform that the target data block does not exist in any target first-level cache is a signal that triggers the intervention of the second-level cache.

[0071] Specifically, after the central tag buffer selects the current second target level 1 cache and constructs a candidate set based on rules such as recent read priority, the current second target level 1 cache receives inter-level cache read requests and queries its local tag table to confirm whether to store the target data block. If a miss occurs, and the candidate second target level 1 cache set has no remaining level 1 caches available for succession (all candidate level 1 caches have been searched), the current second target level 1 cache returns a miss response to the central tag buffer through the interconnect interface unit. The response may include the target data block tag information, the first target level 1 cache identifier, and a status statement indicating that there are no candidate caches.

[0072] This response allows the central tag buffer to quickly identify all target level 1 caches that were originally thought to potentially store the target data block, but in fact did not store the data block. This enables the central tag buffer to terminate the query process between level 1 caches in a timely manner and instead trigger the subsequent level 2 cache data request process, ensuring that data access is not interrupted.

[0073] By returning a miss response to the central tag buffer when the current second target level 1 cache does not store the target data block locally and there are no new alternative level 1 caches, the central tag buffer can quickly confirm that all target level 1 caches do not have valid target data blocks. This eliminates the need for further waiting or meaningless retrieval operations, directly terminating the query process at the level 1 cache. This avoids wasting time and bandwidth resources due to invalid waiting and duplicate requests, reducing unnecessary access latency. The miss response provides a trigger signal to the central tag buffer, enabling it to switch to the level 2 cache data request process, ensuring the continuity and smoothness of data access and preventing data request blocking in the computing core due to poor process integration. The central tag buffer can promptly update the information of the corresponding data item in the global tag table based on the miss response, correcting the storage flag status of the level 1 cache. This prevents incorrect location when other level 1 caches initiate similar queries, improving the real-time performance and accuracy of the global tag table data, thereby optimizing the efficiency of subsequent overall data queries. The query results at the level 1 cache can be efficiently fed back to the scheduling core, achieving precise and intelligent scheduling between cache levels, further improving the resource utilization and overall stability of the graphics processor cache system.

[0074] S230. After receiving an instruction from the central tag buffer to send the target data block to the first target first-level cache via the second target first-level cache, if the target data block is successfully obtained locally, the target data block is sent to the first target first-level cache via the interconnection interface unit.

[0075] S240. When the first target level 1 cache receives the target data block sent by the second target level 1 cache via the interconnect interface unit, the target data block is fed back to the connected computing core.

[0076] Specifically, after receiving the target data block sending instruction forwarded by the central tag buffer through the interconnection interface unit via its own interconnection interface, the second target level cache parses the target tag information in the instruction, queries the local tag table to confirm the validity of the data, and if a valid target data block is successfully obtained locally, it encapsulates the target data block into a data packet according to the communication protocol of the interconnection interface unit, and transmits it to the interconnection interface unit through its own interconnection interface. The interconnection interface unit then uses the pairwise communication links between level caches to directly forward the data to the interconnection interface of the first target level cache.

[0077] After receiving the target data block sent by the second target first-level cache through the interconnect interface unit, the first target first-level cache feeds back the target data block to the computing core that initiated the read request through a dedicated data channel connected to the computing core, thus completing the direct data sharing and core data delivery between the first-level caches.

[0078] Simultaneously, the first target level 1 cache can synchronously store the data block in the local data storage area, update the local tag table (if the storage area is full, the least recently used old data will be evicted using the LRU algorithm), and generate a global tag update instruction to be sent to the central tag buffer in order to update the global tag table and provide accurate storage location information for similar data requests from other computing cores.

[0079] The technical solution of this invention allows the first target level 1 cache to directly query the central tag buffer for the storage status of other level 1 caches when it misses the target data locally. It then uses a global tag table to quickly locate the second target level 1 cache storing the target data. The second target level 1 cache then transmits the data directly to the first target level 1 cache via the interconnect interface unit. Finally, the first target level 1 cache feeds back to the computing core. This avoids the intermediate step of the level 2 cache in traditional solutions, reducing the access pressure on the level 2 cache to alleviate its bandwidth bottleneck, and shortening the data transmission path from the source level 1 cache to the requesting level 1 cache, thus reducing data access latency. Simultaneously, it eliminates the need to rely on complex cache consistency protocols to synchronize the states of multiple level 1 caches, simplifying the data sharing interaction logic and thereby improving the overall operating efficiency of the graphics processor and the real-time performance of data access.

[0080] Example 3 Figure 3 This is a flowchart of another cached data sharing method provided in Embodiment 3 of the present invention. This embodiment is a refinement of the cached data sharing method in the above embodiments. Figure 3 As shown, the method includes: S310. After receiving a read data request for the target data block from the connected computing core, if it is determined that the target data block is not stored locally, the first target level cache requests the central tag buffer via the interconnection interface unit to query whether there is another level cache storing the target data block.

[0081] S320. After receiving a query request for a target data block sent by the first target first-level cache through the central tag buffer, if it is determined from the global tag table that the target data block is stored in the second target first-level cache, then instruct the second target first-level cache to send the target data block to the first target first-level cache.

[0082] S330. After receiving an instruction from the central tag buffer to send the target data block to the first target first-level cache via the second target first-level cache, if the target data block is successfully obtained locally, the target data block is sent to the first target first-level cache via the interconnection interface unit.

[0083] S340. When the first target level 1 cache receives the target data block sent by the second target level 1 cache via the interconnect interface unit, the target data block is fed back to the connected computing core.

[0084] S350: When it is determined through the central tag buffer that none of the first-level caches have stored the target data block, request the second-level cache to send the target data block to the first target first-level cache.

[0085] Specifically, after receiving a query request for the target data block from the first target level cache, the central tag buffer first performs a full validity check of the level cache. Only when it is determined that the data block is not validly stored in any level cache will the fallback data request process of the level cache be triggered.

[0086] The determination is divided into two cases: First, after directly searching the global tag table, no record matching the target data block is found, meaning that none of the first-level caches store the data block. Second, after a matching record is found and a relay query between first-level caches is triggered, a miss response is received from the current second target first-level cache, meaning that none of the first-level caches that originally stored the data block have valid data.

[0087] After determining that there is no target data block in the first-level cache, the central tag buffer will terminate all query processes between first-level caches, initiate a data request to the second-level cache that it is communicating with, instruct the second-level cache to obtain the target data block, and send the data directly to the first target first-level cache that initiated the query.

[0088] Furthermore, based on the above embodiments, after requesting the second-level cache via the central tag buffer to send the target data block to the first target first-level cache, the method further includes: Using the central label buffer, new data items are constructed based on the target label information of the target data block and the first target level cache, and the global label table is updated based on the new data items.

[0089] Specifically, the central tag buffer sends a request to the secondary cache to retrieve the target data block, instructing the secondary cache to send the data to the first target primary cache. Simultaneously, this triggers a dynamic update process for the global tag table. Based on the target tag information corresponding to the requested target data block (e.g., the high-order bits of the data address, serving as a unique identifier for the data block), and the identifier information of the first target primary cache that receives and stores the target data block (e.g., the specific location corresponding to the N-bit identifier), a new data item is constructed according to the unified entry format of the global tag table.

[0090] This newly constructed data item is added to the global tag table in the central tag buffer, completing the update of the global tag table. This synchronizes the global tag table with the state of the target data block stored in the first-level cache of the first target. After the second-level cache sends the target data block to the first-level cache of the first target and completes local storage, the global tag table will have the accurate storage location information of the data block. When other first-level caches subsequently initiate a query request for the target data block, the central tag buffer can directly retrieve the matching data item and quickly locate the target first-level cache without triggering the second-level cache request process again.

[0091] By using a central tag buffer, after requesting the second-level cache to send the target data block to the first-level cache, a new data item is constructed based on the tag information of the target data block and the first-level cache, and the global tag table is updated. This design achieves synchronization between the global tag table and the data storage status of the first-level cache. After the tag table is updated before the second-level cache completes data transmission and the first-level cache achieves local storage, subsequent first-level caches initiating similar data queries can directly and accurately locate the target first-level cache from the global tag table without triggering the second-level cache request process again. This reduces the access frequency of the second-level cache, alleviates the bandwidth bottleneck of the second-level cache, and reduces the overall latency of subsequent data queries. The new data items are constructed and updated in a unified format, ensuring the consistency of the data format and the accuracy of the information in the global tag table. This avoids incorrect location or invalid communication caused by asynchronous tag information, improving the overall query efficiency of the caching system. The global tag table can dynamically record the newly added data storage information of the first-level cache, improving the global address mapping capability of the caching system. This allows direct data sharing between first-level caches to cover more data scenarios and further leverages the low latency advantage of the first-level cache.

[0092] S360: After receiving a data retrieval request for the target data block from the central tag buffer via the second-level cache, the target data block is retrieved and sent to the first target first-level cache.

[0093] Specifically, after receiving a data retrieval request for a target data block from the central tag buffer, the secondary cache parses the target tag information in the request, firstly queries its own local tag table and data storage area. If a matching and valid target data block is found (local hit), the data block is read directly from the local storage area. If no local hit is found, a data request is initiated to the main memory of the graphics processor. After receiving the target data block returned by the main memory, the retrieval is completed. At the same time, the data block can be cached in its own local storage area to facilitate subsequent similar data requests. After successfully retrieving the target data block, the secondary cache encapsulates the data block into a data packet according to the communication protocol and sends it to the first target primary cache corresponding to the request through a dedicated communication link with each primary cache.

[0094] Optionally, based on the above embodiments, the local tag table stores the tag information of the data blocks stored in each cache unit of the first-level cache; correspondingly, based on the above embodiments, before determining that the target data block is not stored locally through the first target first-level cache, the method may further include: querying the local tag table through the first target first-level cache according to the target tag information of the target data block in the read data request sent by the connected computing core; and determining whether the first target first-level cache stores the target data block locally based on the hit result of the target tag information in the local tag table through the first target first-level cache.

[0095] Specifically, the local tag table stores the tag information of the data blocks stored in each cache unit within the first-level cache, such as the tag and validity bit status information. Each cache unit corresponds to one tag information, which is used to identify the address and validity of the data in that unit.

[0096] When the first target L1 cache receives a read data request from the connected computing core, it parses the target tag information from the request address, locates the corresponding group in the local tag table according to the cache address index, matches the target tag information with the tags in the table entries, and checks the validity bit to obtain a hit or miss result. Based on this result, it determines whether the target data block is validly stored locally. If the tag of a table entry matches the target tag information and the validity bit is valid, it is considered a hit, indicating that the target data block has been stored locally. If all table entries do not match the tags, or the tags match but the validity bit is invalid, it is considered a miss, indicating that a valid target data block is not stored locally.

[0097] By recording the data block tag information of each cache unit in the local tag table, and querying and determining the hit based on the target tag information, the first-level cache can quickly and accurately determine whether the target data block is stored locally. This leverages the advantages of low latency and proximity access of the first-level cache, reduces unnecessary global queries and cross-component communication, and lowers the load on the central tag buffer and interconnection interface units. At the same time, the reliability of the hit result is ensured by combining tag matching and valid bit verification, providing accurate pre-judgment for subsequent data sharing between first-level caches or data retrieval from the second-level cache, thereby improving the query efficiency, response speed, and operational stability of the entire caching system.

[0098] Furthermore, based on the above embodiments, the cached data sharing method may further include: After storing the target data block sent by the second target first-level cache or second-level cache into the local data cache area through the first target first-level cache, the local tag table is updated according to the target data block; The first target level cache generates a global label update instruction and sends it to the central label buffer so that the central label buffer can update the global label table.

[0099] Specifically, after receiving a target data block from a second target first-level cache (for direct data sharing between first-level caches) or a second-level cache (as a fallback scenario for a first-level cache miss), the first target first-level cache first checks the space status of its local data cache. If there is free storage space, it directly stores the target data block into the cache, completing local storage. If there is no free space in the cache, it triggers the LRU replacement mechanism. By recording the access timestamps of all old data blocks in the cache, it filters out the least recently used old data block and removes it from the cache. The freed-up storage space is used to store the newly received target data block, ensuring that the target data block can be successfully stored locally. After storage is completed, the first target first-level cache updates its local tag table based on the target data block and generates a corresponding global tag update instruction based on the specific storage method: if it is direct storage, the instruction may include the target data block tag information, the first target first-level cache identifier, and the new storage identifier status; if it is LRU replacement storage, in addition to the above information, the instruction may also include the tag information of the evicted old data block and the old data eviction identifier status. The first target level 1 cache sends the global tag update instruction to the central tag buffer through the interconnect interface unit.

[0100] Upon receiving the instruction, the central tag buffer updates the global tag table according to the specific information in the instruction: For the target data block, it updates the flag bit of the first target L1 cache in its corresponding data item to a valid state (e.g., set to 1), and synchronously updates additional information such as the most recently read L1 cache; For old data blocks evicted by LRU, it finds its corresponding data item in the global tag table and sets the flag bit of the first target L1 cache to an invalid state (e.g., set to 0). If the old data block has no other valid L1 cache, the corresponding data item can be marked as pending evicting, and the least recently used old data can be evicted.

[0101] After storing the target data block sent by the second target first-level cache or second-level cache locally through the first target first-level cache, the local tag table is updated according to the target data block. A global tag update instruction is then generated and sent to the central tag buffer to update the global tag table. This design achieves real-time linkage between the actual local storage state of the first-level cache and the global tag table, allowing the global tag table to synchronize with the newly added storage information of the target data block in a timely manner. When other first-level caches initiate similar data queries, they can directly locate the first target first-level cache, achieving direct data sharing between first-level caches. This avoids triggering the second-level cache request process twice, reducing the access pressure on the second-level cache, alleviating its bandwidth bottleneck, and reducing the overall latency of subsequent data queries. This update mechanism is initiated proactively by the first-level cache where the data is actually stored, reflecting the true state of data storage and avoiding problems such as incorrect location and invalid communication caused by information lag in the global tag table. This improves the overall query efficiency and communication resource utilization of the caching system. The first-level cache stores the target data block locally and updates the global tag synchronously, making the data block a local cache resource. This provides low-latency local access for subsequent similar data requests from connected computing cores, aligning with the principle of locality of reference in cache access and improving the data acquisition efficiency of computing cores. If a stored procedure triggers LRU replacement, the update indicator can synchronously feed back the eviction information of the old data block, allowing the central tag buffer to promptly invalidate the corresponding first-level cache tag position. This ensures the accuracy and validity of data storage information in the global tag table, preventing subsequent queries from requesting the first-level cache that no longer has valid data, further reducing invalid interactions. At the same time, it allows the global tag table to dynamically adapt to changes in the storage of the first-level cache, continuously optimizing the global scheduling capability of the graphics processor cache system and improving the overall efficiency, stability, and utilization of cache resources in data sharing.

[0102] Figure 4 This is a schematic diagram illustrating a graphics processor cache data sharing method applicable to an embodiment of the present invention, as shown below. Figure 4As shown, the system consists of six Level 1 caches (Level 1 caches 1 to 6), one interconnection interface unit, one central tag buffer, and one Level 2 cache (L2). Each Level 1 cache is connected to the interconnection interface unit through a dedicated node (nodes 0 to 2 and 6 to 8, which can be understood as interconnection interfaces). The central tag buffer and Level 2 cache are connected to the interconnection interface unit through nodes 3 to 5, respectively. All nodes are connected to each other through the communication links of the interconnection interface unit. This allows Level 1 caches to interact with other Level 1 caches, the central tag buffer, and Level 2 caches through direct communication links between nodes. The central tag buffer is connected to the interconnection interface unit through nodes 3 to 5 to uniformly manage the global tag information of all Level 1 caches. The Level 2 cache serves as a fallback storage layer, only intervening through the interconnection interface unit when there is no valid data at the Level 1 cache level. The entire architecture realizes direct data sharing between Level 1 caches and global scheduling of the central tag buffer through the communication network built by the interconnection interface unit.

[0103] In this architecture, when the computing core initiates a read request, the corresponding L1 cache queries its local tag table. If a match is found, the data is returned directly. If no match is found, a global query is initiated to the central tag buffer via the interconnect interface unit. After the central tag buffer retrieves the global tag table, if the target data is located in another L1 cache, direct data transfer between L1 caches is triggered via the interconnect interface unit. The receiving L1 cache stores the data and synchronously updates its local tag table and the central tag buffer. If the global query fails, the central tag buffer triggers the intervention of the secondary cache. After the secondary cache retrieves the data, it sends it to the requesting L1 cache via the interconnect interface unit. Finally, the L1 cache returns the data to the computing core. The entire process of message and data transfer between components is completed through the communication link built by the interconnect interface unit. Furthermore, the L1 cache only handles read requests, while write requests bypass the L1 cache and are sent directly to the secondary cache.

[0104] The technical solution of this invention addresses the problems of L2 bandwidth bottleneck, high access latency, low resource utilization, and complex design in existing L1 cache architectures. Through the collaborative design of interconnect interface units, central tag management, and read-only L1 caches, it utilizes interconnect interface units to construct direct communication links between L1 caches, replacing the traditional L2 relay path and reducing the access pressure on L2 caches. A central tag buffer centrally manages global tag information, enabling rapid location of target data and avoiding blind access to L2 caches. Simultaneously, configuring L1 caches in read-only mode circumvents complex cache consistency protocols, simplifies the overall design, and solves the latency and bandwidth problems caused by data sharing relying on L2 in multi-L1 cache scenarios, as well as the design complexity issues brought about by cache consistency.

[0105] In a specific example, taking the core 0 access address 0x12345678 and the interconnect interface unit as NoC, 0x81234 is the high-order address bit, also known as the tag bit, used to uniquely identify the data block within the cache set, and works with the index bit to complete the cache hit determination. 0x56 is the index bit, used to locate the corresponding memory set in the L1 cache and determine which set's tag table to query. 0x78 is the offset bit, used to locate the specific byte within the data block, because a cache block typically contains multiple bytes.

[0106] The specific steps and timing are as follows: t=0: Core 0 initiates a read request, address 0x12345678, and sends it to the corresponding L1_0 (Level 1 cache 0 matching compute core 0); t=1: After resolving the address, L1_0 queries the local Tag table (group 0x56, where 0x56 is the index bit obtained after resolving the target address 0x12345678, used to locate the corresponding storage group in the L1 cache), and the result is a miss; t=2: L1_0 generates a read request containing the target address and its own identifier, and sends it to the central Tag buffer through the NoC's read request virtual channel; t=4: The central Tag buffer receives the request and searches the global Tag table, finding that the target data is stored in L1_2 (Level 1 cache 2); t=5: The central Tag buffer generates a data request containing the target tag information, the L1_0 identifier, and the L1_2 identifier. The request is sent to L1_2 via the read request virtual channel; t=7: After receiving the request, L1_2 queries its local Tag table to confirm the target data is valid; t=8: L1_2 reads the target data block and packages it into a data packet, which is then sent to L1_0 via the NoC data virtual channel; t=10: L1_0 receives the data packet. Since its local data area is full, it replaces the least accessed data in group 0x56 with LRU and completes the storage; t=11: L1_0 updates its local Tag table (adding Tag=0x1234, valid bit=1) and generates a Tag update notification, which is sent to the central Tag buffer via the synchronization virtual channel; t=13: The central Tag buffer receives the notification and updates the global Tag table, setting the corresponding flag bit of L1_0 to 1; t=14: L1_0 returns the target data to core 0, and the read operation is complete.

[0107] By directly sharing data between L1 caches, L1 miss requests can be completed at the L1 level, reducing the number of read requests to the L2 cache and alleviating the L2 bandwidth bottleneck. At the same time, the latency of direct transmission between L1 caches is much lower than that of traditional L2 relay latency, reducing the average data access latency. The dual synchronization mechanism of the central tag buffer and the local tag table of the L1 cache ensures the accuracy of data location and improves the utilization of cache resources. The design of the read-only L1 cache avoids complex cache coherence protocols, optimizes the overall performance of the computing core without increasing hardware costs and design complexity, and this solution is suitable for GPU digital systems.

[0108] The technical solution of this invention allows the first target level 1 cache to directly query the central tag buffer for the storage status of other level 1 caches when it misses the target data locally. It then uses a global tag table to quickly locate the second target level 1 cache storing the target data. The second target level 1 cache then transmits the data directly to the first target level 1 cache via the interconnect interface unit. Finally, the first target level 1 cache feeds back to the computing core. This avoids the intermediate step of the level 2 cache in traditional solutions, reducing the access pressure on the level 2 cache to alleviate its bandwidth bottleneck, and shortening the data transmission path from the source level 1 cache to the requesting level 1 cache, thus reducing data access latency. Simultaneously, it eliminates the need to rely on complex cache consistency protocols to synchronize the states of multiple level 1 caches, simplifying the data sharing interaction logic and thereby improving the overall operating efficiency of the graphics processor and the real-time performance of data access. When the central tag buffer determines that none of the first-level caches have stored the target data block, it directly requests the second-level cache to retrieve the data and sends it to the first target first-level cache. This ensures the integrity of data access, avoids request failures due to no data in the first-level cache, and optimizes the access logic of the second-level cache through unified scheduling by the central tag buffer. It eliminates the need for each first-level cache to send separate requests to the second-level cache, reducing invalid interactions between the second-level caches. At the same time, the second-level cache only intervenes when none of the first-level caches have been hit, avoiding the situation in traditional solutions where the second-level cache indiscriminately accepts all first-level cache miss requests. This further optimizes the allocation of bandwidth resources for the second-level cache, reducing the risk of it being saturated by concurrent requests. Moreover, the data is directly transmitted from the second-level cache to the first target first-level cache corresponding to the demand, reducing unnecessary transit links. While ensuring data reachability, this indirectly improves the overall data access efficiency.

[0109] Example 4 Figure 5 This is a schematic diagram of a cached data sharing device provided in Embodiment 4 of the present invention. Figure 5 As shown, the device includes: a read request module 510, an instruction sending module 520, a data sending module 530, and a data feedback module 540, wherein: The read request module 510 is used to, after receiving a read data request for a target data block sent by the connected computing core through the first target first-level cache, if it is determined that the target data block is not stored locally, request the central tag buffer via the interconnection interface unit to query whether there is another first-level cache storing the target data block. The instruction sending module 520 is used to, upon receiving a query request for a target data block sent by the first target first-level cache through the central tag buffer, instruct the second target first-level cache to send the target data block to the first target first-level cache if it is determined from the global tag table that the target data block is stored in the second target first-level cache. The data transmission module 530 is used to send the target data block to the first target first-level cache via the interconnection interface unit after receiving an instruction from the central tag buffer to send the target data block to the first target first-level cache. If the target data block is successfully obtained locally, the second target first-level cache will send the target data block to the first target first-level cache via the second target first-level cache. The data feedback module 540 is used to feed back the target data block to the connected computing core when it receives the target data block sent by the second target first-level cache through the interconnect interface unit via the first target first-level cache.

[0110] The technical solution of this invention allows the first target level 1 cache to directly query the central tag buffer for the storage status of other level 1 caches when it misses the target data locally. It then uses a global tag table to quickly locate the second target level 1 cache storing the target data. The second target level 1 cache then transmits the data directly to the first target level 1 cache via the interconnect interface unit. Finally, the first target level 1 cache feeds back to the computing core. This avoids the intermediate step of the level 2 cache in traditional solutions, reducing the access pressure on the level 2 cache to alleviate its bandwidth bottleneck, and shortening the data transmission path from the source level 1 cache to the requesting level 1 cache, thus reducing data access latency. Simultaneously, it eliminates the need to rely on complex cache consistency protocols to synchronize the states of multiple level 1 caches, simplifying the data sharing interaction logic and thereby improving the overall operating efficiency of the graphics processor and the real-time performance of data access.

[0111] Based on the above embodiments, the global tag table includes multiple data items, each of which includes tag information matching a set data block, as well as identification information storing all first-level caches of the set data block; Accordingly, based on the above embodiments, the instruction sending module 520 is specifically used for: If, through the central tag buffer, it is determined that there is a target data item in the global tag table that matches the target tag information of the target data block, then all target level-one caches storing the target data block are retrieved from the target data item. The central tag buffer instructs the second target first-level cache, which contains the target data block, to send the target data block to the first target first-level cache.

[0112] Based on the above embodiments, each data item in the global tag table also includes the first-level cache that most recently read the specified data block in all first-level caches storing the specified data block; Accordingly, based on the above embodiments, the instruction sending module 520 is further configured to: Using the central tag buffer, the most recently read target data block in all target first-level caches is obtained from the target data items and used as the current second target first-level cache. A set of alternative second target first-level caches is constructed based on the remaining target first-level caches. Using the central tag buffer, a first-level cache inter-read request is constructed based on the first target first-level cache, target tag information, and the second target first-level cache set, and then the first-level cache inter-read request is sent to the current second target first-level cache; Upon receiving a read request between first-level caches, if it is determined that the target data block in the local storage matches the target tag information, the target data block is sent to the first target first-level cache. If it is determined that the target data block is not stored locally using the current second target first-level cache, then one of the candidate second target first-level caches is sequentially obtained from the candidate second target first-level cache set as the new current second target first-level cache. After that, the first-level cache inter-caching read request is sent to the new current second target first-level cache, so as to relay the instruction to the second target first-level cache in the candidate second target first-level cache set that stores the target data block to send the target data block to the first target first-level cache.

[0113] Based on the above embodiments, the instruction sending module 520 is further configured to: If, through the current second target level 1 cache, it is determined that the target data block is not stored locally, and there is currently no target level 1 cache that can serve as the new current second target level 1 cache, a miss response is returned to the central label buffer to inform that none of the target level 1 caches in the central label buffer store the target data block.

[0114] Furthermore, based on the above embodiments, the cached data sharing device may further include: a request secondary module and a secondary sending module, wherein: The request is made to the second-level module, which, through the central tag buffer, requests the second-level cache to send the target data block to the first target first-level cache when it is determined that none of the first-level caches have stored the target data block. The secondary sending module is used to obtain the target data block after receiving a data retrieval request for the target data block from the central tag buffer through the secondary cache, and then send the target data block to the first target primary cache.

[0115] Optionally, based on the above embodiments, requesting a secondary module may include: a new item construction unit, wherein: The new item unit is used to construct a new data item based on the target label information of the target data block and the first target first-level cache after the target data block is sent to the second-level cache through the central label buffer. The global label table is then updated based on the new data item.

[0116] Based on the above embodiments, the local tag table stores the tag information of the data blocks stored in each cache unit of the first-level cache; correspondingly, based on the above embodiments, the cache data sharing device may further include: a local query module and a hit determination module, wherein: The local query module is used to query the local tag table based on the target tag information of the target data block in the read data request sent by the connected computing core before determining that the target data block is not stored locally through the first target first-level cache. The hit determination module is used to determine whether the first target first-level cache should store the target data block locally based on the hit result of the target tag information in the local tag table, through the first target first-level cache.

[0117] Furthermore, based on the above embodiments, the cached data sharing device may further include: a global update module and a tag update module, wherein: The global update module is used to store the target data block sent by the second target first-level cache or second-level cache into the local data cache area through the first target first-level cache, and then update the local tag table according to the target data block; The tag update module is used to generate a global tag update instruction through the first target level cache, and send the global tag update instruction to the central tag buffer so that the central tag buffer can update the global tag table.

[0118] The cached data sharing device provided in the embodiments of the present invention can execute the cached data sharing method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of executing the method.

[0119] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved in the technical solution disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0120] Example 5 Figure 6 A schematic diagram of an electronic device 610 that can be used to implement embodiments of the present invention is shown. The electronic device 610 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device 610 can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (such as helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0121] like Figure 6 As shown, the electronic device 610 includes a graphics processor 6101 as described in any embodiment of the present invention, comprising multiple computing cores, multiple level-one caches equal in number to the computing cores, an interconnect interface unit, and a central tag buffer; each level-one cache is connected to each computing core in a one-to-one correspondence, and each level-one cache and the central tag buffer establish a pairwise communication link through the interconnect interface unit; the central tag buffer includes a global tag table, which records the tag information of the data blocks stored in each level-one cache, wherein: Each level-1 cache is used to, upon receiving a read data request for a target data block from the connected computing core, if it is determined that the target data block is not stored locally, query the central tag buffer via the interconnect interface unit to see if there is another level-1 cache storing the target data block; and, upon receiving a target data block from another level-1 cache via the interconnect interface unit, feed the target data block back to the connected computing core. The central tag buffer is used to, upon receiving a query request for a target data block from a first-level cache, instruct other first-level caches to send the target data block to the first-level cache that requested the target data block if the global tag table determines that the target data block is stored in another first-level cache.

[0122] The graphics processor 6101 can execute the various methods and processes described above, such as the cached data sharing method, that is: After receiving a read data request for the target data block from the connected computing core, the first target level cache, if it is determined that the target data block is not stored locally, requests the central tag buffer to query whether there is another level cache storing the target data block via the interconnection interface unit. Upon receiving a query request for a target data block from the first target first-level cache via the central tag buffer, if the target data block is determined to be stored in the second target first-level cache based on the global tag table, the second target first-level cache is instructed to send the target data block to the first target first-level cache. After receiving an instruction from the central tag buffer to send the target data block to the first target first-level cache, the second target first-level cache sends the target data block to the first target first-level cache via the interconnect interface unit if the target data block is successfully obtained locally. When the first target level 1 cache receives the target data block sent by the second target level 1 cache via the interconnect interface unit, it feeds back the target data block to the connected computing core.

[0123] In some embodiments, the cached data sharing method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as a storage unit. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 610 via a read-only memory and / or a communication unit. When the computer program is loaded into random access memory and executed by a processor, one or more steps of the cached data sharing method described above may be performed. Alternatively, in other embodiments, the processor may be configured to perform the cached data sharing method by any other suitable means (e.g., by means of firmware).

[0124] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0125] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0126] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0127] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0128] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0129] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0130] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0131] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A graphics processor, characterized in that, It includes multiple computing cores, multiple L1 caches equal to the number of computing cores, interconnect interface units, and a central tag buffer. Each L1 cache is connected to each computing core in a one-to-one correspondence, and each L1 cache and the central tag buffer establish a pairwise communication link through the interconnect interface units. The central tag buffer includes a global tag table, which records the tag information of the data blocks stored in each L1 cache, wherein: Each level-1 cache is used to, upon receiving a read data request for a target data block from the connected computing core, if it is determined that the target data block is not stored locally, query the central tag buffer via the interconnect interface unit to see if there is another level-1 cache storing the target data block; and, upon receiving a target data block from another level-1 cache via the interconnect interface unit, feed the target data block back to the connected computing core. The central tag buffer is used to, upon receiving a query request for a target data block from a first-level cache, instruct other first-level caches to send the target data block to the first-level cache that requested the target data block if the global tag table determines that the target data block is stored in another first-level cache.

2. The graphics processor according to claim 1, characterized in that, The graphics processor also includes: a secondary cache, which is communicatively connected to each primary cache and the central tag buffer; The central tag buffer is also used to request the second-level cache to send the target data block to the first-level cache that requested the target data block when it is determined that none of the first-level caches have stored the target data block. The second-level cache is used to retrieve the target data block and send it to the first-level cache that requested the target data block after receiving a data retrieval request for the target data block from the central tag buffer.

3. The graphics processor according to claim 1, characterized in that, Each of the first-level caches stores a local tag table; Each of the first-level caches is specifically used to determine whether the target data block is stored locally by querying the local tag table after receiving a read data request for the target data block sent by the connected computing core.

4. The graphics processor according to claim 2, characterized in that, Each of the first-level caches is used only to respond to read data requests from each computing core or the central tag buffer; the second-level cache is used to respond to read data requests from each computing core or the central tag buffer, as well as write data requests from each computing core or the central tag buffer.

5. The graphics processor according to any one of claims 1-4, characterized in that, Each level 1 cache and the central tag buffer is equipped with an interconnection interface; each level 1 cache and the central tag buffer are connected to the interconnection interface unit through their respective interconnection interfaces to establish a pairwise communication link through the interconnection interface unit.

6. A method for sharing cached data, characterized in that, The method, executed by a graphics processor as described in any one of claims 1-5, comprises: After receiving a read data request for the target data block from the connected computing core, the first target level cache, if it is determined that the target data block is not stored locally, requests the central tag buffer to query whether there is another level cache storing the target data block via the interconnection interface unit. Upon receiving a query request for a target data block from the first target first-level cache via the central tag buffer, if the target data block is determined to be stored in the second target first-level cache based on the global tag table, the second target first-level cache is instructed to send the target data block to the first target first-level cache. After receiving an instruction from the central tag buffer to send the target data block to the first target first-level cache, the second target first-level cache sends the target data block to the first target first-level cache via the interconnect interface unit if the target data block is successfully obtained locally. When the first target level 1 cache receives the target data block sent by the second target level 1 cache via the interconnect interface unit, it feeds back the target data block to the connected computing core.

7. The method according to claim 6, characterized in that, The global tag table includes multiple data items, each of which includes tag information that matches a set data block, as well as identification information that stores all first-level caches of the set data block; Upon receiving a query request for a target data block from the first target first-level cache via the central tag buffer, if the global tag table determines that the target data block is stored in the second target first-level cache, then the second target first-level cache is instructed to send the target data block to the first target first-level cache. Specifically, this includes: If, through the central tag buffer, it is determined that there is a target data item in the global tag table that matches the target tag information of the target data block, then all target level-one caches storing the target data block are retrieved from the target data item. The central tag buffer instructs the second target first-level cache, which contains the target data block, to send the target data block to the first target first-level cache.

8. The method according to claim 7, characterized in that, Each data item in the global tag table also includes the first-level cache that most recently read the specified data block, which is stored in the first-level cache of the entire specified data block; Correspondingly, through the central tag buffer, the second target first-level cache, which stores the target data block in all target first-level caches, is instructed to send the target data block to the first target first-level cache, specifically including: Using the central tag buffer, the most recently read target data block in all target first-level caches is obtained from the target data items and used as the current second target first-level cache. A set of alternative second target first-level caches is constructed based on the remaining target first-level caches. Using the central tag buffer, a first-level cache inter-read request is constructed based on the first target first-level cache, target tag information, and the second target first-level cache set, and then the first-level cache inter-read request is sent to the current second target first-level cache; Upon receiving a read request between first-level caches, if it is determined that the target data block in the local storage matches the target tag information, the target data block is sent to the first target first-level cache. If it is determined that the target data block is not stored locally using the current second target first-level cache, then one of the candidate second target first-level caches is sequentially obtained from the candidate second target first-level cache set as the new current second target first-level cache. After that, the first-level cache inter-caching read request is sent to the new current second target first-level cache, so as to relay the instruction to the second target first-level cache in the candidate second target first-level cache set that stores the target data block to send the target data block to the first target first-level cache.

9. The method according to claim 8, characterized in that, The method further includes instructing the second target first-level cache, which contains the target data block, to send the target data block to the first target first-level cache via the central tag buffer, and instructing the second target first-level cache, which contains the target data block, to send the target data block to the first target first-level cache. If, through the current second target level 1 cache, it is determined that the target data block is not stored locally, and there is currently no target level 1 cache that can serve as the new current second target level 1 cache, a miss response is returned to the central label buffer to inform that none of the target level 1 caches in the central label buffer store the target data block.

10. The method according to any one of claims 6-9, characterized in that, The method further includes: Using the central tag buffer, when it is determined that none of the first-level caches have stored the target data block, a request is made to the second-level cache to send the target data block to the first target first-level cache. Through the second-level cache, after receiving a data retrieval request for the target data block sent by the central tag buffer, the target data block is retrieved and sent to the first target first-level cache.

11. The method according to claim 10, characterized in that, After requesting the second-level cache via the central tag buffer to send the target data block to the first target first-level cache, the process also includes: Using the central label buffer, new data items are constructed based on the target label information of the target data block and the first target level cache, and the global label table is updated based on the new data items.

12. The method according to any one of claims 6-9, characterized in that, The local tag table stores the tag information of the data blocks stored in each cache unit of the first-level cache; Accordingly, before determining that the target data block is not stored locally through the first target level-one cache, the method further includes: Using the first target level cache, the local tag table is queried based on the target tag information of the target data block in the read data request sent by the connected computing core; Based on the hit results of the target tag information in the local tag table, the system determines whether the target data block should be stored locally in the first target level cache.

13. The method according to claim 12, characterized in that, The method further includes: After storing the target data block sent by the second target first-level cache or second-level cache into the local data cache area through the first target first-level cache, the local tag table is updated according to the target data block; The first target level cache generates a global label update instruction and sends it to the central label buffer so that the central label buffer can update the global label table.

14. An electronic device, characterized in that, The electronic device includes: a graphics processor as described in any one of claims 1-5.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the cache data sharing method according to any one of claims 6-13.

16. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the cached data sharing method according to any one of claims 6-13.

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