Graphics processor, cache data sharing method, device, medium and program product
By setting up a L1 cache corresponding to the computing core in the graphics processor and establishing a communication link with the central tag buffer through the interconnect interface unit, direct data transmission between L1 caches is realized, which solves the problems of low cache resource utilization and high data access latency, and improves the performance and real-time performance of multi-core systems.
CN121961825BActive Publication Date: 2026-07-03RICUN TECH (SHANGHAI) CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- RICUN TECH (SHANGHAI) CO LTD
- Filing Date
- 2026-03-27
- Publication Date
- 2026-07-03
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Figure CN121961825B_ABST
Abstract
The application discloses a kind of graphic processor, cache data sharing method, equipment, medium and program product, it is related to processor technical field, by setting and computing core one-to-one corresponding first cache, and by interconnection interface unit constructs the two-way communication link of each first cache and central tag buffer, with the global tag table of all first cache data block tag information is recorded, when first cache receives the read data request of connected computing core and local does not store target data block, other first cache where target data block is located can be positioned by central tag buffer, direct data transmission between first cache is realized via interconnection interface unit, without relying on second cache transfer, reduce the access pressure of second cache, solve bandwidth bottleneck problem, shorten data transmission path, reduce data access delay, avoid the complex design brought by traditional cache consistency protocol, improve cache resource utilization, optimize the overall operating performance of graphic processor.
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