Gate driver

Abstract

The gate driver includes a plurality of stages. Each of the plurality of stages includes a CQ node charging circuit, a first CQS node charging circuit, a second CQS node charging circuit, a QB node control circuit, a CQ node boost circuit, and a gate output circuit that outputs a first gate clock signal to a P-th (wherein, the first CQS node charging circuit and the second CQS node charging circuit). P is a positive integer greater than or equal to 2) gate clock signal as first to Pth gate signals. The plurality of stages receive first to Q-th (where Q is a positive integer greater than P) gate clock signals. Q may be a minimum value among Q values satisfying a condition that a duration of outputting a (Q + 1) th gate signal of the second stage is separated from a duration of outputting a voltage of a CQ node of the first stage having a high level.

Description

Gate driver Technical Field

[0001] Embodiments of the present invention relate to gate drivers. More specifically, embodiments of the present invention relate to gate drivers for supporting dual-wire gate (DLG) mode. Background Technology

[0002] Recently, display devices supporting dual-line gate (DLG) mode have been developed. In DLG mode, two adjacent gate lines are driven simultaneously to increase the driving frequency of the display panel. For example, a display device that typically operates at 60Hz can use DLG mode to achieve a refresh rate of 120Hz.

[0003] Display devices operating in DLG mode include gate drivers that output gate signals to gate lines. The configuration of the gate driver can vary, particularly the number of gate clock signals used by the gate driver. As the number of gate clock signals increases, the amount of layout area or unused space occupied by the gate driver can also increase. Summary of the Invention

[0004] Embodiments of the present invention provide a gate driver capable of reducing unused space in display devices supporting dual-line gate (DLG) modes.

[0005] In an embodiment of the gate driver according to the present invention, the gate driver includes multiple stages. Each of the multiple stages includes: a CQ node charging circuit configured to provide a previous carry signal and a second high gate voltage to the CQ node in response to a previous carry signal; a first CQS node charging circuit configured to provide a second high gate voltage to the CQS node in response to a previous carry signal; a second CQS node charging circuit configured to provide a first high gate voltage to the CQS node in response to the voltage of the boost node; and a QB node control circuit configured to invert the voltage of the CQ node to provide the inverted voltage of the CQ node to the QB node. The B-node and CQ-node boost circuits are configured to: provide a boost clock signal to the boost node in response to the voltage of the CQ-node, and provide a second low gate voltage to the boost node in response to the voltage of the QB-node; and the gate output circuit is configured to: output a first gate clock signal to a P-th gate clock signal as a first gate signal to a P-th gate signal in response to the voltage of the CQ-node, and output a first low gate voltage as a first gate signal to a P-th gate signal in response to the voltage of the QB-node, where P is a positive integer greater than 2. A pulse of each of the first to P-th gate signals is included in the duration during which the voltage of the boost node is high, and the duration during which the voltage of the boost node is high is included in the duration during which the voltage of the CQ-node is high, wherein multiple stages receive the first to Q-th gate clock signals, where Q is a positive integer greater than P. When the first stage of a plurality of stages is configured to output a first gate clock signal to a P-th gate clock signal as a first gate signal to a P-th gate signal, and the second stage of a plurality of stages is configured to output a P+1-th gate clock signal to a Q-th gate clock signal as a P+1-th gate signal to a Q-th gate signal, and then the second stage is configured to output a first gate clock signal as a Q+1-th gate signal, the duration of the output Q+1-th gate signal is separate from the duration of the high level voltage of the CQ node of the first stage.

[0006] In this embodiment, Q can be a multiple of 2.

[0007] In an embodiment, Q can be the minimum value that satisfies the condition that the duration of the second stage being configured to output the Q+1 gate signal is separate from the duration of the voltage of the CQ node of the first stage being high.

[0008] In an embodiment, the gate driver can be configured to support a two-wire gate mode; and while the gate driver is configured to perform the two-wire gate mode, the pulse duration of each of the first gate clock signal to the Qth gate clock signal can be reduced.

[0009] In an embodiment, P can be 6 and Q can be 10.

[0010] In an embodiment, the CQ node charging circuit may include: a first-first transistor, including: a gate electrode for receiving a previous carry signal, a first electrode for receiving the previous carry signal, and a second electrode for receiving a second high gate voltage; and a first-second transistor, including: a gate electrode for receiving the previous carry signal, a first electrode for receiving the second high gate voltage, and a second electrode connected to the CQ node.

[0011] In one embodiment, the first CQS node charging circuit may include a first transistor, which includes a gate electrode for receiving a previous carry signal, a first electrode for receiving a second high gate voltage, and a second electrode connected to the CQS node. The second CQS node charging circuit includes a second transistor, which includes a gate electrode for receiving the voltage of the boost node, a first electrode for receiving a first high gate voltage, and a second electrode connected to the CQS node.

[0012] In an embodiment, the QB node control circuit may include: a first transistor, including a gate electrode receiving a first high gate voltage, a first electrode receiving the first high gate voltage, and a second electrode; a second transistor, including a gate electrode connected to the second electrode of the first transistor, a first electrode receiving the first high gate voltage, and a second electrode connected to the QB node; a third transistor, including a gate electrode connected to the CQ node, a first electrode receiving a first low gate voltage, and a second electrode connected to the second electrode of the first transistor and the gate electrode of the second transistor; and a fourth transistor, including a gate electrode connected to the CQ node, a first electrode receiving a second low gate voltage, and a second electrode connected to the QB node.

[0013] In an embodiment, the CQ node boost circuit may include: a first transistor, including a gate electrode connected to the CQ node, a first electrode receiving a boost clock signal, and a second electrode connected to the boost node; a second transistor, including a gate electrode connected to the QB node, a first electrode receiving a second low gate voltage, and a second electrode connected to the boost node; and a CQ boost capacitor, including a first electrode connected to the CQ node and a second electrode connected to the boost node.

[0014] In an embodiment, the gate output circuit may include a first gate output circuit to a P-th gate output circuit, which are configured to output a first gate signal to a P-th gate signal. The P-th gate output circuit includes: a P-th gate variable conduction transistor, including a gate electrode connected to a CQS node, a first electrode connected to a CQ node, and a second electrode connected to a P-th gate Q node; a first-P-th transistor, including a gate electrode connected to a P-th gate Q node, a first electrode receiving a P-th gate clock signal, and a second electrode connected to a P-th gate node, wherein the P-th gate signal is output from the P-th gate node; a second-P-th transistor, including a gate electrode connected to a QB node, a first electrode receiving a first low gate voltage, and a second electrode connected to a P-th gate node; and a P-th gate boost capacitor, including a first electrode connected to a P-th gate Q node and a second electrode connected to a boost node.

[0015] According to the gate driver, Q can be the minimum of the Q values ​​that satisfy the condition that the duration of the Q+1th gate signal of the second stage output is separate from the duration of the high-level voltage of the CQ node of the first stage. Therefore, the unused space of the gate driver can be reduced. Attached Figure Description

[0016] The above and other features of the present invention will become more apparent from the detailed description of embodiments of the present invention with reference to the accompanying drawings, in which:

[0017] Figure 1 is a block diagram illustrating a display device according to an embodiment of the concept of the present invention;

[0018] Figure 2 is a circuit diagram showing an example of the pixels in Figure 1;

[0019] Figure 3 is a block diagram showing the gate driver of Figure 1;

[0020] Figure 4 is a circuit diagram showing the stage of Figure 3;

[0021] Figure 5 is a timing diagram showing the operation of the stage in Figure 4;

[0022] Figure 6 is a circuit diagram showing the operation of the stage of Figure 4 during the first duration of Figure 5;

[0023] Figure 7 is a circuit diagram showing the operation of the stage of Figure 4 during the second duration of Figure 5;

[0024] Figure 8 is a circuit diagram showing the operation of the stage of Figure 4 during the third duration of Figure 5;

[0025] Figure 9 is a circuit diagram showing the operation of the stage of Figure 4 during the fourth duration of Figure 5;

[0026] Figures 10 and 11 are conceptual diagrams explaining the number of clock signals;

[0027] Figure 12 is a block diagram illustrating the electronic device; and

[0028] Figure 13 is a diagram illustrating an embodiment in which the electronic device of Figure 12 is implemented as a smartphone. Detailed Implementation

[0029] In the following description, embodiments of the present disclosure will be described more fully with reference to the accompanying drawings. Throughout the drawings, the same reference numerals may refer to the same elements.

[0030] It will be understood that the terms “first,” “second,” “third,” etc., are used herein to distinguish one element from another, and the elements are not limited by these terms. Thus, a “first” element in one embodiment may be described as a “second” element in another embodiment.

[0031] It should be understood that, unless the context clearly indicates otherwise, the description of features or aspects of each embodiment should generally be considered applicable to other similar features or aspects in other embodiments.

[0032] Unless the context clearly indicates otherwise, the singular forms “a,” “one,” and “the” are intended to include the plural forms as used herein.

[0033] It will be understood that when a component is referred to as being "on" another component, "connected to" another component, "coupled to" another component, or "adjacent" to another component, the component may be directly on, directly connected to, directly coupled to, or directly adjacent to the other component, or there may be intermediary components. It will also be understood that when a component is referred to as being "between" two components, the component may be the only component between the two components, or there may be one or more intermediary components. It will also be understood that when a component is referred to as "covering" another component, the component may be the only component covering the other component, or one or more intermediary components may also cover the other component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0034] Embodiments of this invention relate to a gate driver architecture (gate driver) for a display device, capable of efficiently generating multiple gate signals using a reduced number of gate clock signals. For example, the gate driver may include multiple stages, each configured to output multiple gate signals while receiving a subset of shared gate clock signals. This configuration can support high-speed driving modes (such as a dual-line gate (DLG) mode), where two adjacent gate lines are driven simultaneously to increase the refresh rate, for example, from about 60 Hz to about 120 Hz.

[0035] Each stage of the gate driver may include functionally distinct circuitry, such as a CQ node charging circuit, a CQS node charging circuit, a QB node control circuit, a CQ node boost circuit, and a gate output circuit. These circuits can cooperate to sequentially generate P gate signals (e.g., 6 gate signals) within a timing window synchronized with the boost node and CQ node. An aspect of embodiments of the inventive concept is the control of signal timing between stages to avoid interference. For example, the timing of the subsequent stage outputting its Q+1th gate signal is arranged such that this timing does not overlap with the period during which the CQ node of the preceding stage is held high. This separation (discretion or partition) reduces the number (Q) of gate clock signals without compromising the stability or independence of the gate signals generated by each stage.

[0036] By improving internal node timing and utilizing overlapping output windows across stages, embodiments of the present invention can reduce the total number of gate clock signals required. This can minimize or reduce unused space associated with signal routing and improve integration density, making the gate driver particularly suitable for high-resolution and high-speed display applications with tight area constraints.

[0037] Figure 1 is a block diagram illustrating a display device 100 according to an embodiment of the present invention.

[0038] Referring to FIG1, the display device 100 may include a display panel 110 and a display panel driver. The display panel driver may include a drive controller 120, a gate driver 130, a gamma reference voltage generator 140, and a data driver 150.

[0039] The display panel 110 may include a display area in which an image is displayed and a peripheral area adjacent to the display area in which no image is displayed. The peripheral area may correspond to the border area.

[0040] The display panel 110 may include a gate line GL, a data line DL, an emitter line, and pixels PX electrically connected to the gate line GL, the data line DL, and the emitter line, respectively. The gate line GL may extend in a first direction, the data line DL may extend in a second direction intersecting the first direction, and the emitter line may extend in the first direction.

[0041] The drive controller 120 can receive input image data IMG and input control signals CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may also include white image data. The input image data IMG may also include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0042] The drive controller 120 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a data signal DATA based on the image data IMG and the input control signal CONT.

[0043] The drive controller 120 can generate a first control signal CONT1 to control the operation of the gate driver 130 based on the input control signal CONT and output the first control signal CONT1 to the gate driver 130. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0044] The drive controller 120 can generate a second control signal CONT2 based on the input control signal CONT and output the second control signal CONT2 to the data driver 150. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0045] The drive controller 120 can generate a data signal DATA based on the input image data IMG. The drive controller 120 can output the data signal DATA to the data driver 150.

[0046] The drive controller 120 can generate a third control signal CONT3 based on the input control signal CONT to control the operation of the gamma reference voltage generator 140 and output the third control signal CONT3 to the gamma reference voltage generator 140.

[0047] The gate driver 130 can generate a gate signal for driving the gate line GL in response to a first control signal CONT1 received from the drive controller 120. The gate driver 130 can output the gate signal to the gate line GL.

[0048] The gamma reference voltage generator 140 can generate a gamma reference voltage VGREF in response to a third control signal CONT3 received from the drive controller 120. The gamma reference voltage generator 140 can provide the gamma reference voltage VGREF to the data driver 150. The gamma reference voltage VGREF can have a value corresponding to each data signal DATA.

[0049] For example, the gamma reference voltage generator 140 can be located within the drive controller 120 or within the data driver 150.

[0050] Data driver 150 can receive a second control signal CONT2 and a data signal DATA from drive controller 120, and a gamma reference voltage VGREF from gamma reference voltage generator 140. Data driver 150 can use the gamma reference voltage VGREF to convert the data signal DATA into a data voltage of analog type. Data driver 150 can output the data voltage to data line DL.

[0051] Figure 2 is a circuit diagram showing an example of pixel PX in Figure 1.

[0052] Referring to Figures 1 and 2, a pixel PX may include a first pixel transistor PT1, a second pixel transistor PT2, a third pixel transistor PT3, a storage capacitor CST, and a light-emitting element EL. In an embodiment, the first pixel transistor PT1, the second pixel transistor PT2, and the third pixel transistor PT3 may be N-type metal-oxide-semiconductor (NMOS) transistors.

[0053] The first pixel transistor PT1 may include a gate electrode connected to the first pixel node NP1, a first electrode receiving a high power supply voltage ELVDD, and a second electrode connected to the second pixel node NP2. The second pixel transistor PT2 may include a gate electrode receiving a scan gate signal SC, a first electrode connected to a data line DL for transmitting data voltage VDATA, and a second electrode connected to the first pixel node PN1. The third pixel transistor PT3 may include a gate electrode receiving a sense gate signal SS, a first electrode connected to an initialization line IL for transmitting initialization voltage VINT, and a second electrode connected to the second pixel node NP2. The storage capacitor CST may include a first electrode connected to the first pixel node NP1 and a second electrode connected to the second pixel node NP2. The light-emitting element EL may include an anode electrode connected to the second pixel node NP2 and a cathode electrode receiving a low power supply voltage ELVSS, which is lower than the high power supply voltage ELVDD.

[0054] Figure 3 is a block diagram showing the gate driver 130 of Figure 1.

[0055] Referring to Figures 1 to 3, the gate driver 130 may include multiple stages STG1, STG2, STG3, ... Stages STG1, STG2, STG3, ... can output gate signals. Here, the gate signal can be the scan gate signal SC of Figure 2 or the sense gate signal SS.

[0056] Each of stages STG1, STG2, STG3, ... can output P gate signals based on P gate clock signals (where P is a positive integer greater than 2). Stages STG1, STG2, STG3, ... can receive gate clock signals from the first gate clock signal to the Qth gate clock signal (where Q is a positive integer greater than P). As Q increases, the number of gate clock signals may increase, and the unused space of gate driver 130 may increase. Therefore, obtaining a minimum value of Q can be important. Figures 3 through 12 show the case where a minimum value of Q (e.g., 10) is obtained when P is 6. However, gate driver 130 can support DLG mode, and Q can be a multiple of 2. DLG mode will be described later in Figure 4.

[0057] Stages STG1, STG2, STG3, ... can receive the first carry clock signal CR_CK1 and the second carry clock signal CR_CK2, the first boost clock signal BCK1 and the second boost clock signal BCK2, and the first gate clock signal GS_CK1 to the tenth gate clock signal GS_CK10. For example, the first carry clock signal CR_CK1 and the second carry clock signal CR_CK2 can be clock signals with different phases. For example, the first boost clock signal BCK1 and the second boost clock signal BCK2 can be clock signals with different phases. For example, the first gate clock signal GS_CK1 to the tenth gate clock signal GS_CK10 can be clock signals with different phases.

[0058] Furthermore, the first stage STG1 can also receive the gate start signal FLM and the second carry signal CR2. Each of the subsequent stages STG2, STG3, ... can also receive the carry signal from the previous stage (e.g., the previous carry signal) and the carry signal from the next stage (e.g., the next carry signal). However, the inventive concept is not limited thereto.

[0059] Stages STG1, STG2, STG3, ... can sequentially output gate signals GS1, GS2, GS3, GS4, GS5, GS6, GS7, GS8, GS9, GS10, GS11, GS12, GS13, GS14, GS15, GS16, GS17, GS18, ... Furthermore, stages STG1, STG2, STG3, STG4 (not shown), ... can sequentially output carry signals CR1, CR2, CR3, CR4, ...

[0060] For example, the first-stage STG1 can receive the gate start signal FLM, the second carry signal CR2, the first carry clock signal CR_CK1, the first boost clock signal BCK1, and the first gate clock signals GS_CK1 to the sixth gate clock signals GS_CK6. The first-stage STG1 can sequentially output the first gate clock signals GS_CK1 to the sixth gate clock signals GS_CK6 as the first gate signals GS1 to the sixth gate signals GS6. The first-stage STG1 can output the first carry signal CR1.

[0061] For example, the second-stage STG2 can receive the first carry signal CR1, the third carry signal CR3, the second carry clock signal CR_CK2, the second boost clock signal BCK2, the seventh gate clock signal GS_CK7 to the tenth gate clock signal GS_CK10, and the first gate clock signal GS_CK1 and the second gate clock signal GS_CK2. The second-stage STG2 can sequentially output the seventh gate clock signal GS_CK7 to the tenth gate clock signal GS_CK10, and the first gate clock signal GS_CK1 and the second gate clock signal GS_CK2 as the seventh gate clock signal GS7 to the twelfth gate signal GS12. The second-stage STG2 can also output the second carry signal CR2.

[0062] For example, the third-stage STG3 can receive the second carry signal CR2, the fourth carry signal CR4, the first carry clock signal CR_CK1, the first boost clock signal BCK1, and the third gate clock signals GS_CK3 to the eighth gate clock signals GS_CK8. The third-stage STG3 can sequentially output the third gate clock signals GS_CK3 to the eighth gate clock signals GS_CK8 as the thirteenth gate signal GS13 to the eighteenth gate signal GS18. The third-stage STG3 can output the third carry signal CR3.

[0063] Figure 4 is a circuit diagram showing stage STG1, STG2, or STG3 of Figure 3.

[0064] Referring to Figures 1 through 4, the gate driver 130 may include multiple stages 200. Stage 200 in Figure 4 may be the Nth stage of Figure 3 (where N is a positive integer greater than or equal to 1). The gate driver 130 may support DLG (Dual-Line Gate) mode. DLG mode refers to a mode that increases the driving frequency of the display device 100 by simultaneously driving two consecutive gate lines. When the gate driver 130 executes DLG mode, the pulse duration of the gate signal can be reduced to simultaneously drive two consecutive gate lines.

[0065] Each stage 200 can be configured as follows. In an embodiment, the gate driver 130 may include multiple stages 200, each stage 200 including several functional circuits. Each stage 200 may include a CQ node charging circuit configured to supply a previous carry signal and a second high gate voltage to the CQ node in response to a previous carry signal. A first CQS node charging circuit may be configured to provide a second high gate voltage to the CQS node in response to a previous carry signal, and a second CQS node charging circuit may be configured to provide a first high gate voltage to the CQS node in response to the voltage of the boost node. The QB node control circuit may invert the voltage of the CQ node and provide the inverted voltage to the QB node. The CQ node boost circuit may be configured to provide a boost clock signal to the boost node based on the voltage of the CQ node, and to apply a second low gate voltage to the boost node based on the voltage of the QB node. Furthermore, the gate output circuit can output a first gate clock signal to the Pth (where P is a positive integer greater than 2) gate clock signal as the first gate signal to the Pth gate signal in response to the voltage of the CQ node, and output a first low gate voltage as the first gate signal to the Pth gate signal in response to the voltage of the QB node. A pulse of each of the first to Pth gate signals occurs during the period when the boost node has a high-level voltage, and this period is included within the high-level period of the CQ node. Stage 200 receives the first gate clock signal to the Qth (where Q is a positive integer greater than P) gate clock signal. When the first stage outputs the first gate signal to the Pth gate signal, the second stage outputs the P+1th gate signal to the Qth gate signal, and then the second stage uses the first gate clock signal to output the Q+1th gate signal. The output timing of the Q+1th gate signal is separated from the high-level period of the CQ node in the first stage, thereby preventing overlap and minimizing the value of Q.

[0066] Stage 200 may include a CQ node charging circuit 210, a first CQ node discharging circuit 220-1, a second CQ node discharging circuit 220-2, a first CQS node charging circuit 230-1, a second CQS node charging circuit 230-2, a third CQS node charging circuit 230-3, a QB node control circuit 240, a CQ node boost circuit 250, a carry output circuit 260, a gate output circuit, and a CQS node discharging circuit 280. In an embodiment, the transistors included in stage 200 may be NMOS transistors. However, the inventive concept is not limited thereto.

[0067] CQ node charging circuit 210 can provide the previous carry signal CR[N-1] and the second high gate voltage VGH2 to CQ node NCQ in response to the previous carry signal CR[N-1].

[0068] The CQ node charging circuit 210 may include a first-first transistor T1-1 and a first-second transistor T1-2. The first-first transistor T1-1 may include a gate electrode for receiving the previous carry signal CR[N-1], a first electrode for receiving the previous carry signal CR[N-1], and a second electrode for receiving the second high gate voltage VGH2. The first-second transistor T1-2 may include a gate electrode for receiving the previous carry signal CR[N-1], a first electrode for receiving the second high gate voltage VGH2, and a second electrode connected to the CQ node NCQ.

[0069] The first CQ node discharge circuit 220-1 can provide a second low gate voltage VGL2 to the CQ node NCQ in response to the next carry signal CR[N+1].

[0070] The first CQ node discharge circuit 220-1 may include second transistors T2-1 and T2-2. The second transistors T2-1 and T2-2 may include a gate electrode for receiving the next carry signal CR[N+1], a first electrode for receiving a second low gate voltage VGL2, and a second electrode connected to the CQ node NCQ. In an embodiment, the second transistors T2-1 and T2-2 may include a second-first transistor T2-1 and a second-second transistor T2-2 connected in series with their gate electrodes connected to each other.

[0071] The second CQ node discharge circuit 220-2 can provide a second low gate voltage VGL2 to the CQ node NCQ in response to the voltage of the QB node NQB.

[0072] The second CQ node discharge circuit 220-2 may include third transistors T3-1 and T3-2. The third transistors T3-1 and T3-2 may include a gate electrode connected to the QB node NQB, a first electrode receiving a second low gate voltage VGL2, and a second electrode connected to the CQ node NCQ. In an embodiment, the third transistors T3-1 and T3-2 may include a third-first transistor T3-1 and a third-second transistor T3-2 connected in series with their gate electrodes connected to each other.

[0073] As used herein, a CQ node (NCQ) can refer to a node in the gate driver stage that receives and stores voltage in response to a previous carry signal and is used to control the generation of the gate signal; a CQS node (NCQS) can refer to a control node in the gate output circuit that receives a high voltage in response to a carry signal or a boost node voltage and transmits the CQ node voltage to the gate output node; and a QB node can refer to a QB node that maintains an inverted voltage based on the CQ node; and a QB node (NQB) is used to discharge the CQ node, the CQS node, and related nodes and circuits.

[0074] The first CQS node charging circuit 230-1 can provide the second high gate voltage VGH2 to the CQS node NCQS in response to the previous carry signal CR[N-1].

[0075] The first CQS node charging circuit 230-1 may include fourth transistors T4-1 and T4-2. The fourth transistors T4-1 and T4-2 may include a gate electrode receiving the previous carry signal CR[N-1], a first electrode receiving the second high gate voltage VGH2, and a second electrode connected to the CQS node NCQS. In an embodiment, the fourth transistors T4-1 and T4-2 may include a fourth-first transistor T4-1 and a fourth-second transistor T4-2 connected in series with their gate electrodes connected to each other.

[0076] The second CQS node charging circuit 230-2 can provide a first high gate voltage VGH1 to the CQS node NCQS in response to the voltage VNBCR of the boost node NBCR.

[0077] The second CQS node charging circuit 230-2 may include a fifth transistor T5. The fifth transistor T5 may include a gate electrode that receives the voltage VNBCR of the boost node NBCR, a first electrode that receives the first high gate voltage VGH1, and a second electrode connected to the CQS node NCQS.

[0078] The third CQS node charging circuit 230-3 can provide the first high gate voltage VGH1 to the CQS node NCQS in response to the next carry signal CR[N+1].

[0079] The third CQS node charging circuit 230-3 may include a sixth transistor T6. The sixth transistor T6 may include a control electrode that receives the next carry signal CR[N+1], a first electrode that receives the first high gate voltage VGH1, and a second electrode connected to the CQS node NCQS.

[0080] The QB node control circuit 240 can invert the voltage of the CQ node NCQ and provide the inverted voltage of the CQ node NCQ to the QB node NQB.

[0081] QB node control circuit 240 may include seventh transistors T7-1 and T7-2, eighth transistor T8, ninth transistor T9, and tenth transistor T10. Seventh transistors T7-1 and T7-2 may include a gate electrode receiving a first high gate voltage VGH1, a first electrode receiving the first high gate voltage VGH1, and a second electrode. In an embodiment, seventh transistors T7-1 and T7-2 may include a seventh-first transistor T7-1 and a seventh-second transistor T7-2 connected in series with their gate electrodes connected to each other. Eighth transistor T8 may include a second electrode connected to seventh transistors T7-1 and T7-2, a first electrode receiving the first high gate voltage VGH1, and a second electrode connected to QB node NQB. Ninth transistor T9 may include a gate electrode connected to CQ node NCQ, a first electrode receiving a first low gate voltage VGL1, and a second electrode connected to the second electrodes of seventh transistors T7-1 and T7-2 and the gate electrode of eighth transistor T8. The tenth transistor T10 may include a gate electrode connected to the CQ node NCQ, a first electrode receiving a second low gate voltage VGL2, and a second electrode connected to the QB node NQB.

[0082] The CQ node boost circuit 250 can provide a boost clock signal BCK to the boost node NBCR in response to the voltage of the CQ node NCQ, and can provide a second low gate voltage VGL2 to the boost node NBCR in response to the voltage of the QB node NQB.

[0083] The CQ node boost circuit 250 may include an eleventh transistor T11, a twelfth transistor T12, and a CQ boost capacitor CBST_CQ. The eleventh transistor T11 may include a gate electrode connected to the CQ node NCQ, a first electrode receiving the boost clock signal BCK, and a second electrode connected to the boost node NBCR. The twelfth transistor T12 may include a gate electrode connected to the QB node NQB, a first electrode receiving the second low gate voltage VGL2, and a second electrode connected to the boost node NBCR. The CQ boost capacitor CBST_CQ may include a first electrode connected to the CQ node NCQ and a second electrode connected to the boost node NBCR.

[0084] The carry output circuit 260 can output a carry clock signal CR_CK as a carry signal CR[N] in response to the voltage of the CQ node NCQ, and can output a second low gate voltage VGL2 as a carry signal CR[N] in response to the voltage of the QB node NQB.

[0085] The carry output circuit 260 may include a carry variable conduction transistor VOT_CR, a thirteenth transistor T13, and a fourteenth transistor T14. The carry variable conduction transistor VOT_CR may include a gate electrode connected to the CQS node NCQS, a first electrode connected to the CQ node NCQ, and a second electrode connected to the carry Q node NQ_CR. The thirteenth transistor T13 may include a gate electrode connected to the carry Q node NQ_CR, a first electrode receiving the carry clock signal CR_CK, and a second electrode connected to the carry node NCR that outputs the carry signal CR[N]. The fourteenth transistor T14 may include a gate electrode connected to the QB node NQB, a first electrode receiving the second low gate voltage VGL2, and a second electrode connected to the carry node NCR.

[0086] The gate output circuit may include a first gate output circuit to a Pth gate output circuit that outputs a first gate signal to a Pth gate signal.

[0087] The P-gate output circuit may include a P-gate variable conduction transistor, a fifteenth-Pth transistor, a sixteenth-Pth transistor, and a P-gate boost capacitor. The P-gate variable conduction transistor may include a gate electrode connected to the CQS node NCQS, a first electrode connected to the CQ node NCQ, and a second electrode connected to the P-gate Q node. The fifteenth-Pth transistor may include a gate electrode connected to the P-gate Q node, a first electrode receiving the P-gate clock signal, and a second electrode connected to the P-gate node outputting the P-gate signal. The sixteenth-Pth transistor may include a gate electrode connected to the QB node NQB, a first electrode receiving a first low gate voltage VGL1, and a second electrode connected to the P-gate node. The P-gate boost capacitor may include a first electrode connected to the P-gate Q node and a second electrode connected to the boost node NBCR.

[0088] In this embodiment, P can be 6. Therefore, the gate output circuit may include a first gate output circuit 270-1 to a sixth gate output circuit 270-6 that outputs a first gate signal GS1[N] to a sixth gate signal GS6[N].

[0089] For example, the first gate output circuit 270-1 can output a first gate clock signal GS_CK1[N] as a first gate signal GS1[N] in response to the voltage of the CQ node NCQ, and can output a first low gate voltage VGL1 as a first gate signal GS1[N] in response to the voltage of the QB node NQB.

[0090] The first gate output circuit 270-1 may include a first gate variable conduction transistor VOT_GS1, a fifteenth-first transistor T15-1, a sixteenth-first transistor T16-1, and a first gate boost capacitor CBST_GS1. The first gate variable conduction transistor VOT_GS1 may include a gate electrode connected to the CQS node NCQS, a first electrode connected to the CQ node NCQ, and a second electrode connected to the first gate Q node NQ_GS1. The fifteenth-first transistor T15-1 may include a gate electrode connected to the first gate Q node NQ_GS1, a first electrode receiving the first gate clock signal GS_CK1[N], and a second electrode connected to the first gate node NGS1 that outputs the first gate signal GS1[N]. The sixteenth-first transistor T16-1 may include a gate electrode connected to the QB node NQB, a first electrode receiving the first low gate voltage VGL1, and a second electrode connected to the first gate node NGS1. The first gate boost capacitor CBST_GS1 may include a first electrode connected to the first gate Q node NQ_GS1 and a second electrode connected to the boost node NBCR.

[0091] For example, the second gate output circuit can output a second gate clock signal GS_CK2[N] (see Figure 5) as a second gate signal in response to the voltage of the CQ node NCQ, and can output a first low gate voltage VGL1 as a second gate signal in response to the voltage of the QB node NQB.

[0092] The second gate output circuit may include a second gate variable conduction transistor, a fifteenth-second transistor, a sixteenth-second transistor, and a second gate boost capacitor. The second gate variable conduction transistor may include a gate electrode connected to the CQS node NCQS, a first electrode connected to the CQ node NCQ, and a second electrode connected to the second gate Q node. The fifteenth-second transistor may include a gate electrode connected to the second gate Q node, a first electrode receiving the second gate clock signal GS_CK2[N], and a second electrode connected to the second gate node outputting the second gate signal. The sixteenth-second transistor may include a gate electrode connected to the QB node NQB, a first electrode receiving the first low gate voltage VGL1, and a second electrode connected to the second gate node. The second gate boost transistor may include a first electrode connected to the second gate Q node and a second electrode connected to the boost node NBCR.

[0093] For example, the third gate output circuit can output the third gate clock signal GS_CK3[N] (see Figure 5) as the third gate signal in response to the voltage of the CQ node NCQ, and can output the first low gate voltage VGL1 as the third gate signal in response to the voltage of the QB node NQB.

[0094] The third gate output circuit may include a third gate variable conduction transistor, a fifteenth-third transistor, a sixteenth-third transistor, and a third gate boost capacitor. The third gate variable conduction transistor may include a gate electrode connected to the CQS node NCQS, a first electrode connected to the CQ node NCQ, and a second electrode connected to the third gate Q node. The fifteenth-third transistor may include a gate electrode connected to the third gate Q node, a first electrode receiving the third gate clock signal GS_CK3[N], and a second electrode connected to the third gate node, from which the third gate signal is output. The sixteenth-third transistor may include a gate electrode connected to the QB node NQB, a first electrode receiving a first low gate voltage VGL1, and a second electrode connected to the third gate node. The third gate boost capacitor may include a first electrode connected to the third gate Q node and a second electrode connected to the boost node NBCR.

[0095] For example, the fourth gate output circuit can output the fourth gate clock signal GS_CK4[N] (see Figure 5) as the fourth gate signal in response to the voltage of the CQ node NCQ, and can output the first low gate voltage VGL1 as the fourth gate signal in response to the voltage of the QB node NQB.

[0096] The fourth gate output circuit may include a fourth gate variable conduction transistor, a fifteenth-fourth transistor, a sixteenth-fourth transistor, and a fourth gate boost capacitor. The fourth gate variable conduction transistor may include a gate electrode connected to the CQS node NCQS, a first electrode connected to the CQ node NCQ, and a second electrode connected to the fourth gate Q node. The fifteenth-fourth transistor may include a gate electrode connected to the fourth gate Q node, a first electrode receiving the fourth gate clock signal GS_CK4[N], and a second electrode connected to the fourth gate node outputting the fourth gate signal. The sixteenth-fourth transistor may include a gate electrode connected to the QB node NQB, a first electrode receiving a first low gate voltage VGL1, and a second electrode connected to the fourth gate node. The fourth gate boost transistor may include a first electrode connected to the fourth gate Q node and a second electrode connected to the boost node NBCR.

[0097] For example, the fifth gate output circuit can output the fifth gate clock signal GS_CK5[N] (see Figure 5) as the fifth gate signal in response to the voltage of the CQ node NCQ, and can output the first low gate voltage VGL1 as the fifth gate signal in response to the voltage of the QB node NQB.

[0098] The fifth gate output circuit may include a fifth gate variable conduction transistor, a fifteenth-fifth transistor, a sixteenth-fifth transistor, and a fifth gate boost capacitor. The fifth gate variable conduction transistor may include a gate electrode connected to the CQS node NCQS, a first electrode connected to the CQ node NCQ, and a second electrode connected to the fifth gate Q node. The fifteenth-fifth transistor may include a gate electrode connected to the fifth gate Q node, a first electrode receiving the fifth gate clock signal GS_CK5[N], and a second electrode connected to the fifth gate node, from which the fifth gate signal is output. The sixteenth-fifth transistor may include a gate electrode connected to the QB node NQB, a first electrode receiving the first low gate electrode VGL1, and a second electrode connected to the fifth gate node. The fifth gate boost capacitor may include a first electrode connected to the fourth gate Q node and a second electrode connected to the boost node NBCR.

[0099] For example, the sixth gate output circuit 270-6 can output the sixth gate clock signal GS_CK6[N] as the sixth gate signal GS6[N] in response to the voltage of the CQ node NCQ, and can output the first low gate voltage VGL1 as the sixth gate signal GS6[N] in response to the voltage of the QB node NQB.

[0100] The sixth gate output circuit 270-6 may include a sixth gate variable conduction transistor VOT_GS6, a fifteenth-sixth transistor T15-6, a sixteenth-sixth transistor T16-6, and a sixth gate boost capacitor CBST_GS6. The sixth gate variable conduction transistor VOT_GS6 may include a gate electrode connected to the CQS node NCQS, a first electrode connected to the CQ node NCQ, and a second electrode connected to the sixth gate Q node NQ_GS6. The fifteenth-sixth transistor T15-6 may include a gate electrode connected to the sixth gate Q node NQ_GS6, a first electrode receiving the sixth gate clock signal GS_CK6[N], and a second electrode connected to the sixth gate node NGS6, from which the sixth gate signal GS6[N] is output. The sixteenth-sixth transistor T16-6 may include a gate electrode connected to the QB node NQB, a first electrode receiving a first low gate voltage VGL1, and a second electrode connected to the sixth gate node NGS6. The sixth gate boost capacitor CBST_GS6 may include a first electrode connected to the sixth gate Q node NQ_GS6 and a second electrode connected to the boost node NBCR.

[0101] The CQS node discharge circuit 280 can provide a first low gate voltage VGL1 to the CQS node NCQS in response to the voltage of the QB node NQB.

[0102] The CQS node discharge circuit 280 may include nineteenth transistors T19-1 and T19-2. Nineteenth transistors T19-1 and T19-2 may include a gate electrode connected to the QB node NQB, a first electrode receiving a first low gate voltage VGL1, and a second electrode connected to the CQS node NCQS. In an embodiment, nineteenth transistors T19-1 and T19-2 may include a nineteenth-first transistor T19-1 and a nineteenth-second transistor T19-2 connected in series with their gate electrodes connected to each other.

[0103] For example, the second low gate voltage VGL2 can be approximately -10V, the first low gate voltage VGL1 can be approximately -5V, the first high gate voltage VGH1 can be approximately 15V, and the second high gate voltage VGH2 can be approximately 25V. Low levels can include the second low gate voltage VGL2 and the first low gate voltage VGL1. High levels can include the first high gate voltage VGH1 and the second high gate voltage VGH2.

[0104] Figure 5 is a timing diagram showing the operation of stage 200 in Figure 4. Figure 6 is a circuit diagram showing the operation of stage 200 in Figure 4 during the first duration DU1 in Figure 5. Figure 7 is a circuit diagram showing the operation of stage 200 in Figure 4 during the second duration DU2 in Figure 5. Figure 8 is a circuit diagram showing the operation of stage 200 in Figure 4 during the third duration DU3 in Figure 5. Figure 9 is a circuit diagram showing the operation of stage 200 in Figure 4 during the fourth duration DU4 in Figure 5.

[0105] Referring to Figures 5 and 6, during the first duration DU1, the previous carry signal CR[N-1] can have a second high gate voltage VGH2. In Figure 5, 1H represents a horizontal time.

[0106] The first transistor T1-1 and the first transistor T1-2 can be turned on in response to a carry-before signal CR[N-1] having a second high gate voltage VGH2. The carry-before signal CR[N-1] with the second high gate voltage VGH2 can be provided to the CQ node NCQ through the first transistor T1-1 and the first transistor T1-2. The second high gate voltage VGH2 can be provided to the CQ node NCQ through the first transistor T1-2. Therefore, the voltage of the CQ node NCQ can have the second high gate voltage VGH2.

[0107] The fourth transistors T4-1 and T4-2 can be turned on in response to a carry signal CR[N-1] with a second high gate voltage VGH2, to provide the second high gate voltage VGH2 to the CQS node NCQS. The first variable conduction transistors VOT_GS1 to the sixth gate variable conduction transistor VOT_GS6 can have large dimensions and can form parasitic capacitance between the gate electrode and the first electrode. Due to the effect of parasitic capacitance, the voltage of the CQS node NCQS may be higher than the second high gate voltage VGH2. For example, the voltage of the CQS node NCQS may be 30V.

[0108] The first variable conduction transistor VOT_GS1 to the sixth gate variable conduction transistor VOT_GS6 can be turned on in response to the voltage of the CQ node NCQ and the voltage of the CQS node NCQS. Therefore, the first variable conduction transistor VOT_GS1 to the sixth gate variable conduction transistor VOT_GS6 can provide the voltage of the CQ node NCQ to the first gate Q node NQ_GS1 to the sixth gate Q node NQ_GS6.

[0109] Referring to Figures 5 and 7, during the second duration DU2, the eleventh transistor T11 can be turned on in response to the voltage of the CQ node NCQ with a second high gate voltage VGH2 to provide the boost clock signal BCK to the boost node NBCR. Therefore, the voltage VNBCR of the boost node NBCR can change from the second low gate voltage VGL2 to the second high gate voltage VGH2.

[0110] When the voltage VNBCR of the boost node NBCR changes, the voltage of the CQ node NCQ can be bootstrapped by the CQ boost capacitor CBST_CQ. The voltage of the CQS node NCQS can be bootstrapped by the parasitic capacitances of the first variable conduction transistor VOT_GS1 to the sixth gate variable conduction transistor VOT_GS6. The voltages of the first gate Q node NQ_GS1 to the sixth gate Q node NQ_GS6 can be bootstrapped by the first gate boost capacitor CBST_GS1 to the sixth gate boost capacitor GBST_GS6.

[0111] The fifth transistor T5 can be turned on in response to the voltage VNBCR of the boost node NBCR to provide a first high gate voltage VGH1 to the CQS node NCQS. Therefore, the voltage of the CQS node NCQS can have a first high gate voltage VGH1.

[0112] The first variable on-state transistor VOT_GS1 to the sixth variable on-state transistor VOT_GS6 can be turned off in response to the voltage of the CQ node NCQ and the voltage of the CQS node NCQS.

[0113] Referring to Figures 5 and 8, during the third duration DU3, each of the fifteenth-first transistor T15-1 to the fifteenth-sixth transistor T15-6 can be turned on to provide each of the first gate clock signal GS_CK1[N] to the sixth gate clock signal GS_CK6[N] to the first gate node NGS1 to the sixth gate node NGS6. Therefore, the first gate signal GS1[N] to the sixth gate signal GS6[N] can be output sequentially.

[0114] The fifteenth-first transistor T15-1 to the fifteenth-sixth transistor T15-6 can have a large size and can form a parasitic capacitance between the gate electrode and the first electrode. The first gate clock signal GS_CK1[N] to the sixth gate clock signal GS_CK6[N] can be changed from the first low gate voltage VGL1 to the second high gate voltage VGH2.

[0115] When the first gate clock signal GS_CK1[N] to the sixth gate clock signal GS_CK6[N] change, the voltages of the first gate Q node NQ_GS1 to the sixth gate Q node NQ_GS6 can be bootstrapped by parasitic capacitance. Therefore, the fifteenth-first transistor T15-1 to the fifteenth-sixth transistor T15-6 can be fully turned on. In this case, since the voltages of the first gate Q node NQ_GS1 to the sixth gate Q node NQ_GS6 bootstrap during the duration of a high level at the voltage VNBCR of the boost node NBCR, the pulse of each of the first gate signal GS1[N] to the sixth gate signal GS6[N] can be included within the duration of a high level at the voltage VNBCR of the boost node NBCR. Furthermore, the duration of a high level at the voltage VNBCR of the boost node NBCR can be included within the duration of a high level at the voltage of the CQ node NCQ.

[0116] Referring to Figures 5 and 9, during the fourth duration DU4, the next carry signal CR[N+1] can have a second high gate voltage VGH2.

[0117] The second transistors T2-1 and T2-2 can be turned on in response to the next carry signal CR[N+1] having a second high gate voltage VGH2, so as to provide a second low gate voltage VGL2 to the CQ node NCQ. Therefore, the voltage of the CQ node NCQ can have a second low gate voltage VGL2.

[0118] The ninth transistor T9 and the tenth transistor T10 can be turned off in response to the voltage of the CQ node NCQ having a second low gate voltage VGL2. The seventh-first transistor T7-1 and the seventh-second transistor T7-2 can be turned on in response to a first high gate voltage VGH1 to provide the first high gate voltage VGH1 to the gate electrode of the eighth transistor T8. Therefore, the voltage at the gate electrode of the eighth transistor T8 can have the first high gate voltage VGH1, the eighth transistor T8 can be turned on, and the eighth transistor T8 can provide the first high gate voltage VGH1 to the QB node NQB. Therefore, the voltage at the QB node NQB can have the first high gate voltage VGH1.

[0119] Nineteenth transistors T19-1 and T19-2 can be turned on in response to the voltage of the QB node NQB having a first high gate voltage VGH1, so as to provide a first low gate voltage VGL1 to the CQS node NCQS. Therefore, the voltage of the CQS node NCQS can have a first low gate voltage VGL1.

[0120] Figures 10 and 11 are conceptual diagrams explaining the number of clock signals.

[0121] Referring to Figures 1 through 11, P can be 6. That is, a stage can use six gate clock signals to output six gate signals. However, stages can collectively utilize more than six gate clock signals to operate correctly. For example, the total number of gate clock signals used across all stages can be twice the number of gate signals output by a single stage. For example, when a stage uses 6 gate clock signals, the total number of gate clock signals across stages can be 12. In this case, the unused space of the gate driver 130 may increase.

[0122] To address this issue, consecutive gate signals can overlap. This configuration reduces the total number of gate clock signals used across stages. In this case, minimizing the total number of gate clock signals may become beneficial. That is, achieving a minimum Q value allows for a more compact gate driver design.

[0123] For example, P can be 6, and Q can be 8. The pulses of each of the first gate signals GS1[N] to the sixth gate signals GS6[N] of stage 200 can be included in the duration during which the voltage VNBCR of the boost node NBCR is high. Furthermore, the duration during which the voltage VNBCR of the boost node NBCR is high can be included in the duration during which the voltage of the CQ node NCQ is high.

[0124] In Figure 10, for simplicity, the first level time H1 to the thirtieth level time H30 are shown as "1" to "30". For example, in the first stage STG1, the voltage of the CQ node NCQ1 can be high during the first level time H1 to the twelfth level time H12. The voltage of the boost node NBCR1 can be high during the third level time H3 to the eleventh level time H11. The first gate signal GS1 to the sixth gate signal GS6 can be output sequentially during the fourth level time H4 to the tenth level time H10.

[0125] For example, in the second stage STG2, the voltage of the CQ node NCQ2 can be high from the seventh level time H7 to the eighteenth level time H18. The voltage of the boost node NBCR2 can be high from the ninth level time H9 to the seventeenth level time H17. The seventh gate signal GS7 to the twelfth gate signal GS12 can be sequentially output from the tenth level time H10 to the sixteenth level time H16.

[0126] For example, in the third stage STG3, the voltage of the CQ node NCQ3 can be high from the thirteenth level time H13 to the twenty-fourth level time H24. The voltage of the boost node NBCR3 can be high from the fifteenth level time H15 to the twenty-third level time H23. The thirteenth gate signal GS13 to the eighteenth gate signal GS18 can be sequentially output from the sixteenth level time H16 to the twenty-second level time H22.

[0127] For example, in the fourth stage, the voltage of the CQ node NCQ4 can be high from the nineteenth level time H19 to the thirtieth level time H30. The voltage of the boost node NBCR4 can be high from the twenty-first level time H21 to the twenty-ninth level time H29. The nineteenth gate signal GS19 to the twenty-fourth gate signal GS24 can be sequentially output from the twenty-second level time H22 to the twenty-eighth level time H28.

[0128] The gate driver 130 can sequentially output gate signals during the frame duration. However, in order for the gate driver 130 to function properly, it should not output gate signals that have already been output.

[0129] For example, during the fourth level time H4 to the fifth level time H5, the first gate signal GS1 is output based on the first gate clock signal GS_CK1. However, when the ninth gate signal GS9 is output based on the first gate clock signal GS_CK1 during the twelfth level time H12 to the thirteenth level time H13, the voltage of the CQ node NCQ1 of the first stage may still be high. Therefore, the first gate signal GS1 can also be output during the twelfth level time H12 to the thirteenth level time H13. This problem may also occur with the seventh gate signal GS7, the thirteenth gate signal GS13, and so on.

[0130] Referring to Figures 1 to 9 and Figure 11, P can be 6 and Q can be 10.

[0131] In Figure 11, for simplicity, the first level time H1 to the thirty-sixth level time H36 are shown as "1" to "36". For example, in the first stage STG1, the voltage of the CQ node NCQ1 can be high during the first level time H1 to the twelfth level time H12. The voltage of the boost node NBCR1 can be high during the third level time H3 to the eleventh level time H11. The first gate signal GS1 to the sixth gate signal GS6 can be output sequentially during the fourth level time H4 to the tenth level time H10.

[0132] For example, in the second stage STG2, the voltage of the CQ node NCQ2 can be high from the seventh level time H7 to the eighteenth level time H18. The voltage of the boost node NBCR2 can be high from the ninth level time H9 to the seventeenth level time H17. The seventh gate signal GS7 to the twelfth gate signal GS12 can be sequentially output from the tenth level time H10 to the sixteenth level time H16.

[0133] For example, in the third stage STG3, the voltage of the CQ node NCQ3 can be high from the thirteenth level time H13 to the twenty-fourth level time H24. The voltage of the boost node NBCR3 can be high from the fifteenth level time H15 to the twenty-third level time H23. The thirteenth gate signal GS13 to the eighteenth gate signal GS18 can be sequentially output from the sixteenth level time H16 to the twenty-second level time H22.

[0134] For example, in the fourth stage, the voltage of the CQ node NCQ4 can be high from the nineteenth level time H19 to the twenty-ninth level time H29. The voltage of the boost node NBCR4 can be high from the twenty-first level time H21 to the thirtieth level time H30. The nineteenth gate signal GS19 to the twenty-fourth gate signal GS24 can be output sequentially from the twenty-second level time H22 to the twenty-eighth level time H28.

[0135] For example, in the fifth stage, the voltage of the CQ node NCQ5 can be high from the 25th level time H25 to the 36th level time H36. The voltage of the boost node NBCR5 can be high from the 27th level time H27 to the 35th level time H35. The 25th gate signal GS25 to the 30th gate signal GS30 can be sequentially output from the 28th level time H28 to the 34th level time H34.

[0136] The gate driver 130 can sequentially output gate signals during the frame duration. However, in order for the gate driver 130 to function properly, it should not output gate signals that have already been output.

[0137] For example, during the fourth level time H4 to the fifth level time H5, the first gate signal GS1 is output based on the first gate clock signal GS_CK1. When the ninth gate signal GS9 is output based on the ninth gate clock signal GS_CK9 during the twelfth level time H12 to the thirteenth level time H13, the voltage of the CQ node NCQ1 of the first stage can still be high. However, since the first stage does not receive the ninth gate clock signal GS_CK9, the operation of the first stage can be normal. When the tenth gate signal GS10 is output based on the tenth gate clock signal GS_CK10 during the thirteenth level time H13 to the fourteenth level time H14, the voltage of the CQ node NCQ1 of the first stage can be low. Alternatively, the first stage can also not receive the tenth gate clock signal GS_CK10. Therefore, the operation of the first stage can be normal. When the eleventh gate signal GS11 is output based on the first gate clock signal GS_CK1 during the fourteenth level time H14 to the fifteenth level time H15, the voltage of the CQ node NCQ1 of the first stage can be low. Furthermore, when the voltage of CQ node NCQ1 is low, transistors 15-1 to 15-6 can be turned off. Therefore, even if the first stage receives the first gate clock signal GS_CK1, the operation of the first stage can be normal. In other words, Q can be the minimum of the following Q values ​​that satisfy the condition that the duration of the 14th level time H14 to the 15th level time H15, in which the duration of the 11th gate signal GS11 outputting the second stage is separated from the duration in which the voltage of CQ node NCQ1 of the first stage is high.

[0138] The operation can also be applied to the second, third, fourth, and fifth levels.

[0139] Thus, in the gate driver 130 and the display device 10, Q can be the minimum of the Q values ​​that satisfy the condition that the duration of the Q+1th gate signal of the second stage output is separate from the duration of the high-level voltage of the CQ node NCQ1 of the first stage. Therefore, the unused space of the gate driver 130 can be reduced.

[0140] Figure 12 is a block diagram illustrating electronic device 1000. Figure 13 is a diagram illustrating an embodiment in which electronic device 1000 of Figure 12 is implemented as a smartphone.

[0141] Referring to Figures 12 and 13, electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be the display device 100 of Figure 1. Furthermore, electronic device 1000 may also include multiple ports for communicating with, for example, video cards, sound cards, memory cards, Universal Serial Bus (USB) devices, and other electrical devices.

[0142] In an embodiment, as shown in FIG13, the electronic device 1000 can be implemented as a smartphone. However, the electronic device 1000 is not limited to this. For example, the electronic device 1000 can be implemented as a cellular phone, video phone, smart tablet, smartwatch, tablet PC, car navigation system, computer monitor, laptop computer, and head-mounted display (HMD) device, etc.

[0143] Processor 1010 can perform various computing functions. Processor 1010 can be a microprocessor, central processing unit (CPU), application processor (AP), etc. Processor 1010 can be coupled to other components via, for example, address bus, control bus, and data bus. In addition, processor 1010 can also be coupled to an expansion bus (such as a peripheral component interconnect (PCI) bus).

[0144] The memory device 1020 can store data for the operation of the electronic device 1000. For example, the memory device 1020 may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device, and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile DRAM device.

[0145] Storage device 1030 may include solid-state drive (SSD) devices, hard disk drive (HDD) devices, and read-only optical disc (CD-ROM) devices, etc.

[0146] I / O device 1040 may include input devices such as a keyboard, keypad, mouse, touchpad, and touchscreen, as well as output devices such as a printer and speaker. In some embodiments, I / O device 1040 may include display device 1060.

[0147] Power supply 1050 can provide power for the operation of electronic device 1000.

[0148] The display device 1060 can be connected to other components via a bus or other communication link.

[0149] This invention can be applied to any display device and any electronic device, including touch panels. For example, it can be applied to mobile phones, smartphones, tablet computers, digital televisions (TVs), 3D TVs, personal computers (PCs), home appliances, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, etc.

[0150] While this disclosure has been specifically shown and described with reference to embodiments of the inventive concept, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims

1. A gate driver, wherein, The gate driver includes multiple stages, each of which includes: a CQ node charging circuit configured to provide a previous carry signal and a second high gate voltage to the CQ node in response to a previous carry signal; a first CQS node charging circuit configured to provide the second high gate voltage to the CQS node in response to the previous carry signal; a second CQS node charging circuit configured to provide a first high gate voltage to the CQS node in response to the voltage of the boost node; and a QB node control circuit configured to charge the CQ node... The voltage is inverted to provide the inverted voltage of the CQ node to the QB node; the CQ node boost circuit is configured to: provide a boost clock signal to the boost node in response to the voltage of the CQ node, and provide a second low gate voltage to the boost node in response to the voltage of the QB node; and the gate output circuit is configured to: output a first gate clock signal to the Pth gate clock signal as a first gate signal to the Pth gate signal in response to the voltage of the CQ node, and output a first low gate voltage as a first gate signal to the Pth gate signal in response to the voltage of the QB node. The first gate signal to the Pth gate signal, where P is a positive integer greater than 2, wherein the pulse of each of the first gate signal to the Pth gate signal is included in the duration during which the voltage of the boost node has a high level, and the duration during which the voltage of the boost node has a high level is included in the duration during which the voltage of the CQ node has a high level, wherein the plurality of stages receive the first gate clock signal to the Qth gate clock signal, where Q is a positive integer greater than P, and wherein when the first stage of the plurality of stages is configured to output the first gate clock signal to the Pth gate clock signal as the first gate signal to the Pth gate signal, the second stage of the plurality of stages is configured to output the P+1th gate clock signal to the Qth gate clock signal as the P+1th gate signal to the Qth gate signal, and then the second stage is configured to output the first gate clock signal as the Q+1th gate signal, the duration of outputting the Q+1th gate signal is separate from the duration during which the voltage of the CQ node of the first stage has a high level.

2. The gate driver according to claim 1, wherein, Q is a multiple of 2.

3. The gate driver according to claim 1, wherein, Q is the minimum value that satisfies the condition that the duration of the second stage being configured to output the Q+1th gate signal is separate from the duration of the voltage of the CQ node of the first stage having the high level.

4. The gate driver according to claim 1, wherein, The gate driver is configured to support a two-wire gate mode, and while the gate driver is configured to execute the two-wire gate mode, the pulse duration of each of the first gate clock signal to the Qth gate clock signal is reduced.

5. The gate driver according to claim 1, wherein, P is 6 and Q is 10.

6. The gate driver according to claim 1, wherein, The CQ node charging circuit includes: a first-first transistor, comprising: a gate electrode for receiving the previous carry signal, a first electrode for receiving the previous carry signal, and a second electrode for receiving the second high gate voltage; and a first-second transistor, comprising: a gate electrode for receiving the previous carry signal, a first electrode for receiving the second high gate voltage, and a second electrode connected to the CQ node.

7. The gate driver according to claim 1, wherein, The first CQS node charging circuit includes a first transistor, the first transistor including a gate electrode for receiving the previous carry signal, a first electrode for receiving the second high gate voltage, and a second electrode connected to the CQS node, and wherein the second CQS node charging circuit includes a second transistor, the second transistor including a gate electrode for receiving the voltage of the boost node, a first electrode for receiving the first high gate voltage, and a second electrode connected to the CQS node.

8. The gate driver according to claim 1, wherein, The QB node control circuit includes: a first transistor, including a gate electrode receiving the first high gate voltage, a first electrode receiving the first high gate voltage, and a second electrode; a second transistor, including a gate electrode connected to the second electrode of the first transistor, a first electrode receiving the first high gate voltage, and a second electrode connected to the QB node; a third transistor, including a gate electrode connected to the CQ node, a first electrode receiving the first low gate voltage, and a second electrode connected to the second electrode of the first transistor and the gate electrode of the second transistor; and a fourth transistor, including a gate electrode connected to the CQ node, a first electrode receiving the second low gate voltage, and a second electrode connected to the QB node.

9. The gate driver according to claim 1, wherein, The CQ node boost circuit includes: a first transistor, including a gate electrode connected to the CQ node, a first electrode receiving the boost clock signal, and a second electrode connected to the boost node; a second transistor, including a gate electrode connected to the QB node, a first electrode receiving the second low gate voltage, and a second electrode connected to the boost node; and a CQ boost capacitor, including a first electrode connected to the CQ node and a second electrode connected to the boost node.

10. The gate driver according to claim 1, wherein, The gate output circuit includes a first gate output circuit to a P-th gate output circuit, the first gate output circuit to the P-th gate output circuit being configured to output the first gate signal to the P-th gate signal, and wherein the P-th gate output circuit includes: a P-th gate variable conduction transistor, including a gate electrode connected to the CQS node, a first electrode connected to the CQ node, and a second electrode connected to the P-th gate Q node; a first-P-th transistor, including a gate electrode connected to the P-th gate Q node, a first electrode receiving the P-th gate clock signal, and a second electrode connected to the P-th gate node, the P-th gate signal being output from the P-th gate node; a second-P-th transistor, including a gate electrode connected to the QB node, a first electrode receiving the first low gate voltage, and a second electrode connected to the P-th gate node; and a P-th gate boost capacitor, including a first electrode connected to the P-th gate Q node and a second electrode connected to the boost node.

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