Shift register unit and driving method thereof, gate driving circuit, liquid crystal display device and image display method

Abstract

The embodiment of the invention provides a shift register unit and a driving method thereof, a gate driving circuit, a liquid crystal display device and an image display method, relates to the technical field of display, and aims to improve the refresh rate of the liquid crystal display device. The shift register unit comprises a driving sub-circuit and a first reset circuit. The driving sub-circuit is connected with the first scanning output end. The driving sub-circuit is configured to provide a first scanning signal to the first scanning output end. And the first reset circuit is connected with a reset signal end, a first scanning output end and a pull-down node of the driving sub-circuit. The first reset circuit is configured to respond to a reset signal transmitted by a reset signal end and transmit the reset signal to the first scanning output end. Wherein the moment when the reset signal is transmitted to the first scanning output end is later than the moment when the first scanning signal is transmitted to the first scanning output end. The invention discloses a shift register unit and a driving method thereof, a gate driving circuit and a liquid crystal display device. The image display method is used for image display.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a shift register unit and its driving method, a gate driving circuit, a liquid crystal display device, and an image display method. Background Technology

[0002] Liquid crystal displays (LCDs) are characterized by their small size, low power consumption, thinness, and lack of radiation, and have been widely used in the display field. With the development of display technology, their display quality has also been continuously improved along with advancements in manufacturing processes. Summary of the Invention

[0003] The purpose of the embodiments disclosed herein is to provide a shift register unit and its driving method, a gate driving circuit, a liquid crystal display device, and an image display method for improving the refresh rate of the liquid crystal display device.

[0004] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions:

[0005] Some embodiments of this disclosure provide a shift register unit, the shift register unit comprising: a driver sub-circuit and a first reset circuit. The driver sub-circuit is connected to a first scan output terminal. The driver sub-circuit is configured to provide a first scan signal to the first scan output terminal. The first reset circuit is connected to a reset signal terminal, the first scan output terminal, and a pull-down node of the driver sub-circuit. The first reset circuit is configured to transmit a reset signal to the first scan output terminal in response to a reset signal transmitted by the reset signal terminal. The timing of the transmission of the reset signal to the first scan output terminal is later than the timing of the transmission of the first scan signal to the first scan output terminal.

[0006] Some embodiments of this disclosure provide a shift register unit that, by setting a first reset circuit, and ensuring that the reset signal is transmitted to the first scan output terminal later than the first scan signal, resets the sub-pixel after the first scan signal completes scanning of the sub-pixel. This causes the liquid crystal in the sub-pixel to deflect from the target position to a preset position. As a result, during the display of the next frame of the image, the time it takes for the liquid crystal in the sub-pixel to deflect from the preset position to the corresponding target position is shorter, thus shortening the frame time. This helps to improve the refresh rate of the liquid crystal display device, alleviate dizziness during user operation, and enhance the user experience.

[0007] In some embodiments, the first reset circuit includes a first reset transistor and a second reset transistor. The control electrode of the first reset transistor is connected to the reset signal terminal, the first electrode of the first reset transistor is connected to the first scan output terminal, and the second electrode of the first reset transistor is connected to the reset signal terminal. The control electrode of the second reset transistor is connected to the reset signal terminal, the first electrode of the second reset transistor is connected to a first voltage signal terminal, and the second electrode of the second reset transistor is connected to the pull-down node of the driving sub-circuit.

[0008] In some embodiments, the driving sub-circuit is further connected to the second scan output terminal. The driving sub-circuit is also configured to provide a second scan signal to the second scan output terminal. The shift register unit further includes a second reset circuit. The second reset circuit is connected to the second scan output terminal and the reset signal terminal. The second reset circuit is configured to transmit a reset signal to the second scan output terminal in response to a reset signal transmitted from the reset signal terminal.

[0009] In some embodiments, the time at which the reset signal is transmitted to the first scan output terminal is the same as the time at which the reset signal is transmitted to the second scan output terminal.

[0010] In some embodiments, the second reset circuit includes a third reset transistor. The control electrode of the third reset transistor is connected to the reset signal terminal, the first electrode of the third reset transistor is connected to the second scan output terminal, and the second electrode of the third reset transistor is connected to the reset signal terminal.

[0011] In some embodiments, the driving sub-circuit includes a third output module. The third output module is connected to the first node, the pull-down node, the first voltage signal terminal, the fifth clock signal terminal, the second voltage signal terminal, and the second scan output terminal. The third output module is configured to, under the control of the second voltage provided by the second voltage signal terminal, transmit the potential of the first node to the second pull-up node; under the control of the potential of the pull-down node, transmit the first voltage to the second scan output terminal; and under the control of the second pull-up node, transmit the fifth clock signal provided by the fifth clock signal terminal to the second scan output terminal.

[0012] In some embodiments, the driving sub-circuit includes: an input module connected to a first clock signal terminal, an initial signal input terminal, and a first node. The input module is configured to transmit a first clock signal provided by the first clock signal terminal to the first node under the control of an initial signal provided by the initial signal input terminal. A first reset module connected to a second clock signal terminal, a first reset signal terminal, and the first node. The first reset module is configured to transmit a second clock signal provided by the second clock signal terminal to the first node under the control of a first reset signal provided by the first reset signal terminal. A second reset module connected to a second reset signal terminal, a first voltage signal terminal, and the first node. The second reset module is configured to pull down the potential of the first node to the potential of the first voltage signal terminal under the control of a second reset signal provided by the second reset signal terminal. A pull-down control module connected to a fourth clock signal terminal, the first node, the first voltage signal terminal, and a pull-down node. The pull-down control module is configured to pull down the potential of the pull-down node to the potential of the first voltage signal terminal under the control of the potential of the first node. The pull-down control module is further configured to, under the control of the fourth clock signal provided by the fourth clock signal terminal, transmit the fourth clock signal to the pull-down node, so that the pull-down node maintains a first potential, the first potential being different from the potential of the first voltage signal terminal. A first noise reduction module is connected to the first scan output terminal, the pull-down node, and the first voltage signal terminal. The first noise reduction module is configured to, under the control of the first scan signal, pull down the potential of the pull-down node to the potential of the first voltage signal terminal. A second noise reduction module is connected to the pull-down node, the first node, and the first voltage signal terminal. The second noise reduction module is configured to, under the control of the potential of the pull-down node, pull down the potential of the first node to the potential of the first voltage signal terminal. An anti-leakage module is connected to the first node, the second voltage signal terminal, and the first pull-up node. The anti-leakage module is configured to, under the control of the second voltage provided by the second voltage signal terminal, output the potential of the first node to the first pull-up node. A first output module is connected to the first pull-up node, the third clock signal terminal, and the first scan output terminal. The first output module is configured to output the third clock signal provided by the third clock signal terminal to the first scan output terminal under the control of the potential of the first pull-up node. The second output module is connected to the pull-down node, the first scan output terminal, and the first voltage signal terminal. The second output module is configured to transmit the potential of the first voltage signal terminal to the first scan output terminal under the control of the potential of the pull-down node.

[0013] Some embodiments of this disclosure also provide a driving method for a shift register unit, the shift register unit comprising: a shift register unit as described in any of the foregoing embodiments. The display phase of a frame image includes a scanning phase and a reset phase. During the scanning phase, a driving sub-circuit of the shift register unit provides a first scan signal to a first scan output terminal. During the reset phase, a reset circuit of the shift register unit provides a reset signal to the first scan output terminal.

[0014] The beneficial effects that the shift register unit driving method provided in some embodiments of this disclosure can achieve are the same as the beneficial effects that the shift register unit provided in some embodiments above can achieve, and will not be repeated here.

[0015] Some embodiments of this disclosure also provide a driving method for a shift register unit, the shift register unit comprising: an input module connected to a first clock signal terminal, an initial signal input terminal, and a first pull-up node; a first reset module connected to a second clock signal terminal, a first reset signal terminal, and the first pull-up node; and a first output module connected to the first pull-up node, a third clock signal terminal, and a first scan output terminal. The display stage of a frame image includes a scanning stage and a reset stage. During the scanning stage, the input module, in response to an initial signal provided by the initial signal input terminal, transmits a first clock signal provided by the first clock signal terminal to the first pull-up node. The first output module, in response to the potential of the first pull-up node, transmits a third clock signal provided by the third clock signal terminal as a first scan signal to the first scan output terminal. During the reset stage, the input module, in response to the initial signal provided by the initial signal input terminal, transmits a first clock signal provided by the first clock signal terminal to the first pull-up node. The first reset module, in response to a first reset signal provided by the first reset signal terminal, transmits a second clock signal provided by the second clock signal terminal to the first pull-up node. In response to the potential of the first pull-up node, the first output module transmits the third clock signal provided by the third clock signal terminal as a reset signal to the first scan output terminal.

[0016] The beneficial effects that the shift register unit driving method provided in some embodiments of this disclosure can achieve are the same as the beneficial effects that the shift register unit provided in some embodiments above can achieve, and will not be repeated here.

[0017] Some embodiments of this disclosure also provide a gate driving circuit, the gate driving circuit comprising: a plurality of cascaded shift register units as described in any of the foregoing embodiments.

[0018] The beneficial effects that the gate drive circuits provided in some embodiments of this disclosure can achieve are the same as the beneficial effects that the shift register units provided in some embodiments above can achieve, and will not be repeated here.

[0019] Some embodiments of this disclosure also provide a liquid crystal display device, the liquid crystal display device comprising: a plurality of sub-pixels arranged in multiple rows and columns; a gate driving circuit as described in any of the preceding embodiments; a plurality of shift register units in the gate driving circuit, each electrically connected to multiple rows of the sub-pixels; a plurality of data lines electrically connected to a column of the sub-pixels; and a display chip connected to the plurality of data lines.

[0020] The beneficial effects that the liquid crystal display device provided in some embodiments of this disclosure can achieve are the same as the beneficial effects that the shift register unit provided in some embodiments above can achieve, and will not be repeated here.

[0021] In some embodiments, the liquid crystal display device further includes a multiplexer. The multiplexer is connected between the display chip and the plurality of data lines.

[0022] Some embodiments of this disclosure also provide an image display method for a liquid crystal display device, the image display method being applied to the liquid crystal display device described in any of the above embodiments. The display stage of a frame image includes a scanning stage and a reset stage. The image display method includes: in the scanning stage, a gate driving circuit in the liquid crystal display device sequentially outputs a first scanning signal to each row of sub-pixels, and a display chip outputs a data signal to the sub-pixels in the corresponding row. In response to the first scanning signal and the data signal, the liquid crystal in each sub-pixel deflects to its respective target position, so that the sub-pixel displays a target grayscale. In the reset stage, the gate driving circuit outputs a reset signal to each row of sub-pixels, and the display chip outputs a data sub-signal to multiple rows of sub-pixels. In response to the reset signal and the data sub-signal, the liquid crystal in the plurality of sub-pixels deflects to a preset position. The display grayscale corresponding to the plurality of sub-pixels is a preset grayscale. The preset grayscale is greater than or equal to the target grayscale.

[0023] The beneficial effects that the image display method of the liquid crystal display device provided in some embodiments of this disclosure can achieve are the same as the beneficial effects that the shift register unit provided in some embodiments above can achieve, and will not be repeated here.

[0024] In some embodiments, the range of the preset grayscale includes G223 to G255.

[0025] In some embodiments, the liquid crystal display device further includes a multiplexer. The display chip outputs a data signal to the sub-pixel, including: the display chip outputs a data signal to the multiplexer. The multiplexer selectively transmits the data signal from the display chip to a portion of the data lines. The display chip outputs the same data sub-signal to each of the sub-pixels, including: the display chip outputs a data sub-signal to the multiplexer. The multiplexer transmits the data sub-signal from the display chip to the plurality of data lines. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are merely drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. The accompanying drawings described herein are used to provide a further understanding of this disclosure and constitute a part of this disclosure. The illustrative embodiments of this disclosure and their descriptions are used to explain this disclosure and do not constitute a limitation on the actual dimensions of the product, the actual flow of the method, the actual timing of the signals, etc., involved in the embodiments of this disclosure.

[0027] Figure 1 This is a structural diagram of a liquid crystal display device according to some embodiments of the present disclosure;

[0028] Figure 2 This is a structural diagram of another liquid crystal display device according to some embodiments of the present disclosure;

[0029] Figure 3 This is a structural diagram of a display panel according to some embodiments of the present disclosure;

[0030] Figure 4A This is a distribution diagram of the scanning and response time of each row of sub-pixels in a display panel within a frame, based on some embodiments of the related art.

[0031] Figure 4B This is a distribution diagram of the scanning and response time of each row of sub-pixels in a display panel within a frame, according to some embodiments of the present disclosure;

[0032] Figure 5 Here is an equivalent circuit diagram of a shift register unit according to some embodiments of this disclosure;

[0033] Figure 6 An equivalent circuit diagram of another shift register unit according to some embodiments of this disclosure;

[0034] Figure 7 Here is an equivalent circuit diagram of yet another shift register unit according to some embodiments of this disclosure;

[0035] Figure 8 This is a timing diagram of the gate driving circuit of a display panel according to some embodiments of the present disclosure;

[0036] Figure 9A The present disclosure provides an equivalent circuit diagram of another shift register unit according to some embodiments thereof;

[0037] Figure 9B Here is an equivalent circuit diagram of another shift register unit according to some embodiments of this disclosure;

[0038] Figure 9C The present disclosure provides an equivalent circuit diagram of another shift register unit according to some embodiments thereof;

[0039] Figure 10 This is another timing diagram of the gate driving circuit of the display panel according to some embodiments of the present disclosure;

[0040] Figure 11 The above are waveforms of the outputs of different stages of shift register units in a gate drive circuit according to some embodiments of the related art.

[0041] Figure 12 The waveforms are shown for the outputs of different stages of shift register units in a gate drive circuit according to some embodiments of the present disclosure. Detailed Implementation

[0042] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0043] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0044] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0045] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0046] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0047] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0048] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if determination…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination…”, “in response to determination…”, “in the event of detection”, or “in response to the event of detection”.

[0049] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0050] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0051] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0052] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0053] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0054] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0055] The transistors used in the circuits provided in the embodiments of this application can be thin-film transistors, field-effect transistors (e.g., oxide thin-film transistors), or other switching devices with the same characteristics. The embodiments of this application all use thin-film transistors as examples for illustration. Preferably, the thin-film transistors used in the embodiments of this disclosure can be oxide semiconductor transistors or low-temperature polycrystalline silicon (LTPS) thin-film transistors.

[0056] In this embodiment, the coupling methods of the drain and source of each transistor can be interchanged. Therefore, in this embodiment, the drain and source of each transistor are actually indistinguishable. Here, one of the two terminals of the transistor, excluding the control terminal (i.e., the gate), is called the drain, and the other is called the source. The thin-film transistor used in this embodiment can be an N-type transistor or a P-type transistor. In this embodiment, when an N-type thin-film transistor is used, its first terminal can be the source, and its second terminal can be the drain. In the following embodiments, the description uses an N-type thin-film transistor as an example, meaning that the thin-film transistor is turned on when the control terminal signal is high. It is conceivable that when a P-type transistor is used, the timing of the drive signal needs to be adjusted accordingly. Specific details are not elaborated here, but should be within the scope of protection of this invention.

[0057] In the circuits provided in the embodiments of this application, nodes such as pull-up nodes and pull-down nodes do not represent actual existing components, but rather represent the junctions of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junctions of related electrical connections in the circuit diagram.

[0058] In the circuits provided in the embodiments of this application, all transistors are N-type transistors, which will be used as an example for explanation.

[0059] like Figure 1 As shown, some embodiments of this disclosure provide a liquid crystal display device 1000.

[0060] In some examples, the aforementioned liquid crystal display device 1000 can be any display device that displays either moving (e.g., video) or stationary (e.g., still images) text or images. More specifically, the display device of the described embodiments is contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0061] For example, the liquid crystal display device can be a head-mounted display device used in near-eye display fields such as 2D, 3D, VR (Virtual Reality), AR (Augmented Reality), MR (Mixed Reality), and lighting.

[0062] For example, the liquid crystal display device 1000 includes a cover plate and a display panel 300.

[0063] The cover plate is located on the light-emitting side of the display panel and is used to protect the display panel. The cover plate can be made of glass.

[0064] like Figure 2 As shown, the display panel 300 may include an array substrate 10, a liquid crystal layer 11, and a color filter substrate 12 stacked in sequence.

[0065] For example, combining Figure 3 The array substrate 10 may include a plurality of pixel electrodes 101 and a plurality of pixel driving circuits 102. The plurality of pixel electrodes 101 and the plurality of pixel driving circuits 102 are electrically connected in a one-to-one correspondence, and the pixel driving circuits 102 provide pixel voltage signals to the corresponding pixel electrodes 101.

[0066] For example, the pixel driving circuit 102 includes a capacitor that has storage and compensation capacitance as well as voltage regulation function.

[0067] For example, the display panel 300 also includes a common electrode.

[0068] The location of the common electrode is related to the display type of the display panel 300. In the embodiments of this disclosure, when the display panel 300 is an LED (Light Emitting Diode) display panel, the display type of the display panel 300 can be ADS (Advanced Super Dimension Switch), IPS (In-Plane Switching), VA (Vertical Alignment), FFS (Fringe Field Switching), TN (Twisted Nematic), etc. Therefore, there are multiple locations for the common electrode in the embodiments of this disclosure.

[0069] For example, when the display panel 300 is an IPS display type, the common electrode can be disposed on the array substrate 10 and disposed on the same layer as the pixel electrode 101. Thus, the common electrode and the pixel electrode 101 can be formed simultaneously in one patterning process, thereby simplifying the manufacturing process of the display panel 300.

[0070] For example, when the display panel 300 is an FFS or ADS display type, the common electrode can be disposed on the array substrate 10 and located on a different layer from the pixel electrode 101. This avoids interference between the pixel voltage signal on the pixel electrode 101 and the common voltage on the common electrode, improving the signal accuracy of both the pixel voltage signal and the common voltage.

[0071] For example, if the display panel 300 is a TN or VA display type, the common electrode can be disposed on the color filter substrate 12.

[0072] For example, such as Figure 2 As shown, the liquid crystal layer 11 includes a plurality of liquid crystal molecules. For example, taking the display panel 300 as a TN display type, an electric field can be formed between the pixel electrode 101 and the common electrode, and the liquid crystal molecules located between the pixel electrode 101 and the common electrode can be deflected under the action of the electric field.

[0073] For example, the color filter substrate 12 includes various color filters. For instance, when the light incident on the color filter is white light, the color filter may include a red filter, a green filter, and a blue filter. For example, a red filter allows only red light in the incident light to pass through, a green filter allows only green light in the incident light to pass through, and a blue filter allows only blue light in the incident light to pass through.

[0074] Of course, the color filter substrate 12 also includes a black matrix. The black matrix can be used to prevent light mixing.

[0075] In some embodiments, such as Figure 2 As shown, the liquid crystal display device 1000 further includes a backlight module 500. A display panel 300 is stacked on the light-emitting side of the backlight module 500. The light-emitting side of the backlight module 500 refers to the side of the backlight module 500 from which light is emitted. The backlight module 500 provides backlight to the display panel 300.

[0076] Understandably, the backlight provided by the backlight module 500 can pass through the array substrate 10 and be incident on the liquid crystal molecules in the liquid crystal layer 11. Under the action of the electric field formed between the pixel electrode 101 and the common electrode, the liquid crystal molecules are deflected to a certain extent, thereby changing the polarization direction of the light passing through the liquid crystal. The light then passes through the color filter substrate 12 and exits. This exited light includes various colors of light, such as red light, green light, and blue light. The various colors of light work together to enable the display device 1000 to display.

[0077] like Figure 3 As shown, the display panel 300 includes multiple sub-pixels SP, which are arranged in multiple rows and columns. For example, the multiple sub-pixels SP are arranged in multiple columns along the first direction X and in multiple rows along the second direction Y. The first direction X and the second direction Y are parallel to the plane where the display panel 300 is located, and the first direction X and the second direction Y intersect. The angle between the first direction X and the second direction Y can be 80°, 85°, 90°, 110° or 120°.

[0078] The sub-pixel SP includes the aforementioned pixel driving circuit 102, pixel electrode 101, common electrode, and liquid crystal disposed corresponding to the pixel electrode 101.

[0079] The array substrate 10 further includes multiple data lines DT and multiple gate lines GT. The multiple data lines DT extend along a second direction Y, and the multiple gate lines GT extend along a first direction X. The multiple data lines DT and the multiple gate lines GT divide the display panel 300 into multiple sub-pixel regions, and a sub-pixel SP is located within a sub-pixel region. The multiple sub-pixels SP are located in the display area AA of the display panel 300.

[0080] The array substrate 10 further includes a gate driving circuit 13. The gate driving circuit 13 is connected to multiple sub-pixels SP via multiple gate lines GT. The gate driving circuit 13 is located on at least one side of the multiple sub-pixels SP along the second direction Y, thereby facilitating the connection between the gate driving circuit 13 and the multiple gate lines GT, and facilitating the transmission of electrical signals from the gate driving circuit 13 to the gate lines GT.

[0081] The gate driving circuit 13 can be located in the peripheral area BB of the display panel 300. The gate driving circuit 13 includes multiple shift register units. The shift register units in the gate driving circuit 13 are mainly composed of transistors, capacitors, and other devices. During the operation of the shift register units, the output of the scan signal is achieved through the cooperation of the transistors and capacitors.

[0082] For example, the pixel driving circuit 102 described above includes at least one data writing transistor T0. The control electrode of the data writing transistor T0 is connected to the gate line GT, and it receives electrical signals such as scan signal Gt transmitted by the gate line GT.

[0083] The array substrate 10 also includes a display chip 14. The display chip 14 is located on one side of the plurality of sub-pixels SP along the first direction X, and is used to provide data signals Dt, etc., to the sub-pixels SP.

[0084] For example, the display chip 14 is connected to multiple data lines DT and transmits data signals Dt to the data lines DT. One data line DT is connected to a column of sub-pixels SP, thereby transmitting the data signal Dt to the sub-pixels SP.

[0085] For example, the data writing transistor in the sub-pixel SP is turned on by the scan signal Gt transmitted by the gate line GT. The first electrode of the data writing transistor T0 receives the data signal Dt from the data line DT and transmits it to the second electrode of the data writing transistor T0 and the pixel electrode 101. The liquid crystal in the sub-pixel SP is deflected by the electrical signals of the pixel electrode 101 and the common electrode.

[0086] In one implementation, in the field of VR head-mounted displays, in order to improve the user experience and alleviate dizziness and image ghosting during use, the display device needs to have a high refresh rate.

[0087] It should be noted that the aforementioned VR headsets typically use a liquid crystal display (LCD) device 1000. The refresh rate of the LCD device 1000 is related to the time it takes to capture one frame of an image. (Refer to...) Figure 4A The shorter the frame time, the higher the refresh rate of the LCD display. Therefore, the refresh rate of the LCD display can be increased by shortening the frame time. Within the time of one frame, pixel scanning, liquid crystal response and deflection to the corresponding position, and backlight activation of the backlight module must be completed sequentially. In other words, if... Figure 4AAs shown, a frame time includes pixel scanning time, liquid crystal response time, and backlight on-time. Pixel scanning time is the time within one frame for the gate driving circuit 13 to sequentially input scanning signals to each gate line; liquid crystal response time is the time within one frame for the liquid crystal to respond and deflect to the corresponding position. Generally, the higher the pixel density and resolution of the liquid crystal display device 1000, the longer the pixel scanning time in one frame, resulting in shorter liquid crystal response and backlight on-time times for the backlight module 500. As described above, improving the refresh rate of the liquid crystal display device requires shortening the frame time. Higher resolution means a longer pixel scanning time in one frame. Therefore, to improve the refresh rate of the liquid crystal display device 1000 while maintaining its high resolution, the liquid crystal response time must be shortened. Thus, how to shorten the liquid crystal response time, improve the refresh rate of the liquid crystal display device 1000, and enhance the user experience becomes a problem that the liquid crystal display device 1000 needs to solve.

[0088] Based on this, such as Figure 3 As shown, an embodiment of this disclosure provides a shift register unit 20, which is applied to the liquid crystal display device 1000 described above. Specifically, the shift register unit 20 constitutes part of the gate driving circuit 13 in the liquid crystal display device 1000.

[0089] like Figure 5 , Figure 6 and Figure 7 As shown, the shift register unit 20 includes a driver sub-circuit 210 and a first reset circuit 220.

[0090] The driver sub-circuit 210 is connected to the first scan output terminal Gout1. For example, combined with Figure 3 The first scan output terminal Gout1 is connected to at least one gate line GT.

[0091] The driver sub-circuit 210 is configured to provide a first scan signal to the first scan output terminal Gout1. Thereby, the gate line GT receives the first scan signal from the first scan output terminal Gout1 and transmits it to one or more rows of sub-pixels SP connected thereto, for scanning the one or more rows of sub-pixels SP.

[0092] For example, refer to Figure 8 The display phase of a frame image includes at least a scanning phase S0 and a reset phase R0.

[0093] It should be noted that during the image display process of a liquid crystal display device, for example, if N frames of images need to be displayed, Figure 8The N-1Frame shown refers to the stage in which the image of the (N-1)th frame is displayed, and the N Frame refers to the stage in which the image of the Nth frame is displayed.

[0094] The process by which the driver sub-circuit 210 provides the first scan signal to the first scan output terminal Gout1 can be located in the scanning stage S0 of a frame image.

[0095] Combination Figure 3 Taking a gate line GT electrically connected to a row of sub-pixels SP as an example, the gate line GT transmits the first scan signal to each pixel driving circuit 102 of the row of sub-pixels SP. The data writing transistor T0 in the pixel driving circuit 102 is turned on. The first electrode of the data writing transistor T0 receives the data signal Dt provided by the data line DT and transmits it to the second electrode of the data writing transistor T0, which then transmits it to the pixel electrode 101. The pixel electrode 101 is loaded with the data signal Dt. Under the action of the electrical signals provided by the pixel electrode 101 and the common electrode, the liquid crystal in the sub-pixel SP is deflected to the target position. After the liquid crystal in the sub-pixel SP is deflected to the target position, the backlight module 500 in the liquid crystal display device 1000 is turned on, providing backlight to the display panel 300. The sub-pixel SP displays the target grayscale under the action of the backlight. Each row of sub-pixels SP displays the corresponding target grayscale, enabling the display panel 300 and the liquid crystal display device 1000 to display one frame of image.

[0096] It should be noted that the backlight module 500 is turned on after the scanning phase S0.

[0097] The aforementioned first reset circuit 220 is connected to the reset signal terminal GR, the first scan output terminal Gout1, and the pull-down node PD of the driver sub-circuit 210. The first reset circuit 220 is configured to transmit a reset signal to the first scan output terminal Gout1 in response to the reset signal transmitted from the reset signal terminal GR. The reset signal is used to activate the pixel driving circuit 102.

[0098] The process by which the first reset circuit 220 transmits the reset signal to the first scan output terminal Gout1 can be located in the reset stage R0 of a frame image.

[0099] The grid line GT receives the reset signal from the first scan output terminal Gout1 and transmits it to one or more rows of sub-pixels SP to reset the one or more rows of sub-pixels SP.

[0100] Taking a gate line GT electrically connected to a row of sub-pixels SP as an example, the gate line GT transmits a reset signal to each pixel driving circuit 102 of the row of sub-pixels SP. The data writing transistor T0 in the pixel driving circuit 102 is turned on. The first electrode of the data writing transistor T0 receives the electrical signal, such as the data sub-signal Dt1, provided by the data line DT, and transmits it to the second electrode of the data writing transistor T0 and the pixel electrode 101. The pixel electrode 101 is loaded with the data sub-signal Dt1. Under the action of the electrical signals provided by the pixel electrode 101 and the common electrode, the liquid crystal in the sub-pixel SP is deflected to a preset position, completing the reset of the position of the liquid crystal in each sub-pixel SP. When no electric field is formed between the pixel electrode 101 and the common electrode, the deflected position of the liquid crystal molecules in the sub-pixel SP is, for example, the initial position. There is a certain angle between the preset position and the initial position.

[0101] The timing of the reset signal being transmitted to the first scan output terminal Gout1 is later than the timing of the first scan signal being transmitted to the first scan output terminal Gout1.

[0102] Reference Figure 4B During the display phase of one frame of image, the first scan signal is used to scan each row of sub-pixels SP, causing the liquid crystal in each row of sub-pixels SP to deflect to the target position. The reset signal is used to reset the position of the liquid crystal in each row of sub-pixels SP, causing the liquid crystal to deflect to a preset position. Thus, during the display phase of the next frame of image, the liquid crystal of each sub-pixel SP deflects from the reset preset position to the corresponding target position. (Refer to...) Figure 4B The global reset time is the time it takes for all sub-pixels SP to complete the reset of the liquid crystal positions in all sub-pixels SP. Because a reset phase is added to the display of one frame of an image, the deflection of the liquid crystal in each row of sub-pixels SP changes from the original process of moving from the initial position to the target position to a process of moving from the initial position to a preset position, and then to the target position. The inventors' tests revealed that the time it takes for the liquid crystal in each sub-pixel SP to move from the preset position to the corresponding target position is shorter than the time it takes for the liquid crystal in each sub-pixel SP to move from the initial position to the corresponding target position. Therefore, the setting of the reset phase R0 can shorten the response time of the liquid crystal in one frame of an image (the time to move from the preset position to the target position), thus shortening the frame time and improving the refresh rate of the liquid crystal display device 1000.

[0103] Understandably, in combination Figure 8 and Figure 10The reset phase R0 of a single frame constitutes part of the vertical blanking phase (V-Blank) of that frame. The vertical blanking phase is the time interval between the last row of sub-pixels SP being written to the current frame's data signal Dt and the first row of sub-pixels SP being written to the next frame's data signal Dt. Therefore, the reset phase R0 avoids occupying the entire frame's time independently and does not affect the frame's duration, thus improving the display device's refresh rate.

[0104] Combination Figure 5 The shift register unit 20 provided in the embodiments of this disclosure includes a first reset circuit 220. The first reset circuit 220 is used to transmit a reset signal to the first scan output terminal Gout1. The time when the reset signal is transmitted to the first scan output terminal Gout1 is later than the time when the first scan signal is transmitted to the first scan output terminal Gout1. Thus, after the first scan signal completes the scanning of the sub-pixel SP, the reset signal is used to reset the sub-pixel SP, causing the liquid crystal in the sub-pixel SP to deflect from the target position to the preset position. In this way, during the display of the next frame of image, the time for the liquid crystal in the sub-pixel SP to deflect from the preset position to the corresponding target position is shorter, resulting in a shorter frame of image time. This helps to improve the refresh rate of the liquid crystal display device 1000, alleviate dizziness during user use, and improve the user experience.

[0105] It is understood that the structure of the first reset circuit 220 can be varied and can be configured according to actual needs. The embodiments disclosed herein do not limit this.

[0106] In some examples, refer to Figure 5 , Figure 6 and Figure 7 The first reset circuit 220 mentioned above includes: a first reset transistor M1 and a second reset transistor M2.

[0107] For example, the control electrode of the first reset transistor M1 is connected to the reset signal terminal GR, the first electrode of the first reset transistor M1 is connected to the first scan output terminal Gout1, and the second electrode of the first reset transistor M1 is connected to the reset signal terminal GR. For instance, the first transistor M1 is turned on by the reset signal provided by the reset signal terminal GR, transmitting the reset signal to the first scan output terminal Gout1, causing the first scan output terminal Gout1 to output a reset signal to the gate line, which in turn transmits the reset signal through the gate line GT to the sub-pixel SP, thereby turning on the write transistor T0 in the sub-pixel SP, so that the liquid crystal of the sub-pixel SP is deflected to a preset position.

[0108] For example, the control terminal of the second reset transistor M2 is connected to the reset signal terminal GR, the first terminal of the second reset transistor M2 is connected to the first voltage signal terminal VGL, and the second terminal of the second reset transistor M2 is connected to the pull-down node PD of the drive sub-circuit 210.

[0109] For example, the second reset transistor M2 is turned on under the action of the reset signal, transmitting the first voltage signal of the first voltage signal terminal VGL to the pull-down node PD, thus pulling down the potential of the pull-down node PD. This prevents the first scan output terminal Gout1 from outputting the first scan signal.

[0110] In some examples, refer to Figure 5 The aforementioned driving sub-circuit 210 includes: an input module 2100, a first reset module 2200, a second reset module 2300, a pull-down control module 2400, a first noise reduction module 2500, a second noise reduction module 2600, an anti-leakage module 2700, a first output module 2800, and a second output module 2900.

[0111] The input module 2100 is connected to the first clock signal terminal CN, the initial signal input terminal STV, and the first node N1. The input module 2100 is configured to transmit the first clock signal provided by the first clock signal terminal CN to the first node N1 under the control of the initial signal provided by the initial signal input terminal STV.

[0112] The first reset module 2200 is connected to the second clock signal terminal CNB, the first reset signal terminal RST1, and the first node. The first reset module 2200 is configured to transmit the second clock signal provided by the second clock signal terminal CNB to the first node N1 under the control of the first reset signal provided by the first reset signal terminal RST1.

[0113] The second reset module 2300 is connected to the second reset signal terminal RST2, the first voltage signal terminal VGL, and the first node N1. The second reset module 2300 is configured to pull down the potential of the first node N1 to the potential of the first voltage signal terminal VGL under the control of the second reset signal provided by the second reset signal terminal RST2.

[0114] The pull-down control module 2400 is connected to the fourth clock signal terminal CKB, the first node N1, the first voltage signal terminal VGL, and the pull-down node PD. The pull-down control module 2400 is configured to pull down the potential of the pull-down node PD to the potential of the first voltage signal terminal VGL under the control of the potential of the first node N1. The pull-down control module 2400 is also used to transmit the fourth clock signal to the pull-down node PD under the control of the fourth clock signal provided by the fourth clock signal terminal CKB, so that the pull-down node PD maintains the first potential, which is different from the potential of the first voltage signal terminal VGL.

[0115] The first noise reduction module 2500 is connected to the first scan output terminal Gout1, the pull-down node PD, and the first voltage signal terminal VGL. The first noise reduction module 2500 is configured to, under the control of the first scan signal, pull down the first voltage provided by the potential of the pull-down node PD to the potential of the first voltage signal terminal VGL.

[0116] The second noise reduction module 2600 is connected to the pull-down node PD, the first node N1, and the first voltage signal terminal VGL. The second noise reduction module 2600 is configured to pull down the potential of the first node N1 to the potential of the first voltage signal terminal VGL under the control of the potential of the pull-down node PD.

[0117] The leakage current protection module 2700 is connected to the first node N1, the second voltage signal terminal VGH and the first pull-up node PU1. The leakage current protection module 2700 is configured to output the potential of the first node N1 to the first pull-up node PU1 under the control of the second voltage signal provided by the second voltage signal terminal VGH.

[0118] The first output module 2800 is connected to the first pull-up node PU1, the third clock signal terminal CK, and the first scan output terminal Gout1. The first output module 2800 is configured to output the third clock signal provided by the third clock signal terminal CK to the first scan output terminal Gout1 under the control of the potential of the first pull-up node. Here, the third clock signal can be transmitted to the first scan output terminal Gout1 as the first scan signal.

[0119] The second output module 2900 is connected to the pull-down node PD, the first scan output terminal Gout1, and the first voltage signal terminal VGL. The second output module 2900 is configured to transmit the potential of the first voltage signal terminal VGL to the first scan output terminal Gout1 under the control of the potential of the pull-down node PD. The potential of the first voltage signal terminal VGL can be a first voltage.

[0120] For example, the electrical signal provided by the first voltage signal terminal VGL can be a constant low-level electrical signal. The electrical signal provided by the second voltage signal terminal VGH can be a constant high-level electrical signal.

[0121] For example, there are various structures for the shift register unit described above, and the configuration can be selected according to the actual situation. The embodiments disclosed herein do not limit this.

[0122] In some examples, the equivalent circuit diagram of shift register unit 20 is as follows: Figure 5 As shown.

[0123] like Figure 5 As shown, the input module 2100 includes a first transistor T1. The control electrode of the first transistor T1 is connected to the initial signal input terminal STV, the first electrode of the first transistor T1 is electrically connected to the first clock signal terminal CN, and the second electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 is turned on under the action of the initial signal provided by the initial signal input terminal STV, transmitting the first clock signal from the first clock signal terminal CN to the first node N1.

[0124] The first reset module 2200 includes a second transistor T2. The control terminal of the second transistor T2 is connected to the first reset signal terminal RST1, the first terminal of the second transistor T2 is connected to the second clock signal terminal CNB, and the second terminal of the second transistor T2 is connected to the first node. The second transistor T2 is turned on under the action of the first reset signal provided by the first reset signal terminal RST1, transmitting the second clock signal from the second clock signal terminal CNB to the first node N1.

[0125] The first output module 2800 includes a third transistor T3 and a first storage capacitor C1. The control electrode of the third transistor T3 is connected to the first pull-up node PU1, the first electrode of the third transistor T3 is connected to the third clock signal terminal CK, and the second electrode of the third transistor T3 is connected to the first scan output terminal Gout1. The first electrode of the first storage capacitor C1 is connected to the first pull-up node PU1, and the second electrode of the first storage capacitor C1 is connected to the first scan output terminal Gout1. The third transistor T3 is turned on by the first pull-up node PU1, outputting the third clock signal from the third clock signal terminal CK to the first scan output terminal Gout1. Here, the third clock signal can be transmitted to the first scan output terminal Gout1 as the first scan signal. The first storage capacitor C1 is a bootstrap capacitor used to receive and store the voltage of the first pull-up node PU1, ensuring that the voltage of the control electrode of the third transistor T3 remains constant, thus ensuring the normal conduction of the third transistor T3, and also having a voltage stabilizing function.

[0126] The second output module 2900 includes a fourth transistor T4 and a second storage capacitor C2. The control electrode of the fourth transistor T4 is connected to the pull-down node PD, the first electrode of the fourth transistor T4 is connected to the first scan output terminal Gout1, and the second electrode of the fourth transistor T4 is connected to the first voltage signal terminal VGL. The first electrode of the second storage capacitor C2 is connected to the pull-down node PD, and the second electrode of the second storage capacitor C2 is connected to the first voltage signal terminal VGL. The fourth transistor T4 is turned on under the influence of the potential of the pull-down node PD, transmitting the potential of the first voltage signal terminal VGL to the first scan output terminal Gout1. The second storage capacitor C2 is used to receive and store the voltage of the pull-down node PD. When the fourth transistor T4 is turned on and discharging under the influence of the potential of the pull-down node PD, the second storage capacitor C2 allows the fourth transistor T4 to discharge slowly during the on-state process, and the second storage capacitor C2 also has a voltage stabilizing effect.

[0127] The first noise reduction module 2500 includes an eighth transistor T8. The control electrode of the eighth transistor T8 is connected to the first scan output terminal Gout1, the first electrode of the eighth transistor T8 is connected to the pull-down node PD, and the second electrode of the eighth transistor T8 is connected to the first voltage signal terminal VGL. The eighth transistor T8 is turned on under the action of the electrical signal provided by the first scan signal, pulling down the potential of the pull-down node PD to the potential of the first voltage signal terminal VGL.

[0128] The second noise reduction module 2600 includes a fifth transistor T5. The control electrode of the fifth transistor T5 is connected to a pull-down node, the first electrode of the fifth transistor T5 is connected to a first node N1, and the second electrode of the fifth transistor T5 is connected to a first voltage signal terminal VGL. The fifth transistor T5 is turned on by the potential of the pull-down node PD, pulling down the potential of the first node N1 to the potential of the first voltage signal terminal VGL.

[0129] The pull-down control module 2400 includes a sixth transistor T6 and a seventh transistor T7. The control electrode of the seventh transistor T7 is connected to the fourth clock signal terminal CKB, the first electrode of the seventh transistor T7 is connected to the fourth clock signal terminal CKB, and the second electrode of the seventh transistor T7 is connected to the pull-down node PD. The seventh transistor T7 is turned on by the fourth clock signal provided by the fourth clock signal terminal CKB, transmitting the fourth clock signal from the fourth clock signal terminal CKB to the pull-down node PD. The control electrode of the sixth transistor T6 is connected to the first node N1, the first electrode of the sixth transistor T6 is connected to the pull-down node PD, and the second electrode of the sixth transistor T6 is connected to the first voltage signal terminal VGL. The sixth transistor T6 is turned on by the potential of the first node N1, pulling the potential of the pull-down node PD down to the potential of the first voltage signal terminal VGL.

[0130] The leakage current protection module 2700 includes a ninth transistor T9. The control terminal of the ninth transistor T9 is connected to the second voltage signal terminal VGH, the first terminal of the ninth transistor T9 is connected to the first node N1, and the second terminal of the ninth transistor T9 is connected to the first pull-up node PU1. The ninth transistor T9 is turned on by the second voltage provided by the second voltage signal terminal VGH, outputting the potential of the first node N1 to the first pull-up node PU1.

[0131] The second reset module 2300 includes a tenth transistor T10. The control electrode of the tenth transistor T10 is connected to the second reset signal terminal RST2, the first electrode of the tenth transistor T10 is connected to the first node N1, and the second electrode of the tenth transistor T10 is connected to the first voltage signal terminal VGL. The tenth transistor T10 is turned on under the action of the second reset signal provided by the second reset signal terminal RST2, pulling down the potential of the first node N1 to the potential of the first voltage signal terminal VGL.

[0132] In other examples, refer to Figure 6 and Figure 7 The driver sub-circuit 210 is also connected to the second scan output terminal Gout2. The driver sub-circuit 210 is also configured to provide a second scan signal to the second scan output terminal Gout2.

[0133] Reference Figure 6 The aforementioned driving sub-circuit 210 also includes a third output module 2000.

[0134] The third output module 2000 is connected to the first node N1, the pull-down node PD, the first voltage signal terminal VGL, the fifth clock signal terminal CK5, the second voltage signal terminal VGH, and the second scan output terminal Gout2. The third output module 2000 is configured to, under the control of the second voltage provided by the second voltage signal terminal VGH, transmit the potential of the first node N1 to the second pull-up node PU2; under the control of the potential of the pull-down node PD, transmit the first voltage signal to the second scan output terminal Gout2; and under the control of the second pull-up node PU2, transmit the fourth clock signal provided by the fourth clock signal terminal CKB to the second scan output terminal Gout2.

[0135] For example, refer to Figure 6 The third output module 2000 includes: a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, and a third storage capacitor C3.

[0136] For example, refer to Figure 6 and Figure 7 The shift register unit 20 also includes a second reset circuit 230.

[0137] The second reset circuit 230 is connected to the second scan output terminal Gout2 and the reset signal terminal GR. The second reset circuit 230 is configured to transmit a reset signal to the second scan output terminal Gout2 in response to the reset signal transmitted by the reset signal terminal GR.

[0138] For example, combining Figure 3 The second scan output terminal Gout2 is connected to one or more grid lines GT and transmits a reset signal through the grid lines GT, thereby causing the liquid crystal in the sub-pixel SP connected to the grid lines GT to deflect to a preset position.

[0139] For example, the row containing a sub-pixel SP connected to the second scan output terminal Gout2 via a gate line GT is different from the row containing a sub-pixel SP connected to the first scan output terminal Gout1 via another gate line. For instance, the row of sub-pixels connected to the second scan output terminal Gout2 via a gate line GT is the first row of sub-pixels, and the row of sub-pixels connected to the first scan output terminal Gout1 via another gate line is the second row of sub-pixels. Therefore, reset signals can be transmitted to sub-pixels in different rows using the first scan output terminal Gout1 and the second scan output terminal Gout2.

[0140] In some examples, the reset signal is transmitted to the first scan output Gout1 at the same time as the reset signal is transmitted to the second scan output Gout2.

[0141] Therefore, a row of sub-pixels connected to the first scan output terminal Gout1 and another row of sub-pixels connected to the second scan output terminal can simultaneously receive the reset signal. This allows the liquid crystals in the first row of sub-pixels and the other row of sub-pixels to start deflecting simultaneously and to the preset position. This reduces the time it takes for the liquid crystals of each sub-pixel to deflect from the preset position to the corresponding target position, thereby reducing the response time of the liquid crystals in a frame of an image (the time it takes to deflect from the preset position to the target position), shortening the frame of an image, and thus improving the refresh rate of the liquid crystal display device.

[0142] In some examples, continue to refer to Figure 6 The second reset circuit 230 includes a third reset transistor M3.

[0143] The control terminal of the third reset transistor M3 is connected to the reset signal terminal GR, the first terminal of the third reset transistor M3 is connected to the second scan output terminal Gout2, and the second terminal of the third reset transistor M3 is connected to the reset signal terminal GR.

[0144] For example, under the control of the reset signal provided by the reset signal terminal GR, the third reset transistor M3 transmits the reset signal to the second scan signal terminal Gout2. This causes the reset signal to be transmitted to the sub-pixel connected to the second scan signal terminal Gout2, thereby turning on the write transistor T0 in the sub-pixel SP, causing the liquid crystal of the sub-pixel to deflect to a preset position, thereby improving the refresh rate of the liquid crystal display device.

[0145] In the above example, the equivalent circuit diagram of shift register unit 20 is as follows: Figure 6 As shown.

[0146] The driver sub-circuit 210 includes an input module 2100, a first reset module 2200, a second reset module 2300, a second pull-down control module 3400, a third noise reduction module 3500, an anti-leakage module 2700, a first output module 2800, and a second output module 2900.

[0147] The input module 2100 includes a first transistor T1; the first reset module 2200 includes a second transistor T2; the first output module 2800 includes a third transistor T3 and a first storage capacitor C1; the second output module 2900 includes a fourth transistor T4 and a second storage capacitor C2; the leakage protection module 2700 includes a ninth transistor T9; and the second reset module 2300 includes a tenth transistor T10.

[0148] Combination Figure 6 The input module 2100, first reset module 2200, second reset module 2300, leakage protection module 2700, first output module 2800, and second output module 2900 described above have the same transistor configuration and connection relationship as those in the aforementioned embodiments. In other words, the signal transmission method is also the same. For details, please refer to the aforementioned embodiments corresponding to... Figure 5 The descriptions in the text are not repeated here.

[0149] For example, refer to Figure 6 The third noise reduction module 3500 includes an eleventh transistor T11. The control electrode of the eleventh transistor T11 is connected to the first node N1, the first electrode of the eleventh transistor T11 is connected to the pull-down node PD, and the second electrode of the eleventh transistor T11 is connected to the first voltage signal terminal VGL. The eleventh transistor T11 is turned on by the potential of the first node N1, pulling down the potential of the pull-down node PD to the potential of the first voltage signal terminal VGL.

[0150] For example, continue to refer to Figure 6 The second pull-down control module 3400 includes a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, and a fifteenth transistor T15.

[0151] The control electrode of the twelfth transistor T12 is connected to the first clock signal terminal CN, the first electrode of the twelfth transistor T12 is connected to the fourth clock signal terminal CKB, and the second electrode of the twelfth transistor T12 is connected to the second node N2. The twelfth transistor T12 is turned on by the first clock signal provided by the first clock signal terminal CN, transmitting the fourth clock signal from the fourth clock signal terminal CKB to the second node N2.

[0152] The control electrode of the thirteenth transistor T13 is connected to the second clock signal terminal CNB, the first electrode of the thirteenth transistor T13 is connected to the second node N2, and the second electrode of the thirteenth transistor T13 is connected to the sixth clock signal terminal CK6. The thirteenth transistor T13 is turned on by the second clock signal provided by the second clock signal terminal CNB, outputting the sixth clock signal provided by the sixth clock signal terminal CK6 to the second node N2.

[0153] The control electrode of the fourteenth transistor T14 is connected to the pull-down node PD, the first electrode of the fourteenth transistor T14 is connected to the first node N1, and the second electrode of the fourteenth transistor T14 is connected to the first voltage signal terminal VGL. The fourteenth transistor T14 is turned on by the potential of the pull-down node PD, pulling down the potential of the first node N1 to the potential of the first voltage signal terminal VGL.

[0154] The control electrode of the fifteenth transistor T15 is connected to the second node N2, the first electrode of the fifteenth transistor T15 is connected to the second voltage signal terminal VGH, and the second electrode of the fifteenth transistor T15 is connected to the pull-down node PD. The fifteenth transistor T15 is turned on by the potential of the second node N2, outputting the second voltage signal provided by the second voltage signal terminal VGH to the pull-down node PD.

[0155] Continue to refer to Figure 6 The third output module 2000 includes: a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, and a third storage capacitor C3.

[0156] In this configuration, the control terminal of the eighteenth transistor T18 is connected to the second voltage signal terminal VGH, the first terminal of the eighteenth transistor T18 is connected to the first node N1, and the second terminal of the eighteenth transistor T18 is connected to the second pull-up node PU2. The eighteenth transistor T18 is turned on by the second voltage signal provided by the second voltage signal terminal VGH, transferring the potential from the first node N1 to the second pull-up node PU2.

[0157] The control electrode of the seventeenth transistor T17 is connected to the pull-down node PD, the first electrode of the seventeenth transistor T17 is connected to the first voltage signal terminal VGL, and the second electrode of the seventeenth transistor T17 is connected to the second scan output terminal Gout2. The seventeenth transistor T17 is turned on by the potential of the pull-down node PD, transmitting the potential of the first voltage signal terminal VGL to the second scan output terminal Gout2.

[0158] The first terminal of the third storage capacitor C3 is connected to the second pull-up node PU2, and the second terminal of the third storage capacitor C3 is connected to the second scan output terminal Gout2. The third storage capacitor C3 is a bootstrap capacitor used to receive and store the voltage of the second pull-up node PU2, ensuring that the voltage of the control electrode of the sixteenth transistor T16 is constant, so as to ensure the normal conduction of the sixteenth transistor T16, and also has a voltage stabilizing function.

[0159] The control electrode of the sixteenth transistor T16 is connected to the second pull-up node PU2, the first electrode of the sixteenth transistor T16 is connected to the fifth clock signal terminal CK5, and the second electrode of the sixteenth transistor T16 is connected to the second scan output terminal Gout2. The sixteenth transistor T16 is turned on by the potential of the second pull-up node PU2, transmitting the fifth clock signal provided by the fifth clock signal terminal CK5 to the second scan signal terminal Gout2.

[0160] In some other examples, the equivalent circuit diagram of shift register unit 20 is as follows: Figure 7 As shown.

[0161] The shift register unit 20 and Figure 6 The difference in the shift register unit 20 shown is that the first output module 2800 of the shift register unit 20 further includes a nineteenth transistor T19, the second output module 2900 further includes a twentieth transistor T20, and the third output module 2000 further includes a twenty-first transistor T21 and a twenty-second transistor T22.

[0162] In this configuration, the control electrode of the nineteenth transistor T19 is connected to the first pull-up node PU1, the first electrode of the nineteenth transistor T19 is connected to the third clock signal terminal CK, and the second electrode of the nineteenth transistor T19 is connected to the third scan signal output terminal Gout3. The nineteenth transistor T19 is turned on by the first pull-up node PU1, transmitting the third clock signal from the third clock signal terminal CK to the third scan output terminal Gout3.

[0163] The control electrode of the twentieth transistor T20 is connected to the pull-down node PD, the first electrode of the twentieth transistor T20 is connected to the first voltage signal terminal VGL, and the second electrode of the twentieth transistor T20 is connected to the third scan output terminal Gout3. The twentieth transistor T20 is turned on by the pull-down node PD, transmitting the first voltage signal from the first voltage signal terminal VGL to the third scan output terminal Gout3.

[0164] The control electrode of the 21st transistor T21 is connected to the second pull-up node PU2, the first electrode of the 21st transistor T21 is connected to the fifth clock signal terminal CK5, and the second electrode of the 21st transistor T21 is connected to the fourth scan output terminal Gout4. The 21st transistor T21 is turned on by the second pull-up node PU2, transmitting the fifth clock signal from the fifth clock signal terminal CK5 to the fourth scan output terminal Gout4.

[0165] The control electrode of the 22nd transistor T22 is connected to the pull-down node PD, the first electrode of the 22nd transistor T22 is connected to the first voltage signal terminal VGL, and the second electrode of the 22nd transistor T22 is connected to the fourth scan output terminal Gout4. The 22nd transistor T22 is turned on by the pull-down node PD, transmitting the first voltage signal from the first voltage signal terminal VGL to the fourth scan output terminal Gout4.

[0166] It should be noted that the third scan output terminal Gout3 and the fourth scan output terminal Gout4 here can be the cascaded output terminals corresponding to the shift register unit 20.

[0167] Reference Figure 8 The embodiments of this disclosure also provide a driving method for a shift register unit 20, which is applied to the shift register unit 20 described in any of the above embodiments.

[0168] The driving method includes: A100 to A200.

[0169] A100, combined with Figure 8 During the scanning phase S0, the driver sub-circuit 210 of the shift register unit 20 provides the first scan signal to the first scan output terminal Gout1.

[0170] Thus, in the scanning phase S0, the scanning of sub-pixels of all rows is completed.

[0171] In the reset phase R0, the first reset circuit 220 of the shift register unit 20 provides a reset signal to the first scan output terminal Gout1.

[0172] Therefore, in the reset phase R0, the sub-pixels of all rows are reset.

[0173] For example, after the shift register unit 20 completes the scanning phase S0, for instance, the liquid crystal of each sub-pixel deflects to the first target position and enters the reset phase R0, causing the liquid crystal in the sub-pixel connected to the shift register unit 20 to deflect from the first target position to a preset position. When entering the scanning phase S0 of the next frame image, the liquid crystal of each sub-pixel deflects from the preset position to the second target position. Compared with some implementations of related technologies, the time for the liquid crystal of each sub-pixel to deflect from the first target position to the second target position is shorter, thereby effectively shortening the time of one frame image and improving the refresh rate of the liquid crystal display device.

[0174] Embodiments of this disclosure also provide another method for driving the shift register unit 20. For example... Figure 9A , Figure 9B and Figure 9C As shown, the shift register unit 20 includes: an input module 2100, a first reset module 2200, and a first output module 2800.

[0175] The input module 2100 is connected to the first clock signal terminal CN, the initial signal input terminal STV, and the first pull-up node PU1. The first reset module 2200 is connected to the second clock signal terminal CNB, the first reset signal terminal RST1, and the first pull-up node PU1. The first output module 2800 is connected to the first pull-up node PU1, the third clock signal terminal CK, and the first scan output terminal Gout1.

[0176] For example, the input module 2100 includes a first transistor T1. The control electrode of the first transistor T1 is connected to the initial signal input terminal STV, the first electrode of the first transistor T1 is connected to the first clock signal terminal CN, and the second electrode of the first transistor T1 is connected to the pull-up node. The first transistor T1 is turned on under the action of the initial signal provided by the initial signal input terminal STV, transmitting the first clock signal provided by the first clock signal terminal CN to the first pull-up node PU1.

[0177] For example, the first reset module 2200 includes a second transistor T2. The control terminal of the second transistor T2 is connected to the first reset signal terminal RST1, the first terminal of the second transistor T2 is connected to the second clock signal terminal CNB, and the second terminal of the second transistor T2 is connected to the first pull-up node PU1. The second transistor T2 is turned on under the action of the first reset signal provided by the first reset signal terminal RST1, transmitting the second clock signal provided by the second clock signal terminal CNB to the first pull-up node PU1.

[0178] For example, the first output module 2800 includes a third transistor T3. The control electrode of the third transistor T3 is connected to the first pull-up node PU1, the first electrode of the third transistor T3 is connected to the third clock signal terminal CK, and the third transistor T3 is connected to the first scan output terminal Gout1. The third transistor T3 is turned on under the potential of the first pull-up node PU1, transmitting the third clock signal provided by the third clock signal terminal CK to the first scan output terminal Gout1.

[0179] The aforementioned driving methods include: B100 to B200.

[0180] B100, combined with Figure 10 During the scanning phase S0, the input module 2100 responds to the initial signal provided by the initial signal input terminal STV and transmits the first clock signal provided by the first clock signal terminal CN to the first pull-up node PU1; the first output module 2800 responds to the potential of the first pull-up node PU1 and transmits the third clock signal provided by the third clock signal terminal CK as the first scan signal to the first scan signal terminal Gout1.

[0181] Therefore, the sub-pixel connected to the first scan signal terminal Gout1 receives the first scan signal, and the liquid crystal in the sub-pixel deflects to the target position, for example, the target position can be the first target position.

[0182] B200, combined with Figure 10 During the reset phase R0, the input module 2100, in response to the initial signal provided by the initial signal input terminal STV, transmits the first clock signal provided by the first clock signal terminal CN to the first pull-up node PU1; the first reset module 2200, in response to the first reset signal provided by the first reset signal terminal RST1, transmits the second clock signal provided by the second clock signal terminal CNB to the first pull-up node PU1; and the first output module 2800, in response to the potential of the first pull-up node PU1, transmits the third clock signal provided by the third clock signal terminal CK as a reset signal to the first scan signal terminal Gout1.

[0183] Therefore, in the reset phase R0, the reset signal transmitted from the shift register unit 20 to the first scan signal terminal Gout1 can be used to reset the liquid crystal of the corresponding sub-pixel, so that the liquid crystal of the sub-pixel is deflected to the preset position, and the time for the liquid crystal of the sub-pixel to deflect from the preset position to the target position is shorter, so that the response time of the liquid crystal occupies a smaller proportion of the time of one frame of image, thereby improving the refresh rate of the liquid crystal display device.

[0184] Understandably, we should continue to refer to... Figure 9A , Figure 9B and Figure 9CThe shift register unit 20 in this embodiment may further include: a second reset module 2300, a pull-down control module 2400, a first noise reduction module 2500, a second noise reduction module 2600, an anti-leakage module 2700, and a second output module 2900, etc. The configuration and connection relationships of the above modules can be referred to the foregoing section. Figure 5 The descriptions of each module in the document are not detailed here.

[0185] Embodiments of this disclosure also provide a gate drive circuit 13, see reference to Figure 3 The gate drive circuit 13 includes a plurality of cascaded shift register units 20 as described in any of the above embodiments.

[0186] For example, the number of shift register units 20 is N, and the N shift register units include, in sequence: first-level shift register unit, second-level shift register unit, third-level shift register unit, fourth-level shift register unit... Nth-level shift register unit.

[0187] For example, the cascaded output of the i-th stage shift register unit 20 is connected to the cascaded input of the (i+n)-th stage shift register unit 20; the cascaded output of the (i+n)-th stage shift register unit 20 is connected to the cascaded reset of the i-th stage shift register unit 20. Here, i and n are both positive integers.

[0188] For example, refer to Figure 7 , Figure 7 The third scan signal terminal Gout3 and the fourth scan signal terminal Gout4 shown can be the cascaded output terminals of the shift register unit 20, the initial signal input terminal STV can be the cascaded input terminal of the shift register unit 20, and the first reset signal terminal RST1 can be the cascaded reset terminal of the shift register unit 20.

[0189] For example, refer to Figure 3 Each of the multiple shift register units 20 is electrically connected to the gate line GT.

[0190] The embodiments of this disclosure also provide an image display method for a liquid crystal display device 1000, which is applied to the liquid crystal display device 1000 described in the above embodiments.

[0191] During the process of displaying images on the liquid crystal display device 1000, refer to Figure 8 and Figure 10 The display phase of an image frame includes: scanning phase S0 and resetting phase R0.

[0192] Image display methods include: A100 to A200.

[0193] A100, refer to Figure 3and Figure 12 During the scanning phase S0, the gate driving circuit 13 in the liquid crystal display device 1000 sequentially outputs a first scan signal to each row of sub-pixels, and the display chip 14 outputs a data signal Dt to the sub-pixels SP in the corresponding row. In response to the first scan signal and the data signal Dt, the liquid crystal in each sub-pixel SP deflects to its respective target position so that the sub-pixel SP displays the target grayscale.

[0194] For example, refer to Figure 3 and Figure 12 The first-stage shift register unit 20 in the gate drive circuit 13 outputs a first scan signal to the first row of sub-pixels. The control electrode of the data writing transistor T0 of the first row of sub-pixels is turned on under the control of the first scan signal. The display chip 14 outputs a data signal Dt to the first row of sub-pixels. The first electrode of the data writing transistor T0 of the first row of sub-pixels receives the data signal and transmits it to the pixel electrode 101 through the second electrode of the data writing transistor T0. The liquid crystal of the sub-pixel SP is deflected to the target position under the action of the pixel electrode 101 and the common electrode. Then, the second-stage shift register unit in the gate drive circuit 13 outputs a first scan signal to the second row of sub-pixels. The control electrode of the data writing transistor T0 of the second row of sub-pixels is turned on under the control of the first scan signal. The display chip 14 outputs a data signal Dt to the second row of sub-pixels. The first electrode of the data writing transistor T0 of the second row of sub-pixels receives the data signal Dt and transmits it to the pixel electrode 101 through the second electrode of the data writing transistor T0. The liquid crystal of the sub-pixel SP is deflected to the target position under the action of the pixel electrode 101 and the common electrode... The Nth-stage shift register unit in the gate drive circuit outputs a first scan signal to the Nth row of sub-pixels SP. The control electrode of the data writing transistor Dt of the Nth row of sub-pixels is turned on under the control of the first scan signal. The display chip 14 outputs a data signal to the Nth row of sub-pixels. The first electrode of the data writing transistor T0 of the Nth row of sub-pixels receives the data signal Dt and transmits it to the pixel electrode 101 through the second electrode of the data writing transistor T0. The liquid crystal of the sub-pixel SP is deflected to the target position under the action of the pixel electrode 101 and the common electrode. At this point, the gate drive circuit 13 has completed scanning of each sub-pixel SP. Combined with... Figure 2 and 8 When the backlight module 500 is activated, it provides backlight for each sub-pixel SP, and the sub-pixel SP displays the target grayscale.

[0195] A200, continue to refer to Figure 3 and Figure 12During the reset phase R0, the gate drive circuit 13 outputs a reset signal to each row of sub-pixels, and the display chip 14 outputs a data sub-signal Dt1 to the multi-row sub-pixels SP. In response to the reset signal and the data sub-signal Dt1, the liquid crystals in the multiple sub-pixels deflect to a preset position. The display grayscale corresponding to the multiple sub-pixels SP is the preset grayscale. The preset grayscale is greater than or equal to the target grayscale.

[0196] For example, the shift register units 20 at each stage in the gate drive circuit 13 simultaneously output reset signals to each row of sub-pixels SP. The data write transistors T0 of each row of sub-pixels are turned on under the action of the reset signals. The display chip 14 outputs the same data sub-signal Dt1 to multiple rows of sub-pixels SP. The first electrode of each row of sub-pixels T0 receives the data sub-signal Dt1 and transmits it to the pixel electrode 101 via the second electrode of the data write transistor T0. The liquid crystal of each sub-pixel SP is deflected to the same preset position under the action of the pixel electrode 101 and the common electrode. Figure 2 and Figure 8 The backlight module 500 is in the off state. The preset grayscale corresponding to each sub-pixel SP is the same grayscale.

[0197] It should be noted that, referring to Figure 11 and Figure 12 , Figure 11 The waveform diagram shows the output of a cascaded shift register unit in related technologies. Figure 12 This is a waveform diagram of the cascaded output of the shift register unit of this application. Comparative analysis shows that, due to the addition of a reset stage R0 in this application, under the control of the reset signal of the reset sub-circuit, or under the control of multiple signal terminals (for example, when the signals output from the initial signal input terminal STV, the third clock signal terminal CK, the first clock signal terminal CN, the second clock signal terminal CNB, the second voltage signal terminal VGH, and the first voltage signal terminal VGL are all at high levels), the potential of the first scan output terminal Gout of each shift register unit simultaneously becomes high, and the corresponding transistor is turned on. Simultaneously, in response to the reset signal and the data sub-signal Dt1, the liquid crystals in multiple sub-pixels deflect to a preset position, resulting in a shorter time for the liquid crystal to deflect from the preset position to the target position. This reduces the proportion of the liquid crystal response time within a single frame, thereby improving the refresh rate of the liquid crystal display device.

[0198] In some examples, the preset grayscale range includes G223 to G255.

[0199] For example, the preset grayscale can be G223, G235, G240, G245, G250, or G255.

[0200] This allows for a shorter liquid crystal deflection time, i.e., a shorter response time, thereby increasing the refresh rate of the liquid crystal display device.

[0201] In some examples, refer to Figure 3 The liquid crystal display device 1000 also includes a multiplexer 15.

[0202] For example, such as Figure 3 As shown, the multiplexer 15 is connected between the display chip 14 and multiple data lines DT.

[0203] In some embodiments, refer to Figure 3 The display chip 14 outputs a data signal Dt to the sub-pixel SP, including: the display chip 14 outputs a data signal Dt to the multiplexer 15; the multiplexer 15 selectively transmits the data signal Dt from the display chip 14 to a portion of the data lines DT.

[0204] Continue to refer to Figure 3 The display chip 14 outputs the same data sub-signal Dt1 to each sub-pixel SP, including: the display chip 14 outputs the data sub-signal Dt1 to the multiplexer 15; the multiplexer 15 transmits the data sub-signal Dt1 from the display chip 14 to multiple data lines DT.

[0205] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A shift register unit, characterized in that, The shift register unit includes: A driving sub-circuit is connected to the first scan output terminal; the driving sub-circuit is configured to provide a first scan signal to the first scan output terminal; A first reset circuit is connected to a reset signal terminal, a first scan output terminal, and a pull-down node of the driving sub-circuit; the first reset circuit is configured to transmit a reset signal to the first scan output terminal in response to a reset signal transmitted by the reset signal terminal. The reset signal is transmitted to the first scan output terminal at a time later than the first scan signal is transmitted to the first scan output terminal.

2. The shift register unit according to claim 1, characterized in that, The first reset circuit includes: a first reset transistor and a second reset transistor; The control electrode of the first reset transistor is connected to the reset signal terminal, the first electrode of the first reset transistor is connected to the first scan output terminal, and the second electrode of the first reset transistor is connected to the reset signal terminal; The control electrode of the second reset transistor is connected to the reset signal terminal, the first electrode of the second reset transistor is connected to the first voltage signal terminal, and the second electrode of the second reset transistor is connected to the pull-down node of the driving sub-circuit.

3. The shift register unit according to claim 1 or 2, characterized in that, The driving sub-circuit is also connected to the second scan output terminal; the driving sub-circuit is also configured to provide a second scan signal to the second scan output terminal. The shift register unit further includes: a second reset circuit; The second reset circuit is connected to the second scan output terminal and the reset signal terminal; the second reset circuit is configured to transmit the reset signal to the second scan output terminal in response to the reset signal transmitted by the reset signal terminal.

4. The shift register unit according to claim 3, characterized in that, The time when the reset signal is transmitted to the first scan output terminal is the same as the time when the reset signal is transmitted to the second scan output terminal.

5. The shift register unit according to claim 3, characterized in that, The second reset circuit includes: a third reset transistor; The control electrode of the third reset transistor is connected to the reset signal terminal, the first electrode of the third reset transistor is connected to the second scan output terminal, and the second electrode of the third reset transistor is connected to the reset signal terminal.

6. The shift register unit according to claim 3, characterized in that, The driving sub-circuit includes: a third output module; The third output module is connected to the first node, the pull-down node, the first voltage signal terminal, the fifth clock signal terminal, the second voltage signal terminal, and the second scan output terminal. The third output module is configured to transmit the potential of the first node to the second pull-up node under the control of the second voltage provided by the second voltage signal terminal, transmit the first voltage provided by the first voltage signal terminal to the second scan output terminal under the control of the potential of the pull-down node, and transmit the fifth clock signal provided by the fifth clock signal terminal to the second scan output terminal under the control of the second pull-up node.

7. The shift register unit according to claim 1 or 2, characterized in that, The driving sub-circuit includes: An input module is connected to a first clock signal terminal, an initial signal input terminal, and a first node; the input module is configured to transmit a first clock signal provided by the first clock signal terminal to the first node under the control of an initial signal provided by the initial signal input terminal. A first reset module is connected to a second clock signal terminal, a first reset signal terminal, and the first node; the first reset module is configured to transmit a second clock signal provided by the second clock signal terminal to the first node under the control of a first reset signal provided by the first reset signal terminal. The second reset module is connected to the second reset signal terminal, the first voltage signal terminal, and the first node; the second reset module is configured to pull down the potential of the first node to the potential of the first voltage signal terminal under the control of the second reset signal provided by the second reset signal terminal. A pull-down control module is connected to the fourth clock signal terminal, the first node, the first voltage signal terminal, and the pull-down node. The pull-down control module is configured to pull down the potential of the pull-down node to the potential of the first voltage signal terminal under the control of the potential of the first node. The pull-down control module is also used to transmit the fourth clock signal to the pull-down node under the control of the fourth clock signal provided by the fourth clock signal terminal, so that the pull-down node maintains a first potential, which is different from the potential of the first voltage signal terminal. A first noise reduction module is connected to the first scan output terminal, the pull-down node, and the first voltage signal terminal; the first noise reduction module is configured to, under the control of the first scan signal, pull down the potential of the pull-down node to the potential of the first voltage signal terminal; The second noise reduction module is connected to the pull-down node, the first node, and the first voltage signal terminal; the second noise reduction module is configured to pull down the potential of the first node to the potential of the first voltage signal terminal under the control of the potential of the pull-down node. An anti-leakage module is connected to the first node, the second voltage signal terminal, and the first pull-up node. The anti-leakage module is configured to output the potential of the first node to the first pull-up node under the control of the second voltage provided by the second voltage signal terminal. The first output module is connected to the first pull-up node, the third clock signal terminal, and the first scan output terminal; the first output module is configured to output the third clock signal provided by the third clock signal terminal to the first scan output terminal under the control of the potential of the first pull-up node. The second output module is connected to the pull-down node, the first scan output terminal, and the first voltage signal terminal; the second output module is configured to transmit the potential of the first voltage signal terminal to the first scan output terminal under the control of the potential of the pull-down node.

8. A method for driving a shift register unit, characterized in that, The shift register unit includes: a shift register unit as described in any one of claims 1 to 7; The display of a single frame of an image includes a scanning phase and a resetting phase; During the scanning phase, the driver sub-circuit of the shift register unit provides a first scan signal to the first scan output terminal; During the reset phase, the reset circuit of the shift register unit provides a reset signal to the first scan output terminal.

9. A method for driving a shift register unit, characterized in that, The shift register unit includes: The input module is connected to the first clock signal terminal, the initial signal input terminal, and the first pull-up node; The first reset module is connected to the second clock signal terminal, the first reset signal terminal, and the first pull-up node; The first output module is connected to the first pull-up node, the third clock signal terminal, and the first scan output terminal; The display of a single frame of an image includes a scanning phase and a resetting phase; During the scanning phase, the input module, in response to the initial signal provided by the initial signal input terminal, transmits the first clock signal provided by the first clock signal terminal to the first pull-up node; the first output module, in response to the potential of the first pull-up node, transmits the third clock signal provided by the third clock signal terminal as the first scan signal to the first scan output terminal. During the reset phase, the input module, in response to the initial signal provided by the initial signal input terminal, transmits the first clock signal provided by the first clock signal terminal to the first pull-up node; the first reset module, in response to the first reset signal provided by the first reset signal terminal, transmits the second clock signal provided by the second clock signal terminal to the first pull-up node; and the first output module, in response to the potential of the first pull-up node, transmits the third clock signal provided by the third clock signal terminal as a reset signal to the first scan output terminal.

10. A gate driving circuit, characterized in that, The gate drive circuit includes: a plurality of cascaded shift register units as described in any one of claims 1 to 7.

11. A liquid crystal display device, characterized in that, The liquid crystal display device includes: Multiple sub-pixels, wherein the multiple sub-pixels are arranged in multiple rows and columns; The gate driving circuit as described in claim 10; the plurality of shift register units in the gate driving circuit are electrically connected to the plurality of rows of the sub-pixels respectively; Multiple data lines; the data lines are electrically connected to a column of the sub-pixels; The display chip is connected to the multiple data lines.

12. The liquid crystal display device according to claim 11, characterized in that, The liquid crystal display device further includes: a multiplexer; The multiplexer is connected between the display chip and the multiple data lines.

13. An image display method for a liquid crystal display device, characterized in that, The image display method is applied to the liquid crystal display device according to claim 11 or 12; The display of a single frame of an image includes a scanning phase and a resetting phase; The image display method includes: During the scanning phase, the gate driving circuit in the liquid crystal display device sequentially outputs a first scanning signal to each row of sub-pixels, and the display chip outputs a data signal to the sub-pixels in the corresponding row; in response to the first scanning signal and the data signal, the liquid crystal in each sub-pixel deflects to its respective target position so that the sub-pixel displays the target grayscale. During the reset phase, the gate driving circuit outputs a reset signal to each row of sub-pixels, and the display chip outputs a data sub-signal to multiple rows of sub-pixels; in response to the reset signal and the data sub-signal, the liquid crystal in the multiple sub-pixels is deflected to a preset position; the display grayscale corresponding to the multiple sub-pixels is a preset grayscale; the preset grayscale is greater than or equal to the target grayscale.

14. The image display method according to claim 13, characterized in that, The range of the preset grayscale includes G223 to G255.

15. The image display method according to claim 13, characterized in that, The liquid crystal display device also includes a multi-channel distributor; The display chip outputs data signals to the sub-pixels, including: the display chip outputs data signals to the multiplexer; the multiplexer selectively transmits data signals from the display chip to a portion of the data lines; The display chip outputs the same data sub-signal to each of the sub-pixels, including: the display chip outputs the data sub-signal to the multiplexer; the multiplexer transmits the data sub-signal from the display chip to the multiple data lines.

Images