Power supply protection circuit and method and mobile power supply
By combining dual-channel voltage detection and 100K/20K voltage divider resistors, the problem of delayed protection of PMOS transistor output port switching is solved, achieving fast and reliable overcurrent/short circuit protection, and ensuring the safety and stability of the power supply link.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN GREEN CONNECTION TECH CO LTD
- Filing Date
- 2025-12-26
- Publication Date
- 2026-05-01
AI Technical Summary
In the existing technology, mobile power supply overcurrent/short circuit protection using PMOS transistors as output port switches has a slow response and unstable protection judgment, which poses a safety risk.
A dual-channel voltage detection mechanism is adopted, which synchronously acquires voltage signals through the VBUS voltage detection module and the output interface voltage detection module, and performs collaborative judgment by the main controller. Combined with the 100K/20K PMOS transistor gate voltage divider resistor, the protection response is fast and reliable.
It achieves fast and reliable overcurrent/short circuit protection, avoids the critical conduction state of the PMOS transistor, ensures the safety of the power supply link, reduces production and debugging costs, and improves product yield and compatibility.
Smart Images

Figure CN121965415A_ABST
Abstract
Description
A power supply protection circuit, method and mobile power supply Technical Field
[0001] This invention relates to the field of portable power supply technology, and in particular to a power supply protection circuit, method, and portable power supply. Background Technology
[0002] For mobile voltage converters using PMOS transistors as output port switches, overcurrent / short-circuit protection is typically achieved through a single VBUS voltage detection. This means that short-circuit protection is triggered when the VBUS voltage falls below the protection threshold. However, this method has several drawbacks. First, the protection response is slow. The gate voltage divider resistors for the C-port PMOS are typically 100K / 51K. When paired with a PMOS transistor whose on-state voltage is slightly above the upper limit (approximately 2V), the VBUS voltage fluctuates around 3.1V under overcurrent conditions, failing to consistently meet the triggering conditions and causing protection delays. Second, voltage fluctuations can cause the PMOS transistor to be in a critical on-state, leading to unstable judgment by the main control MCU software and a safety risk of continued output even after an overcurrent / short circuit.
[0003] Therefore, designing a power supply protection circuit, method, and mobile power supply with fast protection response, high protection reliability, and strong compatibility is of great importance to those skilled in the art. Summary of the Invention
[0004] This invention provides a power supply protection circuit, method, and mobile power supply with fast protection response, high protection reliability, and strong compatibility, to solve the problems of slow protection response and continued output after overcurrent / short circuit in the prior art.
[0005] This invention discloses a power supply protection circuit, comprising: a lithium battery pack, a lithium battery protection module, a DC-DC module, a PMOS transistor, an output interface, a main controller, a VBUS voltage detection module, and an output interface voltage detection module. The voltage output terminal of the lithium battery pack is connected to the voltage input terminals of the lithium battery protection module and the DC-DC module, respectively. The voltage output terminal of the DC-DC module is connected to the source of the PMOS transistor, and the drain of the PMOS transistor is connected to the output interface. The input terminal of the VBUS voltage detection module is connected to the output terminal of the lithium battery pack, and the input terminal of the output interface voltage detection module is connected to the output interface. The output terminals of both the VBUS voltage detection module and the output interface voltage detection module are connected to the main controller, and the output terminal of the main controller is connected to the gate of the PMOS transistor.
[0006] Optionally, the gate voltage divider resistor ratio of the PMOS transistor is 100K / 20K.
[0007] Optionally, it also includes a display module connected to the main controller for providing feedback on the protection status.
[0008] Optionally, the output interface is a Type-C port.
[0009] To address the problems existing in the prior art, the present invention also provides a power supply protection method, which is implemented through the aforementioned power supply protection circuit and includes the following steps: preset a trigger protection voltage value; real-time acquisition of VBUS voltage and output interface voltage, and comparison of VBUS voltage and output interface voltage with the trigger protection voltage value; when both VBUS voltage and output interface voltage are equal to or greater than the trigger protection voltage value, control the PMOS transistor to conduct, and the output interface outputs normally.
[0010] Optionally, the method further includes the following steps: when either the VBUS voltage or the output interface voltage is lower than the trigger protection voltage value, a short circuit fault is determined, and the PMOS transistor is controlled to turn off, and the output interface stops outputting.
[0011] Optionally, the method further includes the following steps: preset filtering time; when either the VBUS voltage or the output interface voltage is lower than the voltage threshold and the filtering time is met, it is determined to be a short circuit fault.
[0012] Optionally, the power supply protection circuit further includes a display module, and the power supply protection method further includes the following steps: when a short circuit fault occurs, the fault status is fed back through the display module.
[0013] Optionally, the method further includes the following steps: preset protection release voltage value; when both the VBUS voltage and the output interface voltage are greater than or equal to the protection release voltage value, control the PMOS transistor to turn on, and the output interface resumes normal output.
[0014] To address the problems existing in the prior art, the present invention also provides a portable power supply, which includes the aforementioned power supply protection circuit.
[0015] The beneficial effects of the power supply protection circuit provided in this embodiment of the invention are as follows: By synchronously acquiring voltage data through the VBUS voltage detection module and the output interface voltage detection module, the efficiency of capturing fault voltage signals is improved from the source. Moreover, any abnormal voltage detected by either channel can provide a basis for fault judgment, avoiding the protection trigger delay caused by voltage fluctuations in a single channel in traditional solutions, making the protection response faster. At the same time, the collaborative judgment of dual signals ensures the authenticity of the fault state, enabling the main controller to accurately output the PMOS transistor on / off control signal, avoiding the PMOS transistor from falling into the critical state of "conduction-cutoff", completely eliminating the risk of continuous short circuit / overcurrent output caused by unstable judgment in traditional solutions, and comprehensively protecting the safety of the power supply link and external devices. Attached Figure Description
[0016] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. In the drawings: Figure 1 is a structural block diagram of the power supply protection circuit in an embodiment of the present invention; Figure 2 is a circuit diagram of the output interface, output interface voltage detection module, and PMOS transistor in an embodiment of the present invention; Figure 3 is a circuit diagram of the DC-DC module and VBUS voltage detection module in an embodiment of the present invention; Figure 4 is a circuit diagram of the lithium battery pack and lithium battery protection module in an embodiment of the present invention; Figure 5 is a circuit diagram of the main controller in an embodiment of the present invention; Figure 6 is a flowchart of the power supply protection method in an embodiment of the present invention (Flowchart 1); Figure 7 is a flowchart of the power supply protection method in an embodiment of the present invention (Flowchart 2); Figure 8 is a flowchart of the power supply protection method in an embodiment of the present invention (Flowchart 3).
[0017] The labels in the figure are as follows: 10, lithium battery pack; 20, lithium battery protection module; 30, DC-DC module; 40, PMOS transistor; 50, output interface; 60, main controller; 70, VBUS voltage detection module; 80, output interface voltage detection module; 90, display module. Detailed Implementation
[0018] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
[0019] As shown in Figures 1 to 5, the present invention provides a specific embodiment of a power supply protection circuit.
[0020] A power supply protection circuit, referring to Figures 1 to 5, includes: a lithium battery pack 10, a lithium battery protection module 20, a DC-DC module 30, a PMOS transistor 40, an output interface 50, a main controller 60, a VBUS voltage detection module 70, and an output interface voltage detection module 80. The voltage output terminal of the lithium battery pack 10 is connected to the voltage input terminals of the lithium battery protection module 20 and the DC-DC module 30, respectively. The voltage output terminal of the DC-DC module 30 is connected to the source of the PMOS transistor 40, and the drain of the PMOS transistor 40 is connected to the output interface 50. The input terminal of the VBUS voltage detection module 70 is connected to the output terminal of the lithium battery pack 10, and the input terminal of the output interface voltage detection module 80 is connected to the output interface 50. The output terminals of both the VBUS voltage detection module 70 and the output interface voltage detection module 80 are connected to the main controller 60, and the output terminal of the main controller 60 is connected to the gate of the PMOS transistor 40.
[0021] Specifically, referring to Figures 1 to 5, the lithium battery pack 10 is the core power supply in the power supply protection circuit, providing DC power to the entire system. The voltage output terminal of the lithium battery pack 10 is connected to the voltage input terminals of the lithium battery protection module 20, the DC-DC module 30, and the main controller 60, respectively, to provide operating voltage to each module. The lithium battery protection module 20 is used to provide basic protection for the lithium battery pack 10, such as overcharge protection, over-discharge protection, overcurrent protection, and short circuit protection, to prevent the lithium battery pack 10 from being damaged due to abnormal operating conditions, thereby ensuring the safety and service life of the system.
[0022] DC-DC module 30 is a DC-DC voltage conversion unit. Its voltage input terminal is connected to the lithium battery pack 10 to receive the DC voltage output by the lithium battery pack 10 and boost or buck the DC voltage output by the lithium battery pack 10. Its voltage output terminal is connected to the output interface 50 to output a stable target voltage, providing constant power supply to the subsequent circuits, thereby meeting the power demand of the output interface 50. The output interface 50 is the terminal for outputting electrical energy to the outside world and is used to connect electronic devices to be charged.
[0023] The PMOS transistor 40 serves as an electronic switch for the output channel. Its on / off state is controlled by the gate signal output by the main controller 60. The PMOS transistor 40 is turned on during normal operation, allowing power to be transferred from the DC-DC module 30 to the output interface 50. It is turned off in fault condition, cutting off the power supply link to achieve a protection function. The output interface 50 is a Type-C port, which serves as a terminal for outputting power to the outside and is used to connect to electronic devices to be charged.
[0024] The main controller 60 is the core control unit of the entire power supply protection circuit, undertaking the functions of signal reception, logic judgment, and command output. The input terminals of the main controller 60 are connected to the VBUS voltage detection module 70 and the output interface voltage detection module 80 respectively to receive the voltage signals from the VBUS voltage detection module 70 and the output interface voltage detection module 80. The main controller 60 has preset protection logic. After receiving the voltage signals from the VBUS voltage detection module 70 and the output interface voltage detection module 80, it can determine whether the circuit is in a short circuit / overcurrent fault state according to the preset protection logic, and output the corresponding control signal to the gate of the PMOS transistor 40 according to the determination result, thereby controlling the PMOS transistor 40 to be turned on or off.
[0025] The VBUS voltage detection module 70 is a VBUS voltage acquisition unit. Its input terminal is connected to the voltage output terminal of the lithium battery pack 10 to detect the output voltage of the lithium battery pack 10 in real time, and convert the detected voltage signal into an electrical signal that can be recognized by the main controller 60 and feed it back to the main controller 60. The output interface voltage detection module 80 is an output voltage acquisition unit. Its input terminal is connected to the output interface 50 to detect the voltage value of the output terminal in real time. Together with the VBUS voltage detection module 70, it forms a dual voltage detection channel, providing the main controller 60 with a more comprehensive fault judgment basis.
[0026] In one embodiment, referring to Figures 1 to 5, the gate voltage divider resistor ratio of PMOS transistor 40 is 100K / 20K.
[0027] In this embodiment, the gate voltage divider resistor ratio of PMOS transistor 40 is set to 100K / 20K. When using PMOS transistor 40 with AET3122CE signal, its gate withstand voltage range is ±25V. When the circuit outputs a maximum voltage of 28V, the 100K / 20K voltage divider resistor can accurately control the gate voltage to about 23.3V. This value is lower than the 25V withstand voltage limit, which avoids the gate voltage from being too high and breaking down PMOS transistor 40. This ensures the long-term stable operation of the device and also provides sufficient withstand voltage redundancy to improve circuit reliability.
[0028] Furthermore, in the existing technology, the gate voltage divider resistor ratio of the PMOS transistor 40 is 100K / 51K. When the existing design is paired with a MOS transistor whose conduction voltage is slightly above the upper limit (about 2V), the VBUS voltage fluctuates around 3.1V under overcurrent conditions, which cannot continuously meet the protection triggering conditions. After adjusting to 100K / 20K, the voltage divider ratio is more reasonable. Even if the VBUS voltage drops below 3.1V, it can still provide a stable gate voltage for the PMOS transistor 40, keeping it in a stable conduction state. This ensures that the signal collected by the voltage detection module is fluctuation-free, and the main controller 60 can accurately determine the fault state, completely solving the problem of slow protection response.
[0029] Furthermore, in actual production, the turn-on voltage of PMOS transistor 40 varies from batch to batch, ranging from 1.6V to 2.0V. The traditional single resistor ratio cannot adapt to the full range of parameters. The 100K / 20K voltage divider ratio can provide a wider range of gate voltage adjustment. Regardless of the turn-on voltage of PMOS transistor 40 within the batch range, it can be made to work stably through voltage divider control. Combined with dual-channel voltage detection logic, it can effectively avoid protection failures or false triggers caused by differences in component parameters, reduce production and debugging costs, and improve product yield.
[0030] In one embodiment, referring to Figures 1 to 5, the power supply protection module further includes a display module 90. The display module 90 is bidirectionally connected to the main controller 60 and is used to provide real-time feedback on the circuit's operating status and the execution of protection actions. When the main controller 60 determines a short circuit / overcurrent fault and executes a protection action, it will synchronously send a fault signal to the display module 90. The display module 90 will display the fault to remind the user that there is a short circuit fault in the output interface 50 and that the external equipment or line problems need to be eliminated in time.
[0031] As shown in Figures 6 to 8, the present invention also provides a specific embodiment of a power supply protection method.
[0032] A power supply protection method, referring to Figure 6, is implemented through the aforementioned power supply protection circuit and includes the following steps: S1, preset the trigger protection voltage value; S2, collect the VBUS voltage and the output interface 50 voltage in real time, and compare the VBUS voltage and the output interface 50 voltage with the trigger protection voltage value; S31, when the VBUS voltage and the output interface 50 voltage are both equal to or greater than the trigger protection voltage value, control the PMOS transistor 40 to conduct, and the output interface 50 outputs normally.
[0033] S32. When either the VBUS voltage or the output interface 50 voltage is lower than the trigger protection voltage value, a short circuit fault is determined, and the PMOS transistor 40 is turned off, and the output interface 50 stops outputting.
[0034] Step 1: The key parameter for protection judgment, namely the trigger protection voltage value, is pre-written into the main controller 60. When the detected voltage is lower than the trigger protection voltage value, the voltage condition for fault judgment is met. When using a circuit architecture with 100K / 20K voltage divider resistors and AET3122CE PMOS transistor 40, the trigger protection voltage value is 3.1V. This value is based on the voltage drop pattern of short circuit faults and the conduction characteristics of PMOS transistor 40.
[0035] On the one hand, when a short circuit or severe overcurrent occurs at output interface 50, the load on the power supply link increases dramatically, causing the output voltage to drop rapidly. Extensive field testing has verified that, with a circuit architecture using 100K / 20K voltage divider resistors and an AET3122CE PMOS transistor 40, both the VBUS voltage and the output interface 50 voltage drop rapidly below 3.1V when a short circuit occurs, while during normal operation, both voltages remain consistently above this value. Therefore, 3.1V is the critical voltage value distinguishing between "normal operation" and "short circuit fault."
[0036] On the other hand, the AET3122CE PMOS transistor 40 has a turn-on voltage range of 1.6V-2.0V. Combined with 100K / 20K voltage divider resistors, when the voltage drops to 3.1V, the gate voltage of the PMOS transistor 40 is still in a stable control range and will not enter the critical conduction state. At this time, the voltage signal does not fluctuate, which can ensure that the main controller 60 accurately captures the fault state and avoids the failure of protection judgment due to voltage fluctuation.
[0037] Step 2: The VBUS voltage detection module 70 collects the voltage at the output terminal of the lithium battery pack 10 in real time, and the output interface voltage detection module 80 collects the voltage at the output interface 50 in real time. The VBUS voltage detection module 70 and the output interface voltage detection module 80 convert the collected analog voltage signals into digital signals that can be recognized by the main controller 60, and transmit them to the main controller 60 at a fixed frequency (e.g., 10ms / time). After receiving the two voltage data from the VBUS voltage detection module 70 and the output interface voltage detection module 80, the main controller 60 compares the VBUS voltage value and the output interface 50 voltage value with the preset 3.1V trigger protection voltage value to provide data support for anomaly judgment.
[0038] Step 3 is the judgment and execution step. When both the VBUS voltage value and the output interface 50 voltage value are not less than the trigger protection voltage value, the main controller 60 outputs the corresponding gate control signal to adjust the gate voltage of the PMOS transistor 40 to its conduction voltage range, so that the PMOS transistor 40 is in a fully conducting state. The stable voltage output by the DC-DC module is transmitted to the output interface 50 through the PMOS transistor 40, and the output interface 50 outputs a normal voltage, providing stable power to the external device. At the same time, the main controller 60 controls the display module 90 to output a "normal power supply" status indicator. When either the VBUS voltage value or the output interface 50 voltage value is lower than the trigger protection voltage value, the main controller 60 determines that there is a short circuit / overcurrent fault, immediately outputs a shutdown signal, adjusts the gate voltage of the PMOS transistor 40 to completely turn off the PMOS transistor 40, cuts off the power supply link, the output interface 50 stops outputting, and simultaneously sends a fault signal to the display module 90 for fault display.
[0039] In one embodiment, referring to FIG7, the method further includes the following steps: S41, preset filtering time; S42, when either the VBUS voltage or the output interface 50 voltage is lower than the voltage threshold and the filtering time is met, a short circuit fault is determined.
[0040] Specifically, during the initialization phase (synchronously executed with the preset trigger protection voltage value of S1), the main controller 60 pre-writes a filtering time parameter. The essence of the filtering time is the delayed confirmation window for fault determination. Only when the voltage is lower than the trigger protection voltage value for a duration that reaches or exceeds this window is it determined to be a real fault, rather than a momentary interference. In this embodiment, this parameter is set to 50ms. This parameter setting is based on the fact that when the power bank connects or disconnects external devices or during the fast charging protocol handshake phase, the output voltage will experience brief spike fluctuations (the duration is usually <20ms). The 50ms filtering time can completely cover the duration of such interference, avoiding false triggering of protection. Moreover, the 50ms delay will not affect the overall response speed, and can effectively improve the accuracy of determination, achieving rapid triggering of protection within 1 second.
[0041] In one embodiment, referring to FIG8, the following steps are also included: S51, preset protection release voltage value; S52, when both the VBUS voltage and the output interface 50 voltage are greater than or equal to the protection release voltage value, control the PMOS transistor 40 to conduct, and the output interface 50 resumes normal output.
[0042] Specifically, during the initialization phase (synchronously executed with the preset trigger protection voltage of S1 and the preset filtering time of S41), the main controller 60 pre-writes the protection release voltage value. The protection release voltage value is the core voltage threshold for determining whether a short circuit fault has been completely eliminated and whether the circuit is ready to restore power. It must meet the hysteresis design principle of "higher than the trigger protection voltage value". In this embodiment, this parameter is set to 3.3V. This parameter setting is based on the fact that the protection release voltage value (3.3V) is 0.2V higher than the trigger protection voltage value (3.1V), forming a hysteresis voltage difference. This design can avoid the repeated "protection-restore-reprotection" jitter phenomenon when the voltage fluctuates near the trigger threshold (3.1V), ensuring that the voltage state is stable after power restoration. Moreover, 3.3V is the minimum output voltage of PPS mode in the USB PD fast charging protocol. Setting it as the protection release voltage value can ensure that the output voltage directly meets the power supply requirements of the fast charging device after power restoration, without the need for additional voltage adjustment, improving product compatibility. Furthermore, when the dual-channel voltage rises back to 3.3V, the lithium battery pack 10 and DC-DC converter... The core components, such as the module and PMOS transistor 40, are all in a stable operating range. Restoring power at this time will not cause any impact on the components, ensuring the long-term reliability of the circuit.
[0043] It should be understood that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Those skilled in the art can modify the technical solutions described in the above embodiments, or make equivalent substitutions for some of the technical features; and all such modifications and substitutions should fall within the protection scope of the appended claims of the present invention.
Claims
1. A power supply protection circuit, characterized in that, include: The system includes a lithium battery pack, a lithium battery protection module, a DC-DC module, a PMOS transistor, an output interface, a main controller, a VBUS voltage detection module, and an output interface voltage detection module. The voltage output terminal of the lithium battery pack is connected to the voltage input terminals of the lithium battery protection module and the DC-DC module, respectively. The voltage output terminal of the DC-DC module is connected to the source of the PMOS transistor, and the drain of the PMOS transistor is connected to the output interface. The input terminal of the VBUS voltage detection module is connected to the output terminal of the lithium battery pack, and the input terminal of the output interface voltage detection module is connected to the output interface. The output terminals of both the VBUS voltage detection module and the output interface voltage detection module are connected to the main controller, and the output terminal of the main controller is connected to the gate of the PMOS transistor.
2. The power supply protection circuit according to claim 1, characterized in that, The gate voltage divider resistor ratio of the PMOS transistor is 100K / 20K.
3. The power supply protection circuit according to claim 1, characterized in that, It also includes a display module, which is connected to the main controller to provide feedback on the protection status.
4. The power supply protection circuit according to claim 1, characterized in that, The output interface is a Type-C port.
5. A power supply protection method, characterized in that, The power supply protection circuit described in any one of claims 1-4 is implemented by the following steps: preset the trigger protection voltage value; collect the VBUS voltage and the output interface voltage in real time, and compare the VBUS voltage and the output interface voltage with the trigger protection voltage value; when the VBUS voltage and the output interface voltage are both equal to or greater than the trigger protection voltage value, control the PMOS transistor to conduct, and the output interface outputs normally.
6. The power supply protection method according to claim 5, characterized in that, It also includes the following steps: When either the VBUS voltage or the output interface voltage is lower than the trigger protection voltage, a short circuit fault is identified, and the PMOS transistor is turned off, stopping the output interface from outputting.
7. The power supply protection method according to claim 6, characterized in that, It also includes the following steps: Preset filtering time; when either the VBUS voltage or the output interface voltage is lower than the voltage threshold and the filtering time is met, it is determined to be a short circuit fault.
8. The power supply protection method according to claim 6, characterized in that, The power supply protection circuit also includes a display module, and the power supply protection method further includes the following steps: when a short circuit fault occurs, the fault status is fed back through the display module.
9. The power supply protection method according to claim 6, characterized in that, It also includes the following steps: The preset protection release voltage value is set. When both the VBUS voltage and the output interface voltage are greater than or equal to the protection release voltage value, the control PMOS transistor is turned on, and the output interface resumes normal output.
10. A portable power bank, characterized in that, Includes the power supply protection circuit as described in any one of claims 1-4.