High-voltage power switch circuit for intelligent fusion terminal switch power supply

Abstract

The invention discloses a high-voltage power switch circuit for an intelligent fusion terminal switch power supply. The circuit comprises a voltage clamping circuit and an MOS tube cascade circuit. The voltage clamping circuit is connected in parallel between the DC bus voltage end and the grounding end, and forms a clamping voltage according to the first voltage and outputs the clamping voltage through the clamping output node. The MOS tube cascade circuit comprises a transformer and a cascade switch branch formed by connecting a first MOS tube and a second MOS tube in series, one end of the primary winding is connected with a first voltage, and the other end of the primary winding is grounded through the cascade switch branch; clamping voltage is connected to the grid electrode of the first MOS tube, grid electrode driving signals are connected to the grid electrode of the second MOS tube, and a voltage stabilizing diode is connected between the grid electrode and the source electrode of the first MOS tube in parallel. On-off is controlled through a grid driving signal, upper tube grid source driving is established under voltage limiting of a voltage stabilizing diode, controlled on-off of a primary side is achieved, dependence on a single ultrahigh-voltage-resistant MOS device is reduced, and the problems that model selection is limited and cost is high under high-voltage input are solved.

Description

Technical Field

[0001] This application relates to the field of high-voltage power switching circuit technology for intelligent converged terminal switching power supplies, and in particular to a high-voltage power switching circuit for intelligent converged terminal switching power supplies. Background Technology

[0002] In power distribution systems and various electronic devices, AC-DC switching power supplies are widely used to convert AC mains power into DC bus voltage, providing a stable DC power supply for subsequent power conversion and control circuits. As power electronic devices develop towards higher power density, miniaturization, and lower cost, the reliability of switching power supplies under high input voltage conditions and the cost of component selection are receiving increasing attention.

[0003] Various electronic devices in existing power distribution systems typically require AC-DC switching power supplies to convert mains power to DC bus power. For applications with a three-phase four-wire mains input, the DC-side voltage after full-wave rectification can reach approximately DC 700V. To ensure reliable operation of the switching power supply under these high-voltage bus conditions, engineering often requires the selection of high-voltage MOSFETs with a drain-source withstand voltage greater than 1kV as power switching devices. However, in practical applications, these high-voltage MOSFETs generally suffer from limited selection options, difficulty in selection, and high device costs.

[0004] Therefore, in the design of AC-DC switching power supplies with high-voltage bus input, the selection of high-voltage power switching devices is limited and the cost is high. It is also difficult to achieve reliable voltage bearing and safe switching control of power switches under high input voltage conditions, which has become an urgent technical problem to be solved. Summary of the Invention

[0005] This application provides a high-voltage power switching circuit for a smart fusion terminal switching power supply, aiming to solve the problems in the design of AC-DC switching power supplies with high-voltage bus input, such as the limited selection and high cost of high-voltage power switching devices, and the difficulty in achieving reliable voltage bearing and safe switching control of power switches under high input voltage conditions.

[0006] In a first aspect, a high-voltage power switching circuit for a smart fusion terminal switching power supply is provided, the circuit comprising a voltage clamping circuit and a cascaded MOSFET circuit.

[0007] The voltage clamping circuit is connected in parallel between the DC bus voltage terminal and the ground terminal. The voltage clamping circuit is used to form a clamping voltage based on the first voltage output from the DC bus voltage terminal. The voltage clamping circuit is provided with a clamping output node to output the clamping voltage.

[0008] The cascaded MOS transistor circuit includes a cascaded switch branch and a transformer. The cascaded switch branch is used to connect to the primary winding of the transformer and to control the on / off state of the primary winding.

[0009] The cascaded switch branch includes a first MOSFET and a second MOSFET. The gate of the first MOSFET is used to receive the clamping voltage, and the gate of the second MOSFET is used to receive the gate drive signal. The source of the first MOSFET is electrically connected to the drain of the second MOSFET. The drain of the first MOSFET is electrically connected to one end of the primary winding. The source of the second MOSFET is grounded. A Zener diode is connected in parallel between the gate and the source of the first MOSFET.

[0010] The second end of the primary winding is connected to the first voltage;

[0011] When the gate drive signal is high, the second MOS transistor is turned on, causing the potential of the electrical connection node between the source and drain of the first MOS transistor to change towards the ground terminal. Thus, under the voltage limiting effect of the Zener diode, a gate-source voltage is formed between the gate and source of the first MOS transistor to drive the first MOS transistor to turn on.

[0012] When the gate drive signal is low, the second MOS transistor is turned off, and the clamping voltage connected to the gate of the first MOS transistor causes the first MOS transistor to be in a turned-off state, so as to control the on / off state of the primary winding of the transformer through the cascaded switch branch.

[0013] Optionally, in the above scheme, the voltage clamping circuit includes a series branch formed by connecting a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first diode, and a second diode in series; wherein, one end of the first resistor is connected to the first voltage, and one end of the second diode is electrically connected to the ground terminal.

[0014] Optionally, in the above scheme, both the first diode and the second diode are unidirectional transient suppression diodes, and when the first diode and the second diode are connected in series, the cathode of the first diode is electrically connected to the anode of the second diode.

[0015] Optionally, in the above scheme, the connection point between the fourth resistor and the fifth resistor is the clamping output node.

[0016] Optionally, in the above scheme, the fifth resistor is used to limit the current of the first diode and the second diode.

[0017] In the above scheme, optionally, the Zener diode is a Zener diode, and the reverse voltage regulation value of the Zener diode is 10V to 15V.

[0018] Optionally, in the above scheme, an eighth resistor is connected in parallel between the gate and source of the second MOS transistor, and the resistance of the eighth resistor is 10kΩ to 200kΩ.

[0019] In the above scheme, optionally, the resistance values ​​of the first resistor, the second resistor, the third resistor, and the fourth resistor are 750kΩ, and the resistance value of the fifth resistor is 47Ω.

[0020] Optionally, in the above scheme, the gate drive signal is a pulse width modulation signal.

[0021] In a second aspect, an AC-DC switching power supply includes a rectifier and filter unit and a power conversion unit; the rectifier and filter unit is used to rectify and filter the AC input to form the first voltage; the power conversion unit includes the high-voltage power switching circuit for the intelligent fusion terminal switching power supply described in the first aspect.

[0022] Compared with the prior art, this application has at least the following beneficial effects:

[0023] Based on further analysis and research of existing technical problems, this application recognizes that in the design of AC-DC switching power supplies with high-voltage bus input, the selection of high-voltage power switching devices is limited and the cost is high. Furthermore, it addresses the difficulty in achieving reliable voltage withstand and safe switching control of the power switch under high input voltage conditions. This high-voltage power switching circuit decomposes the main power switching function into a cooperative structure where "the voltage clamping circuit outputs a clamping voltage Vclamp and directly connects it to the gate of the first MOSFET Q1" and "the second MOSFET Q2 is directly driven by the gate drive signal GATE." When GATE is high, the second MOSFET Q2 is turned on. The connection node potential between the source of the first MOSFET Q1 and the drain of the second MOSFET Q2 is pulled towards ground, thereby naturally establishing a gate-source voltage between the gate (fixed to Vclamp) and the source of the first MOSFET Q1. This gate-source voltage is limited within a controllable range by the Zener diode ZD1 connected in parallel between the gate and source of the first MOSFET Q1. Under the limited voltage driving condition, the first MOSFET Q1 is turned on, and the cascade switch branch is turned on to energize the primary winding of the transformer T1. When GATE is low, the second MOSFET Q2 is turned off, the cascade switch branch is cut off, thereby achieving power-off control of the primary winding of the transformer T1.

[0024] This solution uses two cascaded MOS devices to form a high-voltage switching path. It achieves the on / off control of the primary side of the transformer on the high-voltage DC bus by using "Vclamp to provide the gate reference of the upper MOSFET, ZD1 to limit the gate-source voltage of the upper MOSFET, and the GATE to implement the switching cycle of the lower MOSFET". This allows the high-voltage load requirement to be shared by the cascaded switching branches instead of falling entirely on a single device. Therefore, in AC-DC switching power supply scenarios with high-voltage bus input, it can meet the high-voltage side switching control requirements while reducing the dependence on a single ultra-high voltage MOS device. This solves the problems in the existing technology of "limited selection and high cost of high-voltage power switching devices, and difficulty in reliable voltage bearing and safe switching control under high input voltage conditions". Attached Figure Description

[0025] Figure 1 A schematic diagram of the application environment for a high-voltage power switching circuit for a smart fusion terminal switching power supply provided in one embodiment of this application;

[0026] Figure 2 A block diagram of a cascaded MOS transistor circuit provided in one embodiment of this application;

[0027] Figure 3 This is a block diagram illustrating the working principle of a switching power supply according to an embodiment of this application. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0029] In one embodiment, such as Figure 1 As shown, a high-voltage power switching circuit for a smart fusion terminal switching power supply is provided, the circuit including a voltage clamping circuit and a cascaded MOSFET circuit;

[0030] The voltage clamping circuit is connected in parallel between the DC bus voltage terminal and the ground terminal. The voltage clamping circuit is used to form a clamping voltage based on the first voltage output from the DC bus voltage terminal. The voltage clamping circuit is provided with a clamping output node to output the clamping voltage.

[0031] The cascaded MOS transistor circuit includes a cascaded switch branch and a transformer T1. The cascaded switch branch is used to connect to the primary winding of the transformer T1 and to control the on / off state of the primary winding.

[0032] The cascaded switch branch includes a first MOSFET Q1 and a second MOSFET Q2. The gate of the first MOSFET Q1 is used to receive the clamping voltage, and the gate of the second MOSFET Q2 is used to receive the gate drive signal. The source of the first MOSFET Q1 is electrically connected to the drain of the second MOSFET Q2. The drain of the first MOSFET Q1 is electrically connected to one end of the primary winding. The source of the second MOSFET Q2 is grounded. A Zener diode ZD1 is connected in parallel between the gate and the source of the first MOSFET Q1.

[0033] The second end of the primary winding is connected to the first voltage;

[0034] When the gate drive signal is high, the second MOS transistor Q2 is turned on, causing the potential of the electrical connection node between the source of the first MOS transistor Q1 and the drain of the second MOS transistor Q2 to change towards the ground terminal. Thus, under the voltage limiting effect of the Zener diode ZD1, a gate-source voltage is formed between the gate and source of the first MOS transistor Q1 to drive the first MOS transistor Q1 to turn on.

[0035] When the gate drive signal is low, the second MOS transistor Q2 is turned off, and the clamping voltage connected to the gate of the first MOS transistor Q1 causes the first MOS transistor Q1 to be in a turned-off state, so as to control the on / off state of the primary winding of the transformer T1 through the cascaded switch branch.

[0036] like Figure 1 and Figure 2 As shown, the high-voltage power switching circuit of the switching power supply in this embodiment includes a voltage clamping circuit and a cascaded MOSFET circuit. The voltage clamping circuit is connected in parallel between the DC bus voltage terminal and the ground terminal, and is used to form a clamping voltage Vclamp based on the first voltage UDC output from the DC bus voltage terminal. A clamping output node is set on the voltage clamping circuit to output the clamping voltage Vclamp.

[0037] The cascaded MOSFET circuit includes a cascaded switch branch and a transformer T1. The cascaded switch branch includes a first MOSFET Q1 and a second MOSFET Q2, wherein: the source of the first MOSFET Q1 is electrically connected to the drain of the second MOSFET Q2; the drain of the first MOSFET Q1 is electrically connected to one end of the primary winding of the transformer T1; and the source of the second MOSFET Q2 is grounded. The second end of the primary winding of the transformer T1 is connected to the first voltage UDC. The gate of the first MOSFET Q1 is connected to the clamping voltage Vclamp, and the gate of the second MOSFET Q2 is connected to the gate drive signal GATE. Simultaneously, a Zener diode ZD1 is connected in parallel between the gate and source of the first MOSFET Q1 to limit the gate-source voltage of the first MOSFET Q1.

[0038] When the gate drive signal GATE is high, the second MOSFET Q2 is turned on, causing the potential of the connection node between the source of the first MOSFET Q1 and the drain of the second MOSFET Q2 to change towards the ground terminal. Under the voltage limiting effect of the Zener diode ZD1, a gate-source voltage is formed between the gate and source of the first MOSFET Q1, thereby driving the first MOSFET Q1 to turn on. At this time, the cascaded switch branch is turned on, and the primary winding of the transformer T1 forms a current path from the first voltage UDC through the primary winding, the first MOSFET Q1, the second MOSFET Q2 to the ground terminal, realizing the energization control of the primary winding.

[0039] When the gate drive signal GATE is low, the second MOS transistor Q2 is turned off; the gate of the first MOS transistor Q1 is connected to the clamping voltage Vclamp and is in the corresponding gate-source bias state under the constraint of the Zener diode ZD1, so that the cascaded switch branch is in the off-path state, thereby realizing the power-off control of the primary winding of transformer T1.

[0040] This embodiment uses a combination structure in which "the clamping voltage Vclamp output by the voltage clamping circuit is connected to the gate of the first MOSFET Q1, the second MOSFET Q2 is driven by the gate drive signal GATE, and the Zener diode ZD1 limits the gate-source voltage of the first MOSFET Q1". This structure enables controlled switching of the primary winding of transformer T1 under high-voltage DC bus conditions and reduces the dependence on a single ultra-high voltage power switching device. This helps to alleviate the problems of limited selection and high cost of high-voltage MOSFETs.

[0041] In this embodiment, the voltage clamping circuit includes a series branch formed by connecting a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first diode TVS1, and a second diode TVS2 in series. One end of the first resistor R1 is connected to the first voltage, and one end of the second diode TVS2 is electrically connected to the ground terminal.

[0042] In a preferred embodiment, the voltage clamping circuit includes a series branch formed by connecting a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first diode TVS1, and a second diode TVS2 in series.

[0043] The series branch is connected between the first voltage UDC and the ground terminal. For example, one end of the first resistor R1 is connected to the first voltage UDC, and one end of the second diode TVS2 is electrically connected to the ground terminal, so that the series branch is connected in parallel between the DC bus voltage terminal and the ground terminal, so as to form corresponding voltage division and clamping working conditions when the first voltage UDC changes.

[0044] This embodiment provides a clear circuit implementation path for the formation of the clamping voltage Vclamp by setting a series branch consisting of the first resistor R1 to the fifth resistor R5 and the first diode TVS1 and the second diode TVS2 between the first voltage UDC and the ground terminal, thereby improving the feasibility and reproducibility of the voltage clamping circuit.

[0045] In this embodiment, both the first diode TVS1 and the second diode TVS2 are unidirectional transient suppression diodes, and when the first diode TVS1 and the second diode TVS2 are connected in series, the cathode of the first diode TVS1 is electrically connected to the anode of the second diode TVS2.

[0046] In one embodiment, both the first diode TVS1 and the second diode TVS2 are unidirectional transient suppression diodes; and when the first diode TVS1 and the second diode TVS2 are connected in series, the cathode of the first diode TVS1 is electrically connected to the anode of the second diode TVS2, so as to clarify the series connection direction and electrode connection relationship of the two unidirectional transient suppression diodes.

[0047] The parameters of the first diode TVS1 and the second diode TVS2, such as reverse breakdown voltage and peak pulse power, can be matched according to the range of the first voltage UDC to meet the operating requirements of the voltage clamping circuit under steady-state and transient conditions.

[0048] This embodiment clarifies the electrode connection relationship between the first diode TVS1 and the second diode TVS2, enabling the series transient suppression diode to form a definite clamping action in a predetermined polarity direction, thereby reducing the risk of uncertain operating state caused by unclear polarity.

[0049] In this embodiment, the connection point between the fourth resistor R4 and the fifth resistor R5 is the clamping output node.

[0050] In one embodiment, the connection point of the fourth resistor R4 and the fifth resistor R5 is defined as the clamp output node. The clamp output node outputs the clamp voltage Vclamp and is electrically connected to the gate of the first MOS transistor Q1, so that the gate of the first MOS transistor Q1 is connected to the clamp voltage Vclamp.

[0051] Since the fourth resistor R4 and the fifth resistor R5 are located at the end of the resistor chain and are adjacent to the regions where the first diode TVS1 and the second diode TVS2 are located, the clamping voltage Vclamp can be correlated with the voltage division of the resistor chain and the operating state of the transient suppression diode by sampling at the connection end of the fourth resistor R4 and the fifth resistor R5.

[0052] This embodiment, by explicitly defining the clamp output node as the connection point of the fourth resistor R4 and the fifth resistor R5, makes the output position of the clamp voltage Vclamp uniquely determined, which facilitates the annotation of the drawings and the reproduction of the prototype, and improves the sufficiency and consistency of the disclosure.

[0053] In this embodiment, the fifth resistor R5 is used to limit the current of the first diode TVS1 and the second diode TVS2.

[0054] In one embodiment, the fifth resistor R5 is configured as an element for limiting the current of the first diode TVS1 and the second diode TVS2, and its resistance value is selected according to the range of the first voltage UDC, the rated parameters of the first diode TVS1 and the second diode TVS2, and the expected transient current.

[0055] When the first voltage UDC increases and causes the first diode TVS1 and the second diode TVS2 to enter the clamping working range, the fifth resistor R5 limits the current of the corresponding branch; when the first diode TVS1 and the second diode TVS2 do not enter the clamping working range, the fifth resistor R5, together with the first resistor R1 to the fourth resistor R4, participates in biasing and voltage division.

[0056] In this embodiment, the current of the first diode TVS1 and the second diode TVS2 is limited by the fifth resistor R5, which can reduce the current stress of the transient suppression diode during the clamping process and improve the working stability of the voltage clamping circuit under high voltage and transient conditions.

[0057] In this embodiment, the Zener diode ZD1 is a Zener diode, and the reverse voltage regulation value of the Zener diode ZD1 is 10V to 15V.

[0058] In one embodiment, the Zener diode ZD1 is a Zener diode, connected in parallel between the gate and source of the first MOSFET Q1; the reverse voltage regulation value of the Zener diode ZD1 is selected to be 10V to 15V, which is used to limit the gate-source voltage of the first MOSFET Q1.

[0059] When the gate drive signal GATE is high and the second MOSFET Q2 is turned on, the gate of the first MOSFET Q1 is connected to the clamping voltage Vclamp, and the gate-source voltage of the first MOSFET Q1 is established as the connection node potential changes; at this time, the Zener diode ZD1 enters the voltage regulation region and limits the gate-source voltage of the first MOSFET Q1.

[0060] In this embodiment, by connecting a Zener diode ZD1 with a reverse voltage regulation value of 10V to 15V in parallel between the gate and source of the first MOSFET Q1, the gate-source voltage of the first MOSFET Q1 can be limited, reducing the risk of gate-source overvoltage and improving the determinism of the driving conditions of the cascaded switch branch.

[0061] In this embodiment, an eighth resistor R8 is connected in parallel between the gate and source of the second MOS transistor Q2, and the resistance of the eighth resistor R8 is 10kΩ to 200kΩ.

[0062] In one embodiment, an eighth resistor R8 is connected in parallel between the gate and source of the second MOSFET Q2 to provide a discharge and reference path for the gate of the second MOSFET Q2.

[0063] When the gate drive signal GATE switches from high level to low level or is in a high impedance state, the eighth resistor R8 provides a path for the gate charge release of the second MOS transistor Q2, so that the gate potential of the second MOS transistor Q2 returns to the reference potential range consistent with the source, thereby cooperating to turn off the second MOS transistor Q2.

[0064] In this embodiment, by connecting an eighth resistor R8 in parallel between the gate and source of the second MOSFET Q2, the controllability and stability of the gate potential of the second MOSFET Q2 can be enhanced, and the probability of malfunction caused by gate drift can be reduced.

[0065] In this embodiment, the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 are 750kΩ, and the resistance value of the fifth resistor R5 is 47Ω.

[0066] In one embodiment, the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 are all 750kΩ, and the fifth resistor R5 is 47Ω, which is used as a specific parameter configuration for the voltage clamping circuit.

[0067] The first resistor R1 to the fourth resistor R4 are high-resistance resistors of the same value, which facilitates the voltage divider configuration of the resistor chain and the standardization of components; the fifth resistor R5 is a small-value resistor to limit the branch current of the first diode TVS1 and the second diode TVS2. In actual design, the selection can be checked based on the range of the first voltage UDC and the rated parameters of the first diode TVS1 and the second diode TVS2.

[0068] This embodiment provides a parameter example that can be directly implemented by giving specific resistance values ​​for the first resistor R1 to the fourth resistor R4 of 750kΩ and the fifth resistor R5 of 47Ω, which facilitates engineering implementation and scheme reproduction.

[0069] In this embodiment, the gate drive signal is a pulse width modulation signal.

[0070] In one embodiment, the gate drive signal GATE is a pulse width modulation signal, which is output by the control chip or driver and input to the gate of the second MOS transistor Q2. The frequency and duty cycle of the pulse width modulation signal are set according to the switching power supply topology and output control requirements.

[0071] When the pulse width modulation signal is at a high level, the second MOSFET Q2 is turned on and, together with the first MOSFET Q1, turns on to turn on the cascaded switch branch; when the pulse width modulation signal is at a low level, the second MOSFET Q2 is turned off and the cascaded switch branch is turned off, thereby realizing the periodic on-off control of the primary winding of transformer T1.

[0072] This embodiment uses a pulse width modulation signal as the gate drive signal GATE, which enables the cascaded switch branch to periodically switch on and off according to the switching power supply control law, improving the compatibility with common control chip drive output forms.

[0073] In this embodiment, both the first diode TVS1 and the second diode TVS2 are unidirectional transient suppression diodes, specifically SMAJ220A, with a reverse conduction voltage of 246V to 274V; the Zener diode ZD1 is a BZT52C12 with a clamping voltage of 12V; the first MOSFET Q1 and the second MOSFET Q2 are CR7N65A4K, with a drain-source current of 7A and a drain-source voltage of 650V.

[0074] In the voltage clamping circuit, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the first diode TVS1 and the second diode TVS2 are connected in series to form a series branch. The two ends of this series branch are connected in parallel across the input voltage terminals, i.e., between the first voltage UDC and ground. A clamping voltage Vclamp is drawn between the fourth resistor R4 and the fifth resistor R5, and this clamping voltage Vclamp is connected to the gate of the first MOSFET Q1. The voltage clamping circuit is used to generate the clamping voltage Vclamp, and this clamping voltage Vclamp is less than the drain-source withstand voltage of 650V for either the first MOSFET Q1 or the second MOSFET Q2.

[0075] In the cascaded MOSFET circuit, the first voltage UDC is connected to the upper end of the primary winding of transformer T1; the drain of the first MOSFET Q1 is connected to the lower end of the primary winding of transformer T1; the source of the first MOSFET Q1 is electrically connected to the drain of the second MOSFET Q2; a Zener diode ZD1 is connected in parallel between the gate and source of the first MOSFET Q1; an eighth resistor R8 is connected in parallel between the gate and source of the second MOSFET Q2; the source of the second MOSFET Q2 is connected to the power supply ground; and the gate of the second MOSFET Q2 is connected to the gate drive signal GATE.

[0076] When the first voltage UDC < 500V, the first voltage UDC is less than the sum of the reverse conduction voltages of the first diode TVS1 and the second diode TVS2. Therefore, no current flows through the first diode TVS1 and the second diode TVS2, and the clamping voltage Vclamp is the first voltage UDC.

[0077] When the gate drive signal GATE is low, the second gate-source voltage VGS2 is 0V, and the second MOSFET Q2 is in an open circuit state; the first gate-source voltage VGS1 is 0V, and the first MOSFET Q1 is in an open circuit state. At this time, the first voltage UDC is shared by the first MOSFET Q1 and the second MOSFET Q2.

[0078] When the gate drive signal GATE is high, the second gate-source voltage VGS2 is 12V, the second MOSFET Q2 is turned on, and the second drain-source voltage VDS2 is approximately 0.3V, close to 0V. At this time, the first voltage UDC forms a current loop through the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the Zener diode ZD1, and the second MOSFET Q2. The first gate-source voltage VGS1 is clamped at 12V by the Zener diode ZD1, causing the first MOSFET Q1 to turn on, and the primary winding current of the transformer T1 flows to complete the magnetization.

[0079] When 500V < first voltage UDC < 700V, the first voltage UDC is greater than the sum of the reverse conduction voltages of the first diode TVS1 and the second diode TVS2. Therefore, current flows through the first diode TVS1 and the second diode TVS2. The clamping voltage Vclamp is 500V. The fifth resistor R5 is used to limit the current of the first diode TVS1 and the second diode TVS2.

[0080] When the gate drive signal GATE is low, the second gate-source voltage VGS2 is 0V, and the second MOSFET Q2 is in an open circuit state; the first gate-source voltage VGS1 is 0V, and the first MOSFET Q1 is in an open circuit state. At this time, the first voltage UDC is shared by the first MOSFET Q1 and the second MOSFET Q2, where the second drain-source voltage VDS2 is approximately 500V, and the first drain-source voltage VDS1 is approximately the first voltage UDC - 500V.

[0081] When the gate drive signal GATE is high, the second gate-source voltage VGS2 is 12V, the second MOSFET Q2 is turned on, and the second drain-source voltage VDS2 is approximately 0.3V, close to 0V. At this time, the first voltage UDC forms a current loop through the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the Zener diode ZD1, and the second MOSFET Q2. The first gate-source voltage VGS1 is clamped at 12V by the Zener diode ZD1, causing the first MOSFET Q1 to turn on, and the primary winding current of the transformer T1 flows to complete the magnetization.

[0082] In one embodiment, such as Figure 3 As shown, an AC-DC switching power supply is provided, which includes a rectification and filtering unit and a power conversion unit; the rectification and filtering unit is used to rectify and filter the AC input to form the first voltage; the power conversion unit includes a high-voltage power switching circuit as described for a smart fusion terminal switching power supply.

[0083] In one embodiment, the AC-DC switching power supply includes a rectifier and filter unit and a power conversion unit. The rectifier and filter unit is used to rectify and filter the AC input to form the first voltage UDC; the power conversion unit includes the high-voltage power switching circuit of the switching power supply described in the above embodiment, and together with the transformer T1 and the secondary rectifier and filter circuit, constitutes a power conversion structure.

[0084] When the AC input is a three-phase four-wire mains power, the rectifier and filter unit can use a three-phase full-wave rectifier bridge and a bus capacitor to form a DC bus voltage, i.e., the first voltage UDC; the high-voltage power switch circuit, as the main switch part, controls the primary winding of transformer T1 to switch on and off under the control of the gate drive signal GATE, thereby realizing the energy transfer required for the output of the subsequent stage.

[0085] Applying the high-voltage power switching circuit of the switching power supply described in the above embodiments to an AC-DC switching power supply unit can realize the controlled switching of the primary winding of transformer T1 under high-voltage DC bus conditions, providing feasible main power switching circuit solutions for engineering applications in high-voltage input scenarios.

[0086] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A high-voltage power switching circuit for a smart converged terminal switching power supply, characterized in that, The circuit includes a voltage clamping circuit and a cascaded MOSFET circuit; The voltage clamping circuit is connected in parallel between the DC bus voltage terminal and the ground terminal. The voltage clamping circuit is used to form a clamping voltage based on the first voltage output from the DC bus voltage terminal. The voltage clamping circuit is provided with a clamping output node to output the clamping voltage. The cascaded MOS transistor circuit includes a cascaded switch branch and a transformer (T1). The cascaded switch branch is used to connect to the primary winding of the transformer (T1) and to control the on / off state of the primary winding. The cascaded switch branch includes a first MOSFET (Q1) and a second MOSFET (Q2). The gate of the first MOSFET (Q1) is used to receive the clamping voltage, and the gate of the second MOSFET (Q2) is used to receive the gate drive signal. The source of the first MOSFET (Q1) is electrically connected to the drain of the second MOSFET (Q2). The drain of the first MOSFET (Q1) is electrically connected to one end of the primary winding. The source of the second MOSFET (Q2) is grounded. A Zener diode (ZD1) is connected in parallel between the gate and source of the first MOSFET (Q1). The second end of the primary winding is connected to the first voltage; When the gate drive signal is high, the second MOS transistor (Q2) is turned on, causing the potential of the electrical connection node between the source of the first MOS transistor (Q1) and the drain of the second MOS transistor (Q2) to change towards the ground terminal. Thus, under the voltage limiting effect of the Zener diode (ZD1), a gate-source voltage is formed between the gate and source of the first MOS transistor (Q1) to drive the first MOS transistor (Q1) to turn on. When the gate drive signal is low, the second MOS transistor (Q2) is turned off, and the clamping voltage connected to the gate of the first MOS transistor (Q1) causes the first MOS transistor (Q1) to be in a turned-off state, so as to control the on / off state of the primary winding of the transformer (T1) through the cascaded switch branch.

2. The circuit according to claim 1, characterized in that, The voltage clamping circuit includes a series branch formed by connecting a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (R4), a fifth resistor (R5), a first diode (TVS1), and a second diode (TVS2) in series in sequence; wherein, one end of the first resistor (R1) is connected to the first voltage, and one end of the second diode (TVS2) is electrically connected to the ground terminal.

3. The circuit according to claim 2, characterized in that, Both the first diode (TVS1) and the second diode (TVS2) are unidirectional transient suppression diodes, and when the first diode (TVS1) and the second diode (TVS2) are connected in series, the cathode of the first diode (TVS1) is electrically connected to the anode of the second diode (TVS2).

4. The circuit according to claim 2, characterized in that, The connection point between the fourth resistor (R4) and the fifth resistor (R5) is the clamping output node.

5. The circuit according to claim 2, characterized in that, The fifth resistor (R5) is used to limit the current of the first diode (TVS1) and the second diode (TVS2).

6. The circuit according to claim 1, characterized in that, The Zener diode (ZD1) is a Zener diode, and the reverse voltage regulation value of the Zener diode (ZD1) is 10V to 15V.

7. The circuit according to claim 1, characterized in that, An eighth resistor (R8) is connected in parallel between the gate and source of the second MOS transistor (Q2), and the resistance of the eighth resistor (R8) is 10kΩ to 200kΩ.

8. The circuit according to claim 2, characterized in that, The resistance values ​​of the first resistor (R1), the second resistor (R2), the third resistor (R3), and the fourth resistor (R4) are 750kΩ, and the resistance value of the fifth resistor (R5) is 47Ω.

9. The circuit according to claim 1, characterized in that, The gate drive signal is a pulse width modulation signal.

10. An AC-DC switching power supply, characterized in that, It includes a rectifier and filter unit and a power conversion unit; the rectifier and filter unit is used to rectify and filter the AC input to form the first voltage; the power conversion unit includes a high-voltage power switching circuit for a smart fusion terminal switching power supply as described in any one of claims 1 to 9.

Images