Transformer-based biasing circuit for push-pull frequency multiplier
By using a transformer-based bias circuit, and by utilizing an input matching network and an elimination network to bias the transistors in the core of the CMOS frequency multiplier, the problems of high phase noise and signal loss in high-frequency signal generation in millimeter-wave systems are solved, resulting in higher voltage swing and lower power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NXP BV
- Filing Date
- 2025-10-27
- Publication Date
- 2026-05-01
AI Technical Summary
High-frequency signal generation in millimeter-wave systems faces challenges such as high phase noise, narrowband operation, and signal loss related to signal distribution.
A transformer-based bias circuit is adopted, including an input matching network and a cancellation network. The transistors of the CMOS frequency multiplier core are biased by applying a bias voltage through the primary and secondary inductors of the transformer and the center tap. The common-mode loop current is eliminated by a capacitive common-mode cancellation network.
It improves voltage swing, reduces phase noise, reduces circuit sensitivity to center tap impedance, and reduces voltage loss and power consumption within the same circuit area.
Smart Images
Figure CN121966460A_ABST
Abstract
Description
Technical Field
[0001] This disclosure generally relates to complementary metal-oxide-semiconductor push-pull frequency multiplier circuits, and more specifically to transformer-based bias circuits for the core of push-pull frequency multiplier circuits. Background Technology
[0002] High-frequency signal generation in millimeter-wave systems may present challenges such as high phase noise, narrowband operation, and signal loss associated with signal distribution. Summary of the Invention
[0003] According to a first aspect of the present invention, a circuit is provided, comprising:
[0004] An output transformer includes a primary output inductor inductively coupled to a secondary output inductor, the primary output inductor including a first terminal and a second terminal;
[0005] The frequency multiplier core includes a first transistor pair and a second transistor pair. The first transistor pair is coupled between a first power supply terminal and a first terminal of the primary output inductor. The first transistor pair includes a first gate and a second gate. The second transistor pair is coupled between a second power supply terminal and a second terminal of the primary output inductor. The second transistor pair includes a third gate and a fourth gate.
[0006] An input matching network includes an input transformer, the input transformer comprising:
[0007] A primary inductor, configured to receive an input signal having a first frequency;
[0008] A first-stage inductor, inductively coupled to the primary inductor and including a third terminal coupled to the first gate, a fourth terminal coupled to the second gate, and a first center tap configured to receive a first bias voltage to bias the first and second gates of the first transistor pair; and
[0009] A second-stage inductor, inductively coupled to the primary inductor, includes a fifth terminal coupled to the third gate, a sixth terminal coupled to the fourth gate, and a second center tap configured to receive a second bias voltage to bias the third and fourth gates of the second transistor pair.
[0010] In one or more embodiments, the circuit further includes:
[0011] Elimination network, coupled to the input matching network, the elimination network comprising:
[0012] A first capacitor includes a first capacitor terminal coupled to the third terminal of the first primary inductor and a second capacitor terminal coupled to the fifth terminal of the second secondary inductor; and
[0013] The second capacitor includes a third capacitor terminal coupled to the fourth terminal of the first stage inductor and a fourth capacitor terminal coupled to the sixth terminal of the second stage inductor.
[0014] In one or more embodiments, the elimination network eliminates common-mode loop current, thereby reducing the sensitivity of the output signal to the impedance of the first and second center taps.
[0015] In one or more embodiments, the first and second capacitors of the elimination network provide current paths to overcome the capacitive effect of the gate-to-drain capacitance of the first and second transistor pairs.
[0016] In one or more embodiments, the first bias voltage biases the gate of the first transistor pair, and the second bias voltage biases the gate of the second transistor pair.
[0017] In one or more embodiments, the second frequency of the output signal at the secondary output inductor is approximately twice the first frequency.
[0018] In one or more embodiments, the first transistor pair includes:
[0019] A first transistor includes a source coupled to a first supply voltage terminal, a first gate coupled to the third terminal of the primary primary inductor, and a drain coupled to the first terminal of the primary output inductor; and
[0020] The second transistor includes a source coupled to the first supply voltage terminal, a second gate coupled to the fourth terminal of the primary inductor, and a drain coupled to the first terminal of the primary output inductor; and
[0021] The second transistor pair includes:
[0022] The third transistor includes a source coupled to a second supply voltage terminal, a third gate coupled to the fifth terminal of the second secondary inductor, and a drain coupled to the second terminal of the primary output inductor; and
[0023] The fourth transistor includes a source coupled to the second supply voltage terminal, a fourth gate coupled to the sixth terminal of the second stage inductor, and a drain coupled to the second terminal of the primary output inductor.
[0024] In one or more embodiments, the input matching network further includes one or more third-stage inductors.
[0025] According to a second aspect of the present invention, a method for doubling the frequency of an input signal is provided, the method comprising:
[0026] A first bias voltage is applied to the first center tap of the first stage inductor of the input transformer of the input matching network, the input transformer further including a primary inductor inductively coupled to the second stage inductor;
[0027] A second bias voltage is applied to the second center tap of the secondary inductor;
[0028] An input signal having a first frequency is received at the primary inductor;
[0029] A first signal related to the input signal is generated at the first and second terminals of the first-stage inductor, and a second signal related to the input signal is generated at the third and fourth terminals of the second-stage inductor;
[0030] The first gate of the first transistor pair in the frequency multiplier core circuit is biased with the first bias voltage to generate a first frequency multiplier signal, and the second gate of the second transistor pair in the frequency multiplier core circuit is biased with the second bias voltage to generate a second frequency multiplier signal.
[0031] The first frequency multiplier signal is applied to a first terminal of the primary output inductor of the output transformer, the output transformer having a secondary output inductor inductively coupled to the primary output inductor; and
[0032] The second frequency multiplier signal is applied to the second terminal of the primary output inductor to provide an output signal at the secondary output inductor, the output signal having a second frequency that is twice the first frequency.
[0033] In one or more embodiments, the method further includes:
[0034] Common-mode loop current is eliminated using a cancellation network coupled to the first and second stage inductors, wherein the cancellation network comprises:
[0035] A first capacitor, coupled between the first terminal of the first-stage inductor and the third terminal of the second-stage inductor; and
[0036] A second capacitor is coupled between the second terminal of the first stage inductor and the fourth terminal of the second stage inductor.
[0037] In one or more embodiments, the method further includes adjusting one or more of the first bias voltage at the first center tap or the second bias voltage at the second center tap to adjust the bias of one or more of the first gate or the second gate.
[0038] According to a third aspect of the present invention, a circuit is provided, comprising:
[0039] An input matching network includes an input transformer, the input transformer comprising:
[0040] A primary inductor, configured to receive an input signal having a first frequency;
[0041] The primary inductor includes a first terminal, a second terminal, and a first center tap, the first center tap being configured to receive a first bias voltage.
[0042] A second-stage inductor includes a first terminal, a second terminal, and a second center tap, the second center tap being configured to receive a second bias voltage;
[0043] Elimination network, coupled to the input matching network, the elimination network comprising:
[0044] A first capacitor includes a first end coupled to the first terminal of the first primary inductor and a second end coupled to the first terminal of the second secondary inductor;
[0045] The second capacitor includes a first end coupled to the second terminal of the first stage inductor and a second end coupled to the second terminal of the second stage inductor;
[0046] An output transformer coupled to the input matching network and the cancellation network, the output transformer comprising:
[0047] A primary output inductor, comprising a first output terminal and a second output terminal; and
[0048] A secondary output inductor, which is inductively coupled to the primary output inductor; and
[0049] The frequency multiplier core is coupled to the cancellation network. and the output transformer The frequency multiplier core includes:
[0050] A first transistor pair includes a first terminal coupled to a first power supply terminal, a second terminal coupled to the first output terminal of the primary output inductor, and gates coupled to the first and second terminals of the primary inductor; and
[0051] The second transistor pair includes a first terminal coupled to the second output terminal of the primary output inductor, a second terminal coupled to the second power supply terminal, and gates coupled to the first and second terminals of the secondary inductor.
[0052] In one or more embodiments, the first bias voltage biases the gate of the first transistor pair, and the second bias voltage biases the gate of the second transistor pair.
[0053] In one or more embodiments, one or more of the first bias voltage and the second bias voltage are adjustable.
[0054] In one or more embodiments, the second frequency of the output signal at the secondary output inductor is approximately twice the first frequency.
[0055] In one or more embodiments, the elimination network eliminates common-mode loop current, thereby reducing the sensitivity of the output signal to the impedance of the first and second center taps.
[0056] In one or more embodiments, the first transistor pair includes:
[0057] A first transistor includes a source coupled to a first supply voltage terminal, a gate coupled to the first terminal of the primary primary inductor, and a drain coupled to the first terminal of the primary output inductor; and
[0058] The second transistor includes a source coupled to the first supply voltage terminal, a gate coupled to the second terminal of the primary primary inductor, and a drain coupled to the first terminal of the primary output inductor; and
[0059] The second transistor pair includes:
[0060] A third transistor includes a source coupled to a second supply voltage terminal, a gate coupled to the first terminal of the second stage inductor, and a drain coupled to the second terminal of the primary output inductor; and
[0061] The fourth transistor includes a source coupled to the second supply voltage terminal, a gate coupled to the second terminal of the second stage inductor, and a drain coupled to the second terminal of the primary output inductor.
[0062] In one or more embodiments, the input matching network further includes one or more third-stage inductors.
[0063] In one or more embodiments, the first and second capacitors of the elimination network provide current paths to overcome the capacitive effect of the gate-to-drain capacitance of the first and second transistor pairs.
[0064] In one or more embodiments, the first bias voltage is different from the second bias voltage.
[0065] These and other aspects of the invention will become apparent from the embodiments described below, and will be illustrated with reference to these embodiments. Attached Figure Description
[0066] Specific embodiments are illustrated with reference to the accompanying drawings. In the drawings, the leftmost digit of the reference numeral indicates the figure in which that reference numeral first appears. The use of the same reference numerals in different figures and specific embodiments indicates similar or identical items or features.
[0067] Figure 1 A circuit according to certain embodiments is depicted, including a transformer-based bias circuit configured to bias a transistor in a complementary metal-oxide-semiconductor (CMOS) frequency multiplier core.
[0068] Figure 2 The text describes the use and non-use of capacitive common-mode elimination according to certain embodiments. Figure 1 A graph showing the power gain at the center tap of the secondary inductor of the input transformer compared to the capacitance value.
[0069] Figure 3 The chip according to certain embodiments is depicted Figure 1 An image of an embodiment of the circuit layout.
[0070] Figure 4 The use according to certain embodiments is described Figure 1 The flowchart shows a method for providing frequency multiplication output using a circuit.
[0071] While embodiments have been described by way of example in this disclosure, those skilled in the art will recognize that embodiments are not limited to the described examples or figures. In fact, the figures and their detailed description are not intended to limit embodiments to the disclosed form, but rather to cover all modifications, equivalents, and alternatives falling within the spirit and scope defined by the appended claims. The headings used in this disclosure are for organizational purposes only and are not intended to limit the scope of the specification or claims. As used throughout this application, the word “may” is used in a permissible sense (in other words, the term “may” is intended to mean “possibly”) rather than in a mandatory sense (such as “must”). Similarly, the term “include / including / includes” means including but not limited to. Detailed Implementation
[0072] Complementary metal-oxide-semiconductor (CMOS) push-pull frequency multipliers may include p-channel MOS field-effect transistors (PMOS) and n-channel MOS field-effect transistors (NMOS) configured to provide a push-pull circuit topology. PMOS and NMOS transistors draw relatively low current while using relatively high voltage supplies. PMOS and NMOS transistors may require different bias voltages.
[0073] The following describes embodiments of circuits and methods that may include a push-pull core with an input matching network and a capacitive common-mode cancellation network, the input matching network comprising a transformer with a primary inductor and two secondary inductors. The secondary inductors may include a center tap to which different bias voltages can be applied, allowing biasing of the NMOS and PMOS gates without the use of bias resistors or series capacitors. Compared to conventional push-pull frequency multiplier circuits, this circuit configuration can exhibit an improvement in voltage swing of approximately one to two dB. The circuit configuration can provide greater voltage swing, no bias resistors, and improved phase noise. The circuit configuration can use the same circuit area as a conventional transformer. Furthermore, the common-mode cancellation network makes the circuit insensitive to impedance at the center tap that provides the gate-bias voltage.
[0074] Figure 1 A circuit 100 according to certain embodiments is depicted. Circuit 100 includes a transformer-based biasing circuit configured to bias transistors of a CMOS frequency multiplier core. Circuit 100 may be an embodiment of a push-pull frequency multiplier circuit. Circuit 100 may include an input matching network 102 configured to receive an input signal, a cancellation network 104 coupled to the input matching network 102, and a CMOS frequency multiplier core 106 coupled to the input matching network 102 via the cancellation network 104. Circuit 100 may include an output transformer comprising a primary inductor 110 coupled to the CMOS frequency multiplier core 106 and a secondary inductor 108 configured to provide an output signal, which may be at twice the frequency of the input signal at the input of the input matching network 102.
[0075] Input matching network 102 may include a transformer including a primary inductor 112 configured to receive an input signal and inductibly coupled to both secondary inductors 114 and 116 with the same coupling coefficient k1 to generate first and second transformer signals based on the input signal. In an alternative embodiment, secondary inductors 114 and 116 may be coupled to the primary inductor 112 with different coupling coefficients k. In one or more embodiments, inductive parasitic coupling (not shown) may exist between secondary inductors 114 and 116. Secondary inductor 114 may include a first end coupled to node 118 and a second end coupled to node 120. Secondary inductor 116 may include a first end coupled to node 122 and a second end coupled to node 124. Secondary inductor 114 may include a first end coupled to node 122 and a second end coupled to node 124. Secondary inductor 114 may include a first bias voltage (Vbias) configured to receive a first bias voltage. P The center tap 115 of the CMOS frequency multiplier core 106 can bias the gates of PMOS transistors 130 and 136. The secondary inductor 116 may include components configured to receive a second bias voltage (Vbias). N The center tap 117 of the first bias voltage can bias the gates of NMOS transistors 140 and 144. In one or more embodiments, the first bias voltage can be greater than the second bias voltage.
[0076] In one or more embodiments, depending on the threshold voltage V of PMOS transistors 130 and 136 tp With the threshold voltage V of NMOS transistors 140 and 144 tn In comparison, the bias voltage Vbias at the center tap 115 P It can be compared with the bias voltage Vbias at the center tap 117 N The bias voltage at center tap 115 may be less than the bias voltage at center tap 117. In one or more embodiments, the bias voltage at center tap 115 may be greater than the bias voltage at center tap 117. In one or more embodiments, one or more of the first bias voltage at center tap 115 or the second bias voltage at center tap 117 may be adjusted to change the gate voltage of the transistor in the CMOS frequency multiplier core 106.
[0077] The cancellation network 104 may be a capacitive common-mode cancellation network, which includes a first capacitor 126, the first capacitor 126 including a first end coupled to node 118 and a second end coupled to node 122. The cancellation network 104 may include a second capacitor 128, the second capacitor 128 including a first end coupled to node 120 and a second end coupled to node 124.
[0078] The CMOS frequency multiplier core 106 may include PMOS transistors 130 and 136 and NMOS transistors 140 and 144. PMOS transistor 130 may include a source coupled to node 132, a gate coupled to node 118, and a drain coupled to node 134. Node 132 may be coupled to a supply voltage V. DD The PMOS transistor 136 may include a source coupled to node 132, a gate coupled to node 120, and a drain coupled to node 134. Node 134 may be coupled to a first terminal of the primary inductor 110 of the output transformer, which may be inductively coupled to the secondary inductor 108 to provide an output signal. The transformer formed by the primary inductor 110 and the secondary inductor 108 may be inductively coupled with a coupling factor k2, which may be the same as or different from the coupling factor k1.
[0079] NMOS transistor 140 may include a drain coupled to node 138, a gate coupled to node 124, and a source coupled to node 142. NMOS transistor 144 may include a drain coupled to node 138, a gate coupled to node 122, and a source coupled to node 142. Node 142 may be coupled to a second supply voltage, such as ground. Node 138 may be coupled to a second terminal of the primary inductor 110 of the output transformer. In one or more embodiments, a capacitor (not shown) may be coupled in parallel with the primary inductor 110, such that the capacitor may include a first terminal coupled to node 134 and a second terminal coupled to node 138.
[0080] In one or more embodiments, to avoid performance degradation associated with resistor-capacitor (RC) bias networks in the prior art, two secondary transformer inductors 114 and 116 are used as part of the input matching network 102. Utilizing the two separate secondary inductors 114 and 116, the bias voltage Vbias can be... P and Vbias N Bias voltages are applied to PMOS transistors 130 and 136 and NMOS transistors 140 and 144, respectively. The bias voltages can be different or the same. Since the center taps 115 and 117 of the secondary inductors 114 and 116 are considered common-mode grids, bias resistors are not required, and the impedance at the center taps 115 and 117 does not affect performance. In one or more embodiments, during operation, one or more of the bias voltages can be adjusted to change the voltage at the gate of one or more of transistors 130, 136, 140, or 144. The bias voltages can be adjusted independently of each other.
[0081] In this embodiment, the 80 GHz output current can be transferred to the input via the transistor gate-to-drain capacitance (Cgd). Without the capacitive common-mode cancellation network 104, this common-mode current could flow into both the secondary inductors 114 and 116 of the input transformer. However, the cancellation network 104 allows the common-mode current to bypass.
[0082] In one or more embodiments, circuit 100 includes a push-pull frequency multiplier core 106, which includes an output coupled to an output transformer (primary inductor 110 and secondary inductor 108) and an input coupled to an input matching network 102 and a cancellation network 104. Input matching network 102 may include an input transformer comprising a primary inductor 112 and secondary inductors 114 and 116, and an input signal can be transmitted from the primary inductor 112 to the secondary inductors 114 and 116 with low loss. In one or more embodiments, the input transformer may include two or more secondary inductors, and an input signal can be transmitted to the two or more secondary inductors with low loss.
[0083] Secondary inductors 114 and 116 (and any other secondary inductors) may include center taps 115 and 117 configured to receive a DC bias voltage applied to the gates of transistors 130, 136, 140, and 144 of the push-pull frequency multiplier core 106. The transformer center taps 115 and 117 allow the bias voltage to be supplied to the gates of PMOS transistors 130 and 136 and NMOS transistors 140 and 144 without degrading noise performance. Capacitors 126 and 128 of the cancellation network 104 provide a well-controlled current path to overcome the gate-to-drain capacitances of transistors 130, 136, 140, and 144.
[0084] In one or more embodiments, circuit 100 can be employed in automotive radar applications. For example, input matching network 102 and cancellation network 104 can provide bias for the CMOS frequency multiplier core 106 to provide a 40 GHz to 80 GHz frequency multiplier for automotive radar applications. In one or more embodiments, circuit 100 can allow an approximately two-dB reduction in the AC voltage in the matching network and an approximately five-dB improvement in phase noise over two MHz compared to conventional frequency multiplier circuitry. The two-dB voltage swing saved using input matching network 102 and cancellation network 104 can provide a 60-percent reduction in DC power consumption under the same operating conditions in a previous driver stage. Furthermore, circuit 100 can be implemented within the same circuit area as conventional frequency multiplier circuitry. Cancellation network 104 can provide capacitive common-mode cancellation, making the circuit insensitive to impedance at the center taps 115 and 117 of the secondary inductors 114 and 116, respectively.
[0085] Figure 2 The text describes the use and non-use of capacitive common-mode elimination according to certain embodiments. Figure 1 The power gain at the center tap of the secondary inductor of the input transformer in the circuit is compared to the capacitance value in graph 200. When using a transformer formed by primary inductor 112 and secondary inductors 114 and 116 for radio frequency (RF) matching, the design should be insensitive to impedance variations at the center taps 115 and 117 of secondary inductors 114 and 116. As previously mentioned, elimination network 104 can make circuit 100 insensitive to impedance variations at center taps 115 and 117.
[0086] In graph 200, the gain of embodiments of circuit 100 with and without the cancellation network 104 is shown. The gain decreases when the center tap impedance is lower, compared to the graph of circuit 100 without the cancellation network 104. In one example, an 80 GHz output current travels to the input via the gate-to-drain capacitance of transistors 130, 136, 140, and 144. This common-mode current can then travel to both the secondary inductors 114 and 116 of the input transformer, thus increasing the importance of the impedance at the center taps 115 and 117.
[0087] In one or more embodiments, the cancellation network 104 of circuit 100 may be a capacitive common-mode cancellation network, which makes circuit 100 relatively insensitive to the impedance at center taps 115 and 117. As shown in graph 200, the gain of circuit 100, including cancellation network 104, remains substantially constant when the center tap impedance changes. In operation, common-mode current can flow into the capacitor instead of the inductance at the center taps 115 and 117 of secondary inductors 114 and 116, thus making circuit 100 insensitive to center tap impedance.
[0088] Figure 3 The chip according to certain embodiments is depicted Figure 1 An image of an embodiment of the layout 300 of circuit 100. In the illustrated example, layout 300 represents circuit 100 arranged on test chip 302. Chip 302 includes a primary inductor 112 and secondary inductors 114 and 116. Center taps 115 and 117 are coupled to secondary inductors 114 and 116, respectively. Chip 302 may include a cancellation network 104, which includes capacitors 126 and 128. Chip 302 may include a frequency multiplier core 106 and an output transformer, the frequency multiplier core 106 including output transistors 130, 136, 140, and 144, and the output transformer including inductors 110 and 108.
[0089] Secondary inductors 114 and 116, and primary inductor 112, can occupy the same area as conventional transformers. In one or more embodiments, input matching network 102 can occupy a circuit area of approximately 200 micrometers (μm) by 150 μm. The two secondary transformers have the same dimensions as a reference design using a conventional transformer topology (the transformer topology used in the reference design and the new transformer topology have the same secondary inductance values). The capacitors 126 and 128 of the common-mode capacitive cancellation network 104 are well integrated in the layout and require less area than the four link capacitors known in the prior art. Therefore, the topology of circuit 302 does not use more circuit area than conventional frequency multiplier circuits.
[0090] Figure 4 The use according to certain embodiments is described Figure 1 The flowchart of method 400 for providing frequency multiplication output is shown. It can be used... Figure 1 The embodiment of circuit 100 is used to perform method 400.
[0091] At 402, method 400 may include circuitry including an input matching network 102, the input matching network 102 including a transformer, the transformer including a primary inductor 112 and a first secondary inductor 114 and a second secondary inductor 116. In one or more embodiments, the transformer may include a primary inductor 112 and two or more secondary inductors.
[0092] At 404, method 400 may include applying a first bias voltage to the center tap 115 of the first intermediate inductor 114 and applying a second bias voltage to the center tap 117 of the second intermediate inductor 116. The first bias voltage may be selected to bias the gates of transistors 130 and 136, and the second bias voltage may be selected to bias the gates of transistors 140 and 144.
[0093] At 406, method 400 may include receiving an input signal at the primary inductor 112 of the input matching network 102. The input signal may be applied to the input of the primary inductor 112.
[0094] At 408, method 400 may include generating a first signal at the primary inductor 114 and a second signal at the secondary inductor 116. The first and second signals may be generated automatically based on the inductive coupling between the primary inductor 112 and the secondary inductors 114 and 116.
[0095] At 410, method 400 may include using a capacitive common-mode cancellation network 104 coupled to the first-stage inductor 114 and the second-stage inductor 116 to cancel common-mode currents of the first and second signals. Cancellation network 104 may include a first capacitor 126 coupled between a first terminal of the first-stage inductor 114 and a first terminal of the second-stage inductor 116. Cancellation network 104 may include a second capacitor 128 coupled between a second terminal of the first-stage inductor 114 and a second terminal of the second-stage inductor 116.
[0096] At 412, method 400 may include driving the gates of a pair of PMOS transistors 130 and 136 using a first signal to generate a first output signal, and driving the gates of a pair of NMOS transistors 140 and 144 using a second signal to generate a second output signal. Transistors 130 and 136 may include a common source and a common drain coupled to a first power supply. Transistors 140 and 144 may include a common drain and a common source coupled to a second power supply (e.g., ground).
[0097] At 414, method 400 may include providing first and second output signals to the primary inductor 110 of the output transformer to generate an output signal on the secondary inductor 108. In one or more embodiments, the primary inductor 110 may include a first terminal coupled to the common drain of PMOS transistors 130 and 136, and may include a second terminal coupled to the common drain of NMOS transistors 140 and 144.
[0098] In conjunction with the above text about Figures 1-4The described circuit and method disclose a push-pull frequency multiplier circuit including a transformer-based matching network 102 comprising a transformer having a primary inductor 112 and two or more secondary inductors (e.g., inductors 114 and 116). The secondary inductors may include center taps, such as center tap 115 for inductor 114 and center tap 117 for inductor 116. The push-pull frequency multiplier circuit 100 may include a cancellation network comprising a first capacitor coupled between a first end of inductor 114 and a first end of inductor 116, and a second capacitor coupled between a second end of inductor 114 and a second end of inductor 116. A push-pull frequency multiplier circuit 100 may include a frequency multiplier core 106, which includes PMOS transistor pairs 130 and 136. The PMOS transistor pairs 130 and 136 have a common source coupled to a first power supply terminal, a common drain coupled to a first terminal of a primary inductor of an output transformer, and a gate. The gate of PMOS transistor 130 may be coupled to a first terminal of inductor 114, and the gate of PMOS transistor 136 may be coupled to a second terminal of inductor 114. The frequency multiplier core 106 may include NMOS transistor pairs 140 and 144, which have a common source coupled to a second power supply terminal (e.g., Vss or ground), a common drain coupled to a second terminal of a primary inductor of an output transformer, and a gate. The gate of NMOS transistor 140 may be coupled to a first terminal of inductor 116, and the gate of NMOS transistor 144 may be coupled to a second terminal of inductor 116. A first bias voltage can be applied to center tap 115 to bias PMOS transistors 130 and 136, and a second bias voltage can be applied to center tap 117 to bias NMOS transistors 140 and 144.
[0099] In one or more embodiments, the windings of the secondary inductors 114 and 116 of the input matching network 102 can transmit the input signal from the primary inductor 112 to the two secondary inductors 114 and 116 with low loss. Center taps 115 and 117 allow bias voltages to be applied to the gates of PMOS transistors 130 and 136 and NMOS transistors 140 and 144 without degrading the noise performance of circuit 100. In one or more embodiments, capacitors 126 and 128 of the elimination network 104 can provide a well-controlled current path for common-mode current to overcome the capacitive effects of the gate-to-drain capacitances of transistors 130, 136, 140, and 144. In one or more embodiments, compared to a conventional frequency multiplier circuit, circuit 100 can reduce the DC power consumption of the previous driver stage by up to 60 percent, while reducing the AC voltage drop in the matching network by 2 dB and improving low-frequency (2 MHz) phase noise by 5 dB in the same circuit area as a conventional frequency multiplier circuit.
[0100] The examples presented below can be used to further understand embodiments of the circuits and methods described above.
[0101] Example 1: A circuit may include: an output transformer including a primary output inductor inductively coupled to a secondary output inductor, the primary output inductor including a first terminal and a second terminal; a frequency multiplier core including a first transistor pair and a second transistor pair, the first transistor pair being coupled between a first power supply terminal and a first terminal of the primary output inductor, the first transistor pair including a first gate and a second gate, the second transistor pair being coupled between a second power supply terminal and a second terminal of the primary output inductor, the second transistor pair including a third gate and a fourth gate; an input matching network may include: an input transformer including configured... A primary inductor that receives an input signal having a first frequency; a second primary inductor that is inductively coupled to the primary inductor and includes a third terminal coupled to a first gate, a fourth terminal coupled to a second gate, and a first center tap configured to receive a first bias voltage to bias the first and second gates of a first transistor pair; and a second secondary inductor that is inductively coupled to the primary inductor and includes a fifth terminal coupled to a third gate, a sixth terminal coupled to a fourth gate, and a second center tap configured to receive a second bias voltage to bias the third and fourth gates of a second transistor pair.
[0102] Example 2: The circuit according to Example 1 further includes a cancellation network coupled to the input matching network, the cancellation network including: a first capacitor including a first capacitor terminal coupled to the third terminal of the first stage inductor and a second capacitor terminal coupled to the fifth terminal of the second stage inductor; and a second capacitor including a third capacitor terminal coupled to the fourth terminal of the first stage inductor and a second capacitor terminal coupled to the sixth terminal of the second stage inductor.
[0103] Example 3: The circuit according to Example 2, wherein the cancellation network eliminates common-mode loop current, thereby reducing the sensitivity of the output signal to the impedance of the first and second center taps.
[0104] Example 4: The circuit according to any one of Examples 2 or 3, wherein the first and second capacitors of the elimination network provide current paths to overcome the capacitive effect of the gate-drain capacitance of the first and second transistor pairs.
[0105] Example 5: The circuit according to any of Examples 1 to 4, wherein a first bias voltage biases the gate of a first transistor pair and a second bias voltage biases the gate of a second transistor pair.
[0106] Example 6: The circuit according to any of Examples 1 to 5, wherein the second frequency of the output signal at the secondary output inductor is approximately twice the first frequency.
[0107] Example 7: A circuit according to any one of Examples 1 to 6, wherein a first transistor pair includes a first transistor, the first transistor including a source coupled to a first supply voltage terminal, a gate coupled to a first terminal of a primary inductor, and a drain coupled to a first terminal of a primary output inductor; and a second transistor including a source coupled to the first supply voltage terminal, a gate coupled to a second terminal of the primary inductor, and a drain coupled to a first terminal of the primary output inductor; and wherein the second transistor pair includes a third transistor, the third transistor including a source coupled to a second supply voltage terminal, a gate coupled to a first terminal of a secondary inductor, and a drain coupled to a second terminal of the primary output inductor; and a fourth transistor including a source coupled to the second supply voltage terminal, a gate coupled to a second terminal of the secondary inductor, and a drain coupled to a second terminal of the primary output inductor.
[0108] Example 8: The circuit according to any one of Examples 1 to 7, wherein the input matching network further includes one or more third-stage inductors.
[0109] Example 9: A method for multiplying the frequency of an input includes: applying a first bias voltage to a first center tap of a primary inductor of an input transformer of an input matching network, the input transformer further including a primary inductor and a secondary inductor; applying a second bias voltage to a second center tap of the secondary inductor; receiving an input signal having a first frequency at the primary inductor; generating a first signal associated with the input signal at first and second terminals of the primary inductor, and generating a second signal associated with the input signal at third and fourth terminals of the secondary inductor; biasing the first gate of a first pair of transistors of a frequency multiplier core circuit with the first bias voltage to generate a first frequency multiplier signal, and biasing the second gate of a second pair of transistors of the frequency multiplier core circuit with the second bias voltage to generate a second frequency multiplier signal; applying the first frequency multiplier signal to a first terminal of a primary output inductor of an output transformer having a secondary output inductor; and applying the second frequency multiplier signal to a second terminal of the primary output inductor to provide an output signal at the secondary output inductor, the output signal having a second frequency that is twice the first frequency.
[0110] Example 10: The method according to Example 9 further includes using a cancellation network coupled to the first and second secondary inductors to cancel the common-mode loop current, wherein the cancellation network includes: a first capacitor coupled between the first terminal of the first primary inductor and the third terminal of the second secondary inductor; and a second capacitor coupled between the second terminal of the first primary inductor and the fourth terminal of the second secondary inductor.
[0111] Example 11: The method according to Example 9 further includes adjusting one or more of a first bias voltage at the first center tap or a second bias voltage at the second center tap to adjust the bias of one or more of the first gate or the second gate.
[0112] Example 12: A circuit comprising an input matching network, a cancellation network, and a frequency multiplier core, the input matching network comprising an input transformer, the input transformer comprising: a primary inductor configured to receive an input signal having a first frequency; a first secondary inductor comprising a first terminal, a second terminal, and a first center tap, the first center tap being configured to receive a first bias voltage; and a second secondary inductor comprising a first terminal, a second terminal, and a second center tap, the second center tap being configured to receive a second bias voltage; the cancellation network being coupled to the input matching network, the cancellation network comprising: a first capacitor comprising a first terminal coupled to the first terminal of the first secondary inductor and a second terminal coupled to the first terminal of the second secondary inductor; and a second capacitor comprising a second terminal coupled to the second terminal of the first secondary inductor. The system comprises: a primary output inductor, including a second terminal coupled to the second terminal of the secondary inductor; an output transformer coupled to the input matching network and the cancellation network, the output transformer including a primary output inductor including a first output terminal and a second output terminal; a secondary output inductor inductively coupled to the primary output inductor; and a frequency multiplier core coupled to the cancellation network and the output transformer, the frequency multiplier core including: a first transistor pair including a first terminal coupled to a first power supply terminal, a second terminal coupled to the first terminal of the primary output inductor, and a gate coupled to the first and second terminals of the primary inductor; and a second transistor pair including a first terminal coupled to the second terminal of the primary output inductor, a second terminal coupled to a second power supply terminal, and gates coupled to the first and second terminals of the secondary inductor.
[0113] Example 13: The circuit according to Example 12, wherein a first bias voltage biases the gate of the first transistor pair and a second bias voltage biases the gate of the second transistor pair.
[0114] Example 14: The circuit according to either Example 12 or 13, wherein one or more of the first bias voltage and the second bias voltage are adjustable.
[0115] Example 15: The circuit according to any of Examples 12 to 14, wherein the second frequency of the output signal at the secondary output inductor is approximately twice the first frequency.
[0116] Example 16: The circuit according to Example 15, wherein the cancellation network eliminates common-mode loop current, thereby reducing the sensitivity of the output signal to the impedance of the first and second center taps.
[0117] Example 17: A circuit according to any one of Examples 12 to 16, wherein the first transistor pair comprises: a first transistor including a source coupled to a first supply voltage terminal, a gate coupled to a first terminal of the primary inductor, and a drain coupled to a first terminal of the primary output inductor; and a second transistor including a source coupled to the first supply voltage terminal, a gate coupled to a second terminal of the primary inductor, and a drain coupled to a first terminal of the primary output inductor; and wherein the second transistor pair comprises: a third transistor including a source coupled to a second supply voltage terminal, a gate coupled to a first terminal of the secondary inductor, and a drain coupled to a second terminal of the primary output inductor; and a fourth transistor including a source coupled to the second supply voltage terminal, a gate coupled to a second terminal of the secondary inductor, and a drain coupled to a second terminal of the primary output inductor.
[0118] Example 18: The circuit according to any one of Examples 12 to 17, wherein the input matching network further includes one or more third-stage inductors.
[0119] Example 19: A circuit according to any one of Examples 12 to 18, wherein the first and second capacitors of the elimination network provide current paths to overcome the capacitive effect of the gate-drain capacitance of the first and second transistor pairs.
[0120] Example 20: A circuit according to any one of Examples 12 to 19, wherein the first bias voltage is different from the second bias voltage.
[0121] The specific embodiments described above are merely illustrative in nature and are not intended to limit the subject matter or the application and use of such embodiments. As used herein, the word "exemplary" means "serving as an example, illustration, or description." Any embodiment described herein as exemplary is not necessarily to be construed as preferred or superior to other embodiments. Furthermore, it is not intended to be bound by any express or implied theory presented in the foregoing technical field, background art, or specific embodiments.
[0122] The connecting lines shown in the figures contained herein represent exemplary functional relationships and / or physical couplings between various elements. It should be noted that many alternative or additional functional relationships or physical connections may exist in the embodiments of the subject matter. In addition, certain terms may also be used herein for reference only and are therefore not intended to be limiting, and unless the context clearly indicates otherwise, the terms “first,” “second,” and other such numerical terms referring to structures do not imply a sequence or order.
[0123] The above description refers to elements or features being "connected" or "coupled" together. As used herein, unless otherwise expressly stated, "connected" means that one element is directly engaged to (or directly connected to) another element, and not necessarily mechanically. Similarly, unless otherwise expressly stated, "coupled" means that one element is directly or indirectly engaged to (or directly or indirectly electrically connected to, or otherwise connected to) another element, and not necessarily mechanically. Therefore, although the schematic diagrams shown in the figures depict an exemplary arrangement of elements, additional intermediate elements, devices, features, or components may be present in embodiments of the subjects depicted.
[0124] While at least one exemplary embodiment has been presented in the above detailed description, it should be understood that numerous variations exist. It should also be understood that the one or more exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. In fact, the above detailed description will provide a convenient guide for those skilled in the art to implement the one or more described embodiments. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims.
Claims
1. A circuit, characterized in that, include: An output transformer includes a primary output inductor inductively coupled to a secondary output inductor, the primary output inductor including a first terminal and a second terminal; The frequency multiplier core includes a first transistor pair and a second transistor pair. The first transistor pair is coupled between a first power supply terminal and a first terminal of the primary output inductor. The first transistor pair includes a first gate and a second gate. The second transistor pair is coupled between a second power supply terminal and a second terminal of the primary output inductor. The second transistor pair includes a third gate and a fourth gate. An input matching network includes an input transformer, the input transformer comprising: A primary inductor, configured to receive an input signal having a first frequency; A first-stage inductor, inductively coupled to the primary inductor and including a third terminal coupled to the first gate, a fourth terminal coupled to the second gate, and a first center tap configured to receive a first bias voltage to bias the first and second gates of the first transistor pair; and A second-stage inductor, inductively coupled to the primary inductor, includes a fifth terminal coupled to the third gate, a sixth terminal coupled to the fourth gate, and a second center tap configured to receive a second bias voltage to bias the third and fourth gates of the second transistor pair.
2. The circuit according to claim 1, characterized in that, In addition, including: Elimination network, coupled to the input matching network, the elimination network comprising: A first capacitor includes a first capacitor terminal coupled to the third terminal of the first primary inductor and a second capacitor terminal coupled to the fifth terminal of the second secondary inductor; as well as The second capacitor includes a third capacitor terminal coupled to the fourth terminal of the first stage inductor and a fourth capacitor terminal coupled to the sixth terminal of the second stage inductor.
3. The circuit according to claim 2, characterized in that, The elimination network eliminates common-mode loop current, thereby reducing the sensitivity of the output signal to the impedance of the first and second center taps.
4. The circuit according to claim 2, characterized in that, The first and second capacitors of the elimination network provide current paths to overcome the capacitive effect of the gate-to-drain capacitance of the first and second transistor pairs.
5. The circuit according to claim 1, characterized in that, The first bias voltage biases the gate of the first transistor pair, and the second bias voltage biases the gate of the second transistor pair.
6. The circuit according to claim 1, characterized in that, The second frequency of the output signal at the secondary output inductor is approximately twice the first frequency.
7. The circuit according to claim 1, characterized in that, The first transistor pair includes: A first transistor includes a source coupled to a first supply voltage terminal, a first gate coupled to the third terminal of the primary primary inductor, and a drain coupled to the first terminal of the primary output inductor; and The second transistor includes a source coupled to the first supply voltage terminal, a second gate coupled to the fourth terminal of the primary inductor, and a drain coupled to the first terminal of the primary output inductor; and The second transistor pair includes: The third transistor includes a source coupled to a second supply voltage terminal, a third gate coupled to the fifth terminal of the second secondary inductor, and a drain coupled to the second terminal of the primary output inductor; and The fourth transistor includes a source coupled to the second supply voltage terminal, a fourth gate coupled to the sixth terminal of the second stage inductor, and a drain coupled to the second terminal of the primary output inductor.
8. The circuit according to claim 1, characterized in that, The input matching network further includes one or more third-stage inductors.
9. A method for doubling the frequency of an input signal, characterized in that, The method includes: A first bias voltage is applied to the first center tap of the first stage inductor of the input transformer of the input matching network, the input transformer further including a primary inductor inductively coupled to the second stage inductor; A second bias voltage is applied to the second center tap of the secondary inductor; An input signal having a first frequency is received at the primary inductor; A first signal related to the input signal is generated at the first and second terminals of the first-stage inductor, and a second signal related to the input signal is generated at the third and fourth terminals of the second-stage inductor; The first gate of the first transistor pair in the frequency multiplier core circuit is biased with the first bias voltage to generate a first frequency multiplier signal, and the second gate of the second transistor pair in the frequency multiplier core circuit is biased with the second bias voltage to generate a second frequency multiplier signal. The first frequency multiplier signal is applied to a first terminal of the primary output inductor of the output transformer, the output transformer having a secondary output inductor inductively coupled to the primary output inductor; and The second frequency multiplier signal is applied to the second terminal of the primary output inductor to provide an output signal at the secondary output inductor, the output signal having a second frequency that is twice the first frequency.
10. A circuit, characterized in that, include: An input matching network includes an input transformer, the input transformer comprising: A primary inductor, configured to receive an input signal having a first frequency; The primary inductor includes a first terminal, a second terminal, and a first center tap, the first center tap being configured to receive a first bias voltage. A second-stage inductor includes a first terminal, a second terminal, and a second center tap, the second center tap being configured to receive a second bias voltage; Elimination network, coupled to the input matching network, the elimination network comprising: A first capacitor includes a first end coupled to the first terminal of the first primary inductor and a second end coupled to the first terminal of the second secondary inductor; The second capacitor includes a first end coupled to the second terminal of the first stage inductor and a second end coupled to the second terminal of the second stage inductor; An output transformer coupled to the input matching network and the cancellation network, the output transformer comprising: A primary output inductor, comprising a first output terminal and a second output terminal; and A secondary output inductor, which is inductively coupled to the primary output inductor; and The frequency multiplier core, coupled to the cancellation network and the output transformer, comprises: A first transistor pair includes a first terminal coupled to a first power supply terminal, a second terminal coupled to the first output terminal of the primary output inductor, and gates coupled to the first and second terminals of the primary inductor; and The second transistor pair includes a first terminal coupled to the second output terminal of the primary output inductor, a second terminal coupled to the second power supply terminal, and gates coupled to the first and second terminals of the secondary inductor.