Analog switch capable of being dynamically turned on

Abstract

The invention discloses an analog switch capable of being dynamically turned on, relates to the technical field of integrated circuits, and aims to solve the problem that when an existing analog switch works, the on resistance of a device changes along with the change of an input signal. Comprising an N-type main power tube and a P-type main power tube which are connected in parallel, and an auxiliary circuit which is connected with the N-type main power tube in parallel, the auxiliary circuit comprises a plurality of auxiliary power tubes which are connected in parallel and a grid control signal generating circuit; the grid control signal generation circuit comprises a comparator and a level shift circuit, the output end of the comparator is connected with the input end of the level shift circuit, and the output end of the level shift circuit is connected with the grid electrode of the auxiliary power tube; the comparator is used for comparing the input voltage with the threshold voltage, and the threshold voltage of the comparator is increased in a gradient mode in the direction away from the N-type main power tube. The analog switch capable of being dynamically turned on provided by the invention is used for enabling the on-resistance of the analog switch to tend to be flat along with the change of an input signal.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a dynamically turn-on analog switch. Background Technology

[0002] An analog switch is a semiconductor device used to switch analog signal paths. Its core function is to turn analog signals on or off under the action of control signals, with almost no change to the signal's amplitude, phase, or other analog characteristics. During design, the signal transmission frequency of the analog switch must be considered to accommodate high-speed signal transmission. Other considerations include the matching degree between signal channels, reducing on-resistance flatness, improving signal transmission linearity, and increasing isolation and crosstalk. Therefore, improving signal transmission capability is crucial for analog switches. On-resistance is an important indicator of an analog switch, and its impact is mainly reflected in total harmonic distortion (THD). For analog switches, the main factors causing THD are on-resistance flatness and junction capacitance.

[0003] Existing CMOS analog switches mainly include single-channel analog switches, complementary-channel analog switches, and T-channel analog switches. Most analog switches use N-type and P-type switching devices connected in parallel. Complementary-channel analog switches require a signal to control the simultaneous on / off state of both the NMOS and PMOS transistors. The on-resistance of analog switches varies greatly with the input signal. When the switch is operating normally, there is a significant substrate bias effect, which changes the threshold voltage of the device, increases the on-resistance, and reduces the matching degree between the NMOS and PMOS switches, affecting the flatness of the on-resistance of the MOS switch. Substrate biased switches can reduce the substrate bias effect and flatten the on-resistance, but when the input signal increases during operation, the gate-source voltage of the switching device decreases, leading to an increase in the on-resistance. Summary of the Invention

[0004] The purpose of this invention is to provide a dynamically operable analog switch to solve the problem that the on-resistance of the device changes with the input signal when the existing analog switch is working.

[0005] To achieve the above objectives, the present invention provides the following technical solution: The present invention provides a dynamically turn-on analog switch, comprising: an N-type main power transistor and a P-type main power transistor connected in parallel, and an auxiliary circuit connected in parallel with the N-type main power transistor; The auxiliary circuit includes multiple auxiliary power transistors connected in parallel and a gate control signal generation circuit, with each auxiliary power transistor's gate connected to a corresponding gate control signal generation circuit. The gate control signal generation circuit includes a comparator and a level shifter circuit. The output terminal of the comparator is connected to the input terminal of the level shifter circuit, and the output terminal of the level shifter circuit is connected to the gate of the auxiliary power transistor. The comparator is used to compare the input voltage with a threshold voltage, and the threshold voltage of the comparator increases in a gradient along the direction away from the N-type main power transistor. During operation, as the voltage of the input signal increases, the gate control signal generation circuit controls the auxiliary power transistor to gradually turn on.

[0006] Optionally, the analog switch further includes a first noise reduction circuit disposed between the P-type substrate port of the P-type main power transistor and the positive power supply, and a second noise reduction circuit disposed between the N-type substrate port of the N-type main power transistor and the negative power supply; the first noise reduction circuit is used to shield the influence of noise signal on the positive power supply, and the second noise reduction circuit is used to shield the influence of noise voltage on the negative power supply.

[0007] Optionally, the first noise reduction circuit includes a first diode and a first MOSFET, wherein the anode of the first diode is connected to the positive power supply, the cathode of the first diode is connected to the source of the first MOSFET, and the drain of the first MOSFET is connected to the P-type substrate port; the second noise reduction circuit includes a second diode and a second MOSFET, wherein the anode of the second diode is connected to the N-type substrate port, the cathode of the second diode is connected to the drain of the second MOSFET, and the source of the second MOSFET is connected to the negative power supply.

[0008] Optionally, the analog switch further includes an analog signal suppression circuit disposed between the P-type substrate port and the N-type substrate port. When the analog switch transmits a signal, the analog signal suppression circuit is turned on, and the P-type substrate port and the N-type substrate port are short-circuited. When the analog switch does not transmit a signal, the analog signal suppression circuit is turned off.

[0009] Optionally, the analog signal suppression circuit includes a first P-type MOS transistor and a first N-type MOS transistor, wherein the source of the first P-type MOS transistor is connected to the P-type substrate port and the drain of the first N-type MOS transistor, and the drain of the first P-type MOS transistor is connected to the N-type substrate port and the source of the first N-type MOS transistor.

[0010] Optionally, the threshold voltage of the Nth comparator along the direction away from the N-type main power transistor is N times the ratio of the maximum input signal to X, where N is a positive integer and X is the total number of comparators.

[0011] Optionally, the analog switch further includes a third MOS transistor and a fourth MOS transistor. The drain of the third MOS transistor is connected to the drain of the P-type main power transistor, the source of the third MOS transistor is connected to the P-type substrate port, and the gate of the third MOS transistor is connected to the gate of the second MOS transistor, the gate of the first P-type MOS transistor, and the gate of the fourth MOS transistor. The source of the fourth MOS transistor is connected to the P-type substrate port, and the drain of the fourth MOS transistor is connected to the source of the P-type main power transistor.

[0012] Optionally, the analog switch further includes a fifth MOS transistor and a sixth MOS transistor. The source of the fifth MOS transistor is connected to the N-type substrate port, the drain of the fifth MOS transistor is connected to the drain of the N-type main power transistor, and the gate of the fifth MOS transistor is connected to the gate of the N-type main power transistor, the gate of the sixth MOS transistor, the gate of the first MOS transistor, and the gate of the first N-type MOS transistor. The source of the sixth MOS transistor is connected to the N-type substrate port, and the drain of the sixth MOS transistor is connected to the source of the N-type main power transistor.

[0013] Optionally, the analog switch further includes a first resistor, a second resistor, a third resistor, and a fourth resistor; one end of the first resistor is connected to the positive terminal of the second diode, and the other end of the first resistor is connected to the N-type substrate port; one end of the second resistor is connected to one end of the first resistor, and the other end of the second resistor is connected to the source of the first N-type MOSFET; one end of the third resistor is connected to the P-type substrate port, and the other end of the third resistor is connected to the source of the first P-type MOSFET; one end of the fourth resistor is connected to the P-type substrate port, and the other end of the fourth resistor is connected to the drain of the first MOSFET.

[0014] Optionally, the comparator's substrate port is connected to an N-type substrate port.

[0015] Compared with the prior art, the present invention provides a dynamically turn-on analog switch, comprising: an N-type main power transistor and a P-type main power transistor connected in parallel, and an auxiliary circuit connected in parallel with the N-type main power transistor; the auxiliary circuit includes multiple auxiliary power transistors connected in parallel and a gate control signal generation circuit, with the gate of each auxiliary power transistor corresponding to a gate control signal generation circuit; the gate control signal generation circuit includes a comparator and a level shift circuit, the output of the comparator is connected to the input of the level shift circuit, and the output of the level shift circuit is connected to the gate of the auxiliary power transistor; the comparator is used to compare the input voltage with a threshold voltage, and the threshold voltage of the comparator increases in a gradient along the direction away from the N-type main power transistor; during operation, as the voltage of the input signal increases, the gate control signal generation circuit controls the auxiliary power transistors to gradually turn on. This application connects an auxiliary circuit in parallel across the N-type main power transistor. The threshold voltage of the comparator in the gate control signal generation circuit increases in a gradient. As the input signal voltage increases, the auxiliary power transistor can be turned on in a gradient through the gate control signal generation circuit, gradually increasing the area of ​​the total power transistor of the switch. This reduces the influence of the input signal voltage on the switch's on-resistance, making the on-resistance change more flat compared to existing analog switches. Attached Figure Description

[0016] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a circuit diagram of a substrate bias switch in the prior art; Figure 2 A circuit diagram of a dynamically operable analog switch provided by the present invention; Figure 3 A schematic diagram of the circuit structure of the gate control signal generation circuit provided by the present invention; Figure 4 A comparison chart of the simulation results of the on-resistance of the dynamically turn-on analog switch provided by the present invention and existing analog switches.

[0017] Figure label: 1-Auxiliary circuit, 2-First noise reduction circuit, 3-Second noise reduction circuit, 4-Analog signal suppression circuit, Pmain-P-type main power transistor, Nmain-N-type main power transistor, D1-First diode, D2-Second diode, M1-First MOSFET, M2-Second MOSFET, P_BLUK-P-type substrate port, N_BLUK-N-type substrate port, P0-First P-type MOSFET, N0-First N-type MOSFET, M3-Third MOSFET, M4-Fourth MOSFET, M5-Fifth MOSFET, M6-Sixth MOSFET, R1-First resistor, R2-Second resistor, R3-Third resistor, R4-Fourth resistor, N1-First auxiliary power transistor, N2-Second auxiliary power transistor, N3-Third auxiliary power transistor, NX-Xth auxiliary power transistor. Detailed Implementation

[0018] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0019] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0020] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0021] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0022] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0023] Existing CMOS analog switches mainly include single-channel analog switches, complementary-channel analog switches, and T-type analog switches. Most analog switches use N-type and P-type switching devices connected in parallel. Complementary-channel analog switches require a signal to control the simultaneous on / off state of both the NMOS and PMOS transistors. The on-resistance of analog switches varies significantly with the input signal, especially for single-channel analog switches. For analog switches, when operating normally, a significant substrate bias effect exists, which changes the threshold voltage, increases the on-resistance, and reduces the matching degree between the NMOS and PMOS switches, affecting the on-resistance flatness of the MOS switch. Another type, substrate-biased switches, lack direct parasitic capacitance from input to output, resulting in excellent turn-off isolation and crosstalk resistance. For example... Figure 1 As shown, MN1, MN2, and MN3 together constitute an NMOS switch, with MN1 being the main large-size switching device. MN2 and MN3 are used to set the well potential of MN1. Similarly, MP1, MP2, and MP3 together constitute a PMOS switch, with MP2 and MP3 used to set the well potential of MP1. Nctrl and Pctrl are complementary switch control terminals. When this switch path is on, Nctrl is high, M1 connects the input and output, and M2 and M3 connect the well to the input, reducing the substrate bias effect of MN1. Pctrl is low, MP1 connects the input and output, and MP2 and MP3 connect the well to the input, reducing the substrate bias effect of MP1. When this switch path is off, Nctrl is low, MP4 is on, pulling the NMOS switch down to VSS, and Pctrl is high, turning on MN4, pulling the PMOS switch up to VDD. This ensures that MN1-MN3 and MP1-MP3 are not forward biased when turned off, ensuring that the switching transistors are fully cut off and reducing leakage current. Because the improved circuit uses a hot-sink technology for the PMOS and NMOS transmission gates—that is, employing two switches simultaneously to control the sink potential of the transmission gate—it eliminates the voltage difference between its B and S ports, delaying the switching transistors from entering the cutoff region. This results in a flatter on-resistance, thus reducing the back-gate effect. A disadvantage of this structure is that the IN signal approaches V... DD -V THNWhen the input signal reaches the near-turn-off value of the NMOS switch, a continued increase in the IN signal will cause the NMOS switch to turn off. The turn-off of the NMOS will increase the on-resistance of the analog switch. However, as IN increases further, the conduction level of the PMOS will increase further, causing a slight decrease in the on-resistance of the analog switch. However, the turn-off of the NMOS will cause a small spike in the on-resistance, and similarly, the turn-off of the PMOS will also cause a small spike in the on-resistance. These spikes significantly reduce the flatness of the on-resistance. However, using this technique, when the input signal increases during analog switch operation, the gate-source voltage of the switching device decreases, leading to an increase in the on-resistance of the device.

[0024] To address the aforementioned problems, this invention provides a dynamically operable analog switch that can keep the on-resistance of the analog switch constant or minimize its change when the input signal changes. Measures are taken in the circuit architecture and design to eliminate the bias effect, thereby making the constantly changing on-resistance tend to flatten.

[0025] See Figure 2 and Figure 3 The present invention provides a dynamically operable analog switch comprising an N-type main power transistor Nmain and a P-type main power transistor Pmain connected in parallel, and an auxiliary circuit 1 connected in parallel with the N-type main power transistor Nmain; the source of the N-type main power transistor Nmain and the source of the P-type main power transistor Pmain are connected, and the drain of the N-type main power transistor Nmain and the drain of the P-type main power transistor Pmain are connected; the auxiliary circuit 1 includes multiple auxiliary power transistors connected in parallel and a gate control signal generation circuit, with each auxiliary power transistor's gate corresponding to a gate control signal generation circuit.

[0026] like Figure 3As shown, the gate control signal generation circuit includes a comparator and a level shifter circuit. The output of the comparator is connected to the input of the level shifter circuit, and the output of the level shifter circuit is connected to the gate of the auxiliary power transistor. The substrate port of the comparator is connected to the N-type substrate port. Specifically, the auxiliary power transistors along the direction away from the N-type main power transistor are, in sequence, the first auxiliary power transistor N1, the second auxiliary power transistor N2, the third auxiliary power transistor N3, ..., the Xth auxiliary power transistor NX. The gate control voltage of the first auxiliary power transistor N1 is G_N1, which is the output of the gate control signal generation circuit composed of the first comparator and the first level shifter circuit. The gate control voltage of the second auxiliary power transistor N2 is G_N2, which is the output of the gate control signal generation circuit composed of the second comparator and the second level shifter circuit. The gate control voltage of the third auxiliary power transistor N3 is G_N3, which is the output of the gate control signal generation circuit composed of the second comparator and the second level shifter circuit. The gate control voltage of the Xth auxiliary power transistor NX is G_NX, which is the output of the Xth comparator circuit. The output of the gate control signal generation circuit composed of the Xth level shift circuit; the comparator is used to compare the input voltage with the threshold voltage, and the threshold voltage of the comparator increases in a gradient along the direction away from the N-type main power transistor; the threshold voltage of the Nth comparator along the direction away from the N-type main power transistor is the ratio of N times the maximum input signal Vsignalmax to X, where N is a positive integer and X is the total number of comparators; for example, the threshold voltage of the first comparator along the direction away from the N-type main power transistor is Vsignalmax / X, the threshold voltage of the second comparator is 2Vsignalmax / X, the threshold voltage of the third comparator is 3Vsignalmax / X, and the threshold voltage of the Xth comparator is Vsignalmax.

[0027] During operation, a signal is input from the input port S of the analog switch and output from the output port D. As the input signal voltage Vsignal increases, the gate control signal generation circuit controls the auxiliary power transistors N1-NX to gradually turn on. As Vsignal increases, the gate-source voltage of the N-type main power transistor Nmain decreases, and its on-resistance increases. By turning on the auxiliary power transistors N1-NX, the transistor area is increased, reducing the impact of the signal voltage on the on-resistance of the analog switch. Specifically, when Vsignal increases to 1 / X of Vsignalmax, the gate of N1 is controlled by a comparator and a level shifter circuit, turning N1 on. When Vsignal increases to 2 / X of Vsignalmax, the gate of N2 is controlled by a comparator and a level shifter circuit, turning N2 on. When Vsignal increases to 3 / X of Vsignalmax, the gate of N3 is controlled by a comparator and a level shifter circuit, turning N3 on. The auxiliary power transistors are turned on sequentially before Vsignal reaches Vsignalmax. When Vsignal increases to Vsignalmax, the gate of NX is controlled by the comparator and level shifter circuit, thus turning on NX.

[0028] Figure 2 The aforementioned analog switch uses an auxiliary circuit connected in parallel across the N-type main power transistor. The threshold voltage of the comparator in the gate control signal generation circuit increases in a gradient. As the input signal voltage increases, the auxiliary power transistor can be turned on in a gradient through the gate control signal generation circuit, gradually increasing the area of ​​the total power transistor of the switch. This reduces the influence of the input signal voltage on the switch's on-resistance, making the change in on-resistance tend to be flat as the input signal voltage increases.

[0029] As an optional approach, such as Figure 2 As shown, the analog switch also includes a first noise reduction circuit 2 disposed between the P-type substrate port P_BLUK of the P-type main power transistor and the positive power supply VDD, and a second noise reduction circuit 3 disposed between the N-type substrate port N_BLUK of the N-type main power transistor and the negative power supply VSS; the first noise reduction circuit 2 is used to shield the influence of noise signals on the positive power supply, and the second noise reduction circuit 3 is used to shield the influence of noise voltage on the negative power supply.

[0030] Specifically, the first noise reduction circuit 2 includes a first diode D1 and a first MOSFET M1. The anode of the first diode D1 is connected to the positive power supply VDD, the cathode of the first diode D1 is connected to the source of the first MOSFET M1, and the drain of the first MOSFET M1 is connected to the P-type substrate port P_BLUK. The second noise reduction circuit 3 includes a second diode D2 and a second MOSFET M2. The anode of the second diode D2 is connected to the N-type substrate port N_BLUK, the cathode of the second diode D2 is connected to the drain of the second MOSFET M2, and the source of the second MOSFET M2 is connected to the negative power supply VSS.

[0031] During operation, if noise occurs in the input signal voltage and the voltage is greater than VDD, the first diode D1 is reverse-biased and cut off, thus shielding the influence of the noise voltage on the positive power supply VDD. If noise occurs in the input signal voltage and the voltage is less than VSS, the second diode D2 is reverse-biased and cut off, thus shielding the influence of the noise voltage on the negative power supply VSS.

[0032] As an optional approach, such as Figure 2 As shown, the analog switch also includes an analog signal suppression circuit 4 disposed between the P-type substrate port P_BLUK and the N-type substrate port N_BLUK.

[0033] Specifically, the analog signal suppression circuit 4 includes a first P-type MOS transistor P0 and a first N-type MOS transistor N0. The source of the first P-type MOS transistor P0 is connected to the P-type substrate port P_BLUK and the drain of the first N-type MOS transistor N0. The drain of the first P-type MOS transistor P0 is connected to the N-type substrate port N_BLUK and the source of the first N-type MOS transistor N0.

[0034] In practical operation, when the analog switch transmits a signal, the first P-type MOSFET P0 and the first N-type MOSFET N0 are turned on, the analog signal suppression circuit 4 is turned on, the P-type substrate port P_BLUK and the N-type substrate port N_BLUK are shorted, and the analog signal voltage is suppressed to eliminate the substrate bias effect. When the analog switch does not transmit a signal, the first P-type MOSFET P0 and the first N-type MOSFET N0 are turned off, the P-type substrate port of the P-type main power transistor Pmain is connected to VDD, the N-type substrate port of the N-type main power transistor Nmain is connected to VSS, the analog signal suppression circuit 4 is turned off, and the static leakage current is reduced.

[0035] As an optional embodiment, the analog switch further includes a third MOSFET M3 and a fourth MOSFET M4. The drain of the third MOSFET M3 is connected to the drain of the P-type main power transistor, the source of the third MOSFET M3 is connected to the P-type substrate port, and the gate of the third MOSFET M3 is connected to the gate of the second MOSFET M2, the gate of the first P-type MOSFET P0, and the gate of the fourth MOSFET M4. The source of the fourth MOSFET M4 is connected to the P-type substrate port, and the drain of the fourth MOSFET M4 is connected to the source of the P-type main power transistor.

[0036] Alternatively, the analog switch further includes a fifth MOSFET M5 and a sixth MOSFET M6. The source of the fifth MOSFET M5 is connected to the N-type substrate port, the drain of the fifth MOSFET M5 is connected to the drain of the N-type main power transistor, and the gate of the fifth MOSFET M5 is connected to the gate of the N-type main power transistor, the gate of the sixth MOSFET M6, the gate of the first MOSFET, and the gate of the first N-type MOSFET. The source of the sixth MOSFET M6 is connected to the N-type substrate port, and the drain of the sixth MOSFET M6 is connected to the source of the N-type main power transistor.

[0037] As an optional embodiment, the analog switch further includes a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4; one end of the first resistor R1 is connected to the positive terminal of the second diode, and the other end of the first resistor R1 is connected to the N-type substrate port; one end of the second resistor R2 is connected to one end of the first resistor R1, and the other end of the second resistor R2 is connected to the source of the first N-type MOSFET; one end of the third resistor R3 is connected to the P-type substrate port, and the other end of the third resistor R3 is connected to the source of the first P-type MOSFET; one end of the fourth resistor R4 is connected to the P-type substrate port, and the other end of the fourth resistor R4 is connected to the drain of the first MOSFET.

[0038] Specifically, in the above structure, the second MOSFET M2, the third MOSFET M3, the fourth MOSFET M4, and the first P-type MOSFET P0 are all P-type MOSFETs, and their gate control signal is SWP; the first MOSFET, the fifth MOSFET M5, the sixth MOSFET M6, the first N-type MOSFET N0, and the auxiliary power transistors N1-NX are all N-type MOSFETs, and their gate control signal is SWN.

[0039] The dynamically variable analog switch of this application can reduce the influence of on-resistance variations with input signal, significantly reducing the flatness of the switch's on-resistance. Under these conditions, the distortion of the analog switch during signal transmission can be greatly reduced. For example... Figure 4As shown, the on-resistance of the dynamically turn-on analog switch of this application changes more smoothly with the input signal voltage compared to existing analog switches.

[0040] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0041] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A dynamically operable analog switch, characterized in that, include: An N-type main power transistor and a P-type main power transistor connected in parallel, and an auxiliary circuit connected in parallel with the N-type main power transistor; The auxiliary circuit includes multiple auxiliary power transistors connected in parallel and a gate control signal generation circuit, with each auxiliary power transistor's gate connected to a corresponding gate control signal generation circuit. The gate control signal generation circuit includes a comparator and a level shifter circuit. The output terminal of the comparator is connected to the input terminal of the level shifter circuit, and the output terminal of the level shifter circuit is connected to the gate of the auxiliary power transistor. The comparator is used to compare the input voltage with a threshold voltage, and the threshold voltage of the comparator increases in a gradient along the direction away from the N-type main power transistor. During operation, as the voltage of the input signal increases, the gate control signal generation circuit controls the auxiliary power transistor to gradually turn on.

2. The dynamically operable analog switch according to claim 1, characterized in that, The analog switch further includes a first noise reduction circuit disposed between the P-type substrate port of the P-type main power transistor and the positive power supply, and a second noise reduction circuit disposed between the N-type substrate port of the N-type main power transistor and the negative power supply; the first noise reduction circuit is used to shield the influence of noise signal on the positive power supply, and the second noise reduction circuit is used to shield the influence of noise voltage on the negative power supply.

3. The dynamically operable analog switch according to claim 2, characterized in that, The first noise reduction circuit includes a first diode and a first MOSFET. The anode of the first diode is connected to the positive power supply, the cathode of the first diode is connected to the source of the first MOSFET, and the drain of the first MOSFET is connected to the P-type substrate port. The second noise reduction circuit includes a second diode and a second MOSFET. The anode of the second diode is connected to the N-type substrate port, the cathode of the second diode is connected to the drain of the second MOSFET, and the source of the second MOSFET is connected to the negative power supply.

4. The dynamically operable analog switch according to claim 2, characterized in that, The analog switch also includes an analog signal suppression circuit disposed between the P-type substrate port and the N-type substrate port. When the analog switch transmits a signal, the analog signal suppression circuit is turned on, and the P-type substrate port and the N-type substrate port are short-circuited. When the analog switch does not transmit a signal, the analog signal suppression circuit is turned off.

5. The dynamically operable analog switch according to claim 4, characterized in that, The analog signal suppression circuit includes a first P-type MOS transistor and a first N-type MOS transistor. The source of the first P-type MOS transistor is connected to the P-type substrate port and the drain of the first N-type MOS transistor, and the drain of the first P-type MOS transistor is connected to the N-type substrate port and the source of the first N-type MOS transistor.

6. The dynamically operable analog switch according to claim 1, characterized in that, The threshold voltage of the Nth comparator along the direction away from the N-type main power transistor is the ratio of N times the maximum input signal to X, where N is a positive integer and X is the total number of comparators.

7. The dynamically operable analog switch according to claim 1, characterized in that, The analog switch further includes a third MOS transistor and a fourth MOS transistor. The drain of the third MOS transistor is connected to the drain of the P-type main power transistor, the source of the third MOS transistor is connected to the P-type substrate port, and the gate of the third MOS transistor is connected to the gate of the second MOS transistor, the gate of the first P-type MOS transistor, and the gate of the fourth MOS transistor. The source of the fourth MOS transistor is connected to the P-type substrate port, and the drain of the fourth MOS transistor is connected to the source of the P-type main power transistor.

8. The dynamically operable analog switch according to claim 1, characterized in that, The analog switch further includes a fifth MOS transistor and a sixth MOS transistor. The source of the fifth MOS transistor is connected to the N-type substrate port, the drain of the fifth MOS transistor is connected to the drain of the N-type main power transistor, and the gate of the fifth MOS transistor is connected to the gate of the N-type main power transistor, the gate of the sixth MOS transistor, the gate of the first MOS transistor, and the gate of the first N-type MOS transistor. The source of the sixth MOS transistor is connected to the N-type substrate port, and the drain of the sixth MOS transistor is connected to the source of the N-type main power transistor.

9. The dynamically operable analog switch according to claim 1, characterized in that, The analog switch further includes a first resistor, a second resistor, a third resistor, and a fourth resistor; one end of the first resistor is connected to the positive terminal of the second diode, and the other end of the first resistor is connected to the N-type substrate port; one end of the second resistor is connected to one end of the first resistor, and the other end of the second resistor is connected to the source of the first N-type MOSFET; one end of the third resistor is connected to the P-type substrate port, and the other end of the third resistor is connected to the source of the first P-type MOSFET; one end of the fourth resistor is connected to the P-type substrate port, and the other end of the fourth resistor is connected to the drain of the first MOSFET.

10. The dynamically operable analog switch according to claim 1, characterized in that, The comparator's substrate port is connected to the N-type substrate port.

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