Reference source and satellite communication system

Abstract

The invention provides a reference source and a satellite communication system.The reference source comprises an atomic clock, a first phase-locked loop, a low-frequency crystal oscillator, a frequency doubling filter circuit, a second phase-locked loop, a high-frequency crystal oscillator and an output device.A miniaturized design scheme is adopted, an ultra-thin rubidium clock, a constant-temperature crystal oscillator and an ultra-low phase noise crystal oscillator are arranged in the reference source; the system has the characteristics of small size and low cost, meets the application requirements of a miniaturized or highly integrated scene, and has a wide prospect; the multi-stage frequency synthesis technology is adopted, so that the output reference signal has the characteristics of high speed, stability and low phase noise, the requirements of the fields of time-frequency measurement, radar detection and the like on the reference source are met, and the application range is wide.

Description

Reference source and satellite communication system Technical Field

[0001] This application belongs to the field of signal processing, and in particular relates to a reference source and a satellite communication system. Background Technology

[0002] Miniaturized, fast-stabilizing reference sources are characterized by small size, fast stabilization speed, and high frequency accuracy. They can be used as high-spectral-purity reference sources in satellite communication systems, radar detection systems, and electronic countermeasures systems. They can also be used as high-stability reference modules in the development of high-performance signal generators, signal analyzers, and other microwave equipment.

[0003] Currently, high-accuracy, small-volume reference sources have long stabilization times, while fast-stabilizing reference sources are often large in size and consume significant power, making it difficult to meet the requirements of integrated and miniaturized electronic devices. With the continuous development of frequency source technology, fields such as electronic countermeasures, satellite guidance, metrology and testing, and the development of low-phase-noise microwave equipment have placed even higher demands on the small size and rapid stabilization characteristics of reference signals. Summary of the Invention

[0004] This application provides a reference source and satellite communication system, which can solve the problems that current domestic small-volume reference source products with high frequency accuracy have long stabilization times, and reference sources that can be quickly stabilized often have large size and power consumption, making it difficult to meet the requirements of integration and miniaturization of modern electronic devices.

[0005] In a first aspect, this application provides a reference source, comprising: an atomic clock, a first phase-locked loop (PLL), a low-frequency crystal oscillator, a frequency multiplication and filtering circuit, a second PLL, a high-frequency crystal oscillator, and an output circuit; the atomic clock is used to output a second pulse synchronization signal and a low-frequency reference signal; the first PLL is used to interlock the low-frequency reference signal output by the atomic clock with the first low-frequency signal output by the low-frequency crystal oscillator to obtain a second low-frequency signal; the frequency multiplication and filtering circuit is used to multiply and filter the second low-frequency signal to obtain a first high-frequency signal; the second PLL is used to interlock the first high-frequency signal output by the frequency multiplication and filtering circuit with the frequency division signal output by the high-frequency crystal oscillator to obtain a second high-frequency signal with the same frequency as the first high-frequency signal; the output circuit is used to process the second high-frequency signal and output a high-frequency reference signal.

[0006] Optionally, the atomic clock is a rubidium atomic clock with a thickness below a set threshold.

[0007] Optionally, the low-frequency reference signal output by the atomic clock is a 10MHz reference signal, the low-frequency crystal oscillator is a 10MHz temperature-controlled crystal oscillator, the first low-frequency signal and the second low-frequency signal are both 10MHz signals, the first high-frequency signal is 50MHz, and the second high-frequency signal is 100MHz.

[0008] Optionally, the first phase-locked loop includes: a digital phase detector, a loop filter, and a loop amplifier; the two input terminals of the digital phase detector are electrically connected to the low-frequency reference signal output terminal of the atomic clock and the first low-frequency signal output terminal of the low-frequency crystal oscillator, respectively, and the output terminal of the digital phase detector is electrically connected to the control terminal of the low-frequency crystal oscillator via the loop filter and the loop amplifier in sequence, forming a closed-loop phase-locked link.

[0009] Optionally, the digital phase detector in the first phase-locked loop is a gate phase detector or a trigger-type phase detector.

[0010] Optionally, the loop filter in the first phase-locked loop is an active filter or a passive filter.

[0011] Optionally, the frequency multiplier filter circuit includes a frequency multiplier and a filter; the frequency multiplier is used to perform spectral expansion on the second low-frequency signal to generate multi-order harmonic signals; the filter is used to extract the first high-frequency signal from the multi-order harmonic signals; wherein, the frequency multiplier is a step diode or a digital frequency multiplier.

[0012] Optionally, the frequency of the high-frequency crystal oscillator output signal is consistent with the frequency of the first high-frequency signal; the second phase-locked loop includes a digital phase detector, a loop filter, and a loop amplifier. The two input terminals of the digital phase detector are electrically connected to the first high-frequency signal output terminal of the frequency multiplication filter circuit and the frequency division signal output terminal of the high-frequency crystal oscillator, respectively. The output terminal of the digital phase detector is electrically connected to the control terminal of the high-frequency crystal oscillator in sequence through the loop filter and the loop amplifier, forming a closed-loop phase-locked link.

[0013] Optionally, the output circuit includes a power divider and an amplifier; the power divider is used to distribute the power of the second high-frequency signal; the amplifier is used to amplify the power-distributed signal; wherein the power divider is a two-way power divider or a multi-way power divider.

[0014] Secondly, this application provides a satellite communication receiving system, comprising: an antenna receiving module, a down-conversion module, a signal demodulation module, a data processing module, and a reference source as described above; the antenna receiving module is used to receive radio frequency communication signals transmitted by a satellite and transmit the radio frequency communication signals to the down-conversion module; the reference source transmits reference signals to the down-conversion module and the signal demodulation module respectively, providing a local oscillator reference signal for the down-conversion module and a clock reference signal for the signal demodulation module; the input terminal of the down-conversion module is electrically connected to the output terminal of the antenna receiving module and the output terminal of the reference source respectively, for base... The received radio frequency communication signal is down-converted to an intermediate frequency (IF) communication signal by the local oscillator reference signal, and the IF communication signal is transmitted to the signal demodulation module. The input terminal of the signal demodulation module is electrically connected to the output terminal of the down-conversion module and the output terminal of the reference source, respectively, and is used to demodulate the IF communication signal based on the clock reference signal to obtain a baseband data signal, and transmit the baseband data signal to the data processing module. The input terminal of the data processing module is electrically connected to the output terminal of the signal demodulation module, and is used to process the baseband data signal and output satellite communication data that conforms to a preset communication standard.

[0015] As can be seen from the above technical solution, the present invention provides a reference source and satellite communication system. It adopts a miniaturized design and integrates an ultra-thin rubidium clock, a temperature-controlled crystal oscillator, and an ultra-low phase noise crystal oscillator. It has the characteristics of small size and low cost, which meets the application requirements of miniaturized or highly integrated scenarios and has broad prospects. It adopts multi-level frequency synthesis technology, which makes the output reference signal fast and stable with low phase noise, meeting the requirements of time and frequency measurement, radar detection and other fields for reference sources, and has a wide range of applications. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 shows a block diagram of the miniaturized fast-stabilized reference source in an embodiment of this application; Figure 2 shows a principle block diagram of the miniaturized fast-stabilized reference source in an embodiment of this application; Figure 3 shows the test results of the 100MHz output port in an embodiment of this application. Detailed Implementation

[0018] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not limiting, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application can also be implemented in other embodiments without such specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of this application with unnecessary detail.

[0019] In a first aspect embodiment, referring to the block diagram of the miniaturized fast-stabilized reference source shown in Figure 1, the principle block diagram of the miniaturized fast-stabilized reference source shown in Figure 2, and the test results of the 100MHz output port shown in Figure 3, as shown in Figures 1 to 3, this application embodiment provides a reference source, including: an atomic clock, a first phase-locked loop, a low-frequency crystal oscillator, a frequency multiplication filter circuit, a second phase-locked loop, a high-frequency crystal oscillator, and an output circuit; the atomic clock is used to output a second pulse synchronization signal and a low-frequency reference signal; the first phase-locked loop is used to interlock the low-frequency reference signal output by the atomic clock with the first low-frequency signal output by the low-frequency crystal oscillator to obtain a second low-frequency signal; the frequency multiplication filter circuit is used to multiply and filter the second low-frequency signal to obtain a first high-frequency signal; the second phase-locked loop is used to interlock the first high-frequency signal output by the frequency multiplication filter circuit with the frequency division signal output by the high-frequency crystal oscillator to obtain a second high-frequency signal with the same frequency as the first high-frequency signal; the output circuit is used to process the second high-frequency signal and output a high-frequency reference signal.

[0020] In this embodiment, the provided reference source aims to solve the problem of existing reference sources struggling to balance miniaturization, stable speed, and signal quality. It achieves efficient generation of a high-frequency reference signal through the coordinated operation of an atomic clock, a first phase-locked loop, a low-frequency crystal oscillator, a frequency multiplication filter circuit, a second phase-locked loop, a high-frequency crystal oscillator, and an output circuit. It should be noted that the atomic clock is used to provide an initial high-precision synchronization signal and a reference signal. The second pulse synchronization signal ensures time synchronization between the reference source and the external system, while the low-frequency reference signal serves as the basis for subsequent signal processing, ensuring the starting point of frequency accuracy for the entire signal link.

[0021] In this embodiment, the core function of the first phase-locked loop is to interlock the low-frequency reference signal output by the atomic clock with the first low-frequency signal output by the low-frequency crystal oscillator. This step combines the high accuracy of the atomic clock with the short-term stability of the low-frequency crystal oscillator to obtain a second low-frequency signal with better performance. For example, if only the atomic clock output signal is relied upon, there may be a problem of large short-term fluctuations, while relying only on the low-frequency crystal oscillator makes it difficult to guarantee long-term frequency accuracy. After the two are interlocked by the first phase-locked loop, they can achieve complementary advantages.

[0022] In this embodiment, the frequency multiplication filter circuit is used to multiply and filter the second low-frequency signal. The reason for multiplying the frequency is that higher frequency reference signals are often required in practical applications, while directly generating high-frequency reference signals is more difficult and costly. By multiplying the low-frequency signal, the required first high-frequency signal can be obtained efficiently while ensuring accuracy. It should be noted that filtering is an essential step because multiple harmonic signals are generated during the frequency multiplication process. If filtering is not performed, the excess harmonics will interfere with the target high-frequency signal, resulting in a decrease in signal purity and affecting the subsequent application effect.

[0023] In this embodiment, the second phase-locked loop interlocks the first high-frequency signal output by the frequency multiplier filter circuit with the frequency-divided signal output by the high-frequency crystal oscillator to obtain the second high-frequency signal. The purpose of this step is to further optimize the stability and phase noise performance of the high-frequency signal. It should be noted that after the high-frequency crystal oscillator output signal is processed by frequency division, its frequency is consistent with the first high-frequency signal. This is necessary to meet the requirements of the phase-locked loop for frequency matching of the input signal and ensure the accuracy of the phase-locking process.

[0024] In this embodiment, the processing of the second high-frequency signal by the output circuit is mainly to adapt to the signal requirements of external devices, such as signal power intensity and impedance matching. For example, if the external device requires multiple reference signals, the output circuit can achieve signal multi-path distribution through appropriate design. If the external device has requirements for signal strength, the output circuit can increase the signal power through amplification. This application is not limited to this. In actual design, the function of the output circuit can be adjusted according to the specific application scenario, such as adding impedance matching circuits, filtering circuits, etc., to further optimize the adaptability of the output signal.

[0025] In some embodiments, the atomic clock is a rubidium atomic clock with a thickness below a set threshold. In this application embodiment, the atomic clock is limited to a rubidium atomic clock with a thickness below the set threshold. The reason for choosing a rubidium atomic clock is that, compared to other types of atomic clocks (such as cesium atomic clocks and hydrogen atomic clocks), rubidium atomic clocks offer a better balance between size, weight, power consumption, and accuracy, making them more suitable for reference source designs that require miniaturization. It should be noted that the core purpose of setting the thickness threshold is to achieve miniaturization of the reference source, avoiding the situation where the entire reference source cannot fit into a compact installation environment due to an excessively large atomic clock.

[0026] In this embodiment, the rubidium atomic clock with a thickness below a set threshold not only meets the miniaturization requirements but also has a fast locking speed, which is crucial for the "fast stabilization" characteristic of the reference source. For example, in some scenarios that require rapid startup and deployment (such as emergency communication equipment and portable testing instruments), the fast locking characteristic of the rubidium atomic clock can shorten the startup and stabilization time of the reference source, ensuring that the device quickly enters a normal working state.

[0027] This application is not limited to this. In addition to rubidium atomic clocks, other types of atomic clocks (such as miniature cesium atomic clocks) that can meet the requirements of having a thickness below the set threshold and possessing the required accuracy and stable speed can also be used in this reference source. It should be noted that the thickness set threshold of the atomic clock is not a fixed value, but is determined according to the overall miniaturization goal of the reference source. The thickness threshold of the atomic clock can be adjusted accordingly for reference sources in different application scenarios.

[0028] In some embodiments, the low-frequency reference signal output by the atomic clock is a 10MHz reference signal, the low-frequency crystal oscillator is a 10MHz temperature-controlled crystal oscillator, the first low-frequency signal and the second low-frequency signal are both 10MHz signals, the first high-frequency signal is 50MHz, and the second high-frequency signal is 100MHz.

[0029] In this embodiment of the application, the low-frequency reference signal output by the atomic clock is explicitly defined as a 10MHz reference signal, the low-frequency crystal oscillator is a 10MHz temperature-controlled crystal oscillator, and both the first low-frequency signal and the second low-frequency signal are 10MHz signals. 10MHz is chosen as the frequency of the low-frequency signal because 10MHz is a commonly used reference frequency in the time and frequency field. It has good stability, and the related signal processing devices (such as phase detectors and filters) are technically mature, easy to obtain, and have reliable performance, which can reduce the design difficulty and cost of the reference source.

[0030] In this embodiment, a temperature-controlled crystal oscillator is selected for the low-frequency signal because it can maintain a stable output frequency over a wide temperature range, reducing the impact of ambient temperature changes on the accuracy of the low-frequency signal. It should be noted that if a room-temperature crystal oscillator is selected, its frequency will change significantly with ambient temperature fluctuations, which will affect the quality of the second low-frequency signal obtained after the first phase-locked loop is interlocked, ultimately leading to a decrease in the accuracy of the entire reference source's output signal. Therefore, the selection of a temperature-controlled crystal oscillator is an important factor in ensuring the frequency stability of the reference source.

[0031] In this embodiment, both the first low-frequency signal and the second low-frequency signal are 10MHz signals. This design ensures that the two input signals of the first phase-locked loop have the same frequency, enabling direct phase comparison without additional frequency conversion steps. This simplifies the structure of the first phase-locked loop and reduces errors introduced by frequency conversion. For example, if the two input signals have different frequencies, they need to be adjusted to the same frequency signal by frequency division or multiplication. This not only increases circuit complexity but may also introduce additional noise and errors, affecting the phase-locking effect.

[0032] This application is not limited to this. In addition to 10MHz, other low-frequency frequencies with good stability and suitable for use as a reference (such as 5MHz and 20MHz) can also be used as low-frequency signal frequencies in this reference source. Accordingly, the frequency of the low-frequency crystal oscillator also needs to be adjusted to the corresponding frequency. It should be noted that when different low-frequency frequencies are selected, it is necessary to ensure that the subsequent frequency doubling and filtering circuit can be adapted to the frequency in order to successfully obtain the required first high-frequency signal.

[0033] It is understood that the first high-frequency signal is 50MHz and the second high-frequency signal is 100MHz.

[0034] In some embodiments, the first phase-locked loop includes: a digital phase detector, a loop filter, and a loop amplifier; the two input terminals of the digital phase detector are electrically connected to the low-frequency reference signal output terminal of the atomic clock and the first low-frequency signal output terminal of the low-frequency crystal oscillator, respectively, and the output terminal of the digital phase detector is electrically connected to the control terminal of the low-frequency crystal oscillator via the loop filter and the loop amplifier in sequence, forming a closed-loop phase-locked link.

[0035] Specifically, in this embodiment, the first phase-locked loop includes a digital phase detector, a loop filter, and a loop amplifier. The components are connected in a manner that "the output of the digital phase detector is sequentially connected to the low-frequency crystal oscillator control terminal via the loop filter and the loop amplifier" to form a closed-loop phase-locked link. This closed-loop structure is the core of the phase-locked loop's ability to achieve signal interlocking. Through continuous signal comparison, filtering, and amplification, the output signal of the low-frequency crystal oscillator is continuously adjusted to keep it consistent with the low-frequency reference signal output by the atomic clock.

[0036] In this embodiment, the two input terminals of the digital phase detector are electrically connected to the low-frequency reference signal output terminal of the atomic clock and the first low-frequency signal output terminal of the low-frequency crystal oscillator, respectively. Its function is to detect the phase difference between the two input signals and convert the phase difference into a corresponding voltage signal (i.e., error voltage signal). It should be noted that, compared with the analog phase detector, the digital phase detector has higher phase detection accuracy and stability, and can more accurately capture the phase difference between the two signals, providing a reliable basis for subsequent signal adjustment.

[0037] In this embodiment, the loop filter is configured to filter the error voltage signal output by the digital phase detector, removing high-frequency noise and spurious signals to obtain a smooth control voltage signal. For example, if the error voltage signal is not filtered, the high-frequency components will cause large fluctuations in the control signal output by the loop amplifier, which will in turn make the output signal of the low-frequency crystal oscillator unstable and affect the quality of the second low-frequency signal. Therefore, the loop filter is a key component to ensure the stable operation of the first phase-locked loop.

[0038] In this embodiment, the loop amplifier amplifies the control voltage signal output by the loop filter to give it sufficient driving capability to control the frequency adjustment of the low-frequency crystal oscillator. It should be noted that the control voltage signal output by the loop filter is usually small in amplitude and cannot directly drive the low-frequency crystal oscillator for frequency adjustment. Therefore, it must be amplified by the loop amplifier to ensure that the control signal can effectively act on the low-frequency crystal oscillator.

[0039] This application is not limited to this. In the specific design of the first phase-locked loop, the models and parameters of the digital phase detector, loop filter and loop amplifier can be selected according to actual needs, as long as the low-frequency reference signal and the first low-frequency signal can be stably interlocked to obtain the required second low-frequency signal. For example, if the phase-locking speed requirement is high, a digital phase detector with a faster response speed can be selected; if the noise control requirement is high, a loop filter with better filtering performance can be selected.

[0040] In some embodiments, the digital phase detector in the first phase-locked loop is a gate phase detector or a trigger-type phase detector.

[0041] In this embodiment, the digital phase detector in the first phase-locked loop can be either a gate phase detector or a trigger-type phase detector. Both of these phase detectors are common types of digital phase detectors, each with its own advantages and applicable scenarios, and can meet the phase detection requirements of the first phase-locked loop under different application needs.

[0042] In this embodiment, the advantage of the gate phase detector is that it has a relatively simple structure and low cost, and it has good stability in low-frequency signal phase detection scenarios. It is suitable for scenarios where cost and stability are required, but the phase detection speed requirement is not extreme. For example, in some applications where the cost of the reference source is strictly controlled and the operating frequency of the reference source is relatively fixed, choosing a gate phase detector can reduce the overall design cost while ensuring the phase detection accuracy.

[0043] In this embodiment, the advantage of the trigger-type phase detector is its faster response speed, which enables it to capture the phase change between two input signals more quickly, making it suitable for scenarios with high requirements for phase-locked loop speed. It should be noted that in some applications that require the reference source to start up quickly and achieve stability, the fast response characteristics of the trigger-type phase detector can shorten the locking time of the first phase-locked loop, thereby improving the fast and stable performance of the entire reference source.

[0044] This application is not limited to this. In addition to gate phase detectors and trigger-type phase detectors, other digital phase detectors with corresponding phase detection accuracy and speed (such as sampling phase detectors and coherent phase detectors) can also be applied to the first phase-locked loop. It should be noted that when selecting different types of digital phase detectors, it is necessary to take into account the overall design goals of the first phase-locked loop (such as phase-locking speed, phase detection accuracy, and cost control) to ensure that the phase detector can be compatible with other components in the loop (such as loop filters and loop amplifiers).

[0045] In some embodiments, the loop filter in the first phase-locked loop is an active filter or a passive filter.

[0046] In this embodiment, the loop filter in the first phase-locked loop can be either an active filter or a passive filter. These two types of filters differ in terms of filtering performance, structural complexity, and cost, and can be selected according to the specific requirements of the first phase-locked loop.

[0047] In this embodiment, the advantages of passive filters are simple structure, no need for external power supply, high reliability and low cost. They are suitable for scenarios where the filtering depth requirement is not extreme and where it is desirable to simplify the circuit structure and reduce costs. For example, in some applications where the reference source volume is limited and the requirements for signal and noise control are relatively relaxed, the simple structure of passive filters can reduce the circuit space occupied and reduce design and manufacturing costs.

[0048] In this embodiment, the advantage of the active filter is that it has a deeper filtering depth and stronger out-of-band suppression capability, which can more effectively remove high-frequency noise and clutter in the error voltage signal. It is suitable for scenarios with high requirements for signal noise control and where it is desirable to further improve the stability of the second low-frequency signal. It should be noted that the active filter requires an external power supply and has a relatively complex structure and higher cost than the passive filter. Therefore, when selecting it, the relationship between filtering performance and circuit complexity and cost must be weighed.

[0049] This application is not limited to this. In addition to active and passive filters, other filter structures that can achieve error voltage signal filtering (such as RC active filters, LC passive filters, and surface acoustic wave filters) can also be applied to the first phase-locked loop. It should be noted that the selection of the loop filter must be matched with the performance of the digital phase detector and the loop amplifier to ensure that the bandwidth, response speed and other parameters of the entire first phase-locked loop meet the design requirements in order to achieve a stable phase-locking effect.

[0050] In some embodiments, the frequency multiplier filter circuit includes a frequency multiplier and a filter; the frequency multiplier is used to perform spectral expansion on the second low-frequency signal to generate a multi-order harmonic signal; the filter is used to extract the first high-frequency signal from the multi-order harmonic signal; wherein the frequency multiplier is a step diode or a digital frequency multiplier.

[0051] Specifically, in the embodiments of this application, the frequency multiplier filter circuit includes a frequency multiplier and a filter. The two have a clear division of labor: the frequency multiplier is responsible for spectral expansion of the second low-frequency signal to generate multi-order harmonic signals, while the filter is responsible for extracting the required first high-frequency signal from the multi-order harmonic signals, thereby realizing an efficient and reliable solution for converting low-frequency signals to high-frequency signals.

[0052] In this embodiment, the frequency multiplier is selected as a step diode or a digital frequency multiplier. The advantage of the step diode frequency multiplier is that it has a wider operating frequency range and a relatively simple structure, making it suitable for scenarios where the frequency multiplication efficiency requirement is not extreme and where it is desirable to simplify the circuit design. For example, in some applications where the operating frequency range of the reference source is wide, the step diode frequency multiplier can adapt to second low-frequency signals of different frequencies to achieve flexible frequency multiplication processing.

[0053] In this embodiment, the advantage of the digital frequency multiplier is that it has high frequency multiplication accuracy and less output signal spuriousness. It can generate multi-order harmonic signals with higher purity and is suitable for scenarios with high requirements for the purity of the first high-frequency signal. It should be noted that digital frequency multipliers usually require an external clock signal to drive them and have a relatively complex structure. Their cost is higher than that of step diode frequency multipliers. Therefore, when selecting one, a comprehensive judgment should be made based on the purity requirements of the first high-frequency signal, circuit complexity, and cost budget.

[0054] In this embodiment, the filter's function is to select the target frequency signal (i.e., the first high-frequency signal) from the multi-order harmonic signals output by the frequency multiplier, and suppress other frequency harmonic signals and noise. It should be noted that the filter's filtering performance directly determines the purity of the first high-frequency signal. If the filtering effect is poor, excess harmonic signals will enter the subsequent second phase-locked loop along with the first high-frequency signal, affecting the quality of the second high-frequency signal and thus reducing the output signal performance of the entire reference source.

[0055] This application is not limited to this. In addition to step diodes and digital frequency multipliers, other devices with frequency multiplication functions (such as varactor diode frequency multipliers and transistor frequency multipliers) can also be used as frequency multipliers in frequency multiplication filter circuits. At the same time, the type of filter can also be selected according to actual needs, as long as it can effectively extract the first high-frequency signal and suppress noise. For example, if the filtering speed requirement is high, a filter with a faster response speed can be selected; if the out-of-band rejection requirement is high, a filter with stronger out-of-band rejection capability can be selected.

[0056] In some embodiments, the frequency of the high-frequency crystal oscillator output signal is consistent with the frequency of the first high-frequency signal; the second phase-locked loop includes a digital phase detector, a loop filter, and a loop amplifier. The two input terminals of the digital phase detector are electrically connected to the first high-frequency signal output terminal of the frequency multiplication filter circuit and the frequency division signal output terminal of the high-frequency crystal oscillator, respectively. The output terminal of the digital phase detector is electrically connected to the control terminal of the high-frequency crystal oscillator in sequence through the loop filter and the loop amplifier, forming a closed-loop phase-locked link.

[0057] Specifically, in this embodiment, the frequency of the high-frequency crystal oscillator output signal is consistent with the frequency of the first high-frequency signal. This design is to ensure that the frequencies of the two input signals of the second phase-locked loop (the first high-frequency signal output by the frequency multiplier filter circuit and the frequency-divided signal output by the high-frequency crystal oscillator) are matched, so that the phase can be compared by the phase detector to achieve stable phase locking. It should be noted that if the frequency of the high-frequency crystal oscillator output signal is inconsistent with the frequency of the first high-frequency signal, one of the signals needs to be divided or multiplied to make its frequency consistent with the other signal. This will increase the circuit complexity and may introduce additional errors and noise. Therefore, directly designing the frequency of the high-frequency crystal oscillator output signal to be consistent with the frequency of the first high-frequency signal is a better solution.

[0058] In this embodiment, the second phase-locked loop includes a digital phase detector, a loop filter, and a loop amplifier. Its structure is similar to that of the first phase-locked loop, but its function is different. The core purpose of the second phase-locked loop is to combine the high accuracy of the first high-frequency signal with the low phase noise characteristics of the high-frequency crystal oscillator to generate a second high-frequency signal with high accuracy and low phase noise. It should be noted that although the first high-frequency signal has high accuracy, it may have a problem with high phase noise, while the high-frequency crystal oscillator has low phase noise, but its accuracy depends on external signal calibration. The two are interlocked through the second phase-locked loop, which can achieve complementary performance and improve the overall quality of the high-frequency signal.

[0059] In this embodiment, the two input terminals of the digital phase detector in the second phase-locked loop are electrically connected to the first high-frequency signal output terminal of the frequency multiplier filter circuit and the frequency divider signal output terminal of the high-frequency crystal oscillator, respectively. Its function is to detect the phase difference between the two input signals and convert the phase difference into an error voltage signal. For example, if there is a phase difference between the first high-frequency signal and the frequency-divided high-frequency crystal oscillator signal, the digital phase detector will output a corresponding error voltage signal. This signal is then processed to adjust the output signal of the high-frequency crystal oscillator until the two signals are in phase.

[0060] In this embodiment, the loop filter and loop amplifier of the second phase-locked loop function similarly to their counterparts in the first phase-locked loop, respectively filtering the error voltage signal and amplifying the control signal. It should be noted that since the second phase-locked loop processes high-frequency signals, the performance parameters (such as bandwidth, response speed, and noise level) of its loop filter and loop amplifier need to be adapted to the characteristics of high-frequency signals to ensure the stable operation of the phase-locked loop and the signal processing effect.

[0061] This application is not limited to this. In the design of the second phase-locked loop, the models and parameters of the digital phase detector, loop filter, and loop amplifier can be adjusted according to the performance requirements of the second high-frequency signal (such as accuracy, phase noise, and stabilization speed). At the same time, the type of high-frequency crystal oscillator can also be selected according to the requirements, as long as its output signal frequency can be consistent with the frequency of the first high-frequency signal and has the required phase noise performance. For example, if the phase noise requirement of the second high-frequency signal is extremely high, a high-frequency crystal oscillator with ultra-low phase noise can be selected.

[0062] In some embodiments, the output circuit includes a power divider and an amplifier; the power divider is used to distribute the power of a second high-frequency signal; the amplifier is used to amplify the power-divided signal; wherein the power divider is a two-way power divider or a multi-way power divider.

[0063] In this embodiment, the output circuit includes a power divider and an amplifier. The two are configured to ensure that the high-frequency reference signal output by the reference source can meet the requirements of the external device. The power divider is mainly used to distribute the power of the second high-frequency signal, while the amplifier is used to amplify the signal after power distribution to increase the signal power intensity.

[0064] In this embodiment, the power divider is selected as a two-way power divider or a multi-way power divider. The advantage of a two-way power divider is that it has a simple structure and high power distribution uniformity, making it suitable for scenarios where external devices only need two high-frequency reference signals. For example, in some devices that only need to provide reference signals to two external modules, a two-way power divider can achieve uniform signal distribution and ensure that the two modules obtain reference signals with consistent performance.

[0065] In this embodiment, the advantage of the power divider is that it can achieve multi-channel signal distribution, meet the high-frequency reference signal requirements of multiple modules of external devices, and is suitable for complex systems that require multiple reference signals. It should be noted that the number of channels of the power divider can be determined according to the needs of the external devices, and when selecting it, attention should be paid to its insertion loss and power distribution uniformity. Excessive insertion loss will lead to excessive signal power attenuation, and poor power distribution uniformity will lead to large power differences between different output signals, affecting the working stability of the external devices.

[0066] In this embodiment, the amplifier amplifies the signal output by the power divider. This is because the power divider generates a certain insertion loss during power distribution, resulting in a decrease in signal power. Without amplification, the signal power requirements of external devices may not be met. It should be noted that the selection of the amplifier should focus on its noise level, with a preference for low-noise amplifiers to avoid introducing too much noise during amplification, which could affect the quality of the high-frequency reference signal. For example, if the external device is sensitive to signal noise, a low-noise amplifier can increase signal power while minimizing noise introduction, ensuring signal purity.

[0067] This application is not limited to this. In addition to two-way power dividers and multi-way power dividers, other devices with power distribution functions (such as directional couplers and power dividers) can also be used as power dividers in the output circuit. At the same time, the type of amplifier can also be adjusted according to the requirements, such as selecting amplifiers with different gains according to the signal power requirements, or selecting amplifiers adapted to high-frequency signals according to the signal frequency. It should be noted that the output circuit can also add other functional modules according to actual needs, such as impedance matching modules and filtering modules, to further optimize the output performance of high-frequency reference signals and improve compatibility with external devices.

[0068] The following is a specific example to illustrate this application in detail.

[0069] This embodiment provides a miniaturized, fast-stabilizing reference source based on multi-level frequency synthesis technology. The circuit includes an ultra-thin rubidium clock, a first phase-locked loop, a 10MHz temperature-controlled crystal oscillator, a frequency doubling filter circuit, a second phase-locked loop, a 100MHz ultra-low phase noise crystal oscillator, and an output circuit, as shown in Figure 1.

[0070] When the miniaturized, fast-stabilizing reference source is working, the 10MHz high-frequency accurate signal output from the ultra-thin rubidium clock and the 10MHz temperature-controlled crystal oscillator output signal are interlocked through a gate phase detector and a loop filter amplifier to output a high-frequency accurate 10MHz signal. The square wave generated by the locked 10MHz signal after passing through the gate circuit has rich spectral components. The useful fifth harmonic signal is filtered out using a surface acoustic wave (SAW) filter to realize the function of the frequency doubling filter circuit. The 100MHz signal generated by the ultra-low phase noise crystal oscillator is frequency divided and interlocked with the signal output from the frequency doubling filter circuit through a second phase-locked loop to generate a high-accuracy 100MHz ultra-low phase noise signal. After passing through an output circuit composed of transistor amplification and a filter, a high-spectral-purity 100MHz reference signal is output. The principle block diagram is shown in Figure 2.

[0071] In the first phase-locked loop (PLL), to ensure both high frequency accuracy and good near-end phase noise in the output signal after the 10MHz cryogenic crystal oscillator is locked, a suitable loop bandwidth needs to be set. In this example, the loop bandwidth is set to around 1Hz. In the second PLL, to achieve ultra-low phase noise in the 100MHz output signal, the loop bandwidth needs to be adjusted to near the intersection of the phase noise parameters of the 10MHz cryogenic crystal oscillator and the 100MHz ultra-low phase noise crystal oscillator. In this example, the loop bandwidth is set to around 30Hz.

[0072] The miniaturized and fast-stabilized reference source structure is designed as a box containing two cavities, separated by a 2mm crossbeam. A 10MHz temperature-controlled crystal oscillator and a 100MHz ultra-low phase noise crystal oscillator are alternately installed on both sides to ensure signal spectrum quality while improving space utilization. A small-volume, ultra-thin, fast-locking rubidium clock is selected to achieve the miniaturized design.

[0073] In this embodiment, the reference source outputs a high-frequency, accurate, low-phase-noise 100MHz reference signal. Its frequency accuracy is better than ±3E-9 for three minutes after power-on and better than ±5E-11 for eight minutes and beyond. Its dimensions are 88×135×20.5 (mm), featuring small size and fast stability.

[0074] In a second aspect embodiment, a satellite communication receiving system is provided, comprising: an antenna receiving module, a down-conversion module, a signal demodulation module, a data processing module, and a reference source as described above; the antenna receiving module is used to receive radio frequency communication signals transmitted by a satellite and transmit the radio frequency communication signals to the down-conversion module; the reference source transmits reference signals to the down-conversion module and the signal demodulation module respectively, providing a local oscillator reference signal for the down-conversion module and a clock reference signal for the signal demodulation module; the input terminal of the down-conversion module is electrically connected to the output terminal of the antenna receiving module and the output terminal of the reference source respectively, for base... The received radio frequency communication signal is down-converted to an intermediate frequency (IF) communication signal by the local oscillator reference signal, and the IF communication signal is transmitted to the signal demodulation module. The input terminal of the signal demodulation module is electrically connected to the output terminal of the down-conversion module and the output terminal of the reference source, respectively, and is used to demodulate the IF communication signal based on the clock reference signal to obtain a baseband data signal, and transmit the baseband data signal to the data processing module. The input terminal of the data processing module is electrically connected to the output terminal of the signal demodulation module, and is used to process the baseband data signal and output satellite communication data that conforms to a preset communication standard.

[0075] The technical efficacy of the satellite communication receiving system in this application corresponds to the aforementioned reference source, and will not be elaborated upon here.

[0076] In this embodiment, the reference source provides a local oscillator reference signal to the downconversion module. Based on this local oscillator reference signal, the downconversion module downconverts the radio frequency communication signal transmitted by the antenna receiving module into an intermediate frequency (IF) communication signal. It should be noted that radio frequency communication signals have high frequencies, making direct demodulation difficult and costly. Converting them to IF signals through downconversion reduces the difficulty of subsequent demodulation and facilitates the selection of mature IF signal processing devices, thereby improving the reliability and economy of the system. The accuracy of the local oscillator reference signal directly determines the accuracy of the downconversion process. If there is a frequency deviation in the local oscillator reference signal, it will cause the frequency of the downconverted IF communication signal to shift, affecting the subsequent demodulation effect. Therefore, the local oscillator reference signal provided by the reference source must have high frequency accuracy.

[0077] In this embodiment, the reference source also provides a clock reference signal to the signal demodulation module. The signal demodulation module demodulates the intermediate frequency communication signal transmitted by the downconversion module based on the clock reference signal to obtain the baseband data signal. It should be noted that the demodulation process has extremely high requirements for the stability of the clock signal. If there are fluctuations or noise in the clock reference signal, it will cause bit errors in the demodulated baseband data signal, affecting the accuracy of the data. Therefore, the clock reference signal provided by the reference source must have low phase noise and high stability to ensure the reliable performance of the demodulation process.

[0078] In this embodiment, the data processing module processes the baseband data signal output by the signal demodulation module, and finally outputs satellite communication data that conforms to a preset communication standard. For example, the processing steps of the data processing module may include filtering (removing noise from the baseband data signal), error correction (correcting errors generated during demodulation), and format conversion (converting the baseband data signal into a data format recognizable by external devices). It should be noted that the processing logic of the data processing module needs to be determined according to the preset communication standard. Different communication standards have different requirements for data format, error correction methods, etc., therefore the data processing module needs to possess a certain degree of flexibility. To adapt to different application scenarios, this application is not limited to this. The satellite communication receiving system can also add other functional modules according to actual needs, such as a signal amplification module (added between the antenna receiving module and the down-conversion module to increase the power of the radio frequency communication signal), an interference suppression module (to reduce the impact of external interference on signal processing), etc. At the same time, the installation position of the reference source in the system can also be adjusted according to the overall layout of the system, as long as it can ensure that it provides a stable reference signal for the down-conversion module and the signal demodulation module. For example, if the system has high requirements for miniaturization, the reference source can be integrated with other modules to further reduce the overall size.

[0079] This application uses specific embodiments to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the methods and ideas of this application. At the same time, for those skilled in the art, there may be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A reference source, characterized in that, include: Atomic clock, first phase-locked loop, low-frequency crystal oscillator, frequency doubling filter circuit, second phase-locked loop, high-frequency crystal oscillator and output circuit; The atomic clock is used to output a second pulse synchronization signal and a low-frequency reference signal; the first phase-locked loop is used to interlock the low-frequency reference signal output by the atomic clock with the first low-frequency signal output by the low-frequency crystal oscillator to obtain a second low-frequency signal; the frequency multiplier filter circuit is used to multiply and filter the second low-frequency signal to obtain a first high-frequency signal; the second phase-locked loop is used to interlock the first high-frequency signal output by the frequency multiplier filter circuit with the frequency divider signal output by the high-frequency crystal oscillator to obtain a second high-frequency signal; the output circuit is used to process the second high-frequency signal and output a high-frequency reference signal.

2. The reference source according to claim 1, characterized in that, The atomic clock is a rubidium atomic clock with a thickness below a set threshold.

3. The reference source according to claim 1, characterized in that, The atomic clock outputs a 10MHz low-frequency reference signal, the low-frequency crystal oscillator is a 10MHz temperature-controlled crystal oscillator, the first low-frequency signal and the second low-frequency signal are both 10MHz signals, the first high-frequency signal is 50MHz, and the second high-frequency signal is 100MHz.

4. The reference source according to claim 1, characterized in that, The first phase-locked loop includes a digital phase detector, a loop filter, and a loop amplifier. The two input terminals of the digital phase detector are electrically connected to the low-frequency reference signal output terminal of the atomic clock and the first low-frequency signal output terminal of the low-frequency crystal oscillator, respectively. The output terminal of the digital phase detector is electrically connected to the control terminal of the low-frequency crystal oscillator via the loop filter and the loop amplifier in sequence, forming a closed-loop phase-locked link.

5. The reference source according to claim 4, characterized in that, The digital phase detector in the first phase-locked loop is a gate phase detector or a trigger-type phase detector.

6. The reference source according to claim 4, characterized in that, The loop filter in the first phase-locked loop is an active filter or a passive filter.

7. The reference source according to claim 1, characterized in that, The frequency multiplier filter circuit includes a frequency multiplier and a filter; the frequency multiplier is used to perform spectral expansion on the second low-frequency signal to generate multi-order harmonic signals; the filter is used to extract the first high-frequency signal from the multi-order harmonic signals; wherein, the frequency multiplier is a step diode or a digital frequency multiplier.

8. The reference source according to claim 1, characterized in that, The frequency of the high-frequency crystal oscillator output signal is consistent with the frequency of the first high-frequency signal; the second phase-locked loop includes a digital phase detector, a loop filter, and a loop amplifier. The two input terminals of the digital phase detector are electrically connected to the first high-frequency signal output terminal of the frequency multiplication filter circuit and the frequency division signal output terminal of the high-frequency crystal oscillator, respectively. The output terminal of the digital phase detector is electrically connected to the control terminal of the high-frequency crystal oscillator in sequence through the loop filter and the loop amplifier, forming a closed-loop phase-locked link.

9. The reference source according to claim 1, characterized in that, The output circuit includes a power divider and an amplifier; the power divider is used to distribute the power of the second high-frequency signal; the amplifier is used to amplify the power-distributed signal; wherein the power divider is a two-way power divider or a multi-way power divider.

10. A satellite communication receiving system, characterized in that, include: The antenna receiving module, the down-conversion module, the signal demodulation module, the data processing module, and the reference source as described in any one of claims 1-9; The antenna receiving module is used to receive radio frequency communication signals transmitted by the satellite and transmit the radio frequency communication signals to the down-conversion module; the reference source transmits reference signals to the down-conversion module and the signal demodulation module respectively, providing a local oscillator reference signal for the down-conversion module and a clock reference signal for the signal demodulation module; The input terminal of the downconversion module is electrically connected to the output terminal of the antenna receiving module and the output terminal of the reference source, respectively, and is used to downconvert the received radio frequency communication signal into an intermediate frequency communication signal based on the local oscillator reference signal, and transmit the intermediate frequency communication signal to the signal demodulation module; The input terminal of the signal demodulation module is electrically connected to the output terminal of the downconverter module and the output terminal of the reference source, respectively. It is used to demodulate the intermediate frequency communication signal based on the clock reference signal to obtain the baseband data signal, and transmit the baseband data signal to the data processing module. The input terminal of the data processing module is electrically connected to the output terminal of the signal demodulation module, and is used to process the baseband data signal and output satellite communication data that conforms to the preset communication standard.

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