Aviation frequency band radio frequency direct acquisition receiver based on FPGA

Abstract

The invention discloses an aviation frequency band radio frequency direct acquisition receiver based on an FPGA (Field Programmable Gate Array), which is integrated in an FPGA chip and comprises a band-pass filtering module, a digital orthogonal down-conversion module, an NCO (Network Controlled Oscillator) frequency control module, a low-pass filtering module, an extraction module and an AGC (Automatic Gain Control) module. According to the scheme, the analog signal processing process of the radio frequency front end part is realized in a digital signal processing mode, so that the analog signal processing process of the radio frequency front end is simplified, the use of analog devices is reduced, the size of the radio frequency front end is reduced, the overall cost of receiver equipment is reduced, and equipment miniaturization is facilitated; and meanwhile, the radio frequency front-end gain control difficulty is reduced, and the index requirements of sensitivity and dynamic range can be met at the same time.

Description

Technical Field

[0001] This invention relates to the field of aviation communication technology, and in particular to an FPGA-based aviation frequency band direct acquisition receiver. Background Technology

[0002] Aviation communication is used to transmit and exchange information such as messages, intelligence, text, instructions, and images. It can be divided into communication between ground control towers and aircraft, and communication between aircraft. As a crucial component of aviation communication systems, receivers currently mostly employ super-extension architectures. Super-extension receivers have complex analog signal processing capabilities, large RF front-ends, and high component costs, posing significant challenges in cost control and miniaturization. Furthermore, controlling the RF front-end gain to meet dynamic range requirements while maintaining sensitivity is also a significant challenge. Summary of the Invention

[0003] To address the aforementioned technical challenges, this invention proposes an FPGA-based direct-sampling receiver for the aviation band, employing digital signal processing to implement the analog signal processing in the RF front-end. The aim is to simplify the analog signal processing in the RF front-end, reduce the use of analog components, decrease the size of the RF front-end, lower the overall cost of the receiver, and facilitate miniaturization. Furthermore, to reduce the difficulty of RF front-end gain control and simultaneously meet the requirements for sensitivity and dynamic range, the specific technical solution is as follows.

[0004] This FPGA-based aviation band RF direct sampling receiver, integrated into a single FPGA chip, includes a bandpass filter module, a digital quadrature downconverter module, an NCO frequency control module, a low-pass filter module, a decimation module, and an AGC automatic gain control module. The receiver first sequentially feeds the ADC-sampled RF signal into the bandpass filter module (Bandpass Filter 1 and Bandpass Filter 2) for filtering. The filtered signal is then fed into the digital quadrature downconverter module for processing, resulting in I and Q signals. The NCO frequency control module provides the local oscillator signal to the digital quadrature downconverter module. The I and Q signals are then sequentially fed into low-pass filter 1, decimation 1, low-pass filter 2, decimation 2, and low-pass filter 3 to complete two stages of downsampling and three stages of low-pass filtering. Finally, both signals are simultaneously fed into the AGC automatic gain control module to adjust the signal amplitude, outputting the final baseband I and baseband Q signals.

[0005] Specifically, the bandpass filter module is connected in sequence to bandpass filter 1 and bandpass filter 2, both of which use FIR filters. The calculation formula is as follows:

[0006]

[0007] Where y is the output of the filter convolution, and h bpThis is the impulse response of a bandpass filter, where x is the input signal and M is the filter order; h bp With the lower sideband w of the passband pl upper passband frequency w ph Lower stopband upper sideband w sl Upper stopband and lower sideband w sh Sampling frequency f s and stopband attenuation a bp The relevant expression is:

[0008] h bp =f(w pl ,w ph ,w sl ,w sh ,f s ,a bp ).

[0009] Specifically, after the bandpass filtering module performs two stages of bandpass filtering on the radio frequency signal, the total out-of-band suppression is equal to the stopband attenuation α of bandpass filter 1. bp,1 With the stopband attenuation a of bandpass filter 2 bp,2 The accumulation of.

[0010] Specifically, the signal processing of the digital quadrature downconversion module and the NCO frequency control module includes: receiving channel control commands through the channel interface; parsing the channel number of the current working channel according to the channel control commands and the corresponding protocol; reading the corresponding frequency control word from the frequency control word stored in the ROM based on the parsed channel number; calculating the relationship between the channel number and the frequency control word using a lookup table; sending the frequency control word to the NCO frequency control module; and outputting the local oscillator signal lo required for quadrature downconversion. cos and lo sin .

[0011] Specifically, the signal processing by the digital quadrature downconversion module and the NCO frequency control module further includes: the radio frequency signal processed by the bandpass filter 1 and the bandpass filter 2 is respectively compared with the local oscillator signal lo. cos and lo sin Multiplying these components yields a mixer s containing the baseband signal, baseband image frequency signal, interference signal, and noise signal. i and s q Signal.

[0012] Specifically, the local oscillator signal required for downconversion by the digital quadrature downconversion module is generated using the DDS IP core within the FPGA; the DDS IP core is configured in an output signal frequency controllable mode, and the output signal frequency is controlled by an input frequency control word. The relationship between the output signal frequency and the frequency control word is as follows:

[0013]

[0014] Among them, f c f is the DDS output frequency. clk The main clock frequency is Δθ, the frequency control word is B, and the frequency control word width is B.

[0015] During quadrature downconversion, the RF signal s after the second-stage bandpass filter bp2 for:

[0016]

[0017] Where f0 is the baseband frequency, f c Let k be the carrier frequency, k be the current time, and fs be the sampling frequency. For phase, in bp2 For interference signals, n bp2 This is a noise signal;

[0018] The formula for calculating quadrature downconversion is:

[0019]

[0020] Among them, in i For I-channel interference signal, n i For I-channel noise signal, n q For Q-channel noise signal, in q This is a Q-channel interference signal.

[0021] Specifically, the relationship between the frequency control word and the DDS output frequency is expressed as follows:

[0022] Specifically, each low-pass filter in the low-pass filter module uses an FIR filter. Out-of-band suppression is achieved by progressively reducing the transition band bandwidth and increasing the stopband attenuation through three stages of low-pass filtering. There is a downsampling decimation process between every two low-pass filter stages. The total out-of-band suppression of the low-pass filter is the product of the stopband attenuation of the three low-pass filters. The impulse response h... lp With cutoff frequency w p Stopband frequency w s Sampling frequency f s and stopband attenuation a lp The relevant expression is:

[0023] h lp =f(w p ,w s ,f s ,a lp ).

[0024] Specifically, the decimation module uses a CIC filter to achieve downsampling decimation, and the CIC filter system response is as follows:

[0025]

[0026] Where R is the decimation factor, M is the differential delay, and N is the filter stage.

[0027] Specifically, the AGC automatic gain control module adopts a logarithmic loop automatic gain control algorithm with base 2 as the logarithm, and the calculation formula includes:

[0028] S out [n] = S in [n]*2 g[n-1] ;

[0029]

[0030] e[n] = A - log2(z[n]);

[0031] g[n] = g[n-1] + K*e[n];

[0032] Among them, S out It is the output signal, S in is the input signal, g is the logarithmic gain, z is the mean filter value of the output signal, N is the size of the mean filter window, e is the error between the logarithm of the average power of the output signal and the set target logarithm of the output power A, and K is the gain adjustment step size.

[0033] The beneficial effects of this invention are as follows: This invention proposes an FPGA-based direct-access RF receiver for the aviation band, which simplifies the analog signal processing of the RF front-end, reduces the use of analog components, reduces the size of the RF front-end, lowers the overall cost of the receiver, and facilitates miniaturization. Compared with existing technologies, it has the following advantages:

[0034] (1) High integration: This invention moves the signal processing process that needs to be performed on the analog end to a single FPGA chip for digital processing, which improves the integration of signal processing and is conducive to reducing the size of the device.

[0035] (2) Low cost: After the analog signal processing is integrated into the FPGA, the RF front-end architecture is simplified, the types and quantities of RF front-end devices required are reduced, which is conducive to reducing equipment costs.

[0036] (3) Simple gain control: This invention has a first-stage AGC after low-pass filtering, which can adaptively adjust the small signal gain, reducing the amplitude requirements of the ADC input signal and helping to balance the system sensitivity and dynamic range requirements.

[0037] (4) Flexible adjustment: FPGA is a programmable logic device. When the design changes, only the corresponding code needs to be modified, without redesigning the hardware circuit.

[0038] (5) Rapid response: When generating the local oscillator signal required for down-conversion, if the frequency changes, it is necessary to wait for the frequency to lock before normal operation can be performed when using a VCO. However, when using a DDS to generate the local oscillator signal, the frequency lock time is negligible. Attached Figure Description

[0039] Figure 1 This is a diagram illustrating the architecture of the aviation frequency band RF direct acquisition receiver based on FPGA of this invention.

[0040] Figure 2 This is a schematic diagram illustrating the principle of frequency control word calculation via table lookup in this embodiment of the invention.

[0041] Figure 3 This is a schematic diagram of the CIC decimation filter structure in an embodiment of the present invention;

[0042] Figure 4 This is a schematic diagram of the automatic gain control (AGC) principle in an embodiment of the present invention. Detailed Implementation

[0043] To provide a clearer understanding of the technical features, objectives, and effects of the present invention, specific embodiments of the present invention will now be described with reference to the accompanying drawings.

[0044] This invention proposes an FPGA-based direct-access radio frequency receiver for the aviation band, the implementation architecture of which is as follows: Figure 1 As shown, the receiver, integrated into a single FPGA chip, includes a bandpass filter module, a digital quadrature downconverter module, an NCO frequency control module, a low-pass filter module, a decimation module, and an AGC automatic gain control module. The FPGA-based aviation band RF direct sampling receiver first sends the ADC-sampled RF signal sequentially to the bandpass filter module (bandpass filter 1 and bandpass filter 2) for filtering. Then, the filtered signal is sent to the digital quadrature downconverter module for processing to obtain I and Q signals. The NCO frequency control module provides the local oscillator signal to the digital quadrature downconverter module. The I and Q signals are sequentially sent to low-pass filter 1, decimation 1, low-pass filter 2, decimation 2, and low-pass filter 3 to complete two stages of downsampling and three stages of low-pass filtering, respectively. Finally, both signals are simultaneously sent to the AGC automatic gain control module to adjust the signal amplitude, outputting the final baseband I and baseband Q signals.

[0045] In this embodiment, both bandpass filter 1 and bandpass filter 2, which are connected sequentially to the bandpass filter module, use FIR filters, and the calculation formula is as follows:

[0046]

[0047] Where y is the output of the filter convolution, and h bp This is the impulse response of a bandpass filter, where x is the input signal and M is the filter order; hbp With the lower sideband w of the passband pl upper passband frequency w ph Lower stopband upper sideband w sl Upper stopband and lower sideband w sh Sampling frequency f s and stopband attenuation a bp The relevant expression is:

[0048] h bp =f(w pl ,w ph ,w sl ,w sh ,f s ,a bp ).

[0049] In this embodiment, after the bandpass filtering module performs two stages of bandpass filtering on the RF signal, the total out-of-band suppression is equal to the stopband attenuation α of bandpass filter 1. bp,1 With the stopband attenuation a of bandpass filter 2 bp,2 The accumulation of.

[0050] In this embodiment, the signal processing of the digital quadrature downconverter module and the NCO frequency control module specifically includes: receiving channel control commands through the channel interface; parsing the channel number of the current working channel according to the channel control commands and the corresponding protocol; reading the corresponding frequency control word from the frequency control word pre-stored in the ROM based on the parsed channel number; calculating the relationship between the channel number and the frequency control word using a lookup table; sending the frequency control word to the NCO frequency control module; and outputting the local oscillator signal lo required for quadrature downconversion. cos and lo sin It also includes: the RF signal processed by the bandpass filtering modules (bandpass filter 1 and bandpass filter 2) and the local oscillator signal lo, respectively. cos and lo sin Multiplying these components yields a mixer s containing the baseband signal, baseband image frequency signal, interference signal, and noise signal. i and s q Signal.

[0051] In this embodiment, the local oscillator signal required for downconversion by the digital quadrature downconversion module is generated using the DDS IP core within the FPGA; the DDS IP core is configured in an output signal frequency controllable mode, and the output signal frequency is controlled by an input frequency control word. The relationship between the output signal frequency and the frequency control word is as follows:

[0052]

[0053] Among them, f c f is the DDS output frequency. clk The main clock frequency is Δθ, the frequency control word is B, and the frequency control word width is B.

[0054] During quadrature downconversion, the RF signal s after the second-stage bandpass filter bp2 for:

[0055]

[0056] Where f0 is the baseband frequency, f c Let f be the carrier frequency, k be the current time, and f be the carrier frequency. s Sampling frequency, For phase, in bp2 For interference signals, n bp2 This is a noise signal;

[0057] The formula for calculating quadrature downconversion is:

[0058]

[0059] Among them, in i For I-channel interference signal, n i For I-channel noise signal, n q For Q-channel noise signal, in q This is a Q-channel interference signal.

[0060] The relationship between the frequency control word and the DDS output frequency is expressed as follows:

[0061] In this embodiment, each low-pass filter (low-pass filter 1, low-pass filter 2, and low-pass filter 3) in the low-pass filter module uses an FIR filter. Out-of-band suppression is achieved by progressively reducing the transition band bandwidth and increasing the stopband attenuation through three stages of low-pass filtering. There is a downsampling decimation process between every two stages of low-pass filters. The total out-of-band suppression of the low-pass filter is the product of the stopband attenuation of the three stages of low-pass filtering. The impulse response h... lp With cutoff frequency w p Stopband frequency w s Sampling frequency f s and stopband attenuation a lp The relevant expression is:

[0062] h lp =f(w p ,w s ,f s ,a lp ).

[0063] In this embodiment, the decimation module uses a CIC filter to achieve downsampling decimation, and the system response of the CIC filter is as follows:

[0064]

[0065] Where R is the decimation factor, M is the differential delay, and N is the filter stage.

[0066] In this embodiment, the AGC automatic gain control module adopts a logarithmic loop automatic gain control algorithm with base 2 as the logarithm. The calculation formula includes:

[0067] S out [n] = S in [n]*2 g[n-1] ;

[0068]

[0069] e[n] = A - log2(z[n]);

[0070] g[n] = g[n-1] + K*e[n];

[0071] Among them, S out It is the output signal, S in is the input signal, g is the logarithmic gain, z is the mean filter value of the output signal, N is the size of the mean filter window, e is the error between the logarithm of the average power of the output signal and the set target logarithm of the output power A, and K is the gain adjustment step size.

[0072] In one embodiment, the present invention includes bandpass filtering, digital quadrature downconversion, NCO frequency control, low-pass filtering, decimation, and automatic gain control (AGC). The implementation scheme is as follows: Figure 1 As shown, the details of each part are as follows.

[0073] 1. Bandpass Filtering: The RF signal sampled by the ADC and fed into the FPGA undergoes bandpass filtering through a two-stage bandpass filter. Both stages use FIR filters. The calculation formula is shown below:

[0074]

[0075] h bp,1 =f(w pl ,w ph ,w sl,1 ,w sh,1 ,f s ,a bp,1 )

[0076] h bp,2 =f(w pl ,w ph ,w sl,2 ,w sh,2 ,f s ,a bp,2 )

[0077] Among them, s rfIt is the ADC sampling input RF signal, s bp,1 This is the output result of bandpass filter 1, s bp,2 This is the output of bandpass filter 2, M. bp,1 It is the first order of bandpass filtering, h bp,1 It is a bandpass filter impulse response, M bp,2 It is the second-order bandpass filter, h bp,2 It is a bandpass filter 2-impulse response, w pl For the lower sideband of the passband, w ph For the upper sideband of the passband, w sl,1 For the lower stopband upper sideband of bandpass filter 1, w sh,1 For the upper stopband lower sideband of bandpass filter 1, f s For the sampling frequency, a bp,1 For bandpass filtering with 1 stopband attenuation, w sl,2 For the upper stopband sideband of bandpass filter 2, w sh,2 For the upper stopband lower sideband of bandpass filter 2, a bp,2 This is for bandpass filtering with 2 stopband attenuation.

[0078] After the radio frequency signal passes through two stages of bandpass filtering, the total out-of-band rejection is equal to the bandpass filter's 1 / 10 stopband attenuation α. bp,1 With bandpass filter 2 stopband attenuation a bp,2 The accumulation of.

[0079] a bp =a bp,1 *a bp,2 2. Digital Quadrature Down-Conversion: The local oscillator signal required for down-conversion is generated using the DDS IP core within the FPGA. The DDS IP core is configured for output signal frequency controllability, and the output signal frequency is controlled by an input frequency control word. The relationship between the output signal frequency and the frequency control word is as follows:

[0080]

[0081] Among them, f ci f is the DDS output frequency. clk Master clock frequency, Δθ i B is the frequency control word, and B is the frequency control word width. The DDS outputs the local oscillator signal lo required for digital quadrature downconversion. cos lo sin for:

[0082]

[0083] During quadrature downconversion, the RF signal s after the second-stage bandpass filter bp2 for:

[0084]

[0085] Where f0 is the baseband frequency, f ci Let k be the carrier frequency, k be the current time, and fs be the sampling frequency. For phase, in bp2 For interference signals, n bp2 This is a noise signal.

[0086] The calculation process for orthogonal downconversion is as follows:

[0087]

[0088] Among them, in i For I-channel interference signal, n i For I-channel noise signal, in q For Q-channel interference signal, n q This is the Q-channel noise signal.

[0089] The signal obtained after quadrature downconversion contains the required baseband I and Q signals, baseband image frequency signal, interference signal, and noise signal.

[0090] 3. NCO Frequency Control: The FPGA connects to an external channel control device via a communication interface. Before each normal operation, the communication interface receives channel control commands and then parses the channel number i of the currently operating channel according to the protocol. To simplify calculations, a lookup table is used to calculate the relationship between the channel number and the frequency control word. The principle of frequency control word calculation using the lookup table is as follows: Figure 2 As shown. The frequency control word corresponding to each channel is pre-stored in the ROM. The required frequency control word Δθ can be read by using the channel number as the read address. i Frequency control word Δθ i With DDS output frequency f ci The relationship is as follows:

[0091]

[0092] 4. Low-pass filtering: Like band-pass filtering, low-pass filtering uses an FIR filter. This invention employs a three-stage low-pass filtering method to progressively reduce the transition band bandwidth and increase stopband attenuation to achieve out-of-band suppression. There is a downsampling decimation process between every two low-pass filter stages. The calculation formula is shown below:

[0093]

[0094] h lp,j =f(w p,j ,w s,j ,f s,j ,a lp,j )

[0095] j = 1, 2, 3

[0096] Among them, sin,j,i It is the I-channel signal of the input low-pass filter j, s in,j,q It is the Q-channel signal of the input low-pass filter j, h lp,j It is the low-pass filter j-impulse response, M lp,j It is the order of the low-pass filter j, s lp,j,i It is the I-channel signal of the output low-pass filter j, s lp,j,q It is the Q-channel signal of the output low-pass filter j, w p,j It is the cutoff frequency of the low-pass filter, w s,j It is the low-pass filter stopband frequency, f s,j The input signal sampling rate of the low-pass filter j is a. lp,j It is the stopband attenuation of the low-pass filter.

[0097] The total out-of-band suppression of a low-pass filter is the product of the stopband attenuation of three low-pass filters.

[0098] a lp =a lp,1 *a lp,2 *a lp,3

[0099] 5. Decimation: Downsampling and decimation are implemented using a CIC filter. The structure of the CIC decimation filter is as follows: Figure 3 As shown, its system response is as follows:

[0100]

[0101] p = 1, 2

[0102] Among them, R p To extract multiples, M p For differential delay, N p For filter order

[0103] 6. Automatic Gain Control (AGC): The automatic gain control employs an improved logarithmic loop automatic gain control algorithm. The traditional algorithm, which calculates the logarithm to the base e, is replaced with a base-2 logarithm calculation, which is more suitable for FPGA implementation. The detailed working principle is as follows... Figure 4 As shown. The mathematical model of the improved logarithmic loop automatic gain control algorithm is as follows:

[0104] S out,i [n] = s lp,3,i [n]*2 g[n-1]

[0105] S out,q [n] = s lp,3,q [n]*2 g[n-1]

[0106]

[0107] e[n] = A - log2(z[n])

[0108] g[n] = g[n-1] + K*e[n]

[0109] Among them, S out,i It outputs I-channel signals, S out,q It outputs the Q-channel signal, s lp,3,i It is the input I-channel signal, s lp,3,q is the input Q-channel signal, g is the logarithmic gain, z is the output signal mean filter value, N is the mean filter window size, e is the error between the logarithm of the output signal average power and the set target output power logarithm A, and K is the gain adjustment step size.

[0110] In this embodiment, the radio frequency signal is directly subjected to digital bandpass filtering, variable local oscillator quadrature downconversion, 3-level downsampling low-pass filtering, and digital AGC processing, and finally outputs the baseband signal corresponding to the working channel.

[0111] In this embodiment, a two-stage bandpass filter is used to achieve high out-of-band rejection, and each stage of the bandpass filter uses FIR filtering.

[0112] The FPGA communication interface first receives channel control commands, then parses the commands to obtain the current operating channel number. Based on the parsed channel number, it reads the corresponding frequency control word from the frequency control word pre-stored in ROM. This frequency control word is then sent to the DDS(NCO) to output the local oscillator signal lo required for quadrature downconversion. cos lo sin .

[0113] In this embodiment, a three-stage low-pass filter is used to achieve high out-of-band rejection and a narrow transition band, with each stage of the low-pass filter employing FIR filtering.

[0114] Two-stage downsampling decimation is employed, with each stage of decimation achieved using a CIC decimation filter.

[0115] Input signal s lp,3,i s lp,3,q The output signal S is obtained by multiplying the logarithmic gain g[n-1] by its base-2 exponent. out,i S out,q S out,i The squared value is mean-filtered using N as a window to obtain the filtered result z. The logarithm of z to base 2 is calculated, and then the logarithm is subtracted from the target output power logarithm A to obtain the logarithmic error e. e is multiplied by the gain adjustment step size K and then accumulated with the logarithmic gain g[n-1] of the previous time step to obtain the logarithmic gain g[n] of the current time step. The real and imaginary parts of the input signal use the same gain to control the output signal power.

[0116] The automatic gain control (AGC) outputs I and Q signals, which are the interference-free, constant power baseband signals corresponding to the current working channel.

[0117] The foregoing description and illustrations have shown and described the basic principles, main features, and advantages of this invention. Those skilled in the art should understand that this invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to this invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. An FPGA-based aviation band RF direct acquisition receiver, characterized in that, Integrated into a single FPGA chip, the receiver includes a bandpass filter module, a digital quadrature downconverter module, an NCO frequency control module, a low-pass filter module, a decimation module, and an AGC automatic gain control module. The FPGA-based aviation band RF direct sampling receiver first sends the ADC-sampled RF signal sequentially to the bandpass filter module (bandpass filter 1 and bandpass filter 2) for filtering. Then, the filtered signal is sent to the digital quadrature downconverter module for processing to obtain I and Q signals. The NCO frequency control module provides the local oscillator signal to the digital quadrature downconverter module. The I and Q signals are sequentially sent to low-pass filter 1, decimation 1, low-pass filter 2, decimation 2, and low-pass filter 3 to complete two stages of downsampling and three stages of low-pass filtering, respectively. Finally, both signals are simultaneously sent to the AGC automatic gain control module to adjust the signal amplitude, outputting the final baseband I and baseband Q signals.

2. The FPGA-based aviation band RF direct acquisition receiver according to claim 1, characterized in that, The bandpass filter module is sequentially connected to bandpass filter 1 and bandpass filter 2, both of which use FIR filters. The calculation formula is as follows: Where y is the output of the filter convolution, and h bp This is the impulse response of a bandpass filter, where x is the input signal and M is the filter order; h bp With the lower sideband w of the passband pl upper passband frequency w ph Lower stopband upper sideband w sl Upper stopband and lower sideband w sh Sampling frequency f s and stopband attenuation a bp The relevant expression is: h bp =f(w pl ,w ph ,w sl ,w sh ,f s ,a bp )。 3. The FPGA-based aviation band RF direct acquisition receiver according to claim 2, characterized in that, After the bandpass filtering module performs two stages of bandpass filtering on the radio frequency signal, the total out-of-band suppression is equal to the stopband attenuation α of bandpass filter 1. bp,1 With the stopband attenuation a of bandpass filter 2 bp,2 The accumulation of.

4. The FPGA-based aviation band RF direct acquisition receiver according to claim 1, characterized in that, The signal processing of the digital quadrature downconverter module and the NCO frequency control module specifically includes: receiving channel control commands through the channel interface; parsing the channel number of the current working channel according to the channel control commands and the corresponding protocol; reading the corresponding frequency control word from the frequency control word pre-stored in the ROM based on the parsed channel number; calculating the relationship between the channel number and the frequency control word using a lookup table; sending the frequency control word to the NCO frequency control module; and outputting the local oscillator signal lo required for quadrature downconversion. cos and lo sin .

5. The FPGA-based aviation band RF direct acquisition receiver according to claim 4, characterized in that, The digital quadrature downconversion module and NCO frequency control module further process signals by: the radio frequency signal processed by bandpass filter 1 and bandpass filter 2 is respectively compared with the local oscillator signal lo. cos and lo sin Multiplying these components yields a mixer s containing the baseband signal, baseband image frequency signal, interference signal, and noise signal. i and s q Signal.

6. The FPGA-based aviation band RF direct acquisition receiver according to claim 5, characterized in that, The local oscillator signal required for downconversion by the digital quadrature downconversion module is generated using the DDS IP core within the FPGA. The DDS IP core is configured for a controllable output signal frequency mode, controlling the output signal frequency via an input frequency control word. The relationship between the output signal frequency and the frequency control word is as follows: Among them, f c f is the DDS output frequency. clk The main clock frequency is Δθ, the frequency control word is B, and the frequency control word width is B. During quadrature downconversion, the RF signal s after the second-stage bandpass filter bp2 for: Where f0 is the baseband frequency, f c Let k be the carrier frequency, k be the current time, and fs be the sampling frequency. For phase, in bp2 For interference signals, n bp2 This is a noise signal; The formula for calculating quadrature downconversion is: Among them, in i For I-channel interference signal, n i For I-channel noise signal, n q For Q-channel noise signal, in q This is a Q-channel interference signal.

7. The FPGA-based aviation band RF direct acquisition receiver according to claim 6, characterized in that, The relationship between the frequency control word and the DDS output frequency is expressed as follows:

8. The FPGA-based aviation band RF direct acquisition receiver according to claim 1, characterized in that, Each low-pass filter in the low-pass filter module uses an FIR filter. Out-of-band suppression is achieved by progressively reducing the transition band bandwidth and increasing the stopband attenuation through three stages of low-pass filtering. There is a downsampling decimation process between every two low-pass filter stages. The total out-of-band suppression of the low-pass filter is the product of the stopband attenuation of the three low-pass filters. The impulse response h... lp With cutoff frequency w p Stopband frequency w s Sampling frequency f s and stopband attenuation a lp The relevant expression is: h lp =f(w p ,w s ,f s ,a lp )。 9. The FPGA-based aviation band RF direct acquisition receiver according to claim 1, characterized in that, The decimation module uses a CIC filter to achieve downsampling decimation, and the CIC filter system response is as follows: Where R is the decimation factor, M is the differential delay, and N is the filter stage.

10. The FPGA-based aviation band RF direct acquisition receiver according to claim 1, characterized in that, The AGC automatic gain control module employs a logarithmic loop automatic gain control algorithm with base 2 as the logarithm. The calculation formula includes: S out [n]=S in [n]*2 g[n-1] ; e[n] = A - log2(z[n]); g[n] = g[n-1] + K*e[n]; Among them, S out It is the output signal, S in is the input signal, g is the logarithmic gain, z is the mean filter value of the output signal, N is the size of the mean filter window, e is the error between the logarithm of the average power of the output signal and the set target logarithm of the output power A, and K is the gain adjustment step size.

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