Cross-hardware platform unified instruction execution architecture and implementation method

Abstract

The invention discloses a cross-hardware platform unified instruction execution architecture, and belongs to the technical field of industrial control and embedded hardware security. The system comprises a unified instruction definition layer, a hardware direct execution adaptation layer and a dual-mode scheduling layer, and the problems that different hardware instructions are incompatible, execution is not safe and uncontrollable, and translation execution is needed are solved. The unified instruction definition layer formulates a full-category hardware general instruction set; the hardware direct execution adaptation layer realizes instruction signature verification, decryption, replay prevention and tampering prevention by solidifying a hardware root key; the dual-mode scheduling layer supports dual-mode operation of a public general instruction and a manufacturer private extension instruction, and all instructions can be directly executed without translation after passing safety verification. The method is suitable for full-class hardware such as machine tools, industrial control equipment, the Internet of Things and robots, and cross-platform unified, safe, authorized and efficient execution is achieved.

Description

[0001] manual Technical Field This invention relates to the field of hardware control and cross-platform execution technology, and in particular to a unified instruction execution architecture and implementation method that spans all types of hardware platforms. It is applicable to the unified instruction control and underlying execution of all types of hardware, such as machine tools, industrial control equipment, consumer electronics, IoT terminals, and robots, and belongs to the underlying infrastructure technology of the hardware industry. Background Technology The current global hardware industry faces core pain points: the underlying instruction execution systems of various categories and brands of hardware are independent and have different standards. Cross-hardware instruction compatibility requires multi-layer middleware translation and dedicated adaptation development, resulting in high cross-hardware adaptation costs, high resource consumption, and low development efficiency. This seriously restricts the large-scale advancement of industrial internet, IoT integration, and intelligent manufacturing, and has also become a core obstacle to the localization and standardization of the hardware industry. In existing technologies, domestic and international research on hardware interconnection and compatibility focuses on upper-layer data interoperability, local domain adaptation, or compilation middleware optimization, without reaching the core level of hardware instruction execution. This fails to fundamentally eliminate cross-hardware instruction barriers. Specific technical limitations include: 1. Mainstream international technologies only address single-stage issues, lacking a unified end-to-end design: MTConnect in the US is merely a data communication standard for machine tools, only achieving unified data acquisition and transmission formats, without addressing the definition, issuance, and execution of hardware instructions; OPC UA internationally is a data semantic interoperability standard for the Industrial Internet of Things, only solving the problem of inconsistent data understanding between different devices, relying on the original instruction sets of each hardware, and lacking a unified design of underlying instructions; LLVM / QIR in the US is a cross-platform compilation middleware, achieving compatibility through multi-layered translation of "high-level code → intermediate code → hardware machine code," essentially code adaptation, requiring the development of dedicated compilation backends for each hardware, resulting in high adaptation costs; Intel's oneAPI and NVIDIA's CUDA-X are brand-closed heterogeneous computing programming frameworks, only applicable to their own brand's chips / computing power clusters, lacking universality across brands and all hardware categories; ROS... 2. Existing technologies are merely upper-level software frameworks in the robotics field, only addressing the unification of robot module software interfaces, without involving the execution of underlying hardware instructions; MQTT / CoAP are merely lightweight data transmission protocols for IoT terminals, only enabling data transmission and reception, without the ability to execute device control instructions. 2. Domestic technologies lack a systematic architecture and remain at the stage of partial adaptation: Domestically, there are only scattered hardware adaptation solutions in sub-sectors such as machine tools and IoT, and none of them have broken away from the traditional logic of "middle-layer translation," lacking a unified design for the entire chain of underlying instruction definition and execution. This fails to solve the instruction compatibility problem across all types of hardware, and there is still a significant gap compared to foreign technologies. In summary, existing technologies have not achieved unified underlying instruction execution across all types of hardware. They can only reduce compatibility difficulty through upper-level adaptation and data interoperability, but cannot fundamentally eliminate cross-hardware adaptation costs. This does not conform to the inevitable development of the hardware industry towards "cost reduction, efficiency improvement, and full-category interconnection," nor can it meet the national industrial strategic needs of "hardware localization, standard autonomy, and the implementation of new quality productivity." Summary of the Invention (I) Purpose of the Invention This invention addresses the core deficiencies of existing technologies by providing a unified instruction execution architecture and implementation method across hardware platforms. The core purpose is to break down the underlying instruction barriers of all types of hardware, including machine tools, industrial control equipment, consumer electronics, IoT terminals, and robots, and to create a unified instruction language + hardware direct execution engine underlying architecture. This enables "one set of instructions to be sent to all hardware, and the hardware to directly recognize and execute them," fundamentally eliminating cross-hardware adaptation costs. At the same time, it takes into account both general execution and the personalized expansion needs of manufacturers. Furthermore, it achieves secure and controllable instruction execution through hardware-level key authentication and encryption verification, ensuring that instructions are not executed without authorization. This provides underlying technical support for the localization, standardization, and security control of the national hardware industry. (II) Core Technical Solution The cross-hardware platform unified instruction execution architecture of this invention includes three core layers: a unified instruction definition layer, a hardware direct execution adaptation layer, and a dual-mode scheduling layer. The three layers work together from top to bottom to achieve unified, secure, authorized, and direct execution of instructions across all types of hardware without any intermediate translation layer. The specific architecture design is as follows: 1. Unified Instruction Definition Layer: This is the core upper layer of the architecture. Based on the core execution logic of all types of hardware such as machine tools, industrial control equipment, consumer electronics, IoT terminals, and robots, it extracts common instruction rules and formulates a general instruction set covering basic needs such as motion control, data acquisition, state adjustment, and function triggering. This achieves the standardization and generalization of the instruction language, providing a unified public instruction standard for all types of hardware without the need to design a dedicated instruction system for different hardware. 2. Hardware Direct Execution Adaptation Layer: This is the core middleware layer of the architecture. Lightweight, secure direct execution plugins are developed for the underlying control systems of various hardware categories. Each plugin has a unique hardware root key embedded by the hardware manufacturer during the production phase. This key is permanently stored in the hardware's underlying secure area, making it unreadable, unexportable, and unalterable. The plugin incorporates an encryption and verification engine. Upon receiving an instruction, it first performs key verification, instruction signature verification, integrity verification, and anti-replay verification. Only after all verifications pass can the instruction be parsed and executed. If verification fails, the instruction is discarded without response, execution, or information leakage. The plugin is a lightweight program that does not require modification of the original core logic of the hardware's underlying control system; it only implements an integrated secure channel for authentication, decryption, verification, and execution. 3. Dual-mode scheduling layer: This is the core scheduling layer of the architecture, with dual execution scheduling logic in both a general mode and a manufacturer-customized extended mode. In general mode, all types of hardware directly execute the publicly available general instruction set of the unified instruction definition layer, meeting cross-hardware basic control requirements. In customized extended mode, hardware manufacturers can add their own hardware-specific extended instructions on top of the general instruction set. The dedicated instructions and general instructions form a unified system, which still requires hardware key verification before execution. Before issuing instructions, the scheduling layer uses the manufacturer's corresponding key for encryption and signing to ensure that the instruction transmission is secure, tamper-proof, non-hijackable, and non-replayable.The cross-hardware platform unified instruction execution method based on the above architecture includes the following steps: 1. Based on the unified instruction definition layer, formulate a public and general instruction set covering the basic execution needs of all types of hardware, and complete the standardization and generalization design of instructions. 2. For the underlying control system of the target hardware, develop a lightweight and secure direct execution plug-in, which is embedded into the underlying hardware after the manufacturer has fixed a unique root key. 3. Select a general mode or a manufacturer-customized extension mode according to the control requirements. In the customized mode, the manufacturer adds exclusive extension instructions to form a unified instruction system. 4. The scheduling layer uses the corresponding key of the hardware to encrypt and sign the instructions, and sends the encrypted secure instruction package to the target hardware. 5. After receiving the instruction package, the hardware plug-in performs key verification, instruction decryption, integrity verification, timestamp validity verification, and anti-replay verification in sequence. If all verifications pass, the instruction is parsed and executed; if any verification fails, the instruction is discarded and the hardware does not perform any action. 6. The hardware synchronously feeds back the instruction execution result to the scheduling layer, completing the entire process of secure, authorized, and controllable cross-hardware instruction unified execution. (III) Beneficial Effects This invention represents a pioneering design of a unified instruction execution architecture across hardware categories at the underlying level. Compared with existing technologies, it offers the following core beneficial effects: 1. Underlying Innovation, Eliminating Cross-Hardware Adaptation Barriers at the Root: Unlike existing technologies that rely on "upper-layer adaptation / data interoperability / middleware translation," this invention reaches the core layer of hardware instruction execution, creating a unified instruction native language and a direct hardware execution engine. Without intermediate translation steps, it fundamentally solves the problem of cross-hardware instruction incompatibility, significantly reducing adaptation costs and improving development efficiency. 2. Balancing Public Standards and Private Extensions, Highly Practical: The unified instruction is publicly available and universal, facilitating industry standardization and promotion; manufacturer-customized extension instructions can be kept private and non-public, meeting both industry-wide unified needs and preserving manufacturers' independent controllability, aligning with actual industrial application scenarios. 3. Hardware-Level Security and Controllability, Never Executing Without Authorization: By solidifying the root key, encrypting signatures, verifying integrity, preventing replay attacks, and preventing hijacking, a full-link security system is constructed. Without a legitimate key, instructions are completely not executed, eliminating the risk of illegal control, tampering, and hijacking from the underlying level. Security and controllability reach the hardware level. 4. Comprehensive Coverage and Highly Universal: Covering all categories of hardware, including machine tools, industrial control systems, consumer electronics, IoT, and robots, breaking through the limitations of niche markets and brand closures, and applicable to all scenarios of industrial internet, intelligent manufacturing, and IoT integration. 5. Lightweight Adaptability with No Large-Scale Hardware Modification Costs: Security plugins are lightweight and embedded without altering the original underlying control core. Existing hardware can be upgraded to a unified instruction set at low cost, facilitating large-scale deployment. 6. Independent and Controllable, Aligned with National Strategy: Achieving independent definition, security, controllability, and standardization of the underlying hardware instruction set, breaking the monopoly of foreign technology and standards, and supporting hardware localization, the implementation of new productivity, and industrial security upgrades. Detailed Implementation The following describes specific implementation methods of the present invention. Any simple replacements, modifications, or extensions based on the core architecture and secure execution logic of the present invention are within the scope of protection of the present invention. Example 1: Secure Execution of Cross-Hardware General Instructions between Machine Tools and IoT Terminals 1. A unified instruction definition layer defines four publicly available general instructions: start, stop, data acquisition, and status feedback. 2. Security plugins are embedded in both the machine tool PLC and the IoT terminal, with manufacturers fixing their respective root keys. 3. A general mode is adopted, without adding customized extended instructions. 4. The scheduling layer uses the corresponding key for encryption and signature, and issues a "start + data acquisition" instruction package. 5. If the hardware plugin verifies the signature, decrypts, and checks successfully, it executes the instruction and collects data; if the verification fails, execution is rejected. 6. The hardware provides feedback on the execution status and collected data, completing the secure execution of the general instructions. Example 2: Secure Execution of Manufacturer-Customized Extended Instructions between Robots and Smart Displays 1. A unified instruction definition layer defines four publicly available general instructions: start, stop, status query, and function activation. 2. Security plugins are embedded in both the robot and the smart display, with manufacturers fixing their respective root keys. 3. A customized extension mode is adopted, adding dedicated extended commands for rotation, grasping, and resetting to the robot, and dedicated extended commands for brightness adjustment, volume adjustment, and screen switching to the display screen. 4. The scheduling layer uses corresponding keys for encryption and signing, and issues secure command packages containing the extended commands. 5. All multi-level security checks of the hardware plug-ins pass, executing the general + extended combined commands; commands are not executed at all without a valid key. 6. The hardware provides feedback on the execution results, completing the secure, controllable, and unified execution of the manufacturer's private customized extended commands. The above embodiments demonstrate that this invention can achieve unified execution of publicly available general commands across hardware, and also supports manufacturer-customized extensions, with strict control throughout by hardware keys and security checks; execution is not performed without authorization, truly achieving open standards, private extensions, underlying security, and global controllability.

Claims

1. A unified instruction execution architecture across hardware platforms, characterized in that, It includes a unified instruction definition layer, a hardware direct execution adaptation layer, and a dual-mode scheduling layer. The unified instruction definition layer is used to formulate a public and universal instruction set for all types of hardware, realizing instruction standardization. The hardware direct execution adaptation layer is used to deploy a security plugin containing a hardware root key to realize multi-level security verification of instruction signature, decryption, integrity verification, replay protection, and tamper protection. Only instructions that pass the verification can be executed. The dual-mode scheduling layer provides a general mode and a manufacturer-customized extension mode, supporting the execution of public and universal instructions and the execution of manufacturer-private extension instructions. All instructions must undergo security verification before running, realizing unified, secure, authorized, and translation-free direct execution across hardware.

2. The architecture according to claim 1, characterized in that, The general instruction set is an open standard that covers basic hardware logic for motion control, data acquisition, state adjustment, and function triggering, and is applicable to all categories of hardware, including machine tools, industrial control equipment, consumer electronics, IoT terminals, and robots.

3. The architecture according to claim 1, characterized in that, The security plugin of the hardware direct execution adaptation layer is fixed with a unique root key by the hardware manufacturer. The key is unreadable, unexportable, and untamperable. If there is no valid key, the instruction is directly discarded, and the hardware does not execute or respond.

4. The architecture according to claim 1, characterized in that, The dual-mode scheduling layer encrypts and digitally signs instructions before issuing them. The instruction packet contains a timestamp and a random number to prevent replay, hijacking, and tampering.

5. The architecture according to claim 1, characterized in that, The manufacturer-customized extension mode allows hardware manufacturers to add exclusive private extension instructions. These extension instructions share the same secure execution system as general instructions and still require root key verification before they can be executed.

6. A method for secure execution of unified instructions across hardware platforms, implemented based on the architecture described in any one of claims 1-5, characterized in that, Including the following steps: (1) Develop a public, universal instruction set for all types of hardware; (2) Hardware manufacturers embed a unique root key into the security plugin and embed it into the underlying hardware. (3) Select the general mode or the manufacturer-customized extension mode. In the customized mode, add manufacturer-specific extension commands; (4) The scheduling layer encrypts and signs the instructions before issuing them; (5) The hardware plugin performs multi-level verification of signature, decryption, integrity, timestamp, and anti-replay. If it passes, it is executed; otherwise, it is discarded. (6) Hardware feedback of execution results to complete a safe and controllable unified instruction execution process.

7. The method according to claim 6, characterized in that, General instructions can be made public and standardized for widespread adoption, while vendor-customized extended instructions can be kept private and not made public, but all are subject to the same key security system.