Printed circuit board, memory module and storage system
By setting pads and resistors in the front-end design of the printed circuit board, the signal transmission path length difference is ensured to be consistent, thus solving the phase difference problem caused by signal bifurcation and improving signal quality and system stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- RUILI INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2024-10-29
- Publication Date
- 2026-05-01
AI Technical Summary
In a storage system, when dual in-line memory modules (DIMMs) form a T-shaped topology, the unequal lengths of the two branch lines branching into the signal result in a phase difference, causing signal distortion such as ringing or overshoot, which affects signal quality.
In the front-end design of printed circuit boards, by setting the first, second, and third pads and resistors, the length difference of the signal transmission path is ensured to be a set value, thereby achieving phase matching of the signal in the two paths and reducing reflection and ringing phenomena.
By using equal-length matched signal paths, the reflected signals are theoretically in phase and cancel each other out, reducing the impact of reflection and improving signal quality and system stability.
Smart Images
Figure CN121968435A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a printed circuit board, a memory module, and a storage system. Background Technology
[0002] In the field of semiconductor technology, especially in memory system design, signal quality is a critical factor. When two dual in-line memory (DIMM) modules are located in the same memory channel, a T-topology is formed. In this structure, the signal branches from the trunk into two branch lines. When the signal reaches the T-fork point, part of the signal propagates along one branch line, and the other part propagates along the other branch line. If the lengths of the two branch lines are not equal, the reflected signals will have different phases when they return to the trunk line. This phase difference will cause the reflected signals to not completely cancel each other out, and may instead produce additional signal distortions, such as ringing or overshoot, thereby degrading signal quality. The greater the difference in line length, the more pronounced this phase difference, and the more severe the signal quality degradation.
[0003] To address such issues, existing technologies often involve adding terminating resistors and buffers in the back-end design where necessary to reduce reflections and improve signal quality. However, back-end design cannot completely solve these problems. Therefore, there is an urgent need for a technical solution to address these issues in the front-end design.
[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0005] This disclosure provides a printed circuit board, a memory module, and a storage system that can improve the signal transmission quality of the printed circuit board.
[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.
[0007] According to one aspect of this disclosure, a printed circuit board is provided.
[0008] include:
[0009] The first signal layer is located on the top layer of the printed circuit board;
[0010] The first signal layer is equipped with:
[0011] First gold finger pin;
[0012] First signal line pin;
[0013] The first pad is used to connect the first resistor. One end of the first pad is electrically connected to the first gold finger pin, and the other end of the first pad is connected to the first signal line pin.
[0014] The second pad is used to connect the second resistor, and one end of the second pad is electrically connected to the first gold finger pin;
[0015] The third pad is used to connect the third resistor. One end of the third pad is electrically connected to the first signal line pin, and the other end of the third pad is electrically connected to the other end of the second pad.
[0016] The first signal transmission path is that the first gold finger pin reaches the first signal line pin through the first resistor, and the second signal transmission path is that the first gold finger pin reaches the first signal line pin through the second resistor and the third resistor respectively. The length difference between the second signal transmission path and the first signal transmission path is a first set value.
[0017] In one embodiment, both the first gold finger pin and the first signal line pin are data pins.
[0018] In one embodiment, the trace between the first gold finger pin and the first pad is equidistant from the trace between the first gold finger pin and the second pad.
[0019] In one embodiment, the trace distance between the first signal line pin and the first pad is equal to the trace distance between the first signal line pin and the third pad.
[0020] In one embodiment, the printed circuit board further includes a second signal layer located in the middle layer of the printed circuit board, and the other end of the third pad is electrically connected to the other end of the second pad through a first blind via, a first trace, and a second blind via.
[0021] In one embodiment, a first blind via and a second blind via connect a first signal layer and a second signal layer, and a first trace is located within the second signal layer.
[0022] In one embodiment, the first trace is a waveform trace.
[0023] In one embodiment, the projection of the first blind via perpendicular to the first signal layer falls within the projection of the third pad perpendicular to the first signal layer, and the projection of the second blind via perpendicular to the first signal layer falls within the projection of the second pad perpendicular to the first signal layer.
[0024] In one embodiment, the first pad, the second pad, and the third pad each have two resistive contacts. One resistive contact of the first pad is shared with one resistive contact of the second pad, and the other resistive contact of the first pad is shared with one resistive contact of the third pad.
[0025] In one embodiment, the first resistor and the second resistor have the same resistance value, and the resistance values of the first resistor and the second resistor are greater than 0 ohms, while the resistance value of the third resistor is 0 ohms.
[0026] In one embodiment, the first signal layer is further provided with: a second gold finger pin; a second signal line pin; the second signal line pin and the second gold finger pin are electrically connected by wiring.
[0027] According to another aspect of this disclosure, a memory module is provided, comprising:
[0028] Printed circuit boards;
[0029] Memory chip, the memory chip is electrically connected to the printed circuit board;
[0030] Printed circuit boards include:
[0031] The first signal layer is located on the top layer of the printed circuit board;
[0032] The first signal layer is equipped with:
[0033] First gold finger pin;
[0034] First signal line pin;
[0035] The first pad is used to connect the first resistor. One end of the first pad is electrically connected to the first gold finger pin, and the other end of the first pad is connected to the first signal line pin.
[0036] The second pad is used to connect the second resistor, and one end of the second pad is electrically connected to the first gold finger pin;
[0037] The third pad is used to connect the third resistor. One end of the third pad is electrically connected to the first signal line pin, and the other end of the third pad is electrically connected to the other end of the second pad.
[0038] The first signal transmission path is that the first gold finger pin reaches the first signal line pin through the first resistor, and the second signal transmission path is that the first gold finger pin reaches the first signal line pin through the second resistor and the third resistor respectively. The length difference between the second signal transmission path and the first signal transmission path is a first set value.
[0039] The memory module includes a first memory module and a second memory module. The first memory module is equipped with a first resistor, and the second memory module is equipped with a second resistor and a third resistor.
[0040] In one embodiment, the first resistor and the second resistor have the same resistance value, and the resistance values of the first resistor and the second resistor are greater than 0 ohms, while the resistance value of the third resistor is 0 ohms.
[0041] According to another aspect of this disclosure, a storage system is provided, comprising:
[0042] Motherboard;
[0043] The memory controller is located on the motherboard.
[0044] The first memory module and the second memory module mentioned above;
[0045] The length difference between the second signal transmission path and the first signal transmission path is the distance between the first memory module and the second memory module.
[0046] In one embodiment, the first memory module and the second memory module are located in the same memory channel.
[0047] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0048] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0049] Figure 1 A schematic diagram of a storage system architecture in the prior art is shown; Figure 2 A top view of a printed circuit board provided in an embodiment of this disclosure; Figure 3 The printed circuit board provided in the embodiments of this disclosure is along Figure 2 A cross-sectional view at the location indicated by the dashed line; Figure 4 A printed circuit board provided for another embodiment of this disclosure along Figure 2 A cross-sectional view at the location indicated by the dashed line; Figure 5 A top view of a printed circuit board provided in another embodiment of this disclosure; Figure 6 A top view of a printed circuit board provided in yet another embodiment of this disclosure; Figure 7 This illustration shows a structural diagram of a memory module of a memory module provided in an embodiment of the present disclosure; Figure 8 This illustration shows a schematic diagram of the structure of another memory module of a memory module provided in an embodiment of the present disclosure; Figure 9 A schematic diagram of the structure of a storage system provided in an embodiment of this disclosure is shown; Detailed Implementation
[0050] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0051] Signal quality is a critical factor in storage system design. When two dual in-line memory modules (DIMMs) are located in the same memory channel, a T-topology is formed, such as... Figure 1 As shown in the schematic diagram of a prior art storage system structure, dual in-line memory module 0 (DIMM0) and dual in-line memory module 1 (DIMM1) are located in the same memory channel and controlled by a central processing unit (CPU). DIMM0 and DIMM1 can be located in the same memory rank, in which case the storage system has a 2DPC1rank (Dimms Per Channel 1rank) structure; or they can be located in different memory rank, in which case the storage system has a 2DPC2rank (Dimms Per Channel 2rank) structure.
[0052] In the above structure, the signal branches off from the main trunk into two branch lines. When the signal reaches the T-bifurcation point, part of the signal propagates along one branch line, while the other part propagates along the other. If the lengths of the two branch lines are unequal, the reflected signals will have different phases when they return to the main trunk. This phase difference prevents the reflected signals from completely canceling each other out, potentially causing additional signal distortions such as ringing or overshoot, thus degrading signal quality. The greater the difference in line length, the more pronounced this phase difference becomes, and the more severe the signal quality degradation.
[0053] To address such issues, existing technologies often incorporate backend designs, such as adding terminating resistors and buffers at necessary locations, to reduce reflections and improve signal quality. However, backend designs cannot completely solve these problems.
[0054] In view of this, the present disclosure provides a printed circuit board, a memory module, and a storage system. By improving the structure of the printed circuit board in the front-end design, the difference in signal transmission paths between the dual in-line memory module 0 (DIMM0) and the dual in-line memory module 1 (DIMM1) is equal to the spacing between the dual in-line memory module 0 (DIMM0) and the dual in-line memory module 1 (DIMM1) on the motherboard. In this way, the lengths of the two branch lines are equal. Theoretically, when the signal is reflected back at the end, since the phase of the reflected signal is the same, they will cancel each other out on the trunk line, thereby reducing the impact of reflection and improving signal quality.
[0055] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0056] Figure 2 A top view of a printed circuit board provided in an embodiment of this disclosure; Figure 3 The printed circuit board provided in the embodiments of this disclosure is along Figure 2 A cross-sectional view at the location indicated by the dashed line;
[0057] Reference Figure 2 and Figure 3 As shown, in one embodiment, a printed circuit board 100,
[0058] include:
[0059] First signal layer 101, the first signal layer 101 is located on the top layer of printed circuit board 100;
[0060] The first signal layer 101 is equipped with:
[0061] First gold finger pin 110;
[0062] First signal line pin 120;
[0063] The first pad 130 is used to connect the first resistor. One end of the first pad 130 is electrically connected to the pin of the first gold finger 110, and the other end of the first pad 130 is connected to the pin of the first signal line 120.
[0064] The second pad 140 is used to connect the second resistor, and one end of the second pad 140 is electrically connected to the pin of the first gold finger 110.
[0065] The third pad 150 is used to connect the third resistor. One end of the third pad 150 is electrically connected to the first signal line pin 120, and the other end of the third pad 150 is electrically connected to the other end of the second pad 140.
[0066] The first signal transmission path is that the first gold finger pin 110 passes through the first resistor to reach the first signal line pin 120. The second signal transmission path is that the first gold finger pin 110 passes through the second resistor and the third resistor respectively to reach the first signal line pin 120. The length difference between the second signal transmission path and the first signal transmission path is a first set value.
[0067] Reference Figures 2-3 The printed circuit board 100 described above will be described in detail.
[0068] The printed circuit board 100 comprises a multilayer structure, typically including a first signal layer 101, an insulating layer 102, a ground layer 103, a power layer 104, a second signal layer 105, a third signal layer 106, and a bottom signal layer 107. The signal layers are the primary layers carrying signal transmission within the circuit. Copper foil on the signal layers is etched to form circuit patterns for signal transmission. The insulating layers are made of dielectric materials such as epoxy resin or fiberglass. These layers isolate the signal layers, preventing short circuits between them and providing mechanical support. The ground layer plays a crucial electrical and mechanical role throughout the printed circuit board. It provides a reference point for grounding all signals in the circuit. The ground layer is typically designed as a single plane to provide a low-impedance ground path, helping to shield against electromagnetic interference (EMI) and aiding in heat dissipation. The power layer provides the required power voltage for the circuit. Similar to the ground layer, the power layer is also typically designed as a single plane to ensure power stability and reduce voltage drop.
[0069] The gold finger pins are a crucial part of the physical and electrical connection between the Dual In-line Memory Module (DIMM) and the memory slots on the motherboard. The first gold finger pin, 110, is one such part. The gold finger pins are actually a row of gold-plated contacts arranged in a specific order, carrying different signal and power lines. For example, some contacts transmit data signals (DQ), some address signals (CA), some clock signals (CK), and others control signals (such as CAS, RAS, WE, etc.), as well as power and ground contacts. The gold finger pins are located on the bottom of the DIMM. When the DIMM is inserted into the memory slot on the motherboard, these contacts make close contact with the metal contacts inside the slot, thereby enabling the transmission of data signals, clock signals, control signals, and power.
[0070] Signal line pins refer to specific pins in a dual in-line memory module (DIMM) used for signal transmission. Signal line pins include data signals (DQ), address signals (CA), clock signals (CK), control signals (such as CAS, RAS, WE, etc.), and other signal pins used for data communication. These pins connect to the memory slots on the motherboard via gold fingers on the bottom of the DIMM, enabling the transmission of data, address, and control signals, as well as communication with the system memory controller. The first signal line pin 120 is a part of this.
[0071] By setting the first, second, and third pads, the signal can be transmitted from the first gold finger pin 110 to the first signal line pin 120 via two paths. The first signal transmission path: the signal travels directly from the first gold finger pin 110 through the first resistor to the first signal line pin 120. The second signal transmission path: the signal travels from the first gold finger pin 110 through the second and third resistors respectively, finally reaching the first signal line pin 120. The length difference between the second and first signal transmission paths is a first set value. This first set value is adjusted by the trace length between the second pad 140 and the third pad 150. The purpose of this first set value is to control the propagation time difference of the signal in the two paths, thereby reducing signal reflection and ringing, and improving signal integrity and stability. By precisely controlling the resistor value and path length, phase matching of the signal in the two paths can be achieved, reducing the phase difference when the signal reaches the first signal line pin 120, thereby optimizing signal quality. The first set value here can be as follows: Figure 1 As shown, the spacing between the dual in-line memory module 0 (DIMM0) and the dual in-line memory module 1 (DIMM1) on the motherboard is arranged.
[0072] In one embodiment, both the first gold finger pin 110 and the first signal line pin 120 are data pins. That is, the first gold finger pin 110 and the first signal line pin 120 are used to transmit data signals. In the communication between the dual in-line memory module (DIMM) and the motherboard, the data pins carry the actual data bits and are a key component of data read and write operations. The first gold finger pin 110 serves as the input terminal for the data signal, receiving data signals from the motherboard, while the first signal line pin 120 serves as the output terminal or further transmission terminal for the data signal, transmitting the data signal to other components or circuits on the printed circuit board 100. This reduces reflection and ringing of the data signal during transmission, thereby improving the integrity of the data signal and the stability of the system. Especially in high-speed data transmission systems, high-speed signals are more susceptible to signal reflection and ringing; this embodiment significantly improves the transmission quality of the data signal.
[0073] In one embodiment, the trace distance between the first gold finger pin 110 and the first pad 130 is equal to the trace distance between the first gold finger pin 110 and the second pad 140. When a signal is transmitted from the first gold finger pin 110 to the first pad 130 or the second pad 140, if the lengths of these two traces are not equal, the signal may experience a phase difference upon reaching its destination due to the difference in propagation time, leading to signal reflection and ringing. By making the trace length from the first gold finger pin 110 to the first pad 130 equal to the trace length from the first gold finger pin 110 to the second pad 140, the propagation time of the signal in both paths can be ensured to be the same, thereby reducing the phase difference, avoiding signal reflection and ringing, and improving signal synchronization and integrity. Simultaneously, the length difference between the second signal transmission path and the first signal transmission path can be calculated more easily.
[0074] In one embodiment, the trace distance between the first signal line pin 120 and the first pad 130 is equal to the trace distance between the first signal line pin 120 and the third pad 150. When a signal is transmitted from the first signal line pin 120 to the first pad 130 or the third pad 150, if the lengths of these two traces are not equal, the signal may experience a phase difference upon reaching its destination due to the difference in propagation time, leading to signal reflection and ringing. By making the trace length from the first signal line pin 120 to the first pad 130 equal to the trace length from the first signal line pin 120 to the third pad 150, it can be ensured that the signal propagation time is the same in both paths, thereby reducing the phase difference and avoiding signal reflection and ringing. Simultaneously, it becomes easier to calculate the length difference between the second signal transmission path and the first signal transmission path.
[0075] In one embodiment, the printed circuit board 100 further includes a second signal layer 105, located in the middle layer of the printed circuit board. The other end of the third pad 150 is electrically connected to the other end of the second pad 140 via a first blind via 181, a first trace 190, and a second blind via 182. Signals can travel from the third pad 150 to the second signal layer 105 via the first blind via 181, then laterally via the first trace 190, and finally to the second pad 140 via the second blind via 182, thus achieving vertical and horizontal signal connectivity within the multilayer printed circuit board 100. This facilitates adjustment of the length of the second signal transmission path.
[0076] In one embodiment, the first blind via 181 and the second blind via 182 connect the first signal layer 101 and the second signal layer 105, and the first trace 190 is located within the second signal layer 105. By using the combination of blind vias and traces, the signal path can be flexibly adjusted, avoiding other components, preventing interference between signal lines and components, optimizing the layout of the printed circuit board 100, and improving the efficiency and performance of the overall design. Compared to placing the first trace 190 within the first signal layer 101, placing the first trace 190 within the second signal layer 105 can avoid components on the first signal layer 101, simplifying the routing complexity and improving the adjustability of the signal path.
[0077] In one embodiment, the first trace 190 is a waveform trace. By adding additional bends or serpentine paths to the signal line, the length of the second signal transmission path can be adjusted, thereby reducing the phase difference when the signal reaches its destination, avoiding signal reflection and ringing, and improving signal integrity and system stability.
[0078] In one embodiment, the projection of the first blind via 181 perpendicular to the first signal layer 101 falls within the projection of the third pad 150 perpendicular to the first signal layer 101, and the projection of the second blind via 182 perpendicular to the first signal layer 101 falls within the projection of the second pad 140 perpendicular to the first signal layer 101. That is, the first blind via 181 is located directly below the third pad 150, ensuring the shortest and most direct vertical electrical connection from the third pad 150 to the second signal layer 105, reducing signal transmission delay and loss, and avoiding potential interference with other traces or components. Similarly, the second blind via 182 is located directly below the second pad 140, ensuring the shortest and most direct vertical electrical connection from the second signal layer 105 to the second pad 140, also reducing signal transmission delay and loss, optimizing the signal path, and improving signal integrity and system stability.
[0079] Figure 4 A printed circuit board provided for another embodiment of this disclosure along Figure 2 A cross-sectional view at the location indicated by the dashed line;
[0080] In one embodiment, see Figure 4As shown, the printed circuit board 100 also includes a third signal layer 106, which is located in the middle layer of the printed circuit board. The other end of the third pad 150 is electrically connected to the other end of the second pad 140 through a first blind via 181, a first trace 190, a third blind via 183, a second trace 191, and a second blind via 182. The first blind via 181 connects the first signal layer 102 and the second signal layer 105, the third blind via 183 connects the second signal layer 105 and the third signal layer 106, and the second blind via 182 connects the first signal layer 102 and the third signal layer 106. The first trace 190 is located within the second signal layer 105, and the second trace 191 is located within the third signal layer 106. This effectively increases the length of the second signal transmission path and allows for flexible trace design, avoiding components and interference between signal lines and components. This optimizes the layout of the printed circuit board 100 and improves the overall design efficiency and performance.
[0081] Figure 5 A top view of a printed circuit board provided in another embodiment of this disclosure;
[0082] Reference Figure 5 As shown, in one embodiment, the first pad 130, the second pad 140, and the third pad 150 each have two resistive contacts. Specifically, the first pad 130 has two resistive contacts 131 and 132, the second pad 140 has two resistive contacts 132 and 141, and the third pad 150 has two resistive contacts 131 and 151. One resistive contact of the first pad 130 is shared with one resistive contact of the second pad 140 (i.e., they share a single resistive contact 132); the other resistive contact of the first pad 130 is shared with one resistive contact of the third pad 150 (i.e., they share a single resistive contact 131). By sharing resistive contacts, the number of independent contacts required for each pad is reduced, thereby saving space on the printed circuit board. Simultaneously, the shared resistive contacts 132 and 131 allow for more flexible adjustment of the routing distances from the first pad 130, the second pad 140, and the third pad 150 to the first gold finger pin 110 and the first signal line pin 120. By precisely controlling trace lengths, it is possible to ensure that signals travel for the same amount of time in different paths, reducing phase differences, avoiding signal reflections and ringing, and improving signal integrity and system stability. Shared resistor contacts simplify the layout of the damping resistor network, reduce the complexity of connections between resistors, help reduce signal path complexity, and improve the manufacturability and testability of the design.
[0083] Reference Figure 5As shown, in one embodiment, the first resistor and the second resistor have the same resistance value, and both resistance values are greater than 0 ohms, while the third resistor has a resistance value of 0 ohms. That is, the first resistor and the second resistor connected to the first gold finger pin have equal resistance values and are both damping resistors. This means that the impedance through the first resistor and the second resistor is the same in both signal paths from the first gold finger pin 110 to the first signal line pin 120. This reduces signal reflection and ringing, improving signal integrity and system stability. The resistance value greater than 0 ohms ensures a damping effect in the signal path, helping to absorb signal reflection and reduce signal ringing. The third resistor has a resistance value of 0 ohms and is generally considered a short circuit, providing no impedance in the circuit, allowing for parallel connection of the signal paths.
[0084] Figure 6 A top view of a printed circuit board provided in yet another embodiment of this disclosure;
[0085] Reference Figure 6 As shown, in one embodiment, the first signal layer 101 further includes: a second gold finger pin 111; a second signal line pin 121; the second signal line pin 121 and the second gold finger pin 111 are electrically connected via traces. The second gold finger pin 111 is a control signal pin or an address signal pin. Common control signals include CS (chip select signal), CK (clock signal), RESET (reset signal), etc. These signals are issued by the memory controller and transmitted to the DIMM through the second gold finger pin 111 to control the operation of the DRAM chip. The address signal is used to specify the address of the memory cell and is the basis for addressing operations. The address signal is issued by the memory controller and transmitted to the DIMM through the second gold finger pin 111 to determine the target memory cell for data read / write operations.
[0086] Reference Figure 2 or Figure 6 As shown, in one embodiment, the first signal layer 101 is further provided with a grounding gold finger pin 170 and a grounding via 160. The grounding gold finger pin 170 is electrically connected to the grounding via 160, and the grounding via 160 is located near the grounding gold finger pin and the first gold finger pin 110, such as in the upper middle position. The function of the grounding gold finger pin 170 is to provide a stable reference potential for grounding all signals in the circuit, helping to shield electromagnetic interference (EMI) and aiding in heat dissipation. The grounding via 160 is used to realize grounding connections between different layers. The grounding via 160 can penetrate multiple layers of printed circuit boards, connecting the first signal layer 101 to the internal ground layer or the ground plane of the bottom layer, providing a low-impedance grounding path. Through the grounding via 160, it can be ensured that the grounding signal in the circuit can be effectively connected to the ground layer of the printed circuit board, achieving stable grounding of the entire circuit.
[0087] This embodiment of the disclosure improves the structure of the printed circuit board in the front-end design, so that the difference in the signal transmission paths of the dual in-line memory module 0 (DIMM0) and the dual in-line memory module 1 (DIMM1) is equal to the spacing between the dual in-line memory module 0 (DIMM0) and the dual in-line memory module 1 (DIMM1) on the motherboard. In this way, the lengths of the two branch lines are equal. Theoretically, when the signal is reflected back at the end, since the phase of the reflected signal is the same, they will cancel each other out on the trunk line, thereby reducing the impact of reflection and improving signal quality.
[0088] Based on the above embodiments, this disclosure also provides a memory module. The following provides a detailed description of this semiconductor device.
[0089] Figure 7 This illustration shows a structural diagram of a memory module of a memory module provided in an embodiment of the present disclosure;
[0090] Figure 8 This illustration shows a schematic diagram of the structure of another memory module of a memory module provided in an embodiment of the present disclosure;
[0091] Reference Figure 7 and Figure 8 As shown, in one embodiment, memory modules 201 and 202 are provided, including:
[0092] Printed circuit board 100;
[0093] Memory chip 210, memory chip 210 is electrically connected to printed circuit board 100;
[0094] Printed circuit board 100 includes:
[0095] First signal layer 101, the first signal layer 101 is located on the top layer of printed circuit board 100;
[0096] The first signal layer 101 is equipped with:
[0097] First gold finger pin 110;
[0098] First signal line pin 120;
[0099] The first pad 130 is used to connect the first resistor 1301. One end of the first pad 130 is electrically connected to the first gold finger 110 pin, and the other end of the first pad 130 is connected to the first signal line pin 120.
[0100] The second pad 140 is used to connect the second resistor 1401. One end of the second pad 140 is electrically connected to the pin of the first gold finger 110.
[0101] The third pad 150 is used to connect the third resistor 1501. One end of the third pad 150 is electrically connected to the first signal line pin 120, and the other end of the third pad 150 is electrically connected to the other end of the second pad 140.
[0102] The first signal transmission path is that the first gold finger pin 110 passes through the first resistor 1301 to reach the first signal line pin 120. The second signal transmission path is that the first gold finger pin 110 passes through the second resistor 1401 and the third resistor 1501 to reach the first signal line pin 120. The length difference between the second signal transmission path and the first signal transmission path is a first set value.
[0103] The memory module includes a first memory module 201 and a second memory module 202. The first memory module 201 is equipped with a first resistor 1301, and the second memory module 202 is equipped with a second resistor 1401 and a third resistor 1501.
[0104] In other words, the first memory module 201 uses a first signal transmission path: the signal travels directly from the first gold finger pin 110 through the first resistor to the first signal line pin 120. The second memory module 202 uses a second signal transmission path: the signal travels from the first gold finger pin 110 through the second resistor and the third resistor, finally reaching the first signal line pin 120. The length difference between the second signal transmission path and the first signal transmission path is a first preset value. This first preset value can be, for example, as follows: Figure 1 The distance between the first memory module 201 and the second memory module 202 on the motherboard is the difference in physical length of the signal path between the two modules. This design ensures that even if the physical lengths of the signal paths of the two modules are different, the propagation time of the signal in different paths remains consistent, thus achieving equal length matching and improving signal integrity and system stability.
[0105] In one embodiment, the first resistor 1301 and the second resistor 1401 have the same resistance value, and both resistance values are greater than 0 ohms. The third resistor 1501 has a resistance value of 0 ohms. That is, the first resistor 1301 and the second resistor 1401 connected to the first gold finger pin have equal resistance values and are both damping resistors. This means that the impedance through the first resistor 1301 and the second resistor 1401 is the same in both signal paths from the first gold finger pin 110 to the first signal line pin 120. This reduces signal reflection and ringing, improving signal integrity and system stability. The resistance value greater than 0 ohms ensures a damping effect in the signal path, helping to absorb signal reflection and reduce signal ringing. The third resistor 1501 has a resistance value of 0 ohms and is generally considered a short circuit, providing no impedance in the circuit, allowing for parallel connection of the signal paths.
[0106] Figure 9 A schematic diagram of the structure of a storage system provided in an embodiment of this disclosure is shown;
[0107] Reference Figure 9 As shown, in another embodiment, a storage system 300 is provided, comprising:
[0108] Motherboard 310;
[0109] The memory controller 320 is located on the motherboard 310.
[0110] The first memory module 201 and the second memory module 202 mentioned above;
[0111] The length difference between the second signal transmission path and the first signal transmission path is the distance between the first memory module 201 and the second memory module 202.
[0112] In other words, the first memory module 201 uses a first signal transmission path: the signal travels directly from the first gold finger pin 110 through the first resistor to the first signal line pin 120. The second memory module 202 uses a second signal transmission path: the signal travels from the first gold finger pin 110 through the second resistor and the third resistor, finally reaching the first signal line pin 120. The first memory module 201 is positioned away from the memory controller 320, resulting in a longer signal path from the memory controller 320 to the first memory module 201; the second memory module 202 is positioned closer to the memory controller 320, resulting in a shorter signal path from the memory controller 320 to the second memory module 202. To achieve equal-length matching with the signal path of the first memory module 201, the second memory module 202 uses a longer second signal transmission path, where the signal travels from the first gold finger pin 110 through the second resistor and the third resistor, finally reaching the first signal line pin 120.
[0113] Through the above design, even if the first memory module 201 and the second memory module 202 are located at different positions relative to the memory controller 320, the propagation time of the signal in different paths can remain consistent, thereby achieving equal-length matching and improving signal integrity and system stability. Especially in high-speed data transmission systems, this helps reduce signal distortion, improve signal quality, and meet the stringent requirements of high-speed signal transmission for signal integrity and system stability.
[0114] In one embodiment, the first memory module 201 and the second memory module 202 are located in the same memory channel. That is, the first memory module 201 and the second memory module 202 form a T-shaped topology on the motherboard 310.
[0115] Through the above embodiments, it can be ensured that the first memory module 201 and the second memory module 202 communicate efficiently and stably with the memory controller 320 in the same memory channel, reducing the reflection and ringing of data signals during transmission, thereby improving the integrity of data signals and the stability of the system.
[0116] In the description of this disclosure, it should be understood that the terms “center,” “longitudinal,” “lateral,” “length,” “width,” “thickness,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.
[0117] In the description of this disclosure, it should be understood that the terms “comprising” and “having” as used herein, and any variations thereof, are intended to cover non-exclusive inclusion, such that a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units that are expressly listed, but may include other steps or units that are not expressly listed or that are inherent to such process, method, product, or apparatus.
[0118] Unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can be a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.
[0119] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit it. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this invention.
Claims
1. A printed circuit board, characterized in that, include: A first signal layer, located on the top layer of the printed circuit board; The first signal layer is provided with: First gold finger pin; First signal line pin; The first pad is used to connect the first resistor. One end of the first pad is electrically connected to the first gold finger pin, and the other end of the first pad is connected to the first signal line pin. The second pad is used to connect the second resistor, and one end of the second pad is electrically connected to the first gold finger pin; The third pad is used to connect the third resistor. One end of the third pad is electrically connected to the first signal line pin, and the other end of the third pad is electrically connected to the other end of the second pad. The first signal transmission path is that the first gold finger pin reaches the first signal line pin through the first resistor, and the second signal transmission path is that the first gold finger pin reaches the first signal line pin through the second resistor and the third resistor respectively. The length difference between the second signal transmission path and the first signal transmission path is a first set value.
2. The printed circuit board according to claim 1, characterized in that, Both the first gold finger pin and the first signal line pin are data pins.
3. The printed circuit board according to claim 1, characterized in that, The trace between the first gold finger pin and the first pad is equidistant from the trace between the first gold finger pin and the second pad.
4. The printed circuit board according to claim 1, characterized in that, The trace distance between the first signal line pin and the first pad is equal to the trace distance between the first signal line pin and the third pad.
5. The printed circuit board according to claim 1, characterized in that, The printed circuit board further includes a second signal layer, which is located in the middle layer of the printed circuit board. The other end of the third pad is electrically connected to the other end of the second pad through a first blind via, a first trace, and a second blind via.
6. The printed circuit board according to claim 5, characterized in that, The first blind via and the second blind via connect the first signal layer and the second signal layer, and the first trace is located within the second signal layer.
7. The printed circuit board according to claim 5, characterized in that, The first trace is a waveform trace.
8. The printed circuit board according to claim 5, characterized in that... The projection of the first blind via perpendicular to the first signal layer falls within the projection of the third pad perpendicular to the first signal layer, and the projection of the second blind via perpendicular to the first signal layer falls within the projection of the second pad perpendicular to the first signal layer.
9. The printed circuit board according to claim 1, characterized in that, The first pad, the second pad, and the third pad each have two resistive contact points. One resistive contact point of the first pad is shared with one resistive contact point of the second pad, and the other resistive contact point of the first pad is shared with one resistive contact point of the third pad.
10. The printed circuit board according to claim 1, characterized in that, The first resistor and the second resistor have the same resistance value, and the resistance values of the first resistor and the second resistor are greater than 0 ohms, while the resistance value of the third resistor is 0 ohms.
11. The printed circuit board according to claim 1, characterized in that, The first signal layer is also provided with: Second gold finger pin; The second signal line pin is electrically connected to the second gold finger pin via a trace.
12. A memory module, characterized in that, include: Printed circuit boards; A memory chip, which is electrically connected to the printed circuit board; The printed circuit board includes: A first signal layer, located on the top layer of the printed circuit board; The first signal layer is provided with: First gold finger pin; First signal line pin; The first pad is used to connect the first resistor. One end of the first pad is electrically connected to the first gold finger pin, and the other end of the first pad is connected to the first signal line pin. The second pad is used to connect the second resistor, and one end of the second pad is electrically connected to the first gold finger pin; The third pad is used to connect the third resistor. One end of the third pad is electrically connected to the first signal line pin, and the other end of the third pad is electrically connected to the other end of the second pad. The first signal transmission path is that the first gold finger pin reaches the first signal line pin through the first resistor, and the second signal transmission path is that the first gold finger pin reaches the first signal line pin through the second resistor and the third resistor respectively. The length difference between the second signal transmission path and the first signal transmission path is a first set value. The memory module includes a first memory module and a second memory module. The first memory module is equipped with the first resistor, and the second memory module is equipped with the second resistor and the third resistor.
13. The memory module according to claim 12, characterized in that, The first resistor and the second resistor have the same resistance value, and the resistance values of the first resistor and the second resistor are greater than 0 ohms, while the resistance value of the third resistor is 0 ohms.
14. A storage system, characterized in that, include: Motherboard; The memory controller is located on the motherboard. The first memory module and the second memory module as described in any one of claims 12-13; The length difference between the second signal transmission path and the first signal transmission path is the distance between the first memory module and the second memory module.
15. The storage system according to claim 14, characterized in that, The first memory module and the second memory module are located in the same memory channel.