Two-dimensional semiconductor transistor with gate dielectric cooperatively inducing channel p-type conduction

Abstract

The invention discloses a two-dimensional semiconductor transistor with a gate dielectric cooperatively inducing channel p-type conduction, and belongs to the technical field of semiconductor devices. The device mainly solves the technical problem that stable and high-performance p-type conduction of a two-dimensional n-type semiconductor material (such as InSe) is difficult to realize. According to the technical scheme, the method is characterized in that a two-dimensional antiferromagnetic insulating material CrOCl is adopted as a gate medium and a p-type induction layer at the same time, effective hole doping of a channel material is achieved through van der Waals interface charge transfer between the CrOCl and a two-dimensional n-type semiconductor channel layer (such as InSe), and a stable p-type conductive channel is formed through induction. The device structure comprises a substrate, a gate electrode, a CrOCl layer, a semiconductor channel layer and a source / drain electrode from bottom to top. A traditional doping technology is not needed, simple construction of the p-type transistor is achieved through material and structure innovation, and a core device scheme is provided for a complementary metal oxide semiconductor (CMOS) logic circuit based on a two-dimensional semiconductor.

Description

A two-dimensional semiconductor transistor with gate dielectric co-induced channel p-type conductivity Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a two-dimensional semiconductor transistor with gate dielectric cooperatively induced channel p-type conductivity. Background Technology

[0002] As silicon-based complementary metal-oxide-semiconductor (CMOS) technology approaches its physical limits, two-dimensional layered semiconductor materials (such as MoS2, WSe2, and InSe) are considered important candidate materials for extending Moore's Law due to their atomic-level thickness, excellent electrostatic gate control properties, and good compatibility with monolithic three-dimensional integrated (M3D) architectures. Among them, indium selenide (InSe) shows great potential in n-type transistor applications due to its extremely high electron mobility and unique band structure. However, this material intrinsically exhibits n-type or weak bipolar conductivity, and achieving its stable and high-performance p-type conductivity remains a significant challenge.

[0003] Currently, conventional techniques for achieving p-type conductivity in two-dimensional semiconductors mainly include surface chemical modification and doping processes such as ion implantation. However, these methods have significant limitations: the poor stability of surface modifiers can lead to performance degradation over time; and processes such as ion implantation can easily cause irreversible damage to the atomically thin lattice of two-dimensional materials, introducing severe scattering centers and resulting in a significant decrease in carrier mobility. These factors severely restrict the development of complementary metal-oxide-semiconductor (CMOS) circuits based on materials such as InSe.

[0004] Therefore, there is an urgent need to develop a non-destructive, stable and controllable new method that can effectively induce reliable p-type conductivity in two-dimensional n-type semiconductors without lattice damage, laying the foundation for building high-performance two-dimensional semiconductor (CMOS) technology. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing two-dimensional semiconductor p-type doping technology and provide a two-dimensional semiconductor transistor that uses a gate dielectric to synergistically induce channel p-type conductivity. This invention utilizes two-dimensional antiferromagnetic insulating material CrOCl as both the gate dielectric and the p-type doping source to achieve a transistor device with high efficiency and stable p-type conductivity in two-dimensional n-type semiconductors (such as InSe).

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A two-dimensional semiconductor transistor with gate dielectric co-induced channel p-type conductivity includes a substrate, a gate electrode, a CrOCl layer, a semiconductor channel layer, and a source electrode and a drain electrode.

[0008] The gate electrode is disposed on the substrate; the CrOCl layer is disposed on the gate electrode; the semiconductor channel layer is disposed on the CrOCl layer, and the semiconductor channel layer is composed of an intrinsic n-type two-dimensional semiconductor material; the source electrode and the drain electrode are disposed on the semiconductor channel layer;

[0009] The CrOCl layer is integrated with the semiconductor channel layer through van der Waals forces, and the CrOCl layer induces the semiconductor channel layer to form a p-type conductive channel through interface charge transfer.

[0010] The substrate is a silicon substrate, a sapphire substrate, or a flexible polymer substrate with an insulating layer on its surface. The substrate is preferably a SiO2 / Si substrate, wherein the thickness of the silicon layer is 400~600 μm, and the thickness of the thermally grown silicon dioxide layer is 250~300 nm.

[0011] The gate electrode is composed of few-layer graphene, thin-layer graphite, or a metal film.

[0012] The thickness of the gate electrode is 5-15 nm, preferably 5-10 nm.

[0013] The thickness of the CrOCl layer is 5~60 nm, preferably 40~60 nm.

[0014] The semiconductor channel layer is made of one of indium selenide (InSe), molybdenum disulfide (MoS2), or tungsten disulfide (WS2).

[0015] The thickness of the semiconductor channel layer is 3~20nm.

[0016] A method for fabricating the transistor device includes the following steps:

[0017] 1) Fabricate the gate electrode on the substrate;

[0018] 2) The CrOCl layer is transferred to the gate electrode using van der Waals transfer technology;

[0019] 3) The semiconductor channel layer is transferred onto the CrOCl layer using van der Waals transfer technology;

[0020] 4) The source electrode and drain electrode are fabricated on the semiconductor channel layer.

[0021] Specifically, Pd-Au source electrodes and Pd-Au drain electrodes are fabricated at both ends of the InSe channel using electron beam lithography and electron beam evaporation processes, and electrode leads are fabricated on few-layer graphene.

[0022] The gate electrode, CrOCl layer, and semiconductor channel layer are all fabricated using a mechanical exfoliation method. The van der Waals transfer technique uses a polydimethylsiloxane (PDMS) film as the transfer medium. For example, few-layer graphene is transferred onto a SiO2 / Si substrate to form a gate electrode via mechanical exfoliation. Then, CrOCl and InSe sheets are prepared separately via mechanical exfoliation, and PDMS is used as the transfer medium to precisely transfer them sequentially onto the gate electrode and CrOCl layer, ultimately forming an InSe / CrOCl / Graphite van der Waals heterojunction structure.

[0023] Compared with the prior art, the beneficial effects achieved by the technical solution of this invention are:

[0024] This invention utilizes the CrOCl layer to simultaneously serve as both a gate dielectric and a p-type inducer. When CrOCl and an n-type two-dimensional semiconductor channel (such as InSe) form an interface through van der Waals forces, the Fermi level difference between them triggers charge redistribution, causing electrons to transfer from the semiconductor channel layer to the CrOCl layer. This effectively injects holes into the semiconductor channel, achieving a conversion from n-type to p-type conductivity. Simultaneously, the CrOCl layer possesses excellent insulating properties, effectively transferring the electric field from the gate electrode and enabling electrostatic control of the p-type channel carrier concentration.

[0025] This invention achieves efficient hole doping induction and electrostatic gate control simultaneously without the need for an additional dielectric layer or traditional doping processes, thereby obtaining a stable, electrically turn-on p-type transistor. Attached Figure Description

[0026] Figure 1 is a three-dimensional structural diagram of the transistor device provided in an embodiment of the present invention.

[0027] Figure 2 is an optical microscope image of the transistor device prepared in the embodiment of the present invention.

[0028] Figure 3 shows the Raman spectral characterization results of CrOCl, InSe, and the heterojunction formed by them (InSe-CrOCl) in the embodiments of the present invention.

[0029] Figure 4 is a schematic diagram of the parallel plate capacitor structure used for measuring the dielectric constant of CrOCl in an embodiment of the present invention.

[0030] Figure 5. Optical microscope image of the CrOCl parallel plate capacitor prepared in the embodiment of the present invention.

[0031] Figure 6 shows the curve of the dielectric constant of CrOCl as a function of the test frequency, measured by a parallel plate capacitor in an embodiment of the present invention.

[0032] Figure 7 shows the transfer characteristic curve (Ids-Vg) of the transistor device prepared in the embodiment of the present invention, which clearly demonstrates its p-type conductivity behavior. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this invention clearer, the following embodiments will be used in conjunction with the accompanying drawings to further illustrate the invention. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention. Rather, the invention encompasses any substitutions, modifications, equivalent methods, and solutions made within the spirit and scope of the invention as defined by the claims. Furthermore, to provide the public with a better understanding of this invention, some specific details are described in detail below. Those skilled in the art will fully understand the invention even without these detailed descriptions.

[0034] As shown in Figures 1-2, the transistor device described in this embodiment includes, from bottom to top: a SiO2 / Si substrate, a few-layer graphene layer as a gate electrode, a CrOCl layer, an InSe channel layer, a Pd-Au source electrode, and a Pd-Au drain electrode; wherein, the CrOCl layer and the InSe channel layer are integrated by van der Waals forces to form an InSe-CrOCl heterojunction interface.

[0035] As shown in Figure 3, Raman spectroscopy was performed on the prepared CrOCl, InSe, and their heterojunction (InSe-CrOCl). The results show that characteristic peaks from both CrOCl and InSe can be clearly distinguished simultaneously in the heterojunction, and the peak positions do not shift significantly. This confirms that a van der Waals heterojunction with a clean interface and complete crystal structure was successfully constructed using the dry transfer technique, and that the interfacial interaction is a weak van der Waals force rather than a strong chemical bond.

[0036] The fabrication process of the device in this embodiment mainly includes the following steps:

[0037] 1. Substrate preparation: Commercially available thermally grown SiO2 (285 nm thick) / Si substrates are treated using standard RCA cleaning process.

[0038] 2. Gate electrode fabrication: Few-layer graphene was peeled from a high-orientation pyrolytic graphite (HOPG) bulk material using a mechanical exfoliation method (using Scotch™ tape) and transferred onto a SiO2 / Si substrate to form the gate electrode. The obtained graphene flakes had a size of approximately 30 × 50 μm² and a thickness of approximately 5–10 nm.

[0039] 3. Material peeling: Using the same mechanical peeling method, the bulk CrOCl crystals and InSe crystals are peeled thin and transferred to a pre-made polydimethylsiloxane (PDMS) elastic film.

[0040] 4. Van der Waals heterojunction assembly:

[0041] a. Using a custom-designed micro / nano manipulator, under the guidance of an optical microscope, the CrOCl sheet attached to PDMS was precisely aligned and imprinted onto the graphene gate electrode prepared in step 2, completing the transfer of the CrOCl / Graphite heterojunction. During this process, the substrate heating stage temperature was controlled at 60°C to promote release.

[0042] b. Repeat this operation to precisely transfer the InSe sheet onto the formed CrOCl layer, ultimately constructing a complete InSe / CrOCl / Graphite van der Waals heterojunction structure. During this process, the CrOCl layer thickness is controlled at approximately 50 nm, and the InSe channel layer thickness is controlled at approximately 8 nm.

[0043] 5. Electrode Fabrication: Electron beam lithography (EBL) was used to define electrode patterns at both ends of the InSe channel. Subsequently, 10 nm thick palladium (Pd) and 50 nm thick gold (Au) layers were sequentially deposited via electron beam evaporation to form the source and drain electrodes. The evaporation process achieved a speed better than 3 × 10⁻⁶. -5 The deposition was carried out under a vacuum of Pa, with Pd and Au deposition rates controlled at 0.5–1 Å / s and 1–1.5 Å / s, respectively.

[0044] To confirm the feasibility of CrOCl as a gate dielectric, a CrOCl parallel-plate capacitor was fabricated (see Figures 4 and 5). The capacitance-voltage characteristics were tested, and the calculated dielectric constant versus frequency is shown in Figure 6. The results show that CrOCl has a relative dielectric constant of approximately 6 at low frequencies and possesses good insulation properties, meeting the basic requirements for a gate dielectric and providing experimental support for its "gate dielectric function" in transistors.

[0045] Finally, the electrical performance of the device was tested on a probe station. As shown in Figure 7, the transfer characteristic curve (Ids-Vg) of the fabricated transistor clearly shows that when the gate voltage (Vg) is scanned from negative to positive, the drain current (Ids) first decreases and then increases, and the current is significant in the negative gate voltage range, exhibiting typical p-type transistor characteristics dominated by hole transport. This result directly confirms that the CrOCl layer has an effective p-type induction effect on the originally n-type InSe channel, and the fabricated device exhibits typical p-type field-effect characteristics, achieving a microampere-level conduction current under a positive gate voltage.

[0046] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical principles disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the claims.

Claims

1. A two-dimensional semiconductor transistor with gate dielectric cooperatively induced channel p-type conductivity, characterized in that: The device includes a substrate, a gate electrode, a CrOCl layer, a semiconductor channel layer, and source and drain electrodes. The gate electrode is disposed on the substrate. The CrOCl layer is disposed on the gate electrode, and the semiconductor channel layer is disposed on the CrOCl layer. The semiconductor channel layer is composed of an intrinsic n-type two-dimensional semiconductor material. The source and drain electrodes are disposed on the semiconductor channel layer. The CrOCl layer and the semiconductor channel layer are integrated by van der Waals forces, and the CrOCl layer induces the semiconductor channel layer to form a p-type conductive channel through interface charge transfer.

2. The two-dimensional semiconductor transistor with gate dielectric cooperatively induced channel p-type conductivity as described in claim 1, characterized in that: The substrate is a silicon substrate, a sapphire substrate, or a flexible polymer substrate with an insulating layer on its surface.

3. A two-dimensional semiconductor transistor with gate dielectric cooperatively induced channel p-type conductivity as described in claim 1, characterized in that: The gate electrode is composed of few-layer graphene, thin-layer graphite, or a metal film.

4. A two-dimensional semiconductor transistor with gate dielectric cooperatively induced channel p-type conductivity as described in claim 1, characterized in that: The thickness of the gate electrode is 5~15nm.

5. A two-dimensional semiconductor transistor with gate dielectric cooperatively induced channel p-type conductivity as described in claim 1, characterized in that: The thickness of the CrOCl layer is 5~60 nm.

6. A two-dimensional semiconductor transistor with gate dielectric cooperatively induced channel p-type conductivity as described in claim 1, characterized in that: The semiconductor channel layer is made of one of indium selenide, molybdenum disulfide, or tungsten disulfide.

7. A two-dimensional semiconductor transistor with gate dielectric cooperatively induced channel p-type conductivity as described in claim 1, characterized in that: The thickness of the semiconductor channel layer is 3~20nm.

8. A method for manufacturing a transistor device as described in any one of claims 1 to 7, characterized in that, Includes the following steps: 1) Fabricate the gate electrode on the substrate; 2) Transfer the CrOCl layer onto the gate electrode using van der Waals transfer technology; 3) Transfer the semiconductor channel layer onto the CrOCl layer using van der Waals transfer technology; 4) The source electrode and drain electrode are fabricated on the semiconductor channel layer.

9. The method as described in claim 8, characterized in that: The gate electrode, CrOCl layer, and semiconductor channel layer were all fabricated using a mechanical exfoliation method.

10. The method as described in claim 8, characterized in that: The van der Waals transfer technique described herein uses polydimethylsiloxane film as the transfer medium.

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