A semiconductor device and a method of fabricating the same

Abstract

The application provides a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate, a channel layer, a barrier layer, a gate layer and a gate electrode. The channel layer is located on one side of the substrate; the barrier layer is located on a side of the channel layer away from the substrate; the gate layer is located on a side of the barrier layer away from the substrate layer; the gate electrode is located on a side of the gate layer away from the substrate layer, and a normal projection of the gate electrode on a thickness direction of the semiconductor device falls within a surface of the gate layer away from the substrate; the gate layer comprises a first gate part and a second gate part, and the first gate part is located on a side of the second gate part away from the substrate; a ratio of a thickness of the first gate part to a thickness of the gate layer is less than or equal to 0.15, and a step structure is formed on a periphery of the first gate part; the step structure comprises a step side wall surface, a step top wall surface and a step bottom wall surface connected to the step side wall surface, the step top wall surface is connected to a top end of the step side wall surface, the step bottom wall surface is connected to a bottom end of the step side wall surface, and the gate electrode is arranged on the step top wall surface.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] With the development of semiconductor technology, people have increasingly higher requirements for the performance of integrated circuits. Semiconductor doped layers (such as gate layers) in semiconductor devices are prone to interface leakage, which limits or reduces the performance of semiconductor devices. Summary of the Invention

[0003] According to a first aspect of the embodiments of this application, a semiconductor device is provided, comprising:

[0004] Substrate;

[0005] A channel layer is located on one side of the substrate;

[0006] A barrier layer is located on the side of the channel layer opposite to the substrate;

[0007] A gate layer is located on the side of the barrier layer opposite to the substrate layer;

[0008] A gate electrode is located on the side of the gate layer away from the substrate layer, and the orthogonal projection of the gate electrode in the thickness direction of the semiconductor device falls into the surface of the gate layer on the side away from the substrate.

[0009] In the thickness direction of the semiconductor device, the gate layer includes a first gate portion and a second gate portion, and the first gate portion is located on the side of the second gate portion away from the substrate. The ratio of the thickness of the first gate portion to the thickness of the gate layer is less than or equal to 0.15, and a stepped structure is formed around the periphery of the first gate portion.

[0010] The stepped structure includes a stepped sidewall and a stepped top wall and a stepped bottom wall that connect the stepped sidewall. The stepped top wall is connected to the top of the stepped sidewall, and the stepped bottom wall is connected to the bottom of the stepped sidewall. The gate electrode is disposed on the stepped top wall.

[0011] In some embodiments, the gate layer includes an insertion layer and a p-type GaN layer; the material of the insertion layer includes Al. 1-x Ga x N (0≤x≤1); the insertion layer is disposed between the gate electrode and the P-type GaN layer.

[0012] In some embodiments, the first gate portion includes only the insertion layer.

[0013] In some embodiments, the first gate portion includes the insertion layer and a P-type GaN layer of a certain thickness that contacts the insertion layer.

[0014] In some embodiments, the gate layer is a P-type GaN layer.

[0015] In some embodiments, the thickness of the first gate portion is less than or equal to 25 nm.

[0016] In some embodiments, the bottom wall of the step is a plane perpendicular to the thickness direction of the semiconductor device.

[0017] In some embodiments, at least a portion of the bottom wall of the step is an inclined surface that approaches the substrate side in the direction from the sidewall of the step toward the outer edge of the gate layer; the inclined surface is an inclined plane or an inclined curved surface.

[0018] In some embodiments, the gate electrode has an electrode top surface and an electrode bottom surface opposite each other in the thickness direction of the semiconductor device, and an electrode sidewall surface connecting the electrode top surface and the electrode bottom surface, the electrode sidewall surface being a concave curved surface.

[0019] According to a second aspect of the embodiments of this application, a method for fabricating a semiconductor device is provided, comprising:

[0020] A substrate is provided, and a trench layer is formed on one side of the substrate;

[0021] A barrier layer is formed on the side of the channel layer opposite to the substrate;

[0022] A gate layer and a gate electrode are formed on the side of the barrier layer opposite to the substrate layer. The orthogonal projection of the gate electrode in the thickness direction of the semiconductor device falls into the surface of the gate layer on the side opposite to the substrate. In the thickness direction of the semiconductor device, the gate layer includes a first gate portion and a second gate portion, and the first gate portion is located on the side of the second gate portion opposite to the substrate. The ratio of the thickness of the first gate portion to the thickness of the gate layer is less than or equal to 0.15, and a stepped structure is formed around the first gate portion. The stepped structure includes a step sidewall and a step top wall and a step bottom wall connecting the step sidewall. The step top wall is connected to the top of the step sidewall, and the step bottom wall is connected to the bottom of the step sidewall. The gate electrode is disposed on the step top wall.

[0023] In some embodiments, the gate layer and the gate electrode are formed using an etching process.

[0024] In some embodiments, the gate layer includes an insertion layer and a p-type GaN layer; the material of the insertion layer is Al.1- x Ga x N (0≤x≤1); a gate layer and a gate electrode located on the side of the barrier layer opposite to the substrate layer are formed, including:

[0025] A P-type GaN material layer, an insertion material layer, and an electrode material layer are sequentially formed on the side of the barrier layer opposite to the substrate layer.

[0026] Etching the electrode material layer and a portion of the insertion material layer to form an intermediate electrode material layer and an intermediate insertion layer;

[0027] The gate layer is formed by etching the intermediate insertion material layer and the P-type GaN material layer.

[0028] The intermediate electrode material layer is etched to form the gate electrode.

[0029] The main technical effects achieved by the embodiments of this application are:

[0030] The semiconductor device and its fabrication method provided in this application embodiment are configured such that the gate electrode is positioned so that its orthogonal projection in the thickness direction of the semiconductor device falls within the surface of the gate layer on the side away from the substrate; and the gate layer is configured to include a first gate portion and a second gate portion in the thickness direction of the semiconductor device, the first gate portion being located on the side of the second gate portion away from the substrate, the ratio of the thickness of the first gate portion to the thickness of the gate layer being less than or equal to 0.15, and a stepped structure is formed around the first gate portion. This facilitates increasing the size of the gate (including the gate electrode and the gate layer) sidewall in the thickness direction, increasing the size of the edge leakage path from the gate sidewall to the barrier layer, optimizing the gate electric field distribution, improving the leakage performance of the gate sidewall, and enhancing the reliability of the gate. Attached Figure Description

[0031] Figure 1 This is a top view of a portion of a semiconductor device provided in an exemplary embodiment of this application;

[0032] Figure 2 It is along Figure 1 The sectional view obtained by section line AA shown;

[0033] Figure 3 This is a cross-sectional view of another semiconductor device provided in an exemplary embodiment of this application;

[0034] Figure 4 This is a cross-sectional view of another semiconductor device provided in an exemplary embodiment of this application;

[0035] Figure 5This is a cross-sectional view of another semiconductor device provided in an exemplary embodiment of this application;

[0036] Figure 6 This is a cross-sectional view of yet another semiconductor device provided in an exemplary embodiment of this application;

[0037] Figure 7 This is a cross-sectional view of another semiconductor device provided in an exemplary embodiment of this application;

[0038] Figure 8 This is a flowchart of a method for fabricating a semiconductor device provided in an exemplary embodiment of this application;

[0039] Figures 9 to 13 These are cross-sectional views corresponding to different fabrication process stages of a semiconductor device fabrication method provided in an exemplary embodiment of this application. Detailed Implementation

[0040] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0041] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0042] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0043] This application provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate, a channel layer, a barrier layer, a gate layer, and a gate electrode. The channel layer is located on one side of the substrate; the barrier layer is located on the side of the channel layer away from the substrate; the gate layer is located on the side of the barrier layer away from the substrate; the gate electrode is located on the side of the gate layer away from the substrate, and the orthogonal projection of the gate electrode in the thickness direction of the semiconductor device falls into the surface of the gate layer away from the substrate. The gate layer includes a first gate portion and a second gate portion, and the first gate portion is located on the side of the second gate portion away from the substrate. The ratio of the thickness of the first gate portion to the thickness of the gate layer is less than or equal to 0.15, and a stepped structure is formed around the periphery of the first gate portion. The stepped structure includes a step sidewall and a step top wall and a step bottom wall connecting the step sidewall. The step top wall is connected to the top of the step sidewall, and the step bottom wall is connected to the bottom of the step sidewall. The gate electrode is disposed on the step top wall.

[0044] The aforementioned semiconductor device, by arranging the gate electrode so that its orthogonal projection in the thickness direction of the semiconductor device falls within the surface of the gate layer on the side facing away from the substrate; and by arranging the gate layer in the thickness direction of the semiconductor device, including a first gate portion and a second gate portion, the first gate portion being located on the side of the second gate portion facing away from the substrate, the ratio of the thickness of the first gate portion to the thickness of the gate layer being less than or equal to 0.15, and forming a stepped structure around the first gate portion, thereby facilitating the increase of the dimension of the gate (including the gate electrode and the gate layer) sidewall in the thickness direction. That is, if the ratio of the thickness of the first gate portion to the thickness of the gate layer is greater than 0.15, it will lead to a thinner overall average thickness of the gate, resulting in weaker control over the two-dimensional electron gas below the gate. In addition, this application can also increase the dimension of the edge leakage path from the gate sidewall to the barrier layer, optimize the gate electric field distribution, improve the leakage performance of the gate sidewall, and improve the reliability of the gate.

[0045] The semiconductor device mentioned here can be a GaN HEMT device.

[0046] The following is in conjunction with the appendix Figures 1 to 13 The semiconductor devices and their fabrication methods in the embodiments of this application will be described in detail.

[0047] Please refer to Figure 1 and combine when necessary Figure 2As shown, the semiconductor device 100 includes a substrate 10, a channel layer 20, a barrier layer 30, a gate layer 40, and a gate electrode 50. The channel layer 20 is located on one side of the substrate 10. The barrier layer 30 is located on the side of the channel layer 20 away from the substrate 10. The gate layer 40 is located on the side of the barrier layer 30 away from the substrate 10. The gate electrode 50 is located on the side of the gate layer 40 away from the substrate 10, and the orthogonal projection of the gate electrode 50 in the thickness direction T of the semiconductor device falls within the surface 403 of the gate layer 40 on the side away from the substrate 10. The gate layer 40 includes a first gate portion 401 and a second gate portion 402, and the first gate portion 401 is located on the side of the second gate portion 402 away from the substrate 10. The ratio of the thickness t1 of the first gate portion 401 to the thickness t2 of the gate layer 40 is less than or equal to 0.15, and a stepped structure 4200 is formed around the periphery of the first gate portion 401.

[0048] It is understandable that the stepped structure 4200 formed around the first gate portion 401 can be as follows: Figure 2 The stepped structure 4200 shown can also be multiple consecutive stepped structures that taper inwards in the direction away from the substrate. For example... Figure 2 As shown, the stepped structure 4200 has a stepped sidewall 4202 and a stepped top wall 4203 and a stepped bottom wall 4201 connecting the stepped sidewall 4202. The stepped top wall 4203 is connected to the top of the stepped sidewall 4202, that is, the end closer to the gate electrode 50. The stepped bottom wall 4201 is connected to the bottom of the stepped sidewall 4202, that is, the end closer to the substrate 10. The stepped top wall 4203 and the stepped sidewall 4202 form a step. The gate electrode 50 is disposed on the stepped top wall 4203.

[0049] In some embodiments, the step bottom wall 4201 may be an annular wall located around the gate electrode. The step bottom wall 4201 may include step bottom walls located on both sides of the gate electrode 50 in the first direction W and step bottom walls located on both sides of the gate electrode 50 in the second direction L. The step bottom walls located on both sides of the gate electrode 50 in the first direction W and the step bottom walls located on both sides of the gate electrode 50 in the second direction L are smoothly connected.

[0050] The first direction W and the second direction L can be perpendicular to each other.

[0051] The substrate 10 may include a Si substrate, a SiC substrate, or a sapphire substrate, etc.

[0052] The channel layer 20 may include a nitride semiconductor layer. For example, the channel layer 20 may be a GaN layer or a semiconductor structure layer including a GaN layer.

[0053] The barrier layer 30 is used to transport electrons. The barrier layer 30 includes ions of metals such as Al and Ga. For example, the barrier layer 30 may be an AlGaN layer, or a semiconductor structure layer including an AlGaN layer.

[0054] The gate layer 40 may include a GaN layer doped with P, Mg, etc. For example, the gate layer 40 may be a P-type GaN layer (P-GaN), or a semiconductor structure layer including a P-type GaN layer.

[0055] The gate electrode 50 contains ions of metals such as titanium and tungsten. For example, it can be titanium nitride (TiN).

[0056] In some embodiments, the gate layer 40 includes an insertion layer 42 and a p-type GaN layer 41. The material of the insertion layer 42 includes Al. 1-x GaxN (0≤x≤1). The insertion layer 42 is disposed between the gate electrode 50 and the P-type GaN layer 41.

[0057] In some embodiments, the first gate portion 401 includes only the insertion layer 42.

[0058] The first gate portion 401 can be an insertion layer 42 of full thickness. For example... Figure 1 and Figure 2 In the semiconductor device 100 shown, the first gate portion 401 is an insertion layer 42 of full thickness. Of course, in other embodiments, the first gate portion may also be an insertion layer of partial thickness, that is, the insertion layer of partial thickness is formed with a stepped structure 4200.

[0059] In some other embodiments, the first gate portion 401 includes the insertion layer 42 and a portion of the thickness of the P-type GaN layer 41 in contact with the insertion layer 42.

[0060] It should be noted that in some other embodiments, the gate layer 40 may be a P-type GaN layer 41, that is, without the insertion layer, only including the P-type GaN layer.

[0061] It should be noted that for the gate layer 40 including the insertion layer 42 and the P-type GaN layer 41, the thickness of the insertion layer 42 may be less than or equal to 1 / 8 of the overall thickness t2 of the gate layer 40.

[0062] In some embodiments, the thickness of the first gate portion 401 is less than or equal to 25 nm. For example, 10 nm, 13 nm, 15 nm, 18 nm, 20 nm, 25 nm, etc.

[0063] The thickness of the gate layer 40 is typically 40nm-150nm, such as 40nm, 50nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, etc.

[0064] The thickness t1 of the first gate portion 401 can be set according to the thickness of the gate layer 40.

[0065] When the gate layer 40 includes an insertion layer 42 and a P-type GaN layer 41, the thickness of the insertion layer 42 can also be set according to the overall thickness t2 of the gate layer 40.

[0066] In some embodiments, the bottom wall surface 4201 of the step is a plane perpendicular to the thickness direction T of the semiconductor device 100.

[0067] for example, Figure 1 and Figure 2 In the semiconductor device 100 shown, the bottom wall 4201 of the step located on the outer periphery of the step is an annular plane. And this plane is perpendicular to the thickness direction T of the semiconductor device 100.

[0068] In other embodiments, at least a portion of the step bottom wall 4201 is an inclined surface that approaches the side of the substrate 10 in the direction from the step sidewall 4202 toward the outer edge of the gate layer 40.

[0069] The inclined surface is an inclined plane or an inclined curved surface.

[0070] The gate electrode 50 has a top electrode surface 502 and a bottom electrode surface 503 opposite each other in the thickness direction T of the semiconductor device 100, and an electrode sidewall surface 501 connecting the top electrode surface 502 and the bottom electrode surface 503. Figure 2 As shown, in some embodiments, the electrode sidewall 501 is a vertical wall.

[0071] Of course, in some other embodiments, the electrode sidewall 501 is curved, such as a concave curved surface, which is beneficial for further optimizing the electric field distribution of the device and improving the performance of the semiconductor device. In addition, the electrode sidewall may also be an inclined wall, for example, the cross-section of the gate electrode 50 is trapezoidal.

[0072] In some embodiments, the distance between the electrode sidewall 501 and the step sidewall 4202 is 10 nm to 100 nm. That is, the electrode sidewall 501 is recessed by 10 nm to 100 nm relative to the step sidewall 4202. This recessed distance increases the edge leakage path from the gate electrode sidewall through the gate layer surface to the barrier layer; at the same time, it also ensures the contact area between the gate electrode 50 and the gate layer 40, which is beneficial for controlling the contact resistance, preventing the contact resistance between the gate electrode 50 and the gate layer 40 from becoming too large, and ensuring the performance of the semiconductor device.

[0073] like Figure 3 As shown, this application also provides a semiconductor device 200. This semiconductor device 200 is substantially the same as the semiconductor device 100 described above; similarities or resemblances can be found in the aforementioned description and will not be repeated here. The difference between semiconductor device 200 and semiconductor device 100 is that, in the direction from the step sidewall 4202 toward the outer edge of the gate layer 40, at least a portion of the step bottom wall 4201 is an inclined plane approaching the substrate 10, i.e., at least a portion of the step bottom wall 4201 is a downwardly inclined plane.

[0074] For example, the step bottom wall 4201 on both sides of the gate electrode 50 in the first direction W and the step bottom wall 4201 on both sides of the gate electrode 50 in the second direction L can both be inclined downward planes.

[0075] like Figure 4 As shown, this application also provides a semiconductor device 300. This semiconductor device 300 is substantially the same as the semiconductor device 200 described above; similarities or resemblances can be found in the aforementioned description and will not be repeated here. The difference between semiconductor device 300 and semiconductor device 200 is that the first gate portion 401 includes an insertion layer 42 and a P-type GaN layer of a certain thickness.

[0076] like Figure 5 As shown, this application also provides a semiconductor device 400. This semiconductor device 400 is substantially the same as the semiconductor device 200 described above; similarities or resemblances can be found in the aforementioned descriptions and will not be repeated here. The difference between semiconductor device 400 and semiconductor device 200 is that, in the direction from the step sidewall 4202 toward the outer edge of the gate layer 40, at least a portion of the step bottom wall 4201 is an inclined curved surface approaching the substrate 10, that is, at least a portion of the step bottom wall 4201 is a downwardly inclined curved surface.

[0077] like Figure 6As shown, this application also provides a semiconductor device 500. This semiconductor device 500 is substantially the same as the semiconductor device 400 described above; similarities or resemblances can be found in the aforementioned descriptions and will not be repeated here. The difference between semiconductor device 500 and semiconductor device 400 is that the first gate portion 401 includes an insertion layer 42 and a P-type GaN layer of a certain thickness.

[0078] like Figure 7 As shown, this application also provides a semiconductor device 600. This semiconductor device 600 is substantially the same as the semiconductor device 100 described above; similarities or resemblances can be found in the aforementioned descriptions and will not be repeated here. The difference between semiconductor device 600 and semiconductor device 100 lies in the fact that the electrode sidewall 501 of semiconductor device 600 has a concave curved surface, which facilitates further optimization of the device's electric field distribution and improves the performance of the semiconductor device.

[0079] like Figure 8 As shown, this application also provides a method for fabricating a semiconductor device. The method for fabricating the semiconductor device includes the following steps S101, S103, and S105.

[0080] In step S101, a substrate is provided and a trench layer is formed on one side of the substrate;

[0081] In step S103, a barrier layer is formed on the side of the channel layer opposite to the substrate;

[0082] In step S105, a gate layer and a gate electrode are formed on the side of the barrier layer opposite to the substrate layer. The orthogonal projection of the gate electrode in the thickness direction of the semiconductor device falls into the surface of the gate layer on the side opposite to the substrate. In the thickness direction of the semiconductor device, the gate layer includes a first gate portion and a second gate portion, and the first gate portion is located on the side of the second gate portion opposite to the substrate. The ratio of the thickness of the first gate portion to the thickness of the gate layer is less than or equal to 0.15, and a stepped structure is formed around the first gate portion.

[0083] The following combination Figures 9 to 13 Taking the fabrication of semiconductor device 100 as an example, the fabrication method of the above-mentioned semiconductor device will be explained.

[0084] Combination Figure 9 As shown, in step S101, a substrate 10 is provided and a channel layer 20 is formed on one side of the substrate 10.

[0085] The channel layer 20 can be formed using epitaxial technologies such as metal-organic chemical vapor deposition, molecular beam epitaxy, or hydride vapor phase epitaxy.

[0086] Combination Figure 9 As shown, in step S103, a barrier layer 30 is formed on the side of the channel layer 20 away from the substrate 10.

[0087] The barrier layer 30 can be formed using epitaxial technologies such as metal-organic chemical vapor deposition or molecular beam epitaxy.

[0088] Combination Figures 9 to 13 As shown, in step S105, a gate layer 40 and a gate electrode 50 are formed on the side of the barrier layer 30 opposite to the substrate 10. The orthogonal projection of the gate electrode 50 in the thickness direction T of the semiconductor device falls within the surface of the gate layer 40 on the side opposite to the substrate 10. In the thickness direction T of the semiconductor device, the gate layer 40 includes a first gate portion 401 and a second gate portion 402, and the first gate portion 401 is located on the side of the second gate portion 402 opposite to the substrate 10. The ratio of the thickness of the first gate portion 401 to the thickness of the gate layer 40 is less than or equal to 0.15, and only the periphery of the first gate portion 401 in the gate layer 40 has a stepped structure.

[0089] The gate layer 40 and the gate electrode 50 can be formed by an etching process.

[0090] In some embodiments, the gate layer 40 includes an insertion layer 42 and a p-type GaN layer 41. The material of the insertion layer 42 is Al. 1-x GaxN (0≤x≤1).

[0091] Step S105, which forms a gate layer 40 on the side of the barrier layer 30 away from the substrate 10 and a gate electrode 50 on the side of the gate layer 40 away from the substrate 10, can be achieved through the following steps S1051, S1052, S1053 and S1054.

[0092] Combination Figure 9 and Figure 10 As shown, in step S1051, a P-type GaN material layer 4001, an insertion material layer 4002, and an electrode material layer 5001 are sequentially formed on the side of the barrier layer 30 opposite to the substrate 10 layer.

[0093] In step S1051, the P-type GaN material layer 4001 and the inserted material layer 4002 can be formed by epitaxial technologies such as metal-organic chemical vapor deposition and molecular beam epitaxy.

[0094] The electrode material layer 5001 can be formed using physical vapor deposition (PVD) or atomic layer deposition (ALD) processes.

[0095] Combination Figure 11 As shown, in step S1052, the electrode material layer 5001 and a portion of the insertion material layer 4002 are etched to form the intermediate electrode material layer 5002 and the intermediate insertion material layer 40020, respectively.

[0096] In step S1052, a dry etching method can be used. For example, a gas including SF6 and chlorine, or other chlorine-containing gases, can be used for etching.

[0097] Combination Figure 12 As shown, in step S1053, the intermediate insertion material layer 40020 and the P-type GaN material layer 4001 are etched to form the gate layer 40.

[0098] In step S1053, a spacer process can be used. In step S1053, a mask layer (not shown) can first be formed on the surface of the area that does not need etching, for example, a hard mask formed of SiO2 can be used. Then, dry etching is used to etch the periphery of the intermediate insertion material layer 40020 and the P-type GaN material layer 4001 to form a patterned gate layer 40. Subsequently, a wet etching process can be used to remove the mask layer. Taking a hard mask formed of SiO2 as an example, a hydrofluoric acid solution can be used to etch and remove the mask layer.

[0099] Combination Figure 13 As shown, in step S1054, the intermediate electrode material layer 5002 is etched to form the gate electrode 50.

[0100] In this step, the sidewalls of the intermediate electrode material layer 5002 can be etched so that the surface of part of the insertion layer 42 (i.e. forming the step top wall 4203) is exposed from the gate electrode 50.

[0101] In step S1054, a wet etching method can be used. For example, a solution containing hydrogen peroxide and sulfuric acid can be used for etching. Using a solution containing hydrogen peroxide and sulfuric acid for wet etching of the intermediate electrode material layer 5002 is beneficial for controlling the depth of inward etching of the sidewalls of the intermediate electrode material layer 5002.

[0102] In this application, the structural embodiments and method embodiments described can complement each other without conflict.

[0103] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0104] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0105] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A channel layer is located on one side of the substrate; A barrier layer is located on the side of the channel layer opposite to the substrate; A gate layer is located on the side of the barrier layer opposite to the substrate layer; A gate electrode is located on the side of the gate layer away from the substrate layer, and the orthogonal projection of the gate electrode in the thickness direction of the semiconductor device falls into the surface of the gate layer on the side away from the substrate. In the thickness direction of the semiconductor device, the gate layer includes a first gate portion and a second gate portion, and the first gate portion is located on the side of the second gate portion away from the substrate. The ratio of the thickness of the first gate portion to the thickness of the gate layer is less than or equal to 0.15, and a stepped structure is formed around the periphery of the first gate portion. The stepped structure includes a stepped sidewall and a stepped top wall and a stepped bottom wall that connect the stepped sidewall. The stepped top wall is connected to the top of the stepped sidewall, and the stepped bottom wall is connected to the bottom of the stepped sidewall. The gate electrode is disposed on the stepped top wall.

2. The semiconductor device as claimed in claim 1, characterized in that, The gate layer includes an insertion layer and a P-type GaN layer; the material of the insertion layer includes Al. 1-x Ga x N (0≤x≤1); the insertion layer is disposed between the gate electrode and the P-type GaN layer.

3. The semiconductor device as described in claim 2, characterized in that, The first gate portion includes only the insertion layer.

4. The semiconductor device as described in claim 2, characterized in that, The first gate portion includes the insertion layer and a portion of the thickness of the P-type GaN layer in contact with the insertion layer.

5. The semiconductor device as claimed in claim 1, characterized in that, The gate layer is a P-type GaN layer.

6. The semiconductor device as claimed in claim 1, characterized in that, The thickness of the first gate portion is less than or equal to 25 nm.

7. The semiconductor device as claimed in claim 1, characterized in that, The bottom wall of the step is a plane perpendicular to the thickness direction of the semiconductor device.

8. The semiconductor device as claimed in claim 7, characterized in that, From the sidewall of the step toward the outer edge of the gate layer, at least a portion of the bottom wall of the step is an inclined surface that approaches the substrate; the inclined surface is an inclined plane or an inclined curved surface.

9. The semiconductor device as claimed in claim 1, characterized in that, The gate electrode has an electrode top surface and an electrode bottom surface opposite each other in the thickness direction of the semiconductor device, and an electrode sidewall surface connecting the electrode top surface and the electrode bottom surface, the electrode sidewall surface being a concave curved surface.

10. The semiconductor device as claimed in claim 1, characterized in that, The gate electrode has an electrode top surface and an electrode bottom surface opposite each other in the thickness direction of the semiconductor device, and an electrode sidewall surface connecting the electrode top surface and the electrode bottom surface, wherein the distance between the electrode sidewall surface and the step sidewall surface is 10 nm - 100 nm.

11. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, and a trench layer is formed on one side of the substrate; A barrier layer is formed on the side of the channel layer opposite to the substrate; A gate layer and a gate electrode are formed on the side of the barrier layer opposite to the substrate layer. The orthogonal projection of the gate electrode in the thickness direction of the semiconductor device falls into the surface of the gate layer on the side opposite to the substrate. In the thickness direction of the semiconductor device, the gate layer includes a first gate portion and a second gate portion, and the first gate portion is located on the side of the second gate portion opposite to the substrate. The ratio of the thickness of the first gate portion to the thickness of the gate layer is less than or equal to 0.15, and a stepped structure is formed around the first gate portion. The stepped structure includes a step sidewall and a step top wall and a step bottom wall connecting the step sidewall. The step top wall is connected to the top of the step sidewall, and the step bottom wall is connected to the bottom of the step sidewall. The gate electrode is disposed on the step top wall.

12. The method for fabricating the semiconductor device as described in claim 11, characterized in that, The gate layer and the gate electrode are formed using an etching process.

13. The method for fabricating the semiconductor device as described in claim 11, characterized in that, The gate layer includes an insertion layer and a P-type GaN layer; the material of the insertion layer is Al. 1-x Ga x N (0≤x≤1); a gate layer and a gate electrode located on the side of the barrier layer opposite to the substrate layer are formed, including: A P-type GaN material layer, an insertion material layer, and an electrode material layer are sequentially formed on the side of the barrier layer opposite to the substrate layer. Etching the electrode material layer and a portion of the insertion material layer to form an intermediate electrode material layer and an intermediate insertion layer; The gate layer is formed by etching the intermediate insertion material layer and the P-type GaN material layer. The intermediate electrode material layer is etched to form the gate electrode.

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