Split gate mosfet with reduced on resistance and reduced gate-drain capacity

Abstract

The invention relates to a split gate MOSFET with reduced on resistance and reduced gate-drain capacity. An electronic device includes a semiconductor body; a trench in the semiconductor body; an insulating field plate region in each trench; a conductive gate region in each trench electrically insulated from the semiconductor body by the respective insulating field plate region; a field plate region in each trench; a gate interconnect within the semiconductor body, transverse to the trench, electrically insulated from the semiconductor body and electrically connected to the conductive gate regions to electrically interconnect the conductive gate regions to each other; and a body region.

Description

Split-gate MOSFET with reduced on-resistance and reduced gate-drain capacitance Technical Field

[0001] This disclosure relates to split-gate MOSFETs with reduced on-resistance and reduced gate-drain capacitance, and more particularly to an electronic device having a gate interconnect that increases the channel perimeter and conductive area, and has a conductive channel with locally selectively inactive characteristics. Furthermore, this disclosure relates to the fabrication process of the electronic device. Background Technology

[0002] MOSFET ("Metal-Oxide-Semiconductor Field-Effect Transistor") technology is now widely recognized as an excellent option for several applications, such as switches in power management circuits.

[0003] Vertically diffused MOSFETs (VDMOS) have seen significant commercial adoption over the past few decades due to their improved electrical performance. However, the high on-resistance of VDMOSFETs has long limited their current handling capabilities.

[0004] This problem has been overcome with "trench gate" MOSFETs. Due to their vertically oriented channels, these devices allow for reduced cell pitch without negatively impacting current diffusion. In particular, the introduction of devices using a field plate insulated from the gate electrode and connected to the source potential as an extension of the gate electrode achieves lateral depletion of the off-state drift region. Because the field plate is electrically insulated from the gate electrode, this structure is also known as a "shielded gate" or "split gate" structure.

[0005] Compared to previous MOSFETs, split-gate technology offers significant advantages, such as improved on-resistance relative to the active region extension and reduced gate-drain capacitance. In fact, the split-gate structure allows for the use of high doping concentrations, thereby significantly improving MOSFET performance.

[0006] As is well known, one of the main goals in developing split-gate power MOSFET devices is to reduce on-resistance.

[0007] This can be achieved in existing technologies by reducing the main resistance contribution and / or by increasing the ratio between the conductive area and the channel perimeter relative to the total device area.

[0008] However, since the basic cell in known technical solutions is strip-shaped, the main limitation to achieving these goals according to known technical solutions is reducing the size of the MOSFET's basic cell. This means that the dimensions of the diffusion process need to be adjusted and the lithography resolution needs to be increased to reduce the lateral dimension of the strip. Obviously, this means that significant additional costs and difficulties will be incurred during the manufacturing process.

[0009] Furthermore, another important issue is that as the channel perimeter and area increase, if the on-resistance decreases on the one hand, and the gate-drain capacitance increases on the other, i.e., the capacitance C... rss (or Miller capacity C) miller The gate charge Q increases, therefore the gate charge Q g This requires longer switching times, power and efficiency losses, and therefore affects the quality factor (FOM=R). sil Q g Or FOM=R on Q g This has a negative impact because of the larger gate charge Q. g This partially offsets the benefits of reducing on-resistance.

[0010] In other words, there is currently a trade-off between reducing on-resistance by increasing channel perimeter and reducing gate-drain capacitance. This trade-off is a design constraint that complicates the design and limits the final performance of the MOSFET. Summary of the Invention

[0011] Embodiments of this disclosure provide an electronic device and a manufacturing process for the electronic device that overcome at least some of the disadvantages of the prior art and provide a significant increase in conductive area without correspondingly increasing the channel perimeter and associated drain-gate capacitance. According to this disclosure, an electronic device and a manufacturing process for the electronic device are provided.

[0012] In one embodiment, an electronic device includes: a semiconductor body having a first conductivity type, having a first side and a second side opposite to each other along a first axis; a plurality of trenches extending from the first side toward the second side within the semiconductor body and terminating within the semiconductor body. The electronic device includes: a corresponding insulating field plate region in each of the trenches, covering the lower wall and sidewalls of the corresponding trench; and a corresponding conductive gate region in each of the trenches on the corresponding insulating field plate region, each conductive gate region being made of a conductive material and electrically insulated from the semiconductor body by the corresponding insulating field plate region. The electronic device further includes: a corresponding field plate region in each of the trenches, each field plate region being embedded in the corresponding insulating field plate region and electrically insulated from the corresponding conductive gate region and the semiconductor body by the corresponding insulating field plate region; and a plurality of gate interconnects extending laterally through the trenches from the first side toward the second side within the semiconductor body and terminating within the semiconductor body, the gate interconnects being made of a conductive material, electrically insulated from the semiconductor body, and electrically connected to the conductive gate regions to electrically interconnect the conductive gate regions with each other. The electronic device includes multiple body regions extending between trenches on a first side. Each body region has a second conductivity type opposite to a first conductivity type, is transverse to the gate interconnects and conductive gate regions, and is electrically insulated relative to the gate interconnects and conductive gate regions. A portion of the conductive gate regions and gate interconnects is part of a corresponding passive gate structure of the electronic device, configured to locally suppress the formation of conductive channels through the body regions. Other portions of the conductive gate regions and gate interconnects are part of a corresponding active gate structure of the electronic device, configured to locally allow the formation of conductive channels through the body regions.

[0013] In one embodiment, a process for manufacturing an electronic device includes: forming a plurality of trenches within a semiconductor body having a first side and a second side opposite to each other along a first axis, the trenches extending from the first side toward the second side and terminating within the semiconductor body, and forming a respective insulating field plate region in each of the trenches, covering the lower wall and sidewalls of the respective trench. The method includes forming a respective field plate region in each of the trenches, each field plate region being embedded within the respective insulating field plate region and electrically insulated from the semiconductor body by the respective insulating field plate region. The method includes forming a respective conductive gate region on the respective insulating field plate region, in each of the trenches, each conductive gate region being made of a conductive material and electrically insulated from the semiconductor body and the respective field plate region by the respective insulating field plate region. The method includes forming a plurality of gate interconnects extending laterally through the trenches from the first side toward the second side within the semiconductor body and terminating within the semiconductor body, the gate interconnects being made of a conductive material, electrically insulated from the semiconductor body, and electrically connected to the conductive gate regions to electrically interconnect the conductive gate regions with each other. The method includes forming a plurality of body regions extending between trenches on a first side, the body regions having a second conductivity type opposite to a first conductivity type, transverse to gate interconnects and conductive gate regions, and electrically insulated relative to the gate interconnects and conductive gate regions. Portions in the conductive gate regions and gate interconnects are part of corresponding passive gate structures of the electronic device, the passive gate structures being configured to locally suppress the formation of conductive channels through the body regions, and other portions in the conductive gate regions and gate interconnects are part of corresponding active gate structures of the electronic device, the active gate structures being configured to locally allow the formation of conductive channels through the body regions.

[0014] In one embodiment, an electronic device includes: a semiconductor body of a first conductivity type; a plurality of trenches extending within and terminating within the semiconductor body; and a plurality of insulating field plate regions, each insulating field plate region being located within a corresponding trench. The electronic device includes: a plurality of respective conductive gate regions, each conductive gate region being located within a corresponding trench; and a plurality of field plate regions, each located within a corresponding trench and electrically insulated from the respective conductive gate region and the semiconductor body via the respective insulating field plate regions. The electronic device includes a plurality of gate interconnects extending adjacent to the trenches within the semiconductor body, terminating within the semiconductor body, electrically insulated from the semiconductor body, and electrically interconnecting the conductive gate regions. The electronic device includes a plurality of body regions of a second conductivity type, extending laterally between the trenches and the gate interconnects and conductive gate regions within the body regions. Attached Figure Description

[0015] To better understand this disclosure, preferred embodiments will now be described by way of non-limiting example with reference to the accompanying drawings, in which:

[0016] Figure 1 shows a schematic perspective view along two different cross-sectional lines of an electronic device according to one embodiment;

[0017] Figures 2A and 2B show detailed cross-sectional views of the electronic device in Figure 1;

[0018] Figures 3A to 3C show top views of the electronic device of Figure 1 according to corresponding embodiments;

[0019] Figures 4A to 4M show schematic perspective views of two different cross-sectional lines along the steps of one embodiment of the manufacturing process of the electronic device in Figure 1;

[0020] Figures 5A to 5H show schematic perspective views of two different cross-sectional lines along the steps of different embodiments of the manufacturing process of the electronic device in Figure 1;

[0021] Figure 6 shows schematic perspective views along two different cross-sectional lines of the electronic device according to different embodiments; and

[0022] Figures 7A and 7B show detailed cross-sectional views of the electronic device in Figure 6.

[0023] In particular, these figures are illustrated with reference to a three-axis Cartesian system defined by mutually orthogonal X, Y, and Z axes.

[0024] In the following description, elements common to different embodiments are indicated by the same reference numerals. Detailed Implementation

[0025] Figure 1 shows an electronic device 10, specifically a power MOSFET. In particular, electronic device 10 is of the "split-gate" type, also known as the "shielded-gate" type. Electronic device 10 will be more simply referred to below as MOSFET 10.

[0026] MOSFET 10 is shown in Figure 1 in cross-sectional view along two different profile lines. Specifically, the right profile in Figure 1 is taken along profile line AA shown in Figure 3A, while the left profile in Figure 1 is taken along profile line BB shown in Figure 3A.

[0027] In detail, the MOSFET 10 includes a semiconductor body 12 having a first side and a second side (or upper side and lower side) 12a, 12b opposite to each other along the Z-axis direction and a first conductivity type (illustratively N in the following text).

[0028] On the first side 12a, the MOSFET 10 also includes multiple trenches 13 in the semiconductor body 12.

[0029] As shown in Figures 3A to 3C and better described below, in the top view (i.e., parallel to the XY plane defined by axes X and Y), the groove 13 has a closed polygonal shape (such as a hexagonal shape, a square shape, etc.) and is arranged in a matrix.

[0030] Referring again to Figure 1, the MOSFET 10 includes a corresponding oxide region (or insulating field plate region) 14 extending at the lower wall and sidewall of the trench 13 for each trench 13.

[0031] Each oxide region 14 has an upper surface, which in this embodiment is curved, specifically concave. Therefore, each oxide region 14 defines a concavity (also shown below by reference numeral 54, e.g., in Figure 54), the depth of which, measured along the Z-axis, is greater at the center than at the ends (in the top view). Specifically, the depth of the concavity in the oxide region 14 varies in a substantially continuous manner.

[0032] For each trench 13, the MOSFET 10 also includes a corresponding conductive gate region (or more simply, a gate region) 15 within the trench 13. Specifically, an oxide region 14 extends below and around the gate region 15 such that the gate region 15 is electrically insulated from the semiconductor body 12 through the oxide region 14.

[0033] The lower surface of the gate region 15 has a shape that is complementary to the upper surface of the oxide region 14.

[0034] In detail, in this embodiment, each gate region 15 has a depth measured along the Z-axis direction, which is greater at the center than at the ends. In other words, the gate region 15 has a first depth (or first thickness) P1 in its first region, which is radially inward in a top view, and a second depth (or second thickness) P2 in its second region, which is radially outward in a top view and surrounds the first radially inward region; the first depth P1 is greater than the second depth P2.

[0035] For purely illustrative and non-limiting purposes, the first depth P1 is between about 0.2 µm and about 0.4 µm, and is, for example, equal to about 0.3 µm, and the second depth P2 is between about 0.7 µm and about 0.9 µm, and is, for example, equal to about 0.8 µm.

[0036] In other words, in the embodiment of FIG1, the lower surface of the gate region 15 is curved, specifically convex, to be accommodated in the concavity of the corresponding oxide region 14, thereby protruding into the oxide region 14 at the first radially inner region. More specifically, the depth of the bottom surface of the gate region 15 varies in a substantially continuous manner, increasing from the second radially outer region toward the first radially inner region to accommodate the concavity of the oxide region 14.

[0037] For each trench 13, the MOSFET 10 also includes a corresponding field plate region 16 made of a conductive material, such as N-doped polysilicon. The field plate region (more simply referred to as the field plate below) 16 extends in the corresponding trench 13 and is buried within an oxide region 14 to be electrically insulated from the conductive gate region 15 by a portion of the oxide region 14.

[0038] In detail, the first portion 16a of the field plate 16 extends below the conductive gate region 15 (particularly at the first radial center region of the conductive gate region 15) without making electrical or physical contact with the latter. Furthermore, the second portion 16b of the field plate 16, continuous with the first portion 16a and stacked on top of the first portion 16a along the Z-axis, extends within the conductive gate region 15 to traverse the conductive gate region 15 along the Z-axis and is physically and electrically separated from the conductive gate region 15 by a portion of the oxide region 14.

[0039] The field plate 16 is used to reduce the electric field in the semiconductor body 12 near the trench 13 and reduce parasitic capacitance.

[0040] In this embodiment, each component of the conductive gate region 15 and the corresponding oxide region 14 (specifically, the portion of the oxide region 14 indicated by reference numeral 14b below) forms a corresponding active gate structure 22' of the MOSFET 10, through which no conductive channel in use is generated, as better described below with reference to Figures 2A and 2B. Since the field plate 16 is electrically insulated from the conductive gate region 15, the active gate structure 22' of the MOSFET 10 is referred to as a "shielded gate" or "split gate" structure.

[0041] For each trench 13, the MOSFET 10 also includes a corresponding upper oxide region 18 extending over the trench 13 and over the conductive gate region 15. In particular, the upper oxide region 18 is not vertically stacked with the second portion 16b of the field plate 16 (i.e., aligned along the Z-axis); in other words, the upper oxide region 18 has a through opening 18' that runs through it along the Z-axis and is vertically stacked on the second portion 16b of the field plate 16.

[0042] For each trench 13, the MOSFET 10 also includes a corresponding plurality of body regions 17 having a second conductivity type (illustratively P-type here). In particular, the number of body regions 17 for each trench 13 is equal to the number of sides of the closed polygonal shape of the trench 13 in a top view, such that each body region 17 is associated with a corresponding side of the trench 13, as better described below.

[0043] Body regions 17 are housed within semiconductor bodies 12, transverse to the corresponding trenches 13, and thus transverse to the radially outer regions of the corresponding gate regions 15, and extend around the trenches 13 to surround them without maintaining continuity, and face the first side 12a of the semiconductor body 12. For example, in the cross-section of FIG1, two body regions 17 are shown adjacent to the opposite (along the Y-axis) sides of the trenches 13. As better shown in FIG3A, in the top view, each body region 17 is thus inserted between the two nearest trenches 13 in the matrix arrangement at the level of the first side 12a of the semiconductor body 12.

[0044] In detail, a portion of the oxide region 14 extends between the body region 17 and the corresponding conductive gate region 15, such that the conductive gate region 15 is electrically insulated from the corresponding body region 17.

[0045] More specifically, each body region 17 has a lower surface that contacts the semiconductor body 12, the depth of which, measured along the Z-axis, is greater than the second depth P2 of the adjacent second radially outer region of the gate region 15, as better illustrated in FIG2A.

[0046] For each trench 13, the MOSFET 10 also includes a corresponding plurality of source regions 20 having a first conductivity type (illustratively N-type here). In particular, the number of source regions 20 for each trench 13 is equal to the number of sides of the closed polygonal shape of the trench 13 in a top view, such that each source region 20 is associated with a corresponding side of the trench 13, as better described below.

[0047] Each source region 20 extends over a corresponding body region 17, located at the radially outer portion of the latter. In other words, each source region 20 has a through opening 20' that traverses the source region 20 along the Z-axis and is vertically stacked on the radially inner (or central) portion of the corresponding body region 17 to expose it. More specifically, in the delivery diagram, the source region 20 is annular in type and is vertically stacked on the radially outer portion of the corresponding body region 17, while the radially inner portion of the corresponding body region 17 is exposed through the through opening 20'.

[0048] Therefore, the source region 20 is accommodated in the semiconductor body 12, transverse to the corresponding trench 13, and thus extends around the trench 13 to surround the trench 13 without maintaining continuity, and is located on the first side 12a of the semiconductor body 12. For example, in the cross-section of FIG1, two source regions 20 are shown for each trench 13, adjacent to the opposite (along the Y-axis) sides of the trench 13. As better shown in FIG3A, therefore, in the top view, at the level of the first side 12a of the semiconductor body 12, each source region 20 is inserted between the two trenches 13 that are closest to each other in the matrix arrangement.

[0049] In detail, the portion of oxide region 14 extending between body region 17 and corresponding conductive gate region 15 also extends between source region 20 and corresponding conductive gate region 15, such that conductive gate region 15 is electrically insulated from corresponding source region 20.

[0050] The MOSFET 10 also includes a source metallization portion 24 extending over the upper oxide region 18, over the body region 17 exposed by the through-opening 20' of the source region 20, and over a second portion 16b of the field plate 16 exposed by the through-opening 18' of the upper oxide region 8. More specifically, the source metallization portion 24 includes a body 24a extending over the upper oxide region 18, a corresponding first metallization portion 24b extending over the corresponding body region 17 exposed by the through-opening 20' of the source region 20, and a corresponding second metallization portion 24c extending over the second portion 16b of the field plate 16 exposed by the through-opening 18' of the upper oxide region 18; in particular, the body 24a extends continuously with the first metallization portion 24b and the second metallization portion 24c. Therefore, the source metallization portion 24 is in direct electrical contact with the body region 17, the source region 20, and the field plate 16.

[0051] In use, the source metallization section 24 operates as a source electrode and can be biased to the source voltage V. S (For example, ground voltage), the source voltage can be used to bias the body region 17, the source region 20 and the field plate 16.

[0052] In addition, the MOSFET 10 also includes a drain metallization 26, which extends in contact with the semiconductor body 12 on the second side 12b.

[0053] In use, the drain metallization section 26 operates as the drain electrode and can be biased to the drain voltage V. D The semiconductor body 12 can be biased using this drain voltage.

[0054] In addition, the MOSFET 10 also includes a gate metallization that extends in contact with the gate region 15, as not shown.

[0055] In use, the gate metallization operates as the gate electrode and can be biased to the gate voltage V. G The gate region 15 can be biased using this gate voltage.

[0056] In detail, Figure 1 shows the active region 11 of the MOSFET 10, which comprises multiple cells, each defined by a corresponding trench 13. Outside the active region 11, i.e., beyond the edge termination region (not shown as is known), there are side surfaces of the semiconductor body, extending substantially orthogonally to the first side, for example. These side surfaces are formed after a dicing step of the SiC wafer, in which multiple MOSFETs 10 are formed. The dicing step serves to separate the MOSFET 10 from another MOSFET 10 on the same wafer. The dicing occurs at a scribe line (not shown) on the SiC wafer from which the MOSFETs 10 are obtained. This scribe line surrounds the active region 11 at a distance in the XY plane and extends, for example, from the outside to a guard ring (not shown), which surrounds the active region 11 in the top view.

[0057] Referring to Figure 1, the MOSFET 10 also includes a gate interconnect 28 that extends between the gate regions 15 and is in physical and electrical contact with the gate regions 15 so that they are in electrical contact with each other.

[0058] In this way, the gate metallization can be made to directly contact only a portion of the gate region 15 (e.g., those portions placed on the outer periphery of the active region 11 of the MOSFET 10 in the top view), while still allowing all gate regions 15 to be biased via the gate interconnect 28.

[0059] Specifically, gate interconnects 28 connect gate regions 15 arranged side by side, and in detail, in the matrix arrangement in the top view, gate regions 15 are closest to each other.

[0060] In detail, the MOSFET 10 has interconnect trenches 31 that extend in the semiconductor body 12 from a first side 12a toward a second side 12b without reaching the latter. The interconnect trenches 31 communicate with trenches 13, that is, they are open in the trenches 13 to define an interconnect network that joins the trenches 13 together at the level of the first side 12a.

[0061] The shape of the interconnecting trench 31 in the top view is shown and discussed below with reference to Figures 2A to 2B and 3A to 3C.

[0062] Gate interconnects 28 are housed in interconnect trenches 31 and are electrically insulated from semiconductor bodies 12, source regions 20, and body regions 17 by insulating interconnect portions 29 of insulating material, which also extend within interconnect trenches 31. Specifically, each insulating interconnect portion 29 extends laterally below the corresponding gate interconnect 28 to be inserted between the gate interconnect 28 and the semiconductor body 12. In detail, the insulating interconnect portions 29 extend continuously with the oxide regions 14 to which they are connected.

[0063] Therefore, each gate interconnect 28 together with the corresponding insulating interconnect portion 29 forms a corresponding insulating interconnect structure 30 that is accommodated in the corresponding interconnect trench 31.

[0064] As shown in Figure 1, the gate interconnect 28 extends on the first side 12a of the semiconductor body 12, particularly flush with the gate region 15.

[0065] The gate interconnects 28 are continuous with the gate regions 15 to which they are coupled, and in particular, they engage with a second radially outer region of the gate regions 15. More specifically, the gate interconnects 28 are made of the same material as the gate regions 15 to extend in continuity relative to the latter.

[0066] Specifically, in this embodiment, the gate interconnect 28 has a substantially constant depth (or thickness) and is greater than the second depth P2 of the radially outer region of the gate region 15. For example, the gate interconnect 28 may have a thickness measured along the Z-axis direction that is approximately equal to the thickness of the gate region 15 in its first radially inner region.

[0067] Therefore, and as can be seen in Figure 1, oxide region 14 protrudes at the point where gate region 15 and gate interconnect 28 are joined within the assembly formed by gate region 15 and gate interconnect 28. However, this protrusion of oxide region 14 does not interrupt the physical and electrical contact between gate region 15 and gate interconnect 28.

[0068] For purely illustrative and non-limiting purposes, the thickness of the gate interconnect 28 may be between about 0.55 µm and about 0.65 µm, and the width, measured in the XY plane along a direction orthogonal to the main extension of the gate interconnect 28, is between about 0.15 µm and about 0.25 µm. The length of the gate interconnect 28, measured in the XY plane along the main extension of the gate interconnect 28, depends, in a manner that is self-evident, on the mutual distance between the trenches 13, as can be better envisioned by reference to Figures 3A to 3C below.

[0069] Similarly, and again for purely illustrative and non-limiting purposes, the thickness of the interconnect trench 31 along the Z-axis may be between approximately 0.65 µm and approximately 0.75 µm, and the width measured in the XY plane along a direction orthogonal to the main extension of the interconnect trench 31 may be between approximately 0.25 µm and approximately 0.35 µm (in other words, the oxide thickness of the insulating interconnect portion 29 is approximately 50 nm). The length of the interconnect trench 31, measured in the XY plane along the main extension of the interconnect trench 31, depends in a manner that is inherently obvious on its own on the relative distances between the trenches 13, as can be better envisioned by reference to Figures 3A to 3C below.

[0070] In this embodiment, each component of the gate interconnect 28 and the insulating interconnect portion 29 also defines a corresponding active gate structure 22'' of the MOSFET 10, through which an active gate structure generates a conductive channel in use, as better illustrated with reference to Figures 2A and 2B.

[0071] In detail, Figure 2A shows an example of an active gate structure 22'.

[0072] As mentioned in Figure 2A, the second radially outer region of the gate region 15 does not reach a depth flush with the interface between the body region 17 and the semiconductor body 12 along the Z-axis. In fact, the gate region 15 only flush with this interface in its first radially inner region; however, the width of the oxide region 14 separating the gate region 15 from this interface is significantly greater than the width of the oxide region extending between the second radially outer region and the body region 17. Specifically, the width of the oxide region 14 separating the gate region 15 from this interface locally prevents electrical coupling between the gate region 15 and the body region 17, thereby locally preventing the formation of conductive channels in the non-active gate structure 22'.

[0073] Conversely, Figure 2B shows an example of an active gate structure 22''.

[0074] As mentioned in Figure 2B, the depth of the gate interconnect 28 is greater than the depth of the interface between the body region 17 and the semiconductor body 12. In other words, the gate interconnect 28 extends laterally to the lower portion of the body region 17 and the semiconductor body 12 that contacts the body region 17, and the width of the inserted oxide is substantially uniform and small enough to locally allow electrical coupling between the gate interconnect 28 and the body region 17, thereby locally ensuring the formation of a conductive channel in the active gate structure 22''. In fact, the insulating interconnect portion 29 inserted between the gate interconnect 28 and the lower portion of the body region 17 and the semiconductor body 12 has a width, for example, measured along the X-axis direction, which is substantially constant and between about 440 nm and about 500 nm, thus allowing, for example, the local formation of a conductive channel in use.

[0075] Typically, in this embodiment, the gate region 15 has a first minimum distance D1 relative to the interface between the body region 17 and the semiconductor body 12, while the gate interconnect 28 has a second minimum distance D2 relative to the interface between the body region 17 and the semiconductor body 12. Specifically, the first minimum distance D1 is the minimum distance existing between the gate region 15 and the interface between the body region 17 and the semiconductor body 12 (specifically measured here between the junction of the interface and the side and bottom surfaces of the gate region 15), and the second minimum distance D2 is the minimum distance existing between the gate interconnect 28 and the interface between the body region 17 and the semiconductor body 12.

[0076] The first minimum distance D1 is greater than the second minimum distance D2: Specifically, the first minimum distance D1 is at least 50% larger than the second minimum distance D2 (i.e., if D2 equals K, D1 equals at least 1.5K), for example, it is 60% to 70% larger than the second minimum distance D2. In detail, the values ​​of the minimum distances D1 and D2 are chosen such that, while the second minimum distance D2, for example, allows for the local formation of conductive channels, the first minimum distance D1, for example, inhibits the local formation of conductive channels.

[0077] In the embodiment of FIG1, this relationship between the minimum distances D1 and D2 is due to the fact that the lower surface of the gate interconnect 28 has a depth measured relative to the first side 12a, which is greater than a similar depth of the junction of the gate region 15 between the side surface and the lower surface of the gate region 15 (corresponding here to the second depth P2) (also indicated by reference numeral 15' in FIG2A). This, together with the convexity of the lower surface of the gate region 15, results in an oxide extension between the interface of the gate region 15 and the body region 17 and the semiconductor body 12 being greater than the oxide extension between the gate interconnect 28 and the interface of the body region 17 and the semiconductor body 12.

[0078] The specific values ​​of the first minimum distance D1 and the second minimum distance D2 obviously depend on the design choices made, such as the materials used and manufacturing process details. However, for illustrative and non-limiting purposes, the first minimum distance D1 can be equal to about 80 nm, and the second minimum distance D2 can be equal to about 50 nm.

[0079] Therefore, the simultaneous presence of the non-active gate structure 22' and the active gate structure 22'' allows for a smaller channel perimeter, thereby reducing the overall gate-drain capacity, and at the same time, due to the cell structure, allows for a larger conductive area than known (especially larger than known structures with strip gates), and such as a significant reduction in the on-resistance of MOSFET 10, all of which contribute to the quality factor.

[0080] The shape and arrangement of the gate interconnect 28 can vary, as shown in Figures 3A to 3C.

[0081] In detail, Figures 3A to 3C show top views of the corresponding embodiments of the MOSFET 10, which are considered to be at the layer of the first side 12a of the semiconductor body 12.

[0082] In the embodiment of FIG3A, the trench 13, as well as the gate region 15 and the gate structure 22, generally have a hexagonal shape parallel to the XY plane.

[0083] In Figure 3A, each vertex of each gate region 15 is connected to a corresponding gate interconnect 28, such that each gate interconnect 28 connects the three gate regions 15 to each other, and in the view of Figure 3A, these gate regions 15 are arranged in a triangle.

[0084] In detail, each gate interconnect 28 has three arms, each arm having a corresponding first end and a second end opposite to each other. In each gate interconnect 28, the first ends of the three arms are joined together to form a joint portion of the gate interconnect 28. In a top view, the three arms extend radially from the joint portion and are spaced apart from each other at equal angles. The second end of each arm is connected to a corresponding vertex of one of the three gate regions 15, which, in a top view, surrounds the gate interconnect 28 under consideration.

[0085] In this way, each mesa region (defined in the top view of FIG3A by the corresponding source region 20, which also has a hexagonal shape in the view of FIG3A) has: two sides opposite to each other, which contact the two sides of the two corresponding gate structures 22 that are first adjacent in the matrix arrangement; and four sides that contact the two corresponding insulating interconnect structures 30 in a two-to-two manner (specifically, the first pair of adjacent sides that contact the two corresponding arms of the insulating interconnect structure 30 and the second pair of adjacent sides that are opposite to the first pair of sides and contact the two corresponding arms of the other insulating interconnect structure 30).

[0086] In other words, in Figure 3A, the gate interconnects 28 are not directly coupled to each other, but are coupled to each other through the gate regions 15 to define the interconnect network of the gate regions 15 and the gate interconnects 28.

[0087] In the embodiment of FIG3B, the trench 13, as well as the gate region 15 and the gate structure 22, generally have a square shape parallel to the XY plane and are arranged to be parallel to both the X-axis and the Y-axis and aligned with each other.

[0088] In Figure 3B, each vertex of each gate region 15 is connected to a corresponding gate interconnect 28. The gate interconnects 28 are grouped into four groups, and each group defines a corresponding square annular closed path that connects the four corresponding gate regions 15, which are arranged in a 2x2 configuration in the matrix under consideration.

[0089] In detail, each group of gate interconnects 28 includes two gate interconnects 28 having a main extension along the X-axis and two gate interconnects 28 having a main extension along the Y-axis. In each group, the ends of the gate interconnects 28 are engaged with each other by alternating horizontal gate interconnects 28 and vertical gate interconnects 28 to define a square annular closed path. For each group, four corresponding gate regions 15 are respectively coupled to the corresponding vertices of the gate interconnect group 28.

[0090] In other words, in Figure 3B, the different groups of gate interconnects 28 are not directly coupled to each other, but are coupled to each other through gate regions 15 to define the interconnect network of gate regions 15 and gate interconnects 28.

[0091] In the embodiment of FIG3C, the trench 13, as well as the gate region 15 and gate structure 22, generally have a square shape parallel to the XY plane and are arranged such that one axis parallel to the XY plane (illustratively parallel to the X-axis here) is aligned with each other and the other axis parallel to the XY plane is alternately aligned with each other (illustratively parallel to the Y-axis here). In other words, the gate region 15 has a checkerboard arrangement in the top view.

[0092] In Figure 3C, each vertex of each gate region 15 is connected to a corresponding gate interconnect 28, and the gate interconnects 28 are connected to each other in a manner that forms a serpentine path (more specifically, a square zigzag path).

[0093] Each serpentine path has a main extension parallel to the X-axis and extends parallel to the Y-axis between two corresponding rows of gate regions 15 so that the two rows of gate regions 15 are electrically in contact with each other, specifically, so that they are electrically in contact one after another along the serpentine path.

[0094] Specifically, in each serpentine path, the gate interconnect 28 includes a gate interconnect 28 having a main extension along the X-axis direction and a gate interconnect 28 having a main extension along the Y-axis direction, which alternate with each other in a manner that defines this square serpentine path. Specifically, for each serpentine path, the ends of the gate interconnects 28 that are continuous with each other are joined and coupled to the apex of the corresponding gate region 15.

[0095] In other words, in Figure 3C, gate interconnects 28 along the same serpentine path are directly coupled to each other, while gate interconnects 28 along different serpentine paths are not directly coupled to each other, but are coupled to each other through gate regions 15, thereby defining the interconnect network of gate regions 15 and gate interconnects 28.

[0096] Based on what has been described so far and returning to Figure 1, it is to be understood that each oxide region 14 includes a body 14a, a first oxide portion 14b, and a second oxide portion 14c. The body 14a extends below the corresponding gate region 15 and around the corresponding field plate 16. The first oxide portion 14b extends laterally and around the corresponding gate region 15 (particularly between the gate region 15 and the semiconductor body 12 and body region 17 and source region 20). The second oxide portion 14c extends laterally and is located inside the corresponding gate region 15 (particularly between the gate region 15 and the second portion 16b of the corresponding field plate 16 and the corresponding second metallized portion 24c of the source metallization portion 24). In particular, in each oxide region 14, the corresponding body 14a, the corresponding first oxide portion 14b, and the corresponding second oxide portion 14c extend continuously to each other.

[0097] Furthermore, the insulated interconnect portion 29 extends laterally below the gate interconnect 28, insulating the gate interconnect 28 from the semiconductor body 12, the source region 20, and the body region 17, while allowing it to make electrical contact with the gate region 15. In particular, the insulated interconnect portion 29 extends continuously from the oxide region 14.

[0098] Clearly, in use, MOSFET 10 forms a vertical conductive channel at the interface between body region 17 and gate interconnect 28, along which charge carriers move. Compared to known solutions, this increases the overall channel perimeter, thus significantly reducing the on-resistance of MOSFET 10, as discussed in more detail below.

[0099] Figures 4A to 4M illustrate embodiments of the process used to manufacture the MOSFET 10 of Figure 1.

[0100] In Figure 4A, a semiconductor substrate is provided on which an optional epitaxial layer is grown. The substrate and the epitaxial layer together form a semiconductor body 12. The substrate and the epitaxial layer are, for example, made of silicon with N-type doping.

[0101] Then, as shown in Figure 4B, the trench 13 is formed by etching the semiconductor body 12 from the upper side 12a. The etching is performed using known techniques such as RIE (Reactive Ion Etching) or DRIE (Deep Reactive Ion Etching). In the figures, the trench 13 has vertical sidewalls; depending on the process used to fabricate the trench, they may also have sloping sidewalls, such as a truncated V-shape or a truncated inverted pyramid shape in the side view. Similarly, the teachings of this disclosure also apply to cases where the sidewalls of the trench 13 are not perfectly parallel to the Z-axis.

[0102] Then, as shown in Figure 4C, the trench 13 portion is filled with an insulating electrical material to form an insulating fill region 51, which is intended to form the body 14a of the oxide region 14. For example, in the case where the semiconductor body 12 is silicon, this step is performed by growing or depositing silicon oxide (SiO2); another insulating material can be grown or deposited based on the material of the semiconductor body 12.

[0103] Then, as shown in FIG. 4D, the step of filling trench 13 with a conductive material is performed to form a conductive region 52 in trench 13 and on semiconductor body 12. The conductive material is, for example, N-doped polysilicon, and completely fills trench 13. The conductive region 52 is intended to form field plate 16.

[0104] Then, in FIG4E, a step for removing a selective portion of the conductive region 52 is performed above the upper side 12a of the semiconductor body 12, leaving the conductive region 52 within the trench 13.

[0105] This step can be performed using CMP (chemical mechanical polishing) technology, followed by an etching step to partially etch the conductive regions 52 within the trenches 13. The conductive regions 52 are then recessed in each trench 13 until they are located below the upper side 12a. For example, the recesses of the conductive regions 52 in the trenches 13 can have a depth between approximately 50 nm and approximately 150 nm, measured from the upper side 12a.

[0106] Then, in Figure 4F, the insulating fill region 51 is partially etched on the upper side 12a to form a recess 54 in each trench 13. This recess 54 corresponds to the concavity in the oxide region 14 described earlier, so its details will not be described here.

[0107] The etching of the material toward the insulating filling region 51 is selective, while the material of the conductive region 52 is retained in the trench 13. The portion of the insulating filling region 51 retained after this etching forms the body 14a of the oxide region 14.

[0108] Specifically, the etching exposes a portion of the sidewall of the trench 13 between the upper side 12a of the semiconductor body 12 and the upper side of the body 14a of the oxide region 14. More specifically, the sidewall of the trench 13 is exposed to a depth of approximately 0.3 µm along the Z-axis direction and measured starting from the upper side 12a.

[0109] Then, as shown in FIG. 4G, a mask 55 is formed on the upper side 12a of the semiconductor body 12. For example, a polymer material mask 55 covers the trench 13 and the region of the upper side 12a of the semiconductor body 12 that is not intended to accommodate the gate interconnect 28. Furthermore, the mask 55 has an opening 55' that traverses the mask 55 and exposes the region of the upper side 12a of the semiconductor body 12 intended to accommodate the gate interconnect 28. In other words, the opening 55' is vertically aligned relative to the location where the gate interconnect 28 is intended to be formed; therefore, the shape and arrangement of the opening 55' are exactly similar to those described previously with reference to the gate interconnect 28.

[0110] Then, as shown in FIG. 4H, an etching step is performed to remove selective portions of the semiconductor body 12, starting from the upper side 12a. This etching step is performed through a mask 55, and interconnect trenches 31 extending from the upper side 12a into the semiconductor body 12 are formed in the area exposed by the mask 55. Therefore, the interconnect trenches 31 are vertically aligned with the opening 55', and thus have a shape and arrangement exactly similar to the opening 55'. In detail, the ends of the interconnect trenches 31 face the trenches 13 to form an interconnect network connecting the trenches 13 to each other.

[0111] Etching is interrupted when the depth of the interconnect trench 31 relative to the first side 12a is greater than the depth at which the interface between the body region 17 and the semiconductor body 12 will subsequently be located. For example, etching is interrupted when the depth of the interconnect trench 31 relative to the first side 12a is approximately 0.6 µm. In this way, a protrusion of the previously described oxide region 14 is formed, which will protrude in the assembly formed by the gate region 15 and the gate interconnect 28 at the point where the gate region 15 and the gate interconnect 28 will join.

[0112] Then, as shown in Figure 4I, an oxidation step (e.g., exposing the wafer to an O2 environment) is performed to form an insulating layer 57 on the exposed surface of the semiconductor material.

[0113] This oxidation step allows the portion of the conductive region 52 that protrudes from and is therefore unprotected by the insulating fill region 51 in the trench 13 to be oxidized. This step is self-limiting and allows for the formation of embedded conductive regions in each trench 13. Each of these embedded conductive regions forms one of the field plates 16 discussed previously. Specifically, for each trench 13, the portion of the conductive region 52 protected by the insulating fill region 51 forms a first portion 16a of the field plate 16, while the portion of the conductive region 52 that protrudes from the insulating fill region 51 and remains after oxidation forms a second portion 16b of the field plate 16. Furthermore, for each trench 13, the portion of the conductive region 52 that protrudes from the insulating fill region 51 and is oxidized is intended to form a second oxide portion 14c.

[0114] This same oxidation step also results in the oxidation of the semiconductor material in the interconnect trench 31 and the remaining exposed portion of the semiconductor material on the upper side 12a of the semiconductor body 12, specifically, the oxidation of the semiconductor material on the exposed areas of the sidewalls of the trench 13. In particular, the oxidized regions of the interconnect trench 31 form the previously described insulating interconnect portion 29, while the oxidized regions of the sidewalls of the trench 13 form the previously described first oxide portion 14b.

[0115] Then, as shown in FIG4J, the steps of forming gate region 15 and gate interconnect 28 are performed. Gate region 15 is formed by depositing a conductive material (e.g., n-doped polysilicon) in recess 54, while gate interconnect 28 is formed by depositing the same conductive material (e.g., n-doped polysilicon) in interconnect trench 31.

[0116] Then, in Figure 4K, the bulk region 17 and the source region 20 are formed by implanting known P-type and N-type dopants, respectively, into the semiconductor region between the trenches 13.

[0117] Then, in Figure 4L, an upper oxide region 18 is formed on the gate region 15 and the gate interconnect 28.

[0118] In detail, firstly, for example, an upper oxide layer is formed by deposition to uniformly cover the gate region 15, gate interconnect 28, source region 20, and field plate 16. Then, the upper oxide layer is etched between trenches 13 to form a contact opening 58 in which a first metallization portion 24b will extend, and extends over the field plate 16 to form a through opening 18' in which a second metallization portion 24c will extend. Furthermore, referring again to FIG. 4L, the through opening 20' is also formed, exposing a radially inner portion of the body region 17; this is achieved by further etching toward a semiconductor material that selectively etches the upper oxide layer. Specifically, the contact opening 58 is stacked on the through opening 20'. Furthermore, the through opening 18' exposes the upper surface of the second portion 16b of the field plate 16.

[0119] Then, as shown in FIG4M, the source metallization portion 24 is formed, for example, by depositing a conductive material. Specifically, a conductive material layer is uniformly deposited on the upper oxide region 18 to form a body 24a, a first metallization portion 24b in the contact opening 58, and a second metallization portion 24c in the through opening 18'. Thus, the first metallization portion 24b contacts the body region 17 and the source region 20, while the second metallization portion 24c contacts the field plate 16.

[0120] Other steps may be performed to complete the fabrication of MOSFET 10, which are not part of this disclosure and therefore will not be described further.

[0121] Figures 5A to 5H illustrate different embodiments of the process used to manufacture the MOSFET 10 of Figure 1.

[0122] In particular, in this embodiment, the manufacturing process initially includes the same steps previously described with reference to Figures 4A to 4F, and therefore will not be described in detail here.

[0123] Then, in FIG5A, the semiconductor body 12 has a trench 13, the trench 13 having recessed portions therein of an insulating filling region 51 and a conductive region 52, and a recess 54 is formed in the recessed portion of the insulating filling region 51.

[0124] Then, as shown in FIG5B, a first intermediate insulating layer 70 is formed, which covers the recessed portions of the insulating filling region 51 and the conductive region 52, as well as the exposed regions of the semiconductor body 12.

[0125] For example, this is achieved by depositing an oxide material such as TEOS with a thickness of approximately 100 nm.

[0126] Then, in Figures 5C and 5D, the formation of the interconnect trench 31 is similar to that previously described with reference to Figures 4G and 4H. Therefore, it is not described in detail again except that the formation of the interconnect trench 31 is performed by a series of etchings through the opening 55' of the mask 55, specifically by a first etching (Figure 5C) that selectively removes a portion of the first intermediate insulating layer 70 exposed by the mask 55 and a second etching (Figure 5D) that removes the bottom layer portion of the semiconductor body 12.

[0127] Then, in FIG. 5E, a portion of the first intermediate insulating layer 70 is selectively removed, leaving the vertically extending portion of the latter (i.e., along the vertically arranged surface). Specifically, the portions of the intermediate insulating layer 70 extending above the upper side 12a of the semiconductor body 12, the upper end of the recessed portion of the conductive region 52, and the recessed portion of the insulating filling region 51 are removed, while the portions of the first intermediate insulating layer 70 extending on the sidewalls of the recessed portion of the conductive region 52 and the sidewalls of the trench 13 are retained.

[0128] This is accomplished by anisotropic etching (specifically, dry etching), which removes the horizontally extending portion of the first intermediate insulating layer 70 while maintaining the vertically extending remaining portion.

[0129] Then, as shown in FIG5F, a second intermediate insulating layer 72 is formed, which uniformly covers the recessed portion of the insulating filling region 51, the exposed region of the semiconductor body 12, the recessed portion of the conductive region 52, and the remaining portion of the first intermediate insulating layer 70.

[0130] For example, this occurs through an oxidation step using a sacrificial oxide with a thickness of, for example, about 55 nm.

[0131] Then, in Figure 5G, the oxide portion is selectively etched to reduce its overall thickness. Specifically, etching (specifically isotropic) is performed to reduce the thickness of the second intermediate insulating layer 72 until the oxide barrier inserted between the recess 54 and the interconnect trench 31 is removed, allowing direct fluid communication and subsequently enabling electrical connection between the conductive gate region 15 and the gate interconnect 28. For example, the etching in Figure 5G removes approximately 65 nm of oxide thickness: since the etching acts simultaneously on both sides of the oxide barrier inserted between the recess 54 and the interconnect trench 31 (i.e., the recess 54 side and the interconnect trench 31 side), the barrier is completely removed.

[0132] Then, in FIG5H, an oxidation step is performed (e.g., exposing the wafer to an O2 environment) to form an insulating layer 57 on the exposed surface of the semiconductor material, similar to that previously described with reference to FIG4I.

[0133] The following steps are exactly the same as those described previously with reference to Figures 4J to 4M, and therefore will not be described in detail.

[0134] Other steps may be performed to complete the fabrication of MOSFET 10, which are not part of this disclosure and therefore will not be described further.

[0135] In detail, compared with the technical solutions of Figures 4A to 4M, the steps of Figures 5B to 5H allow for more precise control of the insulation of the gate region 15 relative to the source metallization 24 at the point where the source metallization 24 contacts the field plate 16.

[0136] More specifically, through these steps, the second oxide portion 14c, having an annular shape and surrounding the corresponding second metallized portion 24c, has a width orthogonal to the Z-axis that is greater than a minimum width equal to or greater than about 50 nm (in particular equal to about 100 nm).

[0137] Furthermore, the thicker oxide portions 14b and 14c result in greater insulation robustness and lower gate-source capacitance C. gs This translates to a lower input capacitance C. i It also produces higher efficiency and lower power loss during switching.

[0138] The advantages it provides become apparent from an examination of the characteristics of this disclosure made in accordance with this disclosure.

[0139] In particular, the split-gate MOSFET 10 allows for reduced on-resistance without adjusting the size of the diffusion process or increasing the lithography resolution, thus saving costs and difficulties during the manufacturing process. Specifically, this is due to the significant increase in conductive area (e.g., an increase of approximately 60%) achieved by using a cell-shaped trench 13 instead of a strip-shaped one, while simultaneously avoiding the need to increase the gate-drain capacitance by using the gate interconnect 28 as an active channel, thereby maximizing the quality factor gain.

[0140] Finally, it will be apparent that modifications and variations may be made to this disclosure as described and illustrated herein without departing from the scope of this disclosure, as defined in the appended claims.

[0141] For example, the different embodiments described can be combined with each other to provide other technical solutions.

[0142] Furthermore, this technical solution can be applied to any type of trench gate vertical conductive device, such as, but not limited to, VDMOS transistors or trench-based power MOSFET devices.

[0143] In addition, other shapes and arrangements can be used as alternatives to those illustratively shown in Figures 3A to 3C. For example, the square shape in Figures 3A to 3C can be replaced by a more general quadrilateral shape, such as, for example, a rectangle or a rhombus.

[0144] Furthermore, according to different embodiments, each oxide region 14 has a substantially flat upper surface. Therefore, each gate region 15 has a lower surface in contact with the oxide region 14, the lower surface having a depth measured along the Z-axis direction that is substantially constant and, for example, equal to the second depth P2 previously described.

[0145] In this case, the previously described relationship between the minimum distances D1 and D2 is maintained due to the difference between the depth of the lower surface of the gate interconnect 28 relative to the first side 12a and the depth of the junction of the gate region 15 with respect to the first side 12a between the lateral surface and the lower surface of the gate region 15. In fact, a sufficiently large difference between these depths still allows the first minimum distance D1 to be greater than the second minimum distance D2.

[0146] In addition, Figures 6 and 7A and 7B show different embodiments of MOSFET 10.

[0147] As mentioned, MOSFET 10 in Figure 6 is similar to MOSFET 10 in Figure 1, so it will not be described in detail here except to emphasize the differences relative to the previously described cases.

[0148] Specifically, in the embodiments of Figures 6 and 7A and 7B, the passive gate structure 22' and the active gate structure 22'' are opposite to those previously described and shown in Figures 1 and 2A and 2B. In detail, each passive gate structure 22' of the MOSFET 10 (Figure 7B) (through which it does not generate a conductive channel in use) is defined here by corresponding components of the gate interconnect 28 and the associated insulating interconnect portion 29, while each active gate structure 22'' of the MOSFET 10 (Figure 7A) (through which it generates a conductive channel in use) is defined here by corresponding components of the conductive gate region 15 and the associated oxide region 14 (particularly the associated first oxide portion 14b).

[0149] This is possible by reversing the design criteria for the depths of the conductive gate regions 15 and the gate interconnects 28: in this case, the depth of each conductive gate region 15 relative to the first side 12a is greater than the depth of each gate interconnect 28 relative to the first side 12a. The lower surface of the conductive gate region 15 may be curved, specifically concave, or substantially planar, similar to what has been previously described.

[0150] This diversity in depth results in a corresponding diversity between the first minimum distance D1 (defined herein as the minimum distance between the gate interconnect 28 and the relative interfaces between the body region 17 and the semiconductor body 12) and the second minimum distance D2 (defined herein as the minimum distance between the conductive gate region 15 and the relative interfaces between the body region 17 and the semiconductor body 12), i.e., the first minimum distance D1 is greater than the second minimum distance D2, and in particular, the first minimum distance D1 is at least 50% greater than the second minimum distance D2.

[0151] As previously described, this ensures that conductivity is generated in the active gate structure 22'' during use, but not in the non-active gate structure 22'.

[0152] It is evident that, by reversing the depth of material removal used to form the conductive gate region 15 and the gate interconnect 28 as previously described, the two variations of the previously described fabrication process can also be used in a completely similar manner to fabricate the MOSFET 10 of FIG. 6. Therefore, the fabrication process of this MOSFET 10 will no longer be described, but will refer to the preceding description.

[0153] In one embodiment, an electronic device (10) includes: a semiconductor body (12) having a first conductivity type (N) and having a first side and a second side (12a, 12b) opposite to each other along a first axis (Z); a plurality of trenches (13) extending within the semiconductor body (12) from the first side (12a) toward the second side (12b) and terminating within the semiconductor body (12); a corresponding insulating field plate region (14) in each of the trenches (13) covering the lower wall and sidewall of the corresponding trench (13); and the trenches (14) on the corresponding insulating field plate region (14) A corresponding conductive gate region (15) in each trench of the 13) is made of a conductive material and electrically insulated from the semiconductor body (12) by a corresponding insulating field plate region (14); a corresponding field plate region (16) in each trench of the 13 is embedded in a corresponding insulating field plate region (14) and electrically insulated from the corresponding conductive gate region (15) and the semiconductor body (12) by a corresponding insulating field plate region (14); a plurality of gate interconnects (28) are located within the semiconductor body (12) from the first side (12). a) Extending laterally to the trench (13) toward the second side (12b) and terminating within the semiconductor body (12), the gate interconnect (28) is made of a conductive material, electrically insulated from the semiconductor body (12), and electrically connected to the conductive gate region (15) to electrically interconnect the conductive gate regions (15) with each other; and a plurality of body regions (17) extending between the trenches (13) on the first side (12a), the body regions (17) having a second conductivity type (P) opposite to the first conductivity type (N), laterally to the gate interconnect (28) and the conductive gate region (15), and relative to The gate interconnect (28) and the conductive gate region (15) are electrically insulated, wherein portions of the conductive gate region (15) and the gate interconnect (28) are part of a corresponding non-active gate structure (22') of the electronic device (10), the non-active gate structure being configured to locally suppress the formation of a conductive channel through the body region (17), and other portions of the conductive gate region (15) and the gate interconnect (28) are part of a corresponding active gate structure (22'') of the electronic device (10), the active gate structure being configured to locally allow the formation of a conductive channel through the body region (17).

[0154] In one embodiment, portions of the conductive gate region (15) and the gate interconnect (28) each have a corresponding first minimum distance (D1) from the interface between the corresponding body region (17) and the semiconductor body (12), and other portions of the conductive gate region (15) and the gate interconnect (28) each have a corresponding second minimum distance (D2) from the interface between the corresponding body region (17) and the semiconductor body (12), wherein the first minimum distance (D1) is greater than the second minimum distance (D2).

[0155] In one embodiment, the first minimum distance (D1) is at least 50% greater than the second minimum distance (D2). <

[0156] In one embodiment, the electronic device further includes a plurality of interconnect trenches (31), each interconnect trench (31) extending from a first side (12a) toward a second side (12b) within a semiconductor body (12) and terminating within the semiconductor body (12), wherein the interconnect trenches (31) are orthogonally inserted between trenches (13) and communicating with the trenches (13), wherein gate interconnects (28) extend within the interconnect trenches (31) to electrically contact conductive gate regions (15) with each other, and the electronic device (10) further includes insulating interconnect portions (29) of insulating material extending in the interconnect trenches (31) to be inserted between the gate interconnects (28) and both the semiconductor body (12) and the body region (17) to electrically insulate the gate interconnects (28) from the body region (17) and the semiconductor body (12).

[0157] In one embodiment, each insulating field plate region (14) has a curved upper surface defining a corresponding concavity (54), wherein each conductive gate region (15) extends with a corresponding concavity (54), wherein each conductive gate region (15) has a first depth (P1), i.e., a maximum depth, in a first region of the conductive gate region (15) located radially inward orthogonal to the first axis (Z), and a second depth (P2), i.e., a minimum depth, in a second region of the conductive gate region (15) located radially outward orthogonal to the first axis (Z) and surrounding the first radially inward region, the first region and the second region being continuous with each other, the first depth (P1) and the second depth (P2) being measured parallel to the first axis (Z) from the upper surface of the conductive gate region (15), the first depth (P1) being greater than the second depth (P2), and the depth of the conductive gate region (15) continuously varying between the first depth (P1) and the second depth (P2).

[0158] In one embodiment, the groove (13) is orthogonal to the first axis (Z) and has a closed polygonal shape and matrix arrangement.

[0159] In one embodiment, one of the following configurations a through c applies:

[0160] a: The trench (13) and the conductive gate region (15) have a hexagonal shape orthogonal to the first axis (Z), wherein each gate interconnect (28) connects the three adjacent gate regions (15) in the matrix arrangement to each other, wherein each gate interconnect (28) has three corresponding arms, each arm having a corresponding first end and a corresponding second end opposite to each other in a direction relative to the main extension of the arm, the first ends of the arms of each gate interconnect (28) are joined to each other to form a joint portion of the gate interconnect (28), from the joint portion, the corresponding three arms extend radially to be spaced apart from each other at equal angles orthogonal to the first axis (Z), wherein the second end of each arm of each gate interconnect (28) is coupled to a corresponding vertex of the corresponding gate region in the three gate regions (15), in the matrix arrangement, the three gate regions surround the corresponding gate interconnect (28).

[0161] b: In the matrix arrangement, trenches (13) are aligned with each other along a second axis (X) orthogonal to the first axis (Z) and along a third axis (Y) orthogonal to the first axis (Z) and the second axis (X), wherein the trenches (13) and conductive gate regions (15) have quadrilateral shapes, particularly square shapes, wherein gate interconnects (28) are grouped in groups of four corresponding gate interconnects (28), each group of gate interconnects (28) connecting the four corresponding gate regions (15) that are closest to each other in the matrix arrangement, wherein each group of gate interconnects (28) forms a conductive path orthogonal to the first axis (Z), the conductive path being of the ring type and having a quadrilateral shape, particularly square shape, wherein each vertex of the quadrilateral shape of each conductive path is connected to the corresponding vertex of the corresponding gate region in the four gate regions (15), the four gate regions surrounding the corresponding group of gate interconnects (28) in the matrix arrangement.

[0162] c: In the matrix arrangement, trenches (13) are aligned with each other along a second axis (X) orthogonal to the first axis (Z) and alternately aligned with each other along a third axis (Y) orthogonal to the first axis (Z) and the second axis (X), wherein the trenches (13) and conductive gate regions (15) are quadrilateral in shape, particularly square in shape, wherein gate interconnects (28) are grouped to form serpentine paths of gate interconnects (28), each serpentine path having a main extension along the direction of the second axis (X) and extending between conductive gate regions (15) in two corresponding rows along the direction of the third axis (Y), each row including corresponding conductive gate regions (15) aligned with each other along the direction of the second axis (X), each serpentine path being coupled to the vertex of the corresponding conductive gate region (15) to be continuously coupled with each other, the serpentine paths being inserted between the conductive gate regions (15) in the two corresponding rows.

[0163] In one embodiment, the electronic device further includes: a gate metallization located on a first side (12a) of the semiconductor body (12) and directly electrically connected to a portion of the conductive gate region (15); a source metallization (24) located on the first side (12a) of the semiconductor body (12) and electrically connected to the source region (20) and the field plate region (16); and a drain metallization (26) located on a second side (12b) of the semiconductor body (12).

[0164] In one embodiment, the source metallization (24) has a corresponding metallization portion (24c) for each trench (13), each metallization portion (24c) extending along the direction of the first axis (Z) through the corresponding conductive gate region (15) until reaching the corresponding field plate region (16), wherein each metallization portion (24c) is electrically insulated relative to the corresponding conductive gate region (15) by a corresponding portion (14c) of the insulating field plate region (14), orthogonal to the first axis (Z), the insulating field plate region having an annular shape, surrounding the corresponding metallization portion (24c) and having a width greater than a minimum width equal to 50 nm.

[0165] In one embodiment, the electronic device is of the vertical conductivity type.

[0166] In one embodiment, a process for manufacturing an electronic device (10) includes the following steps: forming a plurality of trenches (13) within a semiconductor body (12), the semiconductor body (12) having a first side and a second side (12a, 12b) opposite to each other along a first axis (Z), the trenches (13) extending from the first side (12a) toward the second side (12b) and terminating within the semiconductor body (12); forming a corresponding insulating field plate region (14) in each of the trenches (13), covering the lower wall and sidewalls of the corresponding trench (13); forming in each of the trenches (13) A corresponding field plate region (16) is embedded in a corresponding insulating field plate region (14) and electrically insulated from the semiconductor body (12) through the corresponding insulating field plate region (14); a corresponding conductive gate region (15) is formed in each trench (13) on the corresponding insulating field plate region (14), each conductive gate region (15) is made of conductive material and electrically insulated from the semiconductor body (12) and the corresponding field plate region (16) through the corresponding insulating field plate region (14); a plurality of gate interconnects (28) are formed, the gate interconnects being formed within the semiconductor body (12) from the first A side (12a) extends laterally to the trench (13) toward the second side (12b) and terminates within the semiconductor body (12). The gate interconnect (28) is made of a conductive material, electrically insulated from the semiconductor body (12), and electrically connected to the conductive gate region (15) to electrically interconnect the conductive gate regions (15) with each other. A plurality of body regions (17) are formed, the body regions extending between the trenches (13) on the first side (12a), the body regions (17) having a second conductivity type (P) opposite to the first conductivity type (N), and laterally to the gate interconnect (28) and the conductive gate region (15). Furthermore, it is electrically insulated relative to the gate interconnect (28) and the conductive gate region (15), wherein portions of the conductive gate region (15) and the gate interconnect (28) are part of a corresponding non-active gate structure (22') of the electronic device (10), the non-active gate structure being configured to locally suppress the formation of a conductive channel through the body region (17), and other portions of the conductive gate region (15) and the gate interconnect (28) are part of a corresponding active gate structure (22'') of the electronic device (10), the active gate structure being configured to locally allow the formation of a conductive channel through the body region (17).

[0167] In one embodiment, after the step of forming the field plate region (16), the manufacturing process further includes the following steps: partially etching a corresponding insulating fill region (51) in each trench (13) on a first side (12a) to form a recess (54) in each trench (13) and define a body (14a) of each insulating field plate region (14); selectively removing portions of the semiconductor body (12) starting from the first side (12a) to form interconnect trenches (31), each interconnect trench (31) extending from the first side (12a) toward a second side (12b) within the semiconductor body (12) and terminating within the semiconductor body (12), the interconnect trenches (31) The first axis (Z) is orthogonally inserted between the trenches (13) and communicates with the trenches (13); and an insulating layer (57) is formed in the interconnect trenches (31) and the recesses (54), the portion of the insulating layer (57) present in the interconnect trenches (31) defining an insulating interconnect portion (29) extending in the interconnect trenches (31), and wherein the steps of forming the conductive gate region (15) and forming the gate interconnect (28) are performed simultaneously by depositing conductive materials in the recesses (54) and the interconnect trenches (31), respectively, such that the insulating interconnect portion (29) is inserted between the gate interconnect (28) and the semiconductor body (12) in the interconnect trenches (31).

[0168] In one embodiment, after the step of forming the field plate region (16), the manufacturing process further includes the following steps: partially etching a corresponding insulating fill region (51) in each trench (13) on a first side (12a) to form a recess (54) in each trench (13); forming a first intermediate insulating layer (70) in the recess (54) and on the exposed area of ​​the semiconductor body (12); selectively removing a portion of the semiconductor body (12) starting from the first side (12a) to form interconnect trenches (31), each interconnect trench (31) extending from the first side (12a) toward the second side (12b) within the semiconductor body (12) and terminating within the semiconductor body (12), the interconnect trenches (31) being orthogonally inserted between the trenches (13) and communicating with the trenches (13) along a first axis (Z); selectively removing a portion of the first intermediate insulating layer (70), leaving the first intermediate insulating layer (70) on the sidewalls and trenches of the field plate region (16). (13) The portion extending on the sidewall; a second intermediate insulating layer (72) is formed on the recessed portion of the insulating filling region (51), on the exposed portion of the semiconductor body (12) and the field plate region (16), and on the remaining portion of the first intermediate insulating layer (70); a portion of the second intermediate insulating layer (72) is selectively removed so that the recess (54) and the interconnect trench (31) are directly connected; and an insulating layer (57) is formed in the interconnect trench (31) and the recess (54), the portion of the insulating layer (57) present in the interconnect trench (31) defining an insulating interconnect portion (29) extending in the interconnect trench (31), and wherein the steps of forming the conductive gate region (15) and forming the gate interconnect (28) are performed simultaneously by depositing conductive materials in the recess (54) and the interconnect trench (31), respectively, such that the insulating interconnect portion (29) is inserted between the gate interconnect (28) and the semiconductor body (12) in the interconnect trench (31).

[0169] In one embodiment, if the conductive gate region (15) is part of an active gate structure (22') and the gate interconnect (28) is part of an active gate structure (22''), then each of the gate interconnects (28) has a corresponding lower surface at a depth greater than the depth of the interface between the corresponding body region (17) and the semiconductor body (12) relative to the first side (12a) and along the first axis (Z), and each of the conductive gate regions (15) has a corresponding lower surface at a minimum depth less than the depth of the interface between the corresponding body region (17) and the semiconductor body (12) relative to the first side (12a) and along the first axis (Z), relative to the first side (12a) and along the first axis (Z). If the gate interconnect (28) is part of an inactive gate structure (22') and the conductive gate region (15) is part of an active gate structure (22''), then each of the gate interconnects (28) has a corresponding lower surface at a depth relative to the first side (12a) and along the first axis (Z) that is smaller than the depth of the interface between the corresponding body region (17) and the semiconductor body (12) relative to the first side (12a) and along the first axis (Z), and each of the conductive gate regions (15) has a corresponding lower surface at a minimum depth relative to the first side (12a) and along the first axis (Z) that is larger than the depth of the interface between the corresponding body region (17) and the semiconductor body (12) relative to the first side (12a) and along the first axis (Z).

[0170] In view of the detailed description above, these and other changes may be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in this specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents to which such claims are conferred. Therefore, the claims are not limited to this disclosure.

Claims

1. An electronic device, comprising: A semiconductor body having a first conductivity type has a first side and a second side that are opposite to each other along a first axis; Multiple trenches extend from the first side toward the second side within the semiconductor body and terminate within the semiconductor body; a corresponding insulating field plate region in each trench covers the lower wall and sidewall of the corresponding trench; A corresponding conductive gate region in each trench of the trench on the corresponding insulating field plate region, each conductive gate region being made of conductive material and electrically insulated from the semiconductor body through the corresponding insulating field plate region; In each of the trenches, a corresponding field plate region is embedded in the corresponding insulating field plate region and electrically insulated from the corresponding conductive gate region and the semiconductor body through the corresponding insulating field plate region; A plurality of gate interconnects extend laterally through the trench from a first side toward a second side within the semiconductor body and terminate within the semiconductor body. The gate interconnects are made of a conductive material, electrically insulated from the semiconductor body, and electrically connected to the conductive gate regions, thereby electrically interconnecting the conductive gate regions with each other. A plurality of body regions extend between the trenches on the first side. The body regions have a second conductivity type opposite to the first conductivity type, are laterally through the gate interconnects and the conductive gate regions, and are electrically insulated relative to the gate interconnects and the conductive gate regions. A portion of the conductive gate regions and the gate interconnects is part of a corresponding passive gate structure of the electronic device, the passive gate structure being configured to locally suppress the formation of conductive channels through the body regions. Other portions of the conductive gate regions and the gate interconnects are part of a corresponding active gate structure of the electronic device, the active gate structure being configured to locally allow the formation of conductive channels through the body regions.

2. The electronic device of claim 1, wherein the conductive gate region and a portion of the gate interconnect each have a corresponding first minimum distance from the interface between the corresponding body region and the semiconductor body, and wherein the conductive gate region and other portions of the gate interconnect each have a corresponding second minimum distance from the interface between the corresponding body region and the semiconductor body, the first minimum distance being greater than the second minimum distance.

3. The electronic device according to claim 2, wherein the first minimum distance is at least 50% greater than the second minimum distance.

4. The electronic device of claim 1, further comprising a plurality of interconnect trenches, each interconnect trench extending from the first side toward the second side and terminating within the semiconductor body, wherein the interconnect trenches are orthogonally inserted between the trenches and in communication with the first axis, wherein the gate interconnects extend within the interconnect trenches to electrically contact each other with the conductive gate regions, the electronic device further comprising an insulating interconnect portion of insulating material extending in the interconnect trenches to be inserted between the gate interconnects and the semiconductor body and the body regions to electrically insulate the gate interconnects from the body regions and the semiconductor body.

5. The electronic device of claim 1, wherein each insulating field plate region has a corresponding upper surface of a curved shape defining a corresponding concavity, wherein each conductive gate region extends with said corresponding concavity, wherein each conductive gate region has a first depth, a maximum depth, in a first region of the conductive gate region located radially inward orthogonal to the first axis, and a second depth, a minimum depth, in a second region of the conductive gate region located radially outward orthogonal to the first axis and surrounding the first radially inward region, the first region and the second region being continuous with each other, the first depth and the second depth being measured parallel to the first axis from the upper surface of the conductive gate region, the first depth being greater than the second depth, and the depth of the conductive gate region continuously varying between the first depth and the second depth.

6. The electronic device according to any one of claims 1, wherein, The trench has a closed polygonal shape and matrix arrangement orthogonal to the first axis.

7. The electronic device of claim 6, wherein one of the following configurations a to c is applicable: a: the trench and the conductive gate region are orthogonal to the first axis and have a hexagonal shape, wherein each gate interconnect connects the three adjacent gate regions in the matrix arrangement to each other, wherein each gate interconnect has three corresponding arms, each arm having a corresponding first end and a corresponding second end opposite to each other in a direction relative to the main extension of the arm, the first ends of the arms of each gate interconnect engaging with each other to form a engagement portion of the gate interconnect, from which the corresponding three arms extend radially, thereby connecting with... The first axes are orthogonally spaced apart at equal angles, wherein the second end of each arm of each gate interconnect is coupled to a corresponding vertex of the corresponding gate region in the three gate regions, and in the matrix arrangement, the three gate regions surround the corresponding gate interconnect; b: in the matrix arrangement, the trenches are aligned with each other along a second axis orthogonal to the first axis and along a third axis orthogonal to the first and second axes, wherein the trenches and the conductive gate regions have quadrilateral shapes, particularly square shapes, orthogonal to the first axis, and wherein the gate interconnects are grouped into groups, each having four corresponding gate interconnects, each group of gate interconnects... The gate interconnects connect the four nearest adjacent gate regions in the matrix arrangement, wherein each set of gate interconnects forms a conductive path that is annular in shape orthogonal to the first axis and has a quadrilateral shape, particularly a square shape, wherein each vertex of the quadrilateral shape of each conductive path is connected to a corresponding vertex of the corresponding gate region in the four gate regions, the four gate regions surrounding the corresponding set of gate interconnects in the matrix arrangement; c: in the matrix arrangement, the trenches are aligned with each other along a second axis orthogonal to the first axis and alternately along axes orthogonal to both the first and second axes. The third axis is aligned with each other, wherein the trench and the conductive gate region have a quadrilateral shape, particularly a square shape, orthogonal to the first axis, wherein the gate interconnects are grouped to form a serpentine path of gate interconnects, each serpentine path having a main extension along the direction of the second axis and extending between two corresponding rows of conductive gate regions along the direction of the third axis, each row including corresponding conductive gate regions aligned with each other along the direction of the second axis, each serpentine path being coupled to the vertex of the corresponding conductive gate region, thereby being continuously coupled to each other, the serpentine path being inserted between the conductive gate regions of the two corresponding rows.

8. The electronic device according to claim 1, further comprising: A gate metallization portion is located on the first side of the semiconductor body and is directly electrically connected to a portion of the conductive gate region; The source metallization portion is located on the first side of the semiconductor body and is electrically connected to the source region and the field plate region; And a drain metallization portion, located on the second side of the semiconductor body.

9. The electronic device of claim 8, wherein the source metallization has a corresponding metallization portion for each trench, each metallization portion extending along the first axis through the corresponding conductive gate region until reaching the corresponding field plate region, wherein each metallization portion is electrically insulated relative to the corresponding conductive gate region by a corresponding portion of the insulating field plate region, the insulating field plate region having an annular shape orthogonal to the first axis, surrounding the corresponding metallization portion and having a width greater than a minimum width equal to 50 nm.

10. The electronic device according to claim 1 is of the vertical conductivity type.

11. A method for manufacturing an electronic device, comprising: Multiple trenches are formed within a semiconductor body, the semiconductor body having a first side and a second side opposite to each other along a first axis, the trenches extending from the first side toward the second side and terminating within the semiconductor body; A corresponding insulating field plate region is formed in each of the trenches, the corresponding insulating field plate region covering the lower wall and sidewall of the corresponding trench; a corresponding field plate region is formed in each of the trenches, each field plate region is buried in the corresponding insulating field plate region, and is electrically insulated from the semiconductor body through the corresponding insulating field plate region; A corresponding conductive gate region is formed on the corresponding insulating field plate region and in each trench of the trench. Each conductive gate region is made of conductive material and is electrically insulated from the semiconductor body and the corresponding field plate region through the corresponding insulating field plate region. A plurality of gate interconnects are formed, the plurality of gate interconnects extending laterally through the trench from a first side toward a second side within the semiconductor body and terminating within the semiconductor body, the gate interconnects being made of a conductive material, electrically insulated from the semiconductor body, and electrically connected to the conductive gate regions, thereby electrically interconnecting the conductive gate regions with each other; and a plurality of body regions are formed, the plurality of body regions extending between the trenches on the first side, the body regions having a second conductivity type opposite to the first conductivity type, laterally through the gate interconnects and the conductive gate regions, and electrically insulated relative to the gate interconnects and the conductive gate regions, wherein portions of the conductive gate regions and the gate interconnects are part of a corresponding passive gate structure of the electronic device, the passive gate structure being configured to locally suppress the formation of conductive channels through the body regions, and other portions of the conductive gate regions and the gate interconnects are part of a corresponding active gate structure of the electronic device, the active gate structure being configured to locally allow the formation of conductive channels through the body regions.

12. The manufacturing method of claim 11, further comprising, after forming the field plate region: partially etching a corresponding insulating fill region in each trench on the first side to form a recess in each trench and define the body of each insulating field plate region; Starting from the first side, a portion of the semiconductor body is selectively removed to form interconnect trenches. Each interconnect trench extends from the first side toward the second side within the semiconductor body and terminates within the semiconductor body. The interconnect trenches are orthogonally inserted between the trenches and communicate with the trenches. An insulating layer is formed in the interconnect trench and the recess, the portion of the insulating layer present in the interconnect trench defining an insulating interconnect portion extending in the interconnect trench, and wherein the steps of forming the conductive gate region and forming the gate interconnect are performed simultaneously by depositing conductive material in the recess and the interconnect trench respectively, such that the insulating interconnect portion is inserted between the gate interconnect and the semiconductor body in the interconnect trench.

13. The manufacturing method of claim 11, further comprising, after forming the field plate region: partially etching a corresponding insulating fill region in each trench on the first side to form a recess in each trench; A first intermediate insulating layer is formed in the recess and on the exposed area of ​​the semiconductor body; Starting from the first side, a portion of the semiconductor body is selectively removed to form interconnect trenches. Each interconnect trench extends from the first side toward the second side within the semiconductor body and terminates within the semiconductor body. The interconnect trenches are orthogonally inserted between the trenches and communicate with the trenches. Selectively remove a portion of the first intermediate insulating layer, leaving the portion of the first intermediate insulating layer extending on the sidewalls of the field plate region and the sidewalls of the trench; A second intermediate insulating layer is formed on the recessed portion of the insulating filling region, on the exposed portion of the semiconductor body and field plate region, and on the remaining portion of the first intermediate insulating layer; A portion of the second intermediate insulating layer is selectively removed to allow direct communication between the recess and the interconnect trench; and an insulating layer is formed in the interconnect trench and the recess, the portion of the insulating layer present in the interconnect trench defining an insulating interconnect portion extending in the interconnect trench, wherein the steps of forming the conductive gate region and forming the gate interconnect are performed simultaneously by depositing conductive material in the recess and the interconnect trench respectively, such that the insulating interconnect portion is inserted between the gate interconnect and the semiconductor body in the interconnect trench.

14. The manufacturing method according to claim 13, wherein, If the conductive gate region is part of the non-active gate structure and the gate interconnect is part of the active gate structure, then each gate interconnect has a corresponding lower surface at a depth relative to the first side and along the first axis that is greater than the depth of the interface between the corresponding body region and the semiconductor body relative to the first side and along the first axis, and each conductive gate region has a corresponding lower surface at a minimum depth relative to the first side and along the first axis that is smaller than the depth of the interface between the corresponding body region and the semiconductor body relative to the first side and along the first axis, or wherein, if the gate interconnect is part of the non-active gate structure and the conductive gate region is part of the active gate structure, then each gate interconnect has a corresponding lower surface at a depth relative to the first side and along the first axis that is smaller than the depth of the interface between the corresponding body region and the semiconductor body relative to the first side and along the first axis, and each conductive gate region has a corresponding lower surface at a minimum depth relative to the first side and along the first axis that is greater than the depth of the interface between the corresponding body region and the semiconductor body relative to the first side and along the first axis.

15. An electronic device, comprising: Semiconductor body of the first conductivity type; Multiple trenches extend within the semiconductor body and terminate within the semiconductor body; Multiple insulating field plate areas, each insulating field plate area is in a corresponding trench; Multiple corresponding conductive gate regions, each conductive gate region being in a corresponding trench; Multiple field plate regions, each field plate region being in a corresponding trench and electrically insulated from the corresponding conductive gate region and the semiconductor body by a corresponding insulating field plate region; Multiple gate interconnects extend adjacent to the trench within the semiconductor body, terminate within the semiconductor body, are electrically insulated from the semiconductor body, and electrically interconnect the conductive gate regions; And a plurality of body regions of a second conductivity type, wherein the body regions extend laterally between the gate interconnect and the conductive gate region in the trench.

16. The electronic device of claim 15, wherein a first subset of the conductive gate regions and a first subset of the gate interconnects are part of a corresponding active gate structure of the electronic device, the active gate structure being configured to locally suppress the formation of conductive trenches through the body regions.

17. The electronic device of claim 16, wherein the second subset of the conductive gate region and the second subset of the gate interconnect are part of a corresponding active gate structure of the electronic device, the active gate structure being configured to partially allow the formation of conductive trenches through the body region.

18. The electronic device of claim 17, wherein the first subset of the conductive gate regions and the first subset of the gate interconnects each have a corresponding first minimum distance from the interface between the respective body region and the semiconductor body.

19. The electronic device of claim 18, wherein the second subset of the conductive gate region and the second subset of the gate interconnect each have a corresponding second minimum distance from the interface between the respective body region and the semiconductor body, the first minimum distance being greater than the second minimum distance.

20. The electronic device of claim 19, wherein the first minimum distance is at least 50% greater than the second minimum distance.

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